[linux-2.6-block.git] / drivers / i2c / busses / i2c-iop3xx.c

/* ------------------------------------------------------------------------- */
/* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x       */
/* ------------------------------------------------------------------------- */
/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
 *                    <Peter dot Milne at D hyphen TACQ dot com>
 *
 * With acknowledgements to i2c-algo-ibm_ocp.c by
 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
 *
 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
 *
 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
 *
 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
 *
 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
 *
 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
 * - Make it work with IXP46x chips
 * - Cleanup function names, coding style, etc
 *
 * - writing to slave address causes latchup on iop331.
 *	fix: driver refuses to address self.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2.
 */

#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include "i2c-iop3xx.h"

/* global unit counter */
static int i2c_id;

static inline unsigned char
iic_cook_addr(struct i2c_msg *msg)
{
	unsigned char addr;

	addr = (msg->addr << 1);

	if (msg->flags & I2C_M_RD)
		addr |= 1;

	return addr;
}

static void
iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	/* Follows devman 9.3 */
	__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
	__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
	__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
}

static void
iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;

	/*
	 * Every time unit enable is asserted, GPOD needs to be cleared
	 * on IOP3XX to avoid data corruption on the bus.
	 */
#if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
	if (iop3xx_adap->id == 0) {
		gpio_set_value(7, 0);
		gpio_set_value(6, 0);
	} else {
		gpio_set_value(5, 0);
		gpio_set_value(4, 0);
	}
#endif
	/* NB SR bits not same position as CR IE bits :-( */
	iop3xx_adap->SR_enabled =
		IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
		IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;

	cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
		IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}

static void
iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);

	cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
		IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}

/*
 * NB: the handler has to clear the source of the interrupt!
 * Then it passes the SR flags of interest to BH via adap data
 */
static irqreturn_t
iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
	u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);

	if ((sr &= iop3xx_adap->SR_enabled)) {
		__raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
		iop3xx_adap->SR_received |= sr;
		wake_up_interruptible(&iop3xx_adap->waitq);
	}
	return IRQ_HANDLED;
}

/* check all error conditions, clear them , report most important */
static int
iop3xx_i2c_error(u32 sr)
{
	int rc = 0;

	if ((sr & IOP3XX_ISR_BERRD)) {
		if ( !rc ) rc = -I2C_ERR_BERR;
	}
	if ((sr & IOP3XX_ISR_ALD)) {
		if ( !rc ) rc = -I2C_ERR_ALD;
	}
	return rc;
}

static inline u32
iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	unsigned long flags;
	u32 sr;

	spin_lock_irqsave(&iop3xx_adap->lock, flags);
	sr = iop3xx_adap->SR_received;
	iop3xx_adap->SR_received = 0;
	spin_unlock_irqrestore(&iop3xx_adap->lock, flags);

	return sr;
}

/*
 * sleep until interrupted, then recover and analyse the SR
 * saved by handler
 */
typedef int (* compare_func)(unsigned test, unsigned mask);
/* returns 1 on correct comparison */

static int
iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
			  unsigned flags, unsigned* status,
			  compare_func compare)
{
	unsigned sr = 0;
	int interrupted;
	int done;
	int rc = 0;

	do {
		interrupted = wait_event_interruptible_timeout (
			iop3xx_adap->waitq,
			(done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
			1 * HZ;
			);
		if ((rc = iop3xx_i2c_error(sr)) < 0) {
			*status = sr;
			return rc;
		} else if (!interrupted) {
			*status = sr;
			return -ETIMEDOUT;
		}
	} while(!done);

	*status = sr;

	return 0;
}

/*
 * Concrete compare_funcs
 */
static int
all_bits_clear(unsigned test, unsigned mask)
{
	return (test & mask) == 0;
}

static int
any_bits_set(unsigned test, unsigned mask)
{
	return (test & mask) != 0;
}

static int
iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event(
		iop3xx_adap,
	        IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
		status, any_bits_set);
}

static int
iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event(
		iop3xx_adap,
		IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
		status,	any_bits_set);
}

static int
iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event(
		iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
}

static int
iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
				struct i2c_msg* msg)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc;

	/* avoid writing to my slave address (hangs on 80331),
	 * forbidden in Intel developer manual
	 */
	if (msg->addr == MYSAR) {
		return -EBUSY;
	}

	__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);

	cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
	cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);

	return rc;
}

static int
iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
				int stop)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc = 0;

	__raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
	cr &= ~IOP3XX_ICR_MSTART;
	if (stop) {
		cr |= IOP3XX_ICR_MSTOP;
	} else {
		cr &= ~IOP3XX_ICR_MSTOP;
	}
	cr |= IOP3XX_ICR_TBYTE;
	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);

	return rc;
}

static int
iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
				int stop)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc = 0;

	cr &= ~IOP3XX_ICR_MSTART;

	if (stop) {
		cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
	} else {
		cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
	}
	cr |= IOP3XX_ICR_TBYTE;
	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);

	rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);

	*byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);

	return rc;
}

static int
iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int ii;
	int rc = 0;

	for (ii = 0; rc == 0 && ii != count; ++ii)
		rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
	return rc;
}

static int
iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int ii;
	int rc = 0;

	for (ii = 0; rc == 0 && ii != count; ++ii)
		rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);

	return rc;
}

/*
 * Description:  This function implements combined transactions.  Combined
 * transactions consist of combinations of reading and writing blocks of data.
 * FROM THE SAME ADDRESS
 * Each transfer (i.e. a read or a write) is separated by a repeated start
 * condition.
 */
static int
iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int rc;

	rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
	if (rc < 0) {
		return rc;
	}

	if ((pmsg->flags&I2C_M_RD)) {
		return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
	} else {
		return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
	}
}

/*
 * master_xfer() - main read/write entry
 */
static int
iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
				int num)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int im = 0;
	int ret = 0;
	int status;

	iop3xx_i2c_wait_idle(iop3xx_adap, &status);
	iop3xx_i2c_reset(iop3xx_adap);
	iop3xx_i2c_enable(iop3xx_adap);

	for (im = 0; ret == 0 && im != num; im++) {
		ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
	}

	iop3xx_i2c_transaction_cleanup(iop3xx_adap);

	if(ret)
		return ret;

	return im;
}

static u32
iop3xx_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm iop3xx_i2c_algo = {
	.master_xfer	= iop3xx_i2c_master_xfer,
	.functionality	= iop3xx_i2c_func,
};

static int
iop3xx_i2c_remove(struct platform_device *pdev)
{
	struct i2c_adapter *padapter = platform_get_drvdata(pdev);
	struct i2c_algo_iop3xx_data *adapter_data =
		(struct i2c_algo_iop3xx_data *)padapter->algo_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);

	/*
	 * Disable the actual HW unit
	 */
	cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
		IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
	__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);

	iounmap(adapter_data->ioaddr);
	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	kfree(adapter_data);
	kfree(padapter);

	return 0;
}

static int
iop3xx_i2c_probe(struct platform_device *pdev)
{
	struct resource *res;
	int ret, irq;
	struct i2c_adapter *new_adapter;
	struct i2c_algo_iop3xx_data *adapter_data;

	new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
	if (!new_adapter) {
		ret = -ENOMEM;
		goto out;
	}

	adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
	if (!adapter_data) {
		ret = -ENOMEM;
		goto free_adapter;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENODEV;
		goto free_both;
	}

	if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
		ret = -EBUSY;
		goto free_both;
	}

	/* set the adapter enumeration # */
	adapter_data->id = i2c_id++;

	adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE);
	if (!adapter_data->ioaddr) {
		ret = -ENOMEM;
		goto release_region;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = -ENXIO;
		goto unmap;
	}
	ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
				pdev->name, adapter_data);

	if (ret) {
		ret = -EIO;
		goto unmap;
	}

	memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
	new_adapter->owner = THIS_MODULE;
	new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
	new_adapter->dev.parent = &pdev->dev;
	new_adapter->nr = pdev->id;

	/*
	 * Default values...should these come in from board code?
	 */
	new_adapter->timeout = HZ;
	new_adapter->algo = &iop3xx_i2c_algo;

	init_waitqueue_head(&adapter_data->waitq);
	spin_lock_init(&adapter_data->lock);

	iop3xx_i2c_reset(adapter_data);
	iop3xx_i2c_enable(adapter_data);

	platform_set_drvdata(pdev, new_adapter);
	new_adapter->algo_data = adapter_data;

	i2c_add_numbered_adapter(new_adapter);

	return 0;

unmap:
	iounmap(adapter_data->ioaddr);

release_region:
	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);

free_both:
	kfree(adapter_data);

free_adapter:
	kfree(new_adapter);

out:
	return ret;
}


static struct platform_driver iop3xx_i2c_driver = {
	.probe		= iop3xx_i2c_probe,
	.remove		= iop3xx_i2c_remove,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "IOP3xx-I2C",
	},
};

module_platform_driver(iop3xx_i2c_driver);

MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:IOP3xx-I2C");
Commit	Line	Data
1da177e4 LT	1	/* ------------------------------------------------------------------------- */
	2	/* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
	3	/* ------------------------------------------------------------------------- */
	4	/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
	5	* <Peter dot Milne at D hyphen TACQ dot com>
	6	*
67ac88ff	7	* With acknowledgements to i2c-algo-ibm_ocp.c by
1da177e4 LT	8	* Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
	9	*
	10	* And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
	11	*
	12	* Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
67ac88ff	13	*
fbd9a6d7	14	* And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
1da177e4 LT	15	* Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
	16	*
	17	* Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
	18	*
	19	* - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
	20	* - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
	21	* - Make it work with IXP46x chips
	22	* - Cleanup function names, coding style, etc
	23	*
39288e1a PM	24	* - writing to slave address causes latchup on iop331.
	25	* fix: driver refuses to address self.
	26	*
1da177e4 LT	27	* This program is free software; you can redistribute it and/or modify
	28	* it under the terms of the GNU General Public License as published by
	29	* the Free Software Foundation, version 2.
	30	*/
	31
1da177e4 LT	32	#include <linux/interrupt.h>
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/delay.h>
	36	#include <linux/slab.h>
	37	#include <linux/init.h>
	38	#include <linux/errno.h>
d052d1be	39	#include <linux/platform_device.h>
1da177e4	40	#include <linux/i2c.h>
21782180	41	#include <linux/io.h>
701eb264	42	#include <linux/gpio.h>
1da177e4 LT	43
	44	#include "i2c-iop3xx.h"
	45
	46	/* global unit counter */
60507095	47	static int i2c_id;
1da177e4	48
67ac88ff RH	49	static inline unsigned char
67ac88ff RH	50	iic_cook_addr(struct i2c_msg *msg)
1da177e4 LT	51	{
	52	unsigned char addr;
	53
	54	addr = (msg->addr << 1);
	55
	56	if (msg->flags & I2C_M_RD)
	57	addr \|= 1;
	58
67ac88ff	59	return addr;
1da177e4 LT	60	}
1da177e4 LT	61
67ac88ff	62	static void
1da177e4 LT	63	iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
	64	{
	65	/* Follows devman 9.3 */
	66	__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
	67	__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
	68	__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
67ac88ff	69	}
1da177e4	70
67ac88ff	71	static void
1da177e4 LT	72	iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
	73	{
	74	u32 cr = IOP3XX_ICR_GCD \| IOP3XX_ICR_SCLEN \| IOP3XX_ICR_UE;
	75
67ac88ff	76	/*
44bbe87e	77	* Every time unit enable is asserted, GPOD needs to be cleared
72edd84a	78	* on IOP3XX to avoid data corruption on the bus.
1da177e4	79	*/
588ef769	80	#if defined(CONFIG_ARCH_IOP32X) \|\| defined(CONFIG_ARCH_IOP33X)
72edd84a	81	if (iop3xx_adap->id == 0) {
701eb264 RH	82	gpio_set_value(7, 0);
701eb264 RH	83	gpio_set_value(6, 0);
72edd84a	84	} else {
701eb264 RH	85	gpio_set_value(5, 0);
701eb264 RH	86	gpio_set_value(4, 0);
72edd84a	87	}
1da177e4 LT	88	#endif
1da177e4 LT	89	/* NB SR bits not same position as CR IE bits :-( */
67ac88ff	90	iop3xx_adap->SR_enabled =
1da177e4 LT	91	IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD \|
	92	IOP3XX_ISR_RXFULL \| IOP3XX_ISR_TXEMPTY;
	93
	94	cr \|= IOP3XX_ICR_ALD_IE \| IOP3XX_ICR_BERR_IE \|
	95	IOP3XX_ICR_RXFULL_IE \| IOP3XX_ICR_TXEMPTY_IE;
	96
	97	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	98	}
	99
67ac88ff	100	static void
1da177e4 LT	101	iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
	102	{
	103	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
67ac88ff RH	104
67ac88ff RH	105	cr &= ~(IOP3XX_ICR_MSTART \| IOP3XX_ICR_TBYTE \|
1da177e4 LT	106	IOP3XX_ICR_MSTOP \| IOP3XX_ICR_SCLEN);
	107
	108	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	109	}
	110
67ac88ff RH	111	/*
67ac88ff RH	112	* NB: the handler has to clear the source of the interrupt!
1da177e4 LT	113	* Then it passes the SR flags of interest to BH via adap data
1da177e4 LT	114	*/
67ac88ff RH	115	static irqreturn_t
67ac88ff RH	116	iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
1da177e4 LT	117	{
	118	struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
	119	u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
	120
	121	if ((sr &= iop3xx_adap->SR_enabled)) {
	122	__raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
	123	iop3xx_adap->SR_received \|= sr;
	124	wake_up_interruptible(&iop3xx_adap->waitq);
	125	}
	126	return IRQ_HANDLED;
	127	}
	128
	129	/* check all error conditions, clear them , report most important */
67ac88ff	130	static int
1da177e4 LT	131	iop3xx_i2c_error(u32 sr)
	132	{
	133	int rc = 0;
	134
	135	if ((sr & IOP3XX_ISR_BERRD)) {
	136	if ( !rc ) rc = -I2C_ERR_BERR;
	137	}
	138	if ((sr & IOP3XX_ISR_ALD)) {
67ac88ff	139	if ( !rc ) rc = -I2C_ERR_ALD;
1da177e4	140	}
67ac88ff	141	return rc;
1da177e4 LT	142	}
1da177e4 LT	143
67ac88ff	144	static inline u32
1da177e4 LT	145	iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
	146	{
	147	unsigned long flags;
	148	u32 sr;
	149
	150	spin_lock_irqsave(&iop3xx_adap->lock, flags);
	151	sr = iop3xx_adap->SR_received;
	152	iop3xx_adap->SR_received = 0;
	153	spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
	154
	155	return sr;
	156	}
	157
	158	/*
	159	* sleep until interrupted, then recover and analyse the SR
	160	* saved by handler
	161	*/
	162	typedef int (* compare_func)(unsigned test, unsigned mask);
	163	/* returns 1 on correct comparison */
	164
67ac88ff RH	165	static int
67ac88ff RH	166	iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
1da177e4 LT	167	unsigned flags, unsigned* status,
	168	compare_func compare)
	169	{
	170	unsigned sr = 0;
	171	int interrupted;
	172	int done;
	173	int rc = 0;
	174
	175	do {
	176	interrupted = wait_event_interruptible_timeout (
	177	iop3xx_adap->waitq,
fbd9a6d7	178	(done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
1da177e4 LT	179	1 * HZ;
	180	);
	181	if ((rc = iop3xx_i2c_error(sr)) < 0) {
	182	*status = sr;
	183	return rc;
	184	} else if (!interrupted) {
	185	*status = sr;
	186	return -ETIMEDOUT;
	187	}
	188	} while(!done);
	189
	190	*status = sr;
	191
	192	return 0;
	193	}
	194
	195	/*
67ac88ff	196	* Concrete compare_funcs
1da177e4	197	*/
67ac88ff	198	static int
1da177e4 LT	199	all_bits_clear(unsigned test, unsigned mask)
	200	{
	201	return (test & mask) == 0;
	202	}
	203
67ac88ff	204	static int
1da177e4 LT	205	any_bits_set(unsigned test, unsigned mask)
	206	{
	207	return (test & mask) != 0;
	208	}
	209
67ac88ff	210	static int
1da177e4 LT	211	iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
1da177e4 LT	212	{
67ac88ff RH	213	return iop3xx_i2c_wait_event(
67ac88ff RH	214	iop3xx_adap,
1da177e4 LT	215	IOP3XX_ISR_TXEMPTY \| IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD,
	216	status, any_bits_set);
	217	}
	218
67ac88ff	219	static int
1da177e4 LT	220	iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
1da177e4 LT	221	{
67ac88ff RH	222	return iop3xx_i2c_wait_event(
67ac88ff RH	223	iop3xx_adap,
1da177e4 LT	224	IOP3XX_ISR_RXFULL \| IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD,
	225	status, any_bits_set);
	226	}
	227
67ac88ff	228	static int
1da177e4 LT	229	iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
1da177e4 LT	230	{
67ac88ff	231	return iop3xx_i2c_wait_event(
1da177e4 LT	232	iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
	233	}
	234
67ac88ff RH	235	static int
67ac88ff RH	236	iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
1da177e4 LT	237	struct i2c_msg* msg)
	238	{
	239	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	240	int status;
	241	int rc;
	242
39288e1a PM	243	/* avoid writing to my slave address (hangs on 80331),
	244	* forbidden in Intel developer manual
	245	*/
	246	if (msg->addr == MYSAR) {
	247	return -EBUSY;
	248	}
	249
1da177e4	250	__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
67ac88ff	251
1da177e4 LT	252	cr &= ~(IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK);
	253	cr \|= IOP3XX_ICR_MSTART \| IOP3XX_ICR_TBYTE;
	254
	255	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	256	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
	257
	258	return rc;
	259	}
	260
67ac88ff RH	261	static int
67ac88ff RH	262	iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
1da177e4 LT	263	int stop)
	264	{
	265	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	266	int status;
	267	int rc = 0;
	268
	269	__raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
	270	cr &= ~IOP3XX_ICR_MSTART;
	271	if (stop) {
	272	cr \|= IOP3XX_ICR_MSTOP;
	273	} else {
	274	cr &= ~IOP3XX_ICR_MSTOP;
	275	}
	276	cr \|= IOP3XX_ICR_TBYTE;
	277	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	278	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
	279
	280	return rc;
67ac88ff	281	}
1da177e4	282
67ac88ff RH	283	static int
67ac88ff RH	284	iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data iop3xx_adap, char byte,
1da177e4 LT	285	int stop)
	286	{
	287	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	288	int status;
	289	int rc = 0;
	290
	291	cr &= ~IOP3XX_ICR_MSTART;
	292
	293	if (stop) {
	294	cr \|= IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK;
	295	} else {
	296	cr &= ~(IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK);
	297	}
	298	cr \|= IOP3XX_ICR_TBYTE;
	299	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	300
	301	rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
	302
	303	*byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
	304
	305	return rc;
	306	}
	307
67ac88ff	308	static int
1da177e4 LT	309	iop3xx_i2c_writebytes(struct i2c_adapter i2c_adap, const char buf, int count)
	310	{
	311	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	312	int ii;
	313	int rc = 0;
	314
67ac88ff	315	for (ii = 0; rc == 0 && ii != count; ++ii)
1da177e4 LT	316	rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
	317	return rc;
	318	}
	319
67ac88ff	320	static int
1da177e4 LT	321	iop3xx_i2c_readbytes(struct i2c_adapter i2c_adap, char buf, int count)
	322	{
	323	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	324	int ii;
	325	int rc = 0;
	326
	327	for (ii = 0; rc == 0 && ii != count; ++ii)
	328	rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
67ac88ff	329
1da177e4 LT	330	return rc;
	331	}
	332
	333	/*
	334	* Description: This function implements combined transactions. Combined
	335	* transactions consist of combinations of reading and writing blocks of data.
	336	* FROM THE SAME ADDRESS
	337	* Each transfer (i.e. a read or a write) is separated by a repeated start
	338	* condition.
	339	*/
67ac88ff RH	340	static int
67ac88ff RH	341	iop3xx_i2c_handle_msg(struct i2c_adapter i2c_adap, struct i2c_msg pmsg)
1da177e4 LT	342	{
	343	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	344	int rc;
	345
	346	rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
	347	if (rc < 0) {
	348	return rc;
	349	}
	350
	351	if ((pmsg->flags&I2C_M_RD)) {
	352	return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
	353	} else {
	354	return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
	355	}
	356	}
	357
	358	/*
	359	* master_xfer() - main read/write entry
	360	*/
67ac88ff RH	361	static int
67ac88ff RH	362	iop3xx_i2c_master_xfer(struct i2c_adapter i2c_adap, struct i2c_msg msgs,
1da177e4 LT	363	int num)
	364	{
	365	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	366	int im = 0;
	367	int ret = 0;
	368	int status;
	369
	370	iop3xx_i2c_wait_idle(iop3xx_adap, &status);
	371	iop3xx_i2c_reset(iop3xx_adap);
	372	iop3xx_i2c_enable(iop3xx_adap);
	373
	374	for (im = 0; ret == 0 && im != num; im++) {
	375	ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
	376	}
	377
	378	iop3xx_i2c_transaction_cleanup(iop3xx_adap);
67ac88ff	379
1da177e4 LT	380	if(ret)
	381	return ret;
	382
67ac88ff	383	return im;
1da177e4 LT	384	}
1da177e4 LT	385
67ac88ff	386	static u32
1da177e4 LT	387	iop3xx_i2c_func(struct i2c_adapter *adap)
	388	{
	389	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	390	}
	391
8f9082c5	392	static const struct i2c_algorithm iop3xx_i2c_algo = {
1da177e4	393	.master_xfer = iop3xx_i2c_master_xfer,
1da177e4 LT	394	.functionality = iop3xx_i2c_func,
	395	};
	396
67ac88ff	397	static int
3ae5eaec	398	iop3xx_i2c_remove(struct platform_device *pdev)
1da177e4	399	{
3ae5eaec	400	struct i2c_adapter *padapter = platform_get_drvdata(pdev);
67ac88ff	401	struct i2c_algo_iop3xx_data *adapter_data =
1da177e4 LT	402	(struct i2c_algo_iop3xx_data *)padapter->algo_data;
	403	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	404	unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
	405
	406	/*
	407	* Disable the actual HW unit
	408	*/
	409	cr &= ~(IOP3XX_ICR_ALD_IE \| IOP3XX_ICR_BERR_IE \|
	410	IOP3XX_ICR_RXFULL_IE \| IOP3XX_ICR_TXEMPTY_IE);
	411	__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
	412
747fcc91	413	iounmap(adapter_data->ioaddr);
1da177e4 LT	414	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	415	kfree(adapter_data);
	416	kfree(padapter);
	417
1da177e4 LT	418	return 0;
	419	}
	420
67ac88ff	421	static int
3ae5eaec	422	iop3xx_i2c_probe(struct platform_device *pdev)
1da177e4	423	{
1da177e4	424	struct resource *res;
48944738	425	int ret, irq;
1da177e4 LT	426	struct i2c_adapter *new_adapter;
	427	struct i2c_algo_iop3xx_data *adapter_data;
	428
5263ebb5	429	new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
1da177e4 LT	430	if (!new_adapter) {
	431	ret = -ENOMEM;
	432	goto out;
	433	}
1da177e4	434
5263ebb5	435	adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
1da177e4 LT	436	if (!adapter_data) {
	437	ret = -ENOMEM;
	438	goto free_adapter;
	439	}
1da177e4 LT	440
	441	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	442	if (!res) {
	443	ret = -ENODEV;
	444	goto free_both;
	445	}
	446
	447	if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
	448	ret = -EBUSY;
	449	goto free_both;
	450	}
	451
	452	/* set the adapter enumeration # */
	453	adapter_data->id = i2c_id++;
	454
747fcc91	455	adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE);
1da177e4 LT	456	if (!adapter_data->ioaddr) {
	457	ret = -ENOMEM;
	458	goto release_region;
	459	}
	460
48944738 DV	461	irq = platform_get_irq(pdev, 0);
	462	if (irq < 0) {
	463	ret = -ENXIO;
	464	goto unmap;
	465	}
	466	ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
1da177e4	467	pdev->name, adapter_data);
fbd9a6d7 DW	468
fbd9a6d7 DW	469	if (ret) {
1da177e4 LT	470	ret = -EIO;
	471	goto unmap;
	472	}
	473
	474	memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
1da177e4	475	new_adapter->owner = THIS_MODULE;
3401b2ff	476	new_adapter->class = I2C_CLASS_HWMON \| I2C_CLASS_SPD;
1da177e4	477	new_adapter->dev.parent = &pdev->dev;
757ba4c6	478	new_adapter->nr = pdev->id;
1da177e4 LT	479
	480	/*
	481	* Default values...should these come in from board code?
	482	*/
8a52c6b4	483	new_adapter->timeout = HZ;
1da177e4 LT	484	new_adapter->algo = &iop3xx_i2c_algo;
	485
	486	init_waitqueue_head(&adapter_data->waitq);
	487	spin_lock_init(&adapter_data->lock);
	488
	489	iop3xx_i2c_reset(adapter_data);
1da177e4 LT	490	iop3xx_i2c_enable(adapter_data);
1da177e4 LT	491
3ae5eaec	492	platform_set_drvdata(pdev, new_adapter);
1da177e4 LT	493	new_adapter->algo_data = adapter_data;
1da177e4 LT	494
757ba4c6	495	i2c_add_numbered_adapter(new_adapter);
1da177e4 LT	496
	497	return 0;
	498
	499	unmap:
747fcc91	500	iounmap(adapter_data->ioaddr);
1da177e4 LT	501
	502	release_region:
	503	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	504
	505	free_both:
	506	kfree(adapter_data);
	507
	508	free_adapter:
	509	kfree(new_adapter);
	510
	511	out:
	512	return ret;
	513	}
	514
	515
3ae5eaec	516	static struct platform_driver iop3xx_i2c_driver = {
1da177e4	517	.probe = iop3xx_i2c_probe,
3ae5eaec RK	518	.remove = iop3xx_i2c_remove,
	519	.driver = {
	520	.owner = THIS_MODULE,
	521	.name = "IOP3xx-I2C",
	522	},
1da177e4 LT	523	};
1da177e4 LT	524
a3664b51	525	module_platform_driver(iop3xx_i2c_driver);
1da177e4 LT	526
	527	MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
	528	MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
	529	MODULE_LICENSE("GPL");
add8eda7	530	MODULE_ALIAS("platform:IOP3xx-I2C");