Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
b3b8df97 | 5 | Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
1da177e4 LT |
18 | */ |
19 | ||
20 | /* | |
ce316110 JD |
21 | * Supports the following Intel I/O Controller Hubs (ICH): |
22 | * | |
23 | * I/O Block I2C | |
24 | * region SMBus Block proc. block | |
25 | * Chip name PCI ID size PEC buffer call read | |
26 | * --------------------------------------------------------------------------- | |
27 | * 82801AA (ICH) 0x2413 16 no no no no | |
28 | * 82801AB (ICH0) 0x2423 16 no no no no | |
29 | * 82801BA (ICH2) 0x2443 16 no no no no | |
30 | * 82801CA (ICH3) 0x2483 32 soft no no no | |
31 | * 82801DB (ICH4) 0x24c3 32 hard yes no no | |
32 | * 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
33 | * 6300ESB 0x25a4 32 hard yes yes yes | |
34 | * 82801F (ICH6) 0x266a 32 hard yes yes yes | |
35 | * 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
36 | * 82801G (ICH7) 0x27da 32 hard yes yes yes | |
37 | * 82801H (ICH8) 0x283e 32 hard yes yes yes | |
38 | * 82801I (ICH9) 0x2930 32 hard yes yes yes | |
39 | * EP80579 (Tolapai) 0x5032 32 hard yes yes yes | |
40 | * ICH10 0x3a30 32 hard yes yes yes | |
41 | * ICH10 0x3a60 32 hard yes yes yes | |
42 | * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes | |
43 | * 6 Series (PCH) 0x1c22 32 hard yes yes yes | |
44 | * Patsburg (PCH) 0x1d22 32 hard yes yes yes | |
45 | * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes | |
46 | * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
47 | * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
48 | * DH89xxCC (PCH) 0x2330 32 hard yes yes yes | |
49 | * Panther Point (PCH) 0x1e22 32 hard yes yes yes | |
50 | * Lynx Point (PCH) 0x8c22 32 hard yes yes yes | |
51 | * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes | |
52 | * Avoton (SOC) 0x1f3c 32 hard yes yes yes | |
53 | * Wellsburg (PCH) 0x8d22 32 hard yes yes yes | |
54 | * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes | |
55 | * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes | |
56 | * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes | |
57 | * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes | |
b299de83 | 58 | * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes |
ce316110 JD |
59 | * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes |
60 | * BayTrail (SOC) 0x0f12 32 hard yes yes yes | |
15407798 | 61 | * Braswell (SOC) 0x2292 32 hard yes yes yes |
3e27a844 | 62 | * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes |
3eee1799 | 63 | * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes |
84d7f2eb | 64 | * DNV (SOC) 0x19df 32 hard yes yes yes |
dd77f423 | 65 | * Broxton (SOC) 0x5ad4 32 hard yes yes yes |
cdc5a311 AY |
66 | * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes |
67 | * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes | |
31158763 | 68 | * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes |
9827f9eb | 69 | * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes |
09a1de04 SP |
70 | * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes |
71 | * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes | |
cb09d943 | 72 | * Cedar Fork (PCH) 0x18df 32 hard yes yes yes |
ce316110 JD |
73 | * |
74 | * Features supported by this driver: | |
75 | * Software PEC no | |
76 | * Hardware PEC yes | |
77 | * Block buffer yes | |
78 | * Block process call transaction no | |
79 | * I2C block read transaction yes (doesn't use the block buffer) | |
80 | * Slave mode no | |
7b0ed334 | 81 | * SMBus Host Notify yes |
ce316110 JD |
82 | * Interrupt processing yes |
83 | * | |
84 | * See the file Documentation/i2c/busses/i2c-i801 for details. | |
85 | */ | |
1da177e4 | 86 | |
636752bc | 87 | #include <linux/interrupt.h> |
1da177e4 LT |
88 | #include <linux/module.h> |
89 | #include <linux/pci.h> | |
90 | #include <linux/kernel.h> | |
91 | #include <linux/stddef.h> | |
92 | #include <linux/delay.h> | |
1da177e4 LT |
93 | #include <linux/ioport.h> |
94 | #include <linux/init.h> | |
95 | #include <linux/i2c.h> | |
7b0ed334 | 96 | #include <linux/i2c-smbus.h> |
54fb4a05 | 97 | #include <linux/acpi.h> |
1561bfe5 | 98 | #include <linux/io.h> |
fa5bfab7 | 99 | #include <linux/dmi.h> |
665a96b7 | 100 | #include <linux/slab.h> |
636752bc | 101 | #include <linux/wait.h> |
3ad7ea18 | 102 | #include <linux/err.h> |
94246930 MW |
103 | #include <linux/platform_device.h> |
104 | #include <linux/platform_data/itco_wdt.h> | |
a7401ca5 | 105 | #include <linux/pm_runtime.h> |
3ad7ea18 | 106 | |
175c7080 | 107 | #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI |
3ad7ea18 JD |
108 | #include <linux/gpio.h> |
109 | #include <linux/i2c-mux-gpio.h> | |
3ad7ea18 | 110 | #endif |
1da177e4 | 111 | |
1da177e4 | 112 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
113 | #define SMBHSTSTS(p) (0 + (p)->smba) |
114 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
115 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
116 | #define SMBHSTADD(p) (4 + (p)->smba) | |
117 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
118 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
119 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
120 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
121 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
122 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
7b0ed334 BT |
123 | #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ |
124 | #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ | |
125 | #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ | |
1da177e4 LT |
126 | |
127 | /* PCI Address Constants */ | |
6dcc19df | 128 | #define SMBBAR 4 |
aeb8a3d1 | 129 | #define SMBPCICTL 0x004 |
636752bc | 130 | #define SMBPCISTS 0x006 |
1da177e4 | 131 | #define SMBHSTCFG 0x040 |
94246930 MW |
132 | #define TCOBASE 0x050 |
133 | #define TCOCTL 0x054 | |
134 | ||
135 | #define ACPIBASE 0x040 | |
136 | #define ACPIBASE_SMI_OFF 0x030 | |
137 | #define ACPICTRL 0x044 | |
138 | #define ACPICTRL_EN 0x080 | |
139 | ||
140 | #define SBREG_BAR 0x10 | |
141 | #define SBREG_SMBCTRL 0xc6000c | |
1da177e4 | 142 | |
636752bc | 143 | /* Host status bits for SMBPCISTS */ |
fe9ba3ec | 144 | #define SMBPCISTS_INTS BIT(3) |
636752bc | 145 | |
aeb8a3d1 | 146 | /* Control bits for SMBPCICTL */ |
fe9ba3ec | 147 | #define SMBPCICTL_INTDIS BIT(10) |
aeb8a3d1 | 148 | |
1da177e4 | 149 | /* Host configuration bits for SMBHSTCFG */ |
fe9ba3ec BT |
150 | #define SMBHSTCFG_HST_EN BIT(0) |
151 | #define SMBHSTCFG_SMB_SMI_EN BIT(1) | |
152 | #define SMBHSTCFG_I2C_EN BIT(2) | |
153 | #define SMBHSTCFG_SPD_WD BIT(4) | |
1da177e4 | 154 | |
94246930 | 155 | /* TCO configuration bits for TCOCTL */ |
fe9ba3ec | 156 | #define TCOCTL_EN BIT(8) |
94246930 | 157 | |
97d34ec1 | 158 | /* Auxiliary status register bits, ICH4+ only */ |
fe9ba3ec BT |
159 | #define SMBAUXSTS_CRCE BIT(0) |
160 | #define SMBAUXSTS_STCO BIT(1) | |
97d34ec1 | 161 | |
25985edc | 162 | /* Auxiliary control register bits, ICH4+ only */ |
fe9ba3ec BT |
163 | #define SMBAUXCTL_CRC BIT(0) |
164 | #define SMBAUXCTL_E32B BIT(1) | |
ca8b9e32 | 165 | |
1da177e4 | 166 | /* Other settings */ |
84c1af4c | 167 | #define MAX_RETRIES 400 |
1da177e4 LT |
168 | |
169 | /* I801 command constants */ | |
170 | #define I801_QUICK 0x00 | |
171 | #define I801_BYTE 0x04 | |
172 | #define I801_BYTE_DATA 0x08 | |
173 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 174 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 175 | #define I801_BLOCK_DATA 0x14 |
6342064c | 176 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
177 | |
178 | /* I801 Host Control register bits */ | |
fe9ba3ec BT |
179 | #define SMBHSTCNT_INTREN BIT(0) |
180 | #define SMBHSTCNT_KILL BIT(1) | |
181 | #define SMBHSTCNT_LAST_BYTE BIT(5) | |
182 | #define SMBHSTCNT_START BIT(6) | |
183 | #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ | |
1da177e4 | 184 | |
ca8b9e32 | 185 | /* I801 Hosts Status register bits */ |
fe9ba3ec BT |
186 | #define SMBHSTSTS_BYTE_DONE BIT(7) |
187 | #define SMBHSTSTS_INUSE_STS BIT(6) | |
188 | #define SMBHSTSTS_SMBALERT_STS BIT(5) | |
189 | #define SMBHSTSTS_FAILED BIT(4) | |
190 | #define SMBHSTSTS_BUS_ERR BIT(3) | |
191 | #define SMBHSTSTS_DEV_ERR BIT(2) | |
192 | #define SMBHSTSTS_INTR BIT(1) | |
193 | #define SMBHSTSTS_HOST_BUSY BIT(0) | |
1da177e4 | 194 | |
9786b1f1 | 195 | /* Host Notify Status register bits */ |
fe9ba3ec | 196 | #define SMBSLVSTS_HST_NTFY_STS BIT(0) |
7b0ed334 | 197 | |
9786b1f1 | 198 | /* Host Notify Command register bits */ |
fe9ba3ec | 199 | #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) |
7b0ed334 | 200 | |
70a1cc19 DK |
201 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
202 | SMBHSTSTS_DEV_ERR) | |
203 | ||
204 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
205 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 206 | |
a6e5e2be | 207 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
ce316110 | 208 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 |
cb09d943 | 209 | #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df |
34b57f40 | 210 | #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df |
ce316110 JD |
211 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 |
212 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 | 213 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
ce316110 JD |
214 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 |
215 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
216 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
217 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 | |
218 | #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c | |
34b57f40 | 219 | #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 |
ce316110 JD |
220 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 |
221 | #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 | |
9827f9eb | 222 | #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 |
ce316110 | 223 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 |
34b57f40 | 224 | #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 |
ce316110 | 225 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 |
b299de83 | 226 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 |
ce316110 JD |
227 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 |
228 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d | |
229 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e | |
230 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f | |
231 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 | |
afc65924 | 232 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 |
3eee1799 | 233 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 |
09a1de04 | 234 | #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 |
34b57f40 | 235 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 |
cdc5a311 AY |
236 | #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 |
237 | #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 | |
31158763 | 238 | #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 |
09a1de04 | 239 | #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 |
55fee8d7 | 240 | |
3ad7ea18 JD |
241 | struct i801_mux_config { |
242 | char *gpio_chip; | |
243 | unsigned values[3]; | |
244 | int n_values; | |
245 | unsigned classes[3]; | |
246 | unsigned gpios[2]; /* Relative to gpio_chip->base */ | |
247 | int n_gpios; | |
248 | }; | |
249 | ||
0cd96eb0 DW |
250 | struct i801_priv { |
251 | struct i2c_adapter adapter; | |
252 | unsigned long smba; | |
253 | unsigned char original_hstcfg; | |
22e94bd6 | 254 | unsigned char original_slvcmd; |
0cd96eb0 DW |
255 | struct pci_dev *pci_dev; |
256 | unsigned int features; | |
636752bc DK |
257 | |
258 | /* isr processing */ | |
259 | wait_queue_head_t waitq; | |
260 | u8 status; | |
d3ff6ce4 DK |
261 | |
262 | /* Command state used by isr for byte-by-byte block transactions */ | |
263 | u8 cmd; | |
264 | bool is_read; | |
265 | int count; | |
266 | int len; | |
267 | u8 *data; | |
3ad7ea18 | 268 | |
175c7080 | 269 | #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI |
3ad7ea18 | 270 | const struct i801_mux_config *mux_drvdata; |
3ad7ea18 JD |
271 | struct platform_device *mux_pdev; |
272 | #endif | |
94246930 | 273 | struct platform_device *tco_pdev; |
a7ae8195 MW |
274 | |
275 | /* | |
276 | * If set to true the host controller registers are reserved for | |
277 | * ACPI AML use. Protected by acpi_lock. | |
278 | */ | |
279 | bool acpi_reserved; | |
280 | struct mutex acpi_lock; | |
0cd96eb0 DW |
281 | }; |
282 | ||
f91fba62 BT |
283 | #define FEATURE_SMBUS_PEC BIT(0) |
284 | #define FEATURE_BLOCK_BUFFER BIT(1) | |
285 | #define FEATURE_BLOCK_PROC BIT(2) | |
286 | #define FEATURE_I2C_BLOCK_READ BIT(3) | |
287 | #define FEATURE_IRQ BIT(4) | |
288 | #define FEATURE_HOST_NOTIFY BIT(5) | |
e7198fbf | 289 | /* Not really a feature, but it's convenient to handle it as such */ |
f91fba62 BT |
290 | #define FEATURE_IDF BIT(15) |
291 | #define FEATURE_TCO BIT(16) | |
1da177e4 | 292 | |
adff687d JD |
293 | static const char *i801_feature_names[] = { |
294 | "SMBus PEC", | |
295 | "Block buffer", | |
296 | "Block process call", | |
297 | "I2C block read", | |
636752bc | 298 | "Interrupt", |
7b0ed334 | 299 | "SMBus Host Notify", |
adff687d JD |
300 | }; |
301 | ||
302 | static unsigned int disable_features; | |
303 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
53229345 JD |
304 | MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" |
305 | "\t\t 0x01 disable SMBus PEC\n" | |
306 | "\t\t 0x02 disable the block buffer\n" | |
307 | "\t\t 0x08 disable the I2C block read functionality\n" | |
7b0ed334 BT |
308 | "\t\t 0x10 don't use interrupts\n" |
309 | "\t\t 0x20 disable SMBus Host Notify "); | |
adff687d | 310 | |
cf898dc5 JD |
311 | /* Make sure the SMBus host is ready to start transmitting. |
312 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 313 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 314 | { |
2b73809d | 315 | int status; |
1da177e4 | 316 | |
0cd96eb0 | 317 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 318 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 319 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
320 | return -EBUSY; |
321 | } | |
322 | ||
323 | status &= STATUS_FLAGS; | |
324 | if (status) { | |
0cd96eb0 | 325 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 326 | status); |
0cd96eb0 DW |
327 | outb_p(status, SMBHSTSTS(priv)); |
328 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 329 | if (status) { |
0cd96eb0 | 330 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
331 | "Failed clearing status flags (%02x)\n", |
332 | status); | |
97140342 | 333 | return -EBUSY; |
1da177e4 LT |
334 | } |
335 | } | |
336 | ||
97d34ec1 EW |
337 | /* |
338 | * Clear CRC status if needed. | |
339 | * During normal operation, i801_check_post() takes care | |
340 | * of it after every operation. We do it here only in case | |
341 | * the hardware was already in this state when the driver | |
342 | * started. | |
343 | */ | |
344 | if (priv->features & FEATURE_SMBUS_PEC) { | |
345 | status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; | |
346 | if (status) { | |
347 | dev_dbg(&priv->pci_dev->dev, | |
348 | "Clearing aux status flags (%02x)\n", status); | |
349 | outb_p(status, SMBAUXSTS(priv)); | |
350 | status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; | |
351 | if (status) { | |
352 | dev_err(&priv->pci_dev->dev, | |
353 | "Failed clearing aux status flags (%02x)\n", | |
354 | status); | |
355 | return -EBUSY; | |
356 | } | |
357 | } | |
358 | } | |
359 | ||
cf898dc5 JD |
360 | return 0; |
361 | } | |
1da177e4 | 362 | |
6cad93c4 JD |
363 | /* |
364 | * Convert the status register to an error code, and clear it. | |
365 | * Note that status only contains the bits we want to clear, not the | |
366 | * actual register value. | |
367 | */ | |
368 | static int i801_check_post(struct i801_priv *priv, int status) | |
cf898dc5 JD |
369 | { |
370 | int result = 0; | |
1da177e4 | 371 | |
636752bc DK |
372 | /* |
373 | * If the SMBus is still busy, we give up | |
374 | * Note: This timeout condition only happens when using polling | |
375 | * transactions. For interrupt operation, NAK/timeout is indicated by | |
376 | * DEV_ERR. | |
377 | */ | |
6cad93c4 | 378 | if (unlikely(status < 0)) { |
0cd96eb0 | 379 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 380 | /* try to stop the current command */ |
0cd96eb0 DW |
381 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
382 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
383 | SMBHSTCNT(priv)); | |
84c1af4c | 384 | usleep_range(1000, 2000); |
0cd96eb0 DW |
385 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
386 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
387 | |
388 | /* Check if it worked */ | |
0cd96eb0 | 389 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
390 | if ((status & SMBHSTSTS_HOST_BUSY) || |
391 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 392 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 393 | "Failed terminating the transaction\n"); |
0cd96eb0 | 394 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 395 | return -ETIMEDOUT; |
1da177e4 LT |
396 | } |
397 | ||
2b73809d | 398 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 399 | result = -EIO; |
0cd96eb0 | 400 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
401 | } |
402 | if (status & SMBHSTSTS_DEV_ERR) { | |
97d34ec1 EW |
403 | /* |
404 | * This may be a PEC error, check and clear it. | |
405 | * | |
406 | * AUXSTS is handled differently from HSTSTS. | |
407 | * For HSTSTS, i801_isr() or i801_wait_intr() | |
408 | * has already cleared the error bits in hardware, | |
409 | * and we are passed a copy of the original value | |
410 | * in "status". | |
411 | * For AUXSTS, the hardware register is left | |
412 | * for us to handle here. | |
413 | * This is asymmetric, slightly iffy, but safe, | |
414 | * since all this code is serialized and the CRCE | |
415 | * bit is harmless as long as it's cleared before | |
416 | * the next operation. | |
417 | */ | |
418 | if ((priv->features & FEATURE_SMBUS_PEC) && | |
419 | (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { | |
420 | outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); | |
421 | result = -EBADMSG; | |
422 | dev_dbg(&priv->pci_dev->dev, "PEC error\n"); | |
423 | } else { | |
424 | result = -ENXIO; | |
425 | dev_dbg(&priv->pci_dev->dev, "No response\n"); | |
426 | } | |
1da177e4 | 427 | } |
2b73809d | 428 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 429 | result = -EAGAIN; |
0cd96eb0 | 430 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
431 | } |
432 | ||
6cad93c4 JD |
433 | /* Clear status flags except BYTE_DONE, to be cleared by caller */ |
434 | outb_p(status, SMBHSTSTS(priv)); | |
1da177e4 | 435 | |
1da177e4 LT |
436 | return result; |
437 | } | |
438 | ||
6cad93c4 JD |
439 | /* Wait for BUSY being cleared and either INTR or an error flag being set */ |
440 | static int i801_wait_intr(struct i801_priv *priv) | |
cf898dc5 | 441 | { |
cf898dc5 | 442 | int timeout = 0; |
6cad93c4 | 443 | int status; |
cf898dc5 JD |
444 | |
445 | /* We will always wait for a fraction of a second! */ | |
446 | do { | |
84c1af4c | 447 | usleep_range(250, 500); |
0cd96eb0 | 448 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
449 | } while (((status & SMBHSTSTS_HOST_BUSY) || |
450 | !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && | |
451 | (timeout++ < MAX_RETRIES)); | |
cf898dc5 | 452 | |
6cad93c4 JD |
453 | if (timeout > MAX_RETRIES) { |
454 | dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); | |
455 | return -ETIMEDOUT; | |
456 | } | |
457 | return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); | |
cf898dc5 JD |
458 | } |
459 | ||
6cad93c4 JD |
460 | /* Wait for either BYTE_DONE or an error flag being set */ |
461 | static int i801_wait_byte_done(struct i801_priv *priv) | |
ca8b9e32 OR |
462 | { |
463 | int timeout = 0; | |
2b73809d | 464 | int status; |
ca8b9e32 | 465 | |
6cad93c4 | 466 | /* We will always wait for a fraction of a second! */ |
ca8b9e32 | 467 | do { |
84c1af4c | 468 | usleep_range(250, 500); |
0cd96eb0 | 469 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
470 | } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && |
471 | (timeout++ < MAX_RETRIES)); | |
472 | ||
473 | if (timeout > MAX_RETRIES) { | |
474 | dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); | |
475 | return -ETIMEDOUT; | |
476 | } | |
477 | return status & STATUS_ERROR_FLAGS; | |
478 | } | |
479 | ||
480 | static int i801_transaction(struct i801_priv *priv, int xact) | |
481 | { | |
482 | int status; | |
483 | int result; | |
b3b8df97 | 484 | const struct i2c_adapter *adap = &priv->adapter; |
ca8b9e32 | 485 | |
6cad93c4 JD |
486 | result = i801_check_pre(priv); |
487 | if (result < 0) | |
488 | return result; | |
4ccc28f7 | 489 | |
636752bc DK |
490 | if (priv->features & FEATURE_IRQ) { |
491 | outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, | |
492 | SMBHSTCNT(priv)); | |
b3b8df97 JD |
493 | result = wait_event_timeout(priv->waitq, |
494 | (status = priv->status), | |
495 | adap->timeout); | |
496 | if (!result) { | |
497 | status = -ETIMEDOUT; | |
498 | dev_warn(&priv->pci_dev->dev, | |
499 | "Timeout waiting for interrupt!\n"); | |
500 | } | |
636752bc DK |
501 | priv->status = 0; |
502 | return i801_check_post(priv, status); | |
503 | } | |
504 | ||
6cad93c4 JD |
505 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
506 | * SMBSCMD are passed in xact */ | |
507 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
508 | ||
509 | status = i801_wait_intr(priv); | |
510 | return i801_check_post(priv, status); | |
ca8b9e32 OR |
511 | } |
512 | ||
0cd96eb0 DW |
513 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
514 | union i2c_smbus_data *data, | |
7edcb9ab OR |
515 | char read_write, int hwpec) |
516 | { | |
517 | int i, len; | |
97140342 | 518 | int status; |
7edcb9ab | 519 | |
0cd96eb0 | 520 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
521 | |
522 | /* Use 32-byte buffer to process this transaction */ | |
523 | if (read_write == I2C_SMBUS_WRITE) { | |
524 | len = data->block[0]; | |
0cd96eb0 | 525 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 526 | for (i = 0; i < len; i++) |
0cd96eb0 | 527 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
528 | } |
529 | ||
37af8711 | 530 | status = i801_transaction(priv, I801_BLOCK_DATA | |
edbeea63 | 531 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
532 | if (status) |
533 | return status; | |
7edcb9ab OR |
534 | |
535 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 536 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 537 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 538 | return -EPROTO; |
7edcb9ab OR |
539 | |
540 | data->block[0] = len; | |
541 | for (i = 0; i < len; i++) | |
0cd96eb0 | 542 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
543 | } |
544 | return 0; | |
545 | } | |
546 | ||
d3ff6ce4 DK |
547 | static void i801_isr_byte_done(struct i801_priv *priv) |
548 | { | |
549 | if (priv->is_read) { | |
550 | /* For SMBus block reads, length is received with first byte */ | |
551 | if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && | |
552 | (priv->count == 0)) { | |
553 | priv->len = inb_p(SMBHSTDAT0(priv)); | |
554 | if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { | |
555 | dev_err(&priv->pci_dev->dev, | |
556 | "Illegal SMBus block read size %d\n", | |
557 | priv->len); | |
558 | /* FIXME: Recover */ | |
559 | priv->len = I2C_SMBUS_BLOCK_MAX; | |
560 | } else { | |
561 | dev_dbg(&priv->pci_dev->dev, | |
562 | "SMBus block read size is %d\n", | |
563 | priv->len); | |
564 | } | |
565 | priv->data[-1] = priv->len; | |
566 | } | |
567 | ||
568 | /* Read next byte */ | |
569 | if (priv->count < priv->len) | |
570 | priv->data[priv->count++] = inb(SMBBLKDAT(priv)); | |
571 | else | |
572 | dev_dbg(&priv->pci_dev->dev, | |
573 | "Discarding extra byte on block read\n"); | |
574 | ||
575 | /* Set LAST_BYTE for last byte of read transaction */ | |
576 | if (priv->count == priv->len - 1) | |
577 | outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, | |
578 | SMBHSTCNT(priv)); | |
579 | } else if (priv->count < priv->len - 1) { | |
580 | /* Write next byte, except for IRQ after last byte */ | |
581 | outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); | |
582 | } | |
583 | ||
584 | /* Clear BYTE_DONE to continue with next byte */ | |
585 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); | |
586 | } | |
587 | ||
7b0ed334 BT |
588 | static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) |
589 | { | |
590 | unsigned short addr; | |
7b0ed334 BT |
591 | |
592 | addr = inb_p(SMBNTFDADD(priv)) >> 1; | |
7b0ed334 | 593 | |
c912a25a BT |
594 | /* |
595 | * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) | |
4d5538f5 BT |
596 | * always returns 0. Our current implementation doesn't provide |
597 | * data, so we just ignore it. | |
c912a25a | 598 | */ |
4d5538f5 | 599 | i2c_handle_smbus_host_notify(&priv->adapter, addr); |
7b0ed334 BT |
600 | |
601 | /* clear Host Notify bit and return */ | |
602 | outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); | |
603 | return IRQ_HANDLED; | |
604 | } | |
605 | ||
636752bc | 606 | /* |
7b0ed334 | 607 | * There are three kinds of interrupts: |
d3ff6ce4 DK |
608 | * |
609 | * 1) i801 signals transaction completion with one of these interrupts: | |
610 | * INTR - Success | |
611 | * DEV_ERR - Invalid command, NAK or communication timeout | |
612 | * BUS_ERR - SMI# transaction collision | |
613 | * FAILED - transaction was canceled due to a KILL request | |
614 | * When any of these occur, update ->status and wake up the waitq. | |
615 | * ->status must be cleared before kicking off the next transaction. | |
616 | * | |
617 | * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt | |
618 | * occurs for each byte of a byte-by-byte to prepare the next byte. | |
7b0ed334 BT |
619 | * |
620 | * 3) Host Notify interrupts | |
636752bc DK |
621 | */ |
622 | static irqreturn_t i801_isr(int irq, void *dev_id) | |
623 | { | |
624 | struct i801_priv *priv = dev_id; | |
625 | u16 pcists; | |
626 | u8 status; | |
627 | ||
628 | /* Confirm this is our interrupt */ | |
629 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
630 | if (!(pcists & SMBPCISTS_INTS)) | |
631 | return IRQ_NONE; | |
632 | ||
7b0ed334 BT |
633 | if (priv->features & FEATURE_HOST_NOTIFY) { |
634 | status = inb_p(SMBSLVSTS(priv)); | |
635 | if (status & SMBSLVSTS_HST_NTFY_STS) | |
636 | return i801_host_notify_isr(priv); | |
637 | } | |
638 | ||
636752bc | 639 | status = inb_p(SMBHSTSTS(priv)); |
d3ff6ce4 DK |
640 | if (status & SMBHSTSTS_BYTE_DONE) |
641 | i801_isr_byte_done(priv); | |
642 | ||
636752bc DK |
643 | /* |
644 | * Clear irq sources and report transaction result. | |
645 | * ->status must be cleared before the next transaction is started. | |
646 | */ | |
647 | status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; | |
648 | if (status) { | |
649 | outb_p(status, SMBHSTSTS(priv)); | |
a90bc5d9 | 650 | priv->status = status; |
636752bc DK |
651 | wake_up(&priv->waitq); |
652 | } | |
653 | ||
654 | return IRQ_HANDLED; | |
655 | } | |
656 | ||
efa3cb15 DK |
657 | /* |
658 | * For "byte-by-byte" block transactions: | |
659 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
660 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
661 | */ | |
0cd96eb0 DW |
662 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
663 | union i2c_smbus_data *data, | |
6342064c JD |
664 | char read_write, int command, |
665 | int hwpec) | |
1da177e4 LT |
666 | { |
667 | int i, len; | |
668 | int smbcmd; | |
2b73809d | 669 | int status; |
cf898dc5 | 670 | int result; |
b3b8df97 | 671 | const struct i2c_adapter *adap = &priv->adapter; |
cf898dc5 | 672 | |
0cd96eb0 | 673 | result = i801_check_pre(priv); |
cf898dc5 JD |
674 | if (result < 0) |
675 | return result; | |
1da177e4 | 676 | |
7edcb9ab | 677 | len = data->block[0]; |
1da177e4 LT |
678 | |
679 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
680 | outb_p(len, SMBHSTDAT0(priv)); |
681 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
682 | } |
683 | ||
efa3cb15 DK |
684 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
685 | read_write == I2C_SMBUS_READ) | |
686 | smbcmd = I801_I2C_BLOCK_DATA; | |
687 | else | |
688 | smbcmd = I801_BLOCK_DATA; | |
689 | ||
d3ff6ce4 DK |
690 | if (priv->features & FEATURE_IRQ) { |
691 | priv->is_read = (read_write == I2C_SMBUS_READ); | |
692 | if (len == 1 && priv->is_read) | |
693 | smbcmd |= SMBHSTCNT_LAST_BYTE; | |
694 | priv->cmd = smbcmd | SMBHSTCNT_INTREN; | |
695 | priv->len = len; | |
696 | priv->count = 0; | |
697 | priv->data = &data->block[1]; | |
698 | ||
699 | outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
b3b8df97 JD |
700 | result = wait_event_timeout(priv->waitq, |
701 | (status = priv->status), | |
702 | adap->timeout); | |
703 | if (!result) { | |
704 | status = -ETIMEDOUT; | |
705 | dev_warn(&priv->pci_dev->dev, | |
706 | "Timeout waiting for interrupt!\n"); | |
707 | } | |
d3ff6ce4 DK |
708 | priv->status = 0; |
709 | return i801_check_post(priv, status); | |
710 | } | |
711 | ||
1da177e4 | 712 | for (i = 1; i <= len; i++) { |
efa3cb15 | 713 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 714 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
37af8711 | 715 | outb_p(smbcmd, SMBHSTCNT(priv)); |
1da177e4 | 716 | |
1da177e4 | 717 | if (i == 1) |
edbeea63 | 718 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 719 | SMBHSTCNT(priv)); |
1da177e4 | 720 | |
6cad93c4 JD |
721 | status = i801_wait_byte_done(priv); |
722 | if (status) | |
723 | goto exit; | |
1da177e4 | 724 | |
6342064c JD |
725 | if (i == 1 && read_write == I2C_SMBUS_READ |
726 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 727 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 728 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 729 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
730 | "Illegal SMBus block read size %d\n", |
731 | len); | |
732 | /* Recover */ | |
0cd96eb0 DW |
733 | while (inb_p(SMBHSTSTS(priv)) & |
734 | SMBHSTSTS_HOST_BUSY) | |
735 | outb_p(SMBHSTSTS_BYTE_DONE, | |
736 | SMBHSTSTS(priv)); | |
737 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 738 | return -EPROTO; |
cf898dc5 | 739 | } |
1da177e4 LT |
740 | data->block[0] = len; |
741 | } | |
742 | ||
743 | /* Retrieve/store value in SMBBLKDAT */ | |
744 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 745 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 746 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 747 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 748 | |
cf898dc5 | 749 | /* signals SMBBLKDAT ready */ |
6cad93c4 | 750 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); |
1da177e4 | 751 | } |
cf898dc5 | 752 | |
6cad93c4 JD |
753 | status = i801_wait_intr(priv); |
754 | exit: | |
755 | return i801_check_post(priv, status); | |
7edcb9ab | 756 | } |
1da177e4 | 757 | |
0cd96eb0 | 758 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 759 | { |
0cd96eb0 DW |
760 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
761 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 762 | return -EIO; |
7edcb9ab OR |
763 | return 0; |
764 | } | |
765 | ||
766 | /* Block transaction function */ | |
0cd96eb0 DW |
767 | static int i801_block_transaction(struct i801_priv *priv, |
768 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
769 | int command, int hwpec) |
770 | { | |
771 | int result = 0; | |
772 | unsigned char hostc; | |
773 | ||
774 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
775 | if (read_write == I2C_SMBUS_WRITE) { | |
776 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
777 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
778 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 779 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
780 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
781 | dev_err(&priv->pci_dev->dev, | |
6342064c | 782 | "I2C block read is unsupported!\n"); |
97140342 | 783 | return -EOPNOTSUPP; |
7edcb9ab OR |
784 | } |
785 | } | |
786 | ||
6342064c JD |
787 | if (read_write == I2C_SMBUS_WRITE |
788 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
789 | if (data->block[0] < 1) |
790 | data->block[0] = 1; | |
791 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
792 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
793 | } else { | |
6342064c | 794 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
795 | } |
796 | ||
c074c39d JD |
797 | /* Experience has shown that the block buffer can only be used for |
798 | SMBus (not I2C) block transactions, even though the datasheet | |
799 | doesn't mention this limitation. */ | |
0cd96eb0 | 800 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 801 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
802 | && i801_set_block_buffer_mode(priv) == 0) |
803 | result = i801_block_transaction_by_block(priv, data, | |
804 | read_write, hwpec); | |
7edcb9ab | 805 | else |
0cd96eb0 DW |
806 | result = i801_block_transaction_byte_by_byte(priv, data, |
807 | read_write, | |
6342064c | 808 | command, hwpec); |
7edcb9ab | 809 | |
6342064c JD |
810 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
811 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 812 | /* restore saved configuration register value */ |
0cd96eb0 | 813 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
814 | } |
815 | return result; | |
816 | } | |
817 | ||
97140342 | 818 | /* Return negative errno on error. */ |
3fb21c64 | 819 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 820 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 821 | int size, union i2c_smbus_data *data) |
1da177e4 | 822 | { |
e8aac4a9 | 823 | int hwpec; |
1da177e4 | 824 | int block = 0; |
a7401ca5 | 825 | int ret = 0, xact = 0; |
0cd96eb0 | 826 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 827 | |
a7ae8195 MW |
828 | mutex_lock(&priv->acpi_lock); |
829 | if (priv->acpi_reserved) { | |
830 | mutex_unlock(&priv->acpi_lock); | |
831 | return -EBUSY; | |
832 | } | |
833 | ||
a7401ca5 JN |
834 | pm_runtime_get_sync(&priv->pci_dev->dev); |
835 | ||
0cd96eb0 | 836 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
837 | && size != I2C_SMBUS_QUICK |
838 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
839 | |
840 | switch (size) { | |
841 | case I2C_SMBUS_QUICK: | |
842 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 843 | SMBHSTADD(priv)); |
1da177e4 LT |
844 | xact = I801_QUICK; |
845 | break; | |
846 | case I2C_SMBUS_BYTE: | |
847 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 848 | SMBHSTADD(priv)); |
1da177e4 | 849 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 850 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
851 | xact = I801_BYTE; |
852 | break; | |
853 | case I2C_SMBUS_BYTE_DATA: | |
854 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
855 | SMBHSTADD(priv)); |
856 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 857 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 858 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
859 | xact = I801_BYTE_DATA; |
860 | break; | |
861 | case I2C_SMBUS_WORD_DATA: | |
862 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
863 | SMBHSTADD(priv)); |
864 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 865 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
866 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
867 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
868 | } |
869 | xact = I801_WORD_DATA; | |
870 | break; | |
871 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 872 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
873 | SMBHSTADD(priv)); |
874 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
875 | block = 1; |
876 | break; | |
6342064c | 877 | case I2C_SMBUS_I2C_BLOCK_DATA: |
ba9ad2af JD |
878 | /* |
879 | * NB: page 240 of ICH5 datasheet shows that the R/#W | |
880 | * bit should be cleared here, even when reading. | |
881 | * However if SPD Write Disable is set (Lynx Point and later), | |
882 | * the read will fail if we don't set the R/#W bit. | |
883 | */ | |
884 | outb_p(((addr & 0x7f) << 1) | | |
885 | ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? | |
886 | (read_write & 0x01) : 0), | |
887 | SMBHSTADD(priv)); | |
6342064c JD |
888 | if (read_write == I2C_SMBUS_READ) { |
889 | /* NB: page 240 of ICH5 datasheet also shows | |
890 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 891 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 892 | } else |
0cd96eb0 | 893 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
894 | block = 1; |
895 | break; | |
1da177e4 | 896 | default: |
0cd96eb0 DW |
897 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
898 | size); | |
a7401ca5 JN |
899 | ret = -EOPNOTSUPP; |
900 | goto out; | |
1da177e4 LT |
901 | } |
902 | ||
ca8b9e32 | 903 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 904 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 905 | else |
0cd96eb0 DW |
906 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
907 | SMBAUXCTL(priv)); | |
e8aac4a9 | 908 | |
3fb21c64 | 909 | if (block) |
0cd96eb0 DW |
910 | ret = i801_block_transaction(priv, data, read_write, size, |
911 | hwpec); | |
7edcb9ab | 912 | else |
37af8711 | 913 | ret = i801_transaction(priv, xact); |
1da177e4 | 914 | |
c79cfbac | 915 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
916 | time, so we forcibly disable it after every transaction. Turn off |
917 | E32B for the same reason. */ | |
a0921b6c | 918 | if (hwpec || block) |
0cd96eb0 DW |
919 | outb_p(inb_p(SMBAUXCTL(priv)) & |
920 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 921 | |
3fb21c64 | 922 | if (block) |
a7401ca5 | 923 | goto out; |
3fb21c64 | 924 | if (ret) |
a7401ca5 | 925 | goto out; |
1da177e4 | 926 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
a7401ca5 | 927 | goto out; |
1da177e4 LT |
928 | |
929 | switch (xact & 0x7f) { | |
930 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
931 | case I801_BYTE_DATA: | |
0cd96eb0 | 932 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
933 | break; |
934 | case I801_WORD_DATA: | |
0cd96eb0 DW |
935 | data->word = inb_p(SMBHSTDAT0(priv)) + |
936 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
937 | break; |
938 | } | |
a7401ca5 JN |
939 | |
940 | out: | |
941 | pm_runtime_mark_last_busy(&priv->pci_dev->dev); | |
942 | pm_runtime_put_autosuspend(&priv->pci_dev->dev); | |
a7ae8195 | 943 | mutex_unlock(&priv->acpi_lock); |
a7401ca5 | 944 | return ret; |
1da177e4 LT |
945 | } |
946 | ||
947 | ||
948 | static u32 i801_func(struct i2c_adapter *adapter) | |
949 | { | |
0cd96eb0 DW |
950 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
951 | ||
1da177e4 | 952 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
953 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
954 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
955 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
956 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
7b0ed334 BT |
957 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | |
958 | ((priv->features & FEATURE_HOST_NOTIFY) ? | |
959 | I2C_FUNC_SMBUS_HOST_NOTIFY : 0); | |
960 | } | |
961 | ||
4d5538f5 | 962 | static void i801_enable_host_notify(struct i2c_adapter *adapter) |
7b0ed334 BT |
963 | { |
964 | struct i801_priv *priv = i2c_get_adapdata(adapter); | |
965 | ||
966 | if (!(priv->features & FEATURE_HOST_NOTIFY)) | |
4d5538f5 | 967 | return; |
7b0ed334 | 968 | |
22e94bd6 BT |
969 | priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); |
970 | ||
971 | if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) | |
972 | outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, | |
973 | SMBSLVCMD(priv)); | |
974 | ||
7b0ed334 BT |
975 | /* clear Host Notify bit to allow a new notification */ |
976 | outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); | |
1da177e4 LT |
977 | } |
978 | ||
22e94bd6 BT |
979 | static void i801_disable_host_notify(struct i801_priv *priv) |
980 | { | |
981 | if (!(priv->features & FEATURE_HOST_NOTIFY)) | |
982 | return; | |
983 | ||
984 | outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); | |
985 | } | |
986 | ||
8f9082c5 | 987 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
988 | .smbus_xfer = i801_access, |
989 | .functionality = i801_func, | |
990 | }; | |
991 | ||
392debf1 | 992 | static const struct pci_device_id i801_ids[] = { |
1da177e4 LT |
993 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
994 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
995 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
996 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
997 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
998 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
999 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
1000 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
1001 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 1002 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 1003 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 1004 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 1005 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
1006 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
1007 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
1008 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
1009 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 1010 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
1011 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
1012 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
1013 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 1014 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 1015 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 1016 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
4a8f1ddd | 1017 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, |
c2db409c | 1018 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, |
a3fc0ff0 JR |
1019 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, |
1020 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, | |
1021 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, | |
1022 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, | |
f39901c1 | 1023 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, |
9827f9eb | 1024 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, |
b299de83 | 1025 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, |
afc65924 | 1026 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, |
1b31e9b7 | 1027 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, |
39e8e30e | 1028 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, |
3e27a844 | 1029 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, |
3eee1799 | 1030 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, |
cb09d943 | 1031 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, |
84d7f2eb | 1032 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, |
dd77f423 | 1033 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, |
cdc5a311 AY |
1034 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, |
1035 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, | |
31158763 | 1036 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, |
09a1de04 SP |
1037 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, |
1038 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, | |
1da177e4 LT |
1039 | { 0, } |
1040 | }; | |
1041 | ||
3fb21c64 | 1042 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 1043 | |
8eacfceb | 1044 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
1045 | static unsigned char apanel_addr; |
1046 | ||
1047 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
1048 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
1049 | { | |
1050 | ssize_t offset; | |
1051 | const unsigned char signature[] = "FJKEYINF"; | |
1052 | ||
1053 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
1054 | if (check_signature(bios + offset, signature, | |
1055 | sizeof(signature)-1)) | |
1056 | return bios + offset; | |
1057 | } | |
1058 | return NULL; | |
1059 | } | |
1060 | ||
1061 | static void __init input_apanel_init(void) | |
1062 | { | |
1063 | void __iomem *bios; | |
1064 | const void __iomem *p; | |
1065 | ||
1066 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
1067 | p = bios_signature(bios); | |
1068 | if (p) { | |
1069 | /* just use the first address */ | |
1070 | apanel_addr = readb(p + 8 + 3) >> 1; | |
1071 | } | |
1072 | iounmap(bios); | |
1073 | } | |
1561bfe5 | 1074 | |
fa5bfab7 HG |
1075 | struct dmi_onboard_device_info { |
1076 | const char *name; | |
1077 | u8 type; | |
1078 | unsigned short i2c_addr; | |
1079 | const char *i2c_type; | |
1080 | }; | |
1081 | ||
0b255e92 | 1082 | static const struct dmi_onboard_device_info dmi_devices[] = { |
fa5bfab7 HG |
1083 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, |
1084 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
1085 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
1086 | }; | |
1087 | ||
0b255e92 BP |
1088 | static void dmi_check_onboard_device(u8 type, const char *name, |
1089 | struct i2c_adapter *adap) | |
fa5bfab7 HG |
1090 | { |
1091 | int i; | |
1092 | struct i2c_board_info info; | |
1093 | ||
1094 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
1095 | /* & ~0x80, ignore enabled/disabled bit */ | |
1096 | if ((type & ~0x80) != dmi_devices[i].type) | |
1097 | continue; | |
faabd47f | 1098 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
1099 | continue; |
1100 | ||
1101 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
1102 | info.addr = dmi_devices[i].i2c_addr; | |
1103 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
1104 | i2c_new_device(adap, &info); | |
1105 | break; | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | /* We use our own function to check for onboard devices instead of | |
1110 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
1111 | in marked as disabled */ | |
0b255e92 | 1112 | static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) |
fa5bfab7 HG |
1113 | { |
1114 | int i, count; | |
1115 | ||
1116 | if (dm->type != 10) | |
1117 | return; | |
1118 | ||
1119 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
1120 | for (i = 0; i < count; i++) { | |
1121 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
1122 | const char *name = ((char *) dm) + dm->length; | |
1123 | u8 type = d[0]; | |
1124 | u8 s = d[1]; | |
1125 | ||
1126 | if (!s) | |
1127 | continue; | |
1128 | s--; | |
1129 | while (s > 0 && name[0]) { | |
1130 | name += strlen(name) + 1; | |
1131 | s--; | |
1132 | } | |
1133 | if (name[0] == 0) /* Bogus string reference */ | |
1134 | continue; | |
1135 | ||
1136 | dmi_check_onboard_device(type, name, adap); | |
1137 | } | |
1138 | } | |
fa5bfab7 | 1139 | |
e7198fbf | 1140 | /* Register optional slaves */ |
0b255e92 | 1141 | static void i801_probe_optional_slaves(struct i801_priv *priv) |
e7198fbf JD |
1142 | { |
1143 | /* Only register slaves on main SMBus channel */ | |
1144 | if (priv->features & FEATURE_IDF) | |
1145 | return; | |
1146 | ||
e7198fbf JD |
1147 | if (apanel_addr) { |
1148 | struct i2c_board_info info; | |
1149 | ||
1150 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
1151 | info.addr = apanel_addr; | |
1152 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
1153 | i2c_new_device(&priv->adapter, &info); | |
1154 | } | |
8eacfceb | 1155 | |
e7198fbf JD |
1156 | if (dmi_name_in_vendors("FUJITSU")) |
1157 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 1158 | } |
8eacfceb JD |
1159 | #else |
1160 | static void __init input_apanel_init(void) {} | |
0b255e92 | 1161 | static void i801_probe_optional_slaves(struct i801_priv *priv) {} |
8eacfceb | 1162 | #endif /* CONFIG_X86 && CONFIG_DMI */ |
e7198fbf | 1163 | |
175c7080 | 1164 | #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI |
3ad7ea18 JD |
1165 | static struct i801_mux_config i801_mux_config_asus_z8_d12 = { |
1166 | .gpio_chip = "gpio_ich", | |
1167 | .values = { 0x02, 0x03 }, | |
1168 | .n_values = 2, | |
1169 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
1170 | .gpios = { 52, 53 }, | |
1171 | .n_gpios = 2, | |
1172 | }; | |
1173 | ||
1174 | static struct i801_mux_config i801_mux_config_asus_z8_d18 = { | |
1175 | .gpio_chip = "gpio_ich", | |
1176 | .values = { 0x02, 0x03, 0x01 }, | |
1177 | .n_values = 3, | |
1178 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
1179 | .gpios = { 52, 53 }, | |
1180 | .n_gpios = 2, | |
1181 | }; | |
1182 | ||
0b255e92 | 1183 | static const struct dmi_system_id mux_dmi_table[] = { |
3ad7ea18 JD |
1184 | { |
1185 | .matches = { | |
1186 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1187 | DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), | |
1188 | }, | |
1189 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1190 | }, | |
1191 | { | |
1192 | .matches = { | |
1193 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1194 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), | |
1195 | }, | |
1196 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1197 | }, | |
1198 | { | |
1199 | .matches = { | |
1200 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1201 | DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), | |
1202 | }, | |
1203 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1204 | }, | |
1205 | { | |
1206 | .matches = { | |
1207 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1208 | DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), | |
1209 | }, | |
1210 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1211 | }, | |
1212 | { | |
1213 | .matches = { | |
1214 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1215 | DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), | |
1216 | }, | |
1217 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1218 | }, | |
1219 | { | |
1220 | .matches = { | |
1221 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1222 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), | |
1223 | }, | |
1224 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1225 | }, | |
1226 | { | |
1227 | .matches = { | |
1228 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1229 | DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), | |
1230 | }, | |
1231 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1232 | }, | |
1233 | { | |
1234 | .matches = { | |
1235 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1236 | DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), | |
1237 | }, | |
1238 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1239 | }, | |
1240 | { | |
1241 | .matches = { | |
1242 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1243 | DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), | |
1244 | }, | |
1245 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1246 | }, | |
1247 | { } | |
1248 | }; | |
1249 | ||
3ad7ea18 | 1250 | /* Setup multiplexing if needed */ |
0b255e92 | 1251 | static int i801_add_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1252 | { |
1253 | struct device *dev = &priv->adapter.dev; | |
1254 | const struct i801_mux_config *mux_config; | |
3ad7ea18 | 1255 | struct i2c_mux_gpio_platform_data gpio_data; |
f82b8626 | 1256 | int err; |
3ad7ea18 JD |
1257 | |
1258 | if (!priv->mux_drvdata) | |
1259 | return 0; | |
1260 | mux_config = priv->mux_drvdata; | |
1261 | ||
3ad7ea18 JD |
1262 | /* Prepare the platform data */ |
1263 | memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); | |
1264 | gpio_data.parent = priv->adapter.nr; | |
1265 | gpio_data.values = mux_config->values; | |
1266 | gpio_data.n_values = mux_config->n_values; | |
1267 | gpio_data.classes = mux_config->classes; | |
f82b8626 JD |
1268 | gpio_data.gpio_chip = mux_config->gpio_chip; |
1269 | gpio_data.gpios = mux_config->gpios; | |
3ad7ea18 JD |
1270 | gpio_data.n_gpios = mux_config->n_gpios; |
1271 | gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; | |
1272 | ||
1273 | /* Register the mux device */ | |
1274 | priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", | |
f82b8626 | 1275 | PLATFORM_DEVID_AUTO, &gpio_data, |
3ad7ea18 JD |
1276 | sizeof(struct i2c_mux_gpio_platform_data)); |
1277 | if (IS_ERR(priv->mux_pdev)) { | |
1278 | err = PTR_ERR(priv->mux_pdev); | |
1279 | priv->mux_pdev = NULL; | |
1280 | dev_err(dev, "Failed to register i2c-mux-gpio device\n"); | |
1281 | return err; | |
1282 | } | |
1283 | ||
1284 | return 0; | |
1285 | } | |
1286 | ||
0b255e92 | 1287 | static void i801_del_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1288 | { |
1289 | if (priv->mux_pdev) | |
1290 | platform_device_unregister(priv->mux_pdev); | |
1291 | } | |
1292 | ||
0b255e92 | 1293 | static unsigned int i801_get_adapter_class(struct i801_priv *priv) |
3ad7ea18 JD |
1294 | { |
1295 | const struct dmi_system_id *id; | |
1296 | const struct i801_mux_config *mux_config; | |
1297 | unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1298 | int i; | |
1299 | ||
1300 | id = dmi_first_match(mux_dmi_table); | |
1301 | if (id) { | |
28901f57 | 1302 | /* Remove branch classes from trunk */ |
3ad7ea18 JD |
1303 | mux_config = id->driver_data; |
1304 | for (i = 0; i < mux_config->n_values; i++) | |
1305 | class &= ~mux_config->classes[i]; | |
1306 | ||
1307 | /* Remember for later */ | |
1308 | priv->mux_drvdata = mux_config; | |
1309 | } | |
1310 | ||
1311 | return class; | |
1312 | } | |
1313 | #else | |
1314 | static inline int i801_add_mux(struct i801_priv *priv) { return 0; } | |
1315 | static inline void i801_del_mux(struct i801_priv *priv) { } | |
1316 | ||
1317 | static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) | |
1318 | { | |
1319 | return I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1320 | } | |
1321 | #endif | |
1322 | ||
94246930 MW |
1323 | static const struct itco_wdt_platform_data tco_platform_data = { |
1324 | .name = "Intel PCH", | |
1325 | .version = 4, | |
1326 | }; | |
1327 | ||
1328 | static DEFINE_SPINLOCK(p2sb_spinlock); | |
1329 | ||
1330 | static void i801_add_tco(struct i801_priv *priv) | |
1331 | { | |
1332 | struct pci_dev *pci_dev = priv->pci_dev; | |
1333 | struct resource tco_res[3], *res; | |
1334 | struct platform_device *pdev; | |
1335 | unsigned int devfn; | |
1336 | u32 tco_base, tco_ctl; | |
1337 | u32 base_addr, ctrl_val; | |
1338 | u64 base64_addr; | |
bfd4473b | 1339 | u8 hidden; |
94246930 MW |
1340 | |
1341 | if (!(priv->features & FEATURE_TCO)) | |
1342 | return; | |
1343 | ||
1344 | pci_read_config_dword(pci_dev, TCOBASE, &tco_base); | |
1345 | pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); | |
1346 | if (!(tco_ctl & TCOCTL_EN)) | |
1347 | return; | |
1348 | ||
1349 | memset(tco_res, 0, sizeof(tco_res)); | |
1350 | ||
1351 | res = &tco_res[ICH_RES_IO_TCO]; | |
1352 | res->start = tco_base & ~1; | |
1353 | res->end = res->start + 32 - 1; | |
1354 | res->flags = IORESOURCE_IO; | |
1355 | ||
1356 | /* | |
1357 | * Power Management registers. | |
1358 | */ | |
1359 | devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); | |
1360 | pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); | |
1361 | ||
1362 | res = &tco_res[ICH_RES_IO_SMI]; | |
1363 | res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; | |
1364 | res->end = res->start + 3; | |
1365 | res->flags = IORESOURCE_IO; | |
1366 | ||
1367 | /* | |
1368 | * Enable the ACPI I/O space. | |
1369 | */ | |
1370 | pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); | |
1371 | ctrl_val |= ACPICTRL_EN; | |
1372 | pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); | |
1373 | ||
1374 | /* | |
1375 | * We must access the NO_REBOOT bit over the Primary to Sideband | |
1376 | * bridge (P2SB). The BIOS prevents the P2SB device from being | |
1377 | * enumerated by the PCI subsystem, so we need to unhide/hide it | |
1378 | * to lookup the P2SB BAR. | |
1379 | */ | |
1380 | spin_lock(&p2sb_spinlock); | |
1381 | ||
1382 | devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); | |
1383 | ||
bfd4473b QZ |
1384 | /* Unhide the P2SB device, if it is hidden */ |
1385 | pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); | |
1386 | if (hidden) | |
1387 | pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); | |
94246930 MW |
1388 | |
1389 | pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); | |
1390 | base64_addr = base_addr & 0xfffffff0; | |
1391 | ||
1392 | pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); | |
1393 | base64_addr |= (u64)base_addr << 32; | |
1394 | ||
bfd4473b QZ |
1395 | /* Hide the P2SB device, if it was hidden before */ |
1396 | if (hidden) | |
1397 | pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); | |
94246930 MW |
1398 | spin_unlock(&p2sb_spinlock); |
1399 | ||
1400 | res = &tco_res[ICH_RES_MEM_OFF]; | |
1401 | res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; | |
1402 | res->end = res->start + 3; | |
1403 | res->flags = IORESOURCE_MEM; | |
1404 | ||
1405 | pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, | |
1406 | tco_res, 3, &tco_platform_data, | |
1407 | sizeof(tco_platform_data)); | |
1408 | if (IS_ERR(pdev)) { | |
1409 | dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); | |
1410 | return; | |
1411 | } | |
1412 | ||
1413 | priv->tco_pdev = pdev; | |
1414 | } | |
1415 | ||
a7ae8195 MW |
1416 | #ifdef CONFIG_ACPI |
1417 | static acpi_status | |
1418 | i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, | |
1419 | u64 *value, void *handler_context, void *region_context) | |
1420 | { | |
1421 | struct i801_priv *priv = handler_context; | |
1422 | struct pci_dev *pdev = priv->pci_dev; | |
1423 | acpi_status status; | |
1424 | ||
1425 | /* | |
1426 | * Once BIOS AML code touches the OpRegion we warn and inhibit any | |
1427 | * further access from the driver itself. This device is now owned | |
1428 | * by the system firmware. | |
1429 | */ | |
1430 | mutex_lock(&priv->acpi_lock); | |
1431 | ||
1432 | if (!priv->acpi_reserved) { | |
1433 | priv->acpi_reserved = true; | |
1434 | ||
1435 | dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); | |
1436 | dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); | |
1437 | ||
1438 | /* | |
1439 | * BIOS is accessing the host controller so prevent it from | |
1440 | * suspending automatically from now on. | |
1441 | */ | |
1442 | pm_runtime_get_sync(&pdev->dev); | |
1443 | } | |
1444 | ||
1445 | if ((function & ACPI_IO_MASK) == ACPI_READ) | |
1446 | status = acpi_os_read_port(address, (u32 *)value, bits); | |
1447 | else | |
1448 | status = acpi_os_write_port(address, (u32)*value, bits); | |
1449 | ||
1450 | mutex_unlock(&priv->acpi_lock); | |
1451 | ||
1452 | return status; | |
1453 | } | |
1454 | ||
1455 | static int i801_acpi_probe(struct i801_priv *priv) | |
1456 | { | |
1457 | struct acpi_device *adev; | |
1458 | acpi_status status; | |
1459 | ||
1460 | adev = ACPI_COMPANION(&priv->pci_dev->dev); | |
1461 | if (adev) { | |
1462 | status = acpi_install_address_space_handler(adev->handle, | |
1463 | ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, | |
1464 | NULL, priv); | |
1465 | if (ACPI_SUCCESS(status)) | |
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); | |
1470 | } | |
1471 | ||
1472 | static void i801_acpi_remove(struct i801_priv *priv) | |
1473 | { | |
1474 | struct acpi_device *adev; | |
1475 | ||
1476 | adev = ACPI_COMPANION(&priv->pci_dev->dev); | |
1477 | if (!adev) | |
1478 | return; | |
1479 | ||
1480 | acpi_remove_address_space_handler(adev->handle, | |
1481 | ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); | |
1482 | ||
1483 | mutex_lock(&priv->acpi_lock); | |
1484 | if (priv->acpi_reserved) | |
1485 | pm_runtime_put(&priv->pci_dev->dev); | |
1486 | mutex_unlock(&priv->acpi_lock); | |
1487 | } | |
1488 | #else | |
1489 | static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } | |
1490 | static inline void i801_acpi_remove(struct i801_priv *priv) { } | |
1491 | #endif | |
1492 | ||
0b255e92 | 1493 | static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 1494 | { |
02dd7ae2 | 1495 | unsigned char temp; |
adff687d | 1496 | int err, i; |
0cd96eb0 DW |
1497 | struct i801_priv *priv; |
1498 | ||
1621c59d | 1499 | priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); |
0cd96eb0 DW |
1500 | if (!priv) |
1501 | return -ENOMEM; | |
1502 | ||
1503 | i2c_set_adapdata(&priv->adapter, priv); | |
1504 | priv->adapter.owner = THIS_MODULE; | |
3ad7ea18 | 1505 | priv->adapter.class = i801_get_adapter_class(priv); |
0cd96eb0 | 1506 | priv->adapter.algo = &smbus_algorithm; |
8eb5c87a DB |
1507 | priv->adapter.dev.parent = &dev->dev; |
1508 | ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); | |
1509 | priv->adapter.retries = 3; | |
a7ae8195 | 1510 | mutex_init(&priv->acpi_lock); |
1da177e4 | 1511 | |
0cd96eb0 | 1512 | priv->pci_dev = dev; |
250d1bd3 | 1513 | switch (dev->device) { |
94246930 MW |
1514 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: |
1515 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: | |
09a1de04 SP |
1516 | case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: |
1517 | case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: | |
1a1503c5 AY |
1518 | case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: |
1519 | case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: | |
cb09d943 | 1520 | case PCI_DEVICE_ID_INTEL_CDF_SMBUS: |
84d7f2eb | 1521 | case PCI_DEVICE_ID_INTEL_DNV_SMBUS: |
31158763 | 1522 | case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: |
94246930 MW |
1523 | priv->features |= FEATURE_I2C_BLOCK_READ; |
1524 | priv->features |= FEATURE_IRQ; | |
1525 | priv->features |= FEATURE_SMBUS_PEC; | |
1526 | priv->features |= FEATURE_BLOCK_BUFFER; | |
1f6dbb02 MW |
1527 | /* If we have ACPI based watchdog use that instead */ |
1528 | if (!acpi_has_watchdog()) | |
1529 | priv->features |= FEATURE_TCO; | |
7b0ed334 | 1530 | priv->features |= FEATURE_HOST_NOTIFY; |
94246930 MW |
1531 | break; |
1532 | ||
e7198fbf JD |
1533 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
1534 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
1535 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
a3fc0ff0 JR |
1536 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: |
1537 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: | |
1538 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: | |
e7198fbf JD |
1539 | priv->features |= FEATURE_IDF; |
1540 | /* fall through */ | |
e0e8398c | 1541 | default: |
0cd96eb0 | 1542 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6676a847 | 1543 | priv->features |= FEATURE_IRQ; |
6342064c JD |
1544 | /* fall through */ |
1545 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
1546 | priv->features |= FEATURE_SMBUS_PEC; |
1547 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
1548 | /* fall through */ |
1549 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
7b0ed334 BT |
1550 | priv->features |= FEATURE_HOST_NOTIFY; |
1551 | /* fall through */ | |
e0e8398c JD |
1552 | case PCI_DEVICE_ID_INTEL_82801BA_2: |
1553 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
1554 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 1555 | break; |
250d1bd3 | 1556 | } |
02dd7ae2 | 1557 | |
adff687d JD |
1558 | /* Disable features on user request */ |
1559 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 1560 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
1561 | dev_notice(&dev->dev, "%s disabled by user\n", |
1562 | i801_feature_names[i]); | |
1563 | } | |
0cd96eb0 | 1564 | priv->features &= ~disable_features; |
adff687d | 1565 | |
fef220da | 1566 | err = pcim_enable_device(dev); |
02dd7ae2 JD |
1567 | if (err) { |
1568 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
1569 | err); | |
fef220da | 1570 | return err; |
02dd7ae2 | 1571 | } |
fef220da | 1572 | pcim_pin_device(dev); |
02dd7ae2 JD |
1573 | |
1574 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
1575 | priv->smba = pci_resource_start(dev, SMBBAR); |
1576 | if (!priv->smba) { | |
9cbbf3dc JN |
1577 | dev_err(&dev->dev, |
1578 | "SMBus base address uninitialized, upgrade BIOS\n"); | |
fef220da | 1579 | return -ENODEV; |
02dd7ae2 JD |
1580 | } |
1581 | ||
a7ae8195 | 1582 | if (i801_acpi_probe(priv)) |
fef220da | 1583 | return -ENODEV; |
54fb4a05 | 1584 | |
fef220da JN |
1585 | err = pcim_iomap_regions(dev, 1 << SMBBAR, |
1586 | dev_driver_string(&dev->dev)); | |
02dd7ae2 | 1587 | if (err) { |
9cbbf3dc JN |
1588 | dev_err(&dev->dev, |
1589 | "Failed to request SMBus region 0x%lx-0x%Lx\n", | |
1590 | priv->smba, | |
598736c5 | 1591 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
a7ae8195 | 1592 | i801_acpi_remove(priv); |
fef220da | 1593 | return err; |
02dd7ae2 JD |
1594 | } |
1595 | ||
0cd96eb0 DW |
1596 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
1597 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
1598 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
1599 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
1600 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
1601 | temp |= SMBHSTCFG_HST_EN; | |
1602 | } | |
0cd96eb0 | 1603 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 | 1604 | |
636752bc | 1605 | if (temp & SMBHSTCFG_SMB_SMI_EN) { |
02dd7ae2 | 1606 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
636752bc DK |
1607 | /* Disable SMBus interrupt feature if SMBus using SMI# */ |
1608 | priv->features &= ~FEATURE_IRQ; | |
636752bc | 1609 | } |
ba9ad2af JD |
1610 | if (temp & SMBHSTCFG_SPD_WD) |
1611 | dev_info(&dev->dev, "SPD Write Disable is set\n"); | |
1da177e4 | 1612 | |
a0921b6c | 1613 | /* Clear special mode bits */ |
0cd96eb0 DW |
1614 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
1615 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
1616 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 1617 | |
b3b8df97 JD |
1618 | /* Default timeout in interrupt mode: 200 ms */ |
1619 | priv->adapter.timeout = HZ / 5; | |
1620 | ||
6e0c9507 HG |
1621 | if (dev->irq == IRQ_NOTCONNECTED) |
1622 | priv->features &= ~FEATURE_IRQ; | |
1623 | ||
aeb8a3d1 JD |
1624 | if (priv->features & FEATURE_IRQ) { |
1625 | u16 pcictl, pcists; | |
1626 | ||
1627 | /* Complain if an interrupt is already pending */ | |
1628 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
1629 | if (pcists & SMBPCISTS_INTS) | |
1630 | dev_warn(&dev->dev, "An interrupt is pending!\n"); | |
1631 | ||
1632 | /* Check if interrupts have been disabled */ | |
1633 | pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); | |
1634 | if (pcictl & SMBPCICTL_INTDIS) { | |
1635 | dev_info(&dev->dev, "Interrupts are disabled\n"); | |
1636 | priv->features &= ~FEATURE_IRQ; | |
1637 | } | |
1638 | } | |
1639 | ||
636752bc DK |
1640 | if (priv->features & FEATURE_IRQ) { |
1641 | init_waitqueue_head(&priv->waitq); | |
1642 | ||
1621c59d JN |
1643 | err = devm_request_irq(&dev->dev, dev->irq, i801_isr, |
1644 | IRQF_SHARED, | |
1645 | dev_driver_string(&dev->dev), priv); | |
636752bc DK |
1646 | if (err) { |
1647 | dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", | |
1648 | dev->irq, err); | |
ae944717 | 1649 | priv->features &= ~FEATURE_IRQ; |
636752bc DK |
1650 | } |
1651 | } | |
ae944717 JD |
1652 | dev_info(&dev->dev, "SMBus using %s\n", |
1653 | priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); | |
636752bc | 1654 | |
94246930 MW |
1655 | i801_add_tco(priv); |
1656 | ||
0cd96eb0 DW |
1657 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
1658 | "SMBus I801 adapter at %04lx", priv->smba); | |
1659 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 | 1660 | if (err) { |
a7ae8195 | 1661 | i801_acpi_remove(priv); |
fef220da | 1662 | return err; |
02dd7ae2 | 1663 | } |
1561bfe5 | 1664 | |
4d5538f5 | 1665 | i801_enable_host_notify(&priv->adapter); |
7b0ed334 | 1666 | |
e7198fbf | 1667 | i801_probe_optional_slaves(priv); |
3ad7ea18 JD |
1668 | /* We ignore errors - multiplexing is optional */ |
1669 | i801_add_mux(priv); | |
1561bfe5 | 1670 | |
0cd96eb0 | 1671 | pci_set_drvdata(dev, priv); |
636752bc | 1672 | |
a7401ca5 JN |
1673 | pm_runtime_set_autosuspend_delay(&dev->dev, 1000); |
1674 | pm_runtime_use_autosuspend(&dev->dev); | |
1675 | pm_runtime_put_autosuspend(&dev->dev); | |
1676 | pm_runtime_allow(&dev->dev); | |
1677 | ||
d6fcb3b9 | 1678 | return 0; |
1da177e4 LT |
1679 | } |
1680 | ||
0b255e92 | 1681 | static void i801_remove(struct pci_dev *dev) |
1da177e4 | 1682 | { |
0cd96eb0 DW |
1683 | struct i801_priv *priv = pci_get_drvdata(dev); |
1684 | ||
a7401ca5 JN |
1685 | pm_runtime_forbid(&dev->dev); |
1686 | pm_runtime_get_noresume(&dev->dev); | |
1687 | ||
22e94bd6 | 1688 | i801_disable_host_notify(priv); |
3ad7ea18 | 1689 | i801_del_mux(priv); |
0cd96eb0 | 1690 | i2c_del_adapter(&priv->adapter); |
a7ae8195 | 1691 | i801_acpi_remove(priv); |
0cd96eb0 | 1692 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
636752bc | 1693 | |
94246930 MW |
1694 | platform_device_unregister(priv->tco_pdev); |
1695 | ||
d6fcb3b9 DR |
1696 | /* |
1697 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
1698 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
1699 | */ | |
1da177e4 LT |
1700 | } |
1701 | ||
a5aaea37 | 1702 | #ifdef CONFIG_PM |
2ee73c48 | 1703 | static int i801_suspend(struct device *dev) |
a5aaea37 | 1704 | { |
2ee73c48 JN |
1705 | struct pci_dev *pci_dev = to_pci_dev(dev); |
1706 | struct i801_priv *priv = pci_get_drvdata(pci_dev); | |
0cd96eb0 | 1707 | |
2ee73c48 | 1708 | pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
1709 | return 0; |
1710 | } | |
1711 | ||
2ee73c48 | 1712 | static int i801_resume(struct device *dev) |
a5aaea37 | 1713 | { |
7b0ed334 BT |
1714 | struct pci_dev *pci_dev = to_pci_dev(dev); |
1715 | struct i801_priv *priv = pci_get_drvdata(pci_dev); | |
7b0ed334 | 1716 | |
4d5538f5 | 1717 | i801_enable_host_notify(&priv->adapter); |
7b0ed334 | 1718 | |
f85da3f5 | 1719 | return 0; |
a5aaea37 | 1720 | } |
a5aaea37 JD |
1721 | #endif |
1722 | ||
2ee73c48 JN |
1723 | static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend, |
1724 | i801_resume, NULL); | |
1725 | ||
1da177e4 LT |
1726 | static struct pci_driver i801_driver = { |
1727 | .name = "i801_smbus", | |
1728 | .id_table = i801_ids, | |
1729 | .probe = i801_probe, | |
0b255e92 | 1730 | .remove = i801_remove, |
2ee73c48 JN |
1731 | .driver = { |
1732 | .pm = &i801_pm_ops, | |
1733 | }, | |
1da177e4 LT |
1734 | }; |
1735 | ||
1736 | static int __init i2c_i801_init(void) | |
1737 | { | |
6aa1464d JD |
1738 | if (dmi_name_in_vendors("FUJITSU")) |
1739 | input_apanel_init(); | |
1da177e4 LT |
1740 | return pci_register_driver(&i801_driver); |
1741 | } | |
1742 | ||
1743 | static void __exit i2c_i801_exit(void) | |
1744 | { | |
1745 | pci_unregister_driver(&i801_driver); | |
1746 | } | |
1747 | ||
7c81c60f | 1748 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); |
1da177e4 LT |
1749 | MODULE_DESCRIPTION("I801 SMBus driver"); |
1750 | MODULE_LICENSE("GPL"); | |
1751 | ||
1752 | module_init(i2c_i801_init); | |
1753 | module_exit(i2c_i801_exit); |