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i2c-i801: Consolidate polling
[linux-block.git] / drivers / i2c / busses / i2c-i801.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
84c1af4c 5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
0cd96eb0
DW		 6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
1da177e4
LT		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/
23
24/*
ae7b0497
JD		 25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
cb04e95b 43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
d28dc711
GJ		 44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
cb04e95b 46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
662cda8a 47 6 Series (PCH) 0x1c22 32 hard yes yes yes
e30d9859 48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
55fee8d7
DW		 49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
662cda8a 52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
6e2a851e 53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
062737fb 54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
ae7b0497
JD		 55
56 Features supported by this driver:
57 Software PEC no
58 Hardware PEC yes
59 Block buffer yes
60 Block process call transaction no
6342064c 61 I2C block read transaction yes (doesn't use the block buffer)
55fee8d7 62 Slave mode no
ae7b0497
JD		 63
64 See the file Documentation/i2c/busses/i2c-i801 for details.
1da177e4
LT		 65*/
66
1da177e4
LT		 67#include <linux/module.h>
68#include <linux/pci.h>
69#include <linux/kernel.h>
70#include <linux/stddef.h>
71#include <linux/delay.h>
1da177e4
LT		 72#include <linux/ioport.h>
73#include <linux/init.h>
74#include <linux/i2c.h>
54fb4a05 75#include <linux/acpi.h>
1561bfe5 76#include <linux/io.h>
fa5bfab7 77#include <linux/dmi.h>
665a96b7 78#include <linux/slab.h>
1da177e4 79
1da177e4 80/* I801 SMBus address offsets */
0cd96eb0
DW		 81#define SMBHSTSTS(p) (0 + (p)->smba)
82#define SMBHSTCNT(p) (2 + (p)->smba)
83#define SMBHSTCMD(p) (3 + (p)->smba)
84#define SMBHSTADD(p) (4 + (p)->smba)
85#define SMBHSTDAT0(p) (5 + (p)->smba)
86#define SMBHSTDAT1(p) (6 + (p)->smba)
87#define SMBBLKDAT(p) (7 + (p)->smba)
88#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
89#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
90#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
1da177e4
LT		 91
92/* PCI Address Constants */
6dcc19df 93#define SMBBAR 4
1da177e4 94#define SMBHSTCFG 0x040
1da177e4
LT		 95
96/* Host configuration bits for SMBHSTCFG */
97#define SMBHSTCFG_HST_EN 1
98#define SMBHSTCFG_SMB_SMI_EN 2
99#define SMBHSTCFG_I2C_EN 4
100
25985edc 101/* Auxiliary control register bits, ICH4+ only */
ca8b9e32
OR		 102#define SMBAUXCTL_CRC 1
103#define SMBAUXCTL_E32B 2
104
1da177e4 105/* Other settings */
84c1af4c 106#define MAX_RETRIES 400
1da177e4
LT		 107
108/* I801 command constants */
109#define I801_QUICK 0x00
110#define I801_BYTE 0x04
111#define I801_BYTE_DATA 0x08
112#define I801_WORD_DATA 0x0C
ae7b0497 113#define I801_PROC_CALL 0x10 /* unimplemented */
1da177e4 114#define I801_BLOCK_DATA 0x14
6342064c 115#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
edbeea63
DK		 116
117/* I801 Host Control register bits */
118#define SMBHSTCNT_INTREN 0x01
119#define SMBHSTCNT_KILL 0x02
120#define SMBHSTCNT_LAST_BYTE 0x20
121#define SMBHSTCNT_START 0x40
122#define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
1da177e4 123
ca8b9e32
OR		 124/* I801 Hosts Status register bits */
125#define SMBHSTSTS_BYTE_DONE 0x80
126#define SMBHSTSTS_INUSE_STS 0x40
127#define SMBHSTSTS_SMBALERT_STS 0x20
128#define SMBHSTSTS_FAILED 0x10
129#define SMBHSTSTS_BUS_ERR 0x08
130#define SMBHSTSTS_DEV_ERR 0x04
131#define SMBHSTSTS_INTR 0x02
132#define SMBHSTSTS_HOST_BUSY 0x01
1da177e4 133
70a1cc19
DK		 134#define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
135 SMBHSTSTS_DEV_ERR)
136
137#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
138 STATUS_ERROR_FLAGS)
cf898dc5 139
a6e5e2be
JD		 140/* Older devices have their ID defined in <linux/pci_ids.h> */
141#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
142#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
55fee8d7
DW		 143/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
144#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
145#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
146#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
6e2a851e 147#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
a6e5e2be
JD		 148#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
149#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
062737fb 150#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
55fee8d7 151
0cd96eb0
DW		 152struct i801_priv {
153 struct i2c_adapter adapter;
154 unsigned long smba;
155 unsigned char original_hstcfg;
156 struct pci_dev *pci_dev;
157 unsigned int features;
158};
159
d6072f84 160static struct pci_driver i801_driver;
369f6f4a
JD		 161
162#define FEATURE_SMBUS_PEC (1 << 0)
163#define FEATURE_BLOCK_BUFFER (1 << 1)
164#define FEATURE_BLOCK_PROC (1 << 2)
165#define FEATURE_I2C_BLOCK_READ (1 << 3)
e7198fbf
JD		 166/* Not really a feature, but it's convenient to handle it as such */
167#define FEATURE_IDF (1 << 15)
1da177e4 168
adff687d
JD		 169static const char *i801_feature_names[] = {
170 "SMBus PEC",
171 "Block buffer",
172 "Block process call",
173 "I2C block read",
174};
175
176static unsigned int disable_features;
177module_param(disable_features, uint, S_IRUGO | S_IWUSR);
178MODULE_PARM_DESC(disable_features, "Disable selected driver features");
179
cf898dc5
JD		 180/* Make sure the SMBus host is ready to start transmitting.
181 Return 0 if it is, -EBUSY if it is not. */
0cd96eb0 182static int i801_check_pre(struct i801_priv *priv)
1da177e4 183{
2b73809d 184 int status;
1da177e4 185
0cd96eb0 186 status = inb_p(SMBHSTSTS(priv));
cf898dc5 187 if (status & SMBHSTSTS_HOST_BUSY) {
0cd96eb0 188 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
cf898dc5
JD		 189 return -EBUSY;
190 }
191
192 status &= STATUS_FLAGS;
193 if (status) {
0cd96eb0 194 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
2b73809d 195 status);
0cd96eb0
DW		 196 outb_p(status, SMBHSTSTS(priv));
197 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
cf898dc5 198 if (status) {
0cd96eb0 199 dev_err(&priv->pci_dev->dev,
cf898dc5
JD		 200 "Failed clearing status flags (%02x)\n",
201 status);
97140342 202 return -EBUSY;
1da177e4
LT		 203 }
204 }
205
cf898dc5
JD		 206 return 0;
207}
1da177e4 208
6cad93c4
JD		 209/*
210 * Convert the status register to an error code, and clear it.
211 * Note that status only contains the bits we want to clear, not the
212 * actual register value.
213 */
214static int i801_check_post(struct i801_priv *priv, int status)
cf898dc5
JD		 215{
216 int result = 0;
1da177e4
LT		 217
218 /* If the SMBus is still busy, we give up */
6cad93c4 219 if (unlikely(status < 0)) {
0cd96eb0 220 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
ca8b9e32 221 /* try to stop the current command */
0cd96eb0
DW		 222 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
223 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
224 SMBHSTCNT(priv));
84c1af4c 225 usleep_range(1000, 2000);
0cd96eb0
DW		 226 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
227 SMBHSTCNT(priv));
cf898dc5
JD		 228
229 /* Check if it worked */
0cd96eb0 230 status = inb_p(SMBHSTSTS(priv));
cf898dc5
JD		 231 if ((status & SMBHSTSTS_HOST_BUSY) ||
232 !(status & SMBHSTSTS_FAILED))
0cd96eb0 233 dev_err(&priv->pci_dev->dev,
cf898dc5 234 "Failed terminating the transaction\n");
0cd96eb0 235 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
cf898dc5 236 return -ETIMEDOUT;
1da177e4
LT		 237 }
238
2b73809d 239 if (status & SMBHSTSTS_FAILED) {
97140342 240 result = -EIO;
0cd96eb0 241 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
cf898dc5
JD		 242 }
243 if (status & SMBHSTSTS_DEV_ERR) {
244 result = -ENXIO;
0cd96eb0 245 dev_dbg(&priv->pci_dev->dev, "No response\n");
1da177e4 246 }
2b73809d 247 if (status & SMBHSTSTS_BUS_ERR) {
dcb5c923 248 result = -EAGAIN;
0cd96eb0 249 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
1da177e4
LT		 250 }
251
6cad93c4
JD		 252 /* Clear status flags except BYTE_DONE, to be cleared by caller */
253 outb_p(status, SMBHSTSTS(priv));
1da177e4 254
1da177e4
LT		 255 return result;
256}
257
6cad93c4
JD		 258/* Wait for BUSY being cleared and either INTR or an error flag being set */
259static int i801_wait_intr(struct i801_priv *priv)
cf898dc5 260{
cf898dc5 261 int timeout = 0;
6cad93c4 262 int status;
cf898dc5
JD		 263
264 /* We will always wait for a fraction of a second! */
265 do {
84c1af4c 266 usleep_range(250, 500);
0cd96eb0 267 status = inb_p(SMBHSTSTS(priv));
6cad93c4
JD		 268 } while (((status & SMBHSTSTS_HOST_BUSY) ||
269 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
270 (timeout++ < MAX_RETRIES));
cf898dc5 271
6cad93c4
JD		 272 if (timeout > MAX_RETRIES) {
273 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
274 return -ETIMEDOUT;
275 }
276 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
cf898dc5
JD		 277}
278
6cad93c4
JD		 279/* Wait for either BYTE_DONE or an error flag being set */
280static int i801_wait_byte_done(struct i801_priv *priv)
ca8b9e32
OR		 281{
282 int timeout = 0;
2b73809d 283 int status;
ca8b9e32 284
6cad93c4 285 /* We will always wait for a fraction of a second! */
ca8b9e32 286 do {
84c1af4c 287 usleep_range(250, 500);
0cd96eb0 288 status = inb_p(SMBHSTSTS(priv));
6cad93c4
JD		 289 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
290 (timeout++ < MAX_RETRIES));
291
292 if (timeout > MAX_RETRIES) {
293 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
294 return -ETIMEDOUT;
295 }
296 return status & STATUS_ERROR_FLAGS;
297}
298
299static int i801_transaction(struct i801_priv *priv, int xact)
300{
301 int status;
302 int result;
ca8b9e32 303
6cad93c4
JD		 304 result = i801_check_pre(priv);
305 if (result < 0)
306 return result;
4ccc28f7 307
6cad93c4
JD		 308 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
309 * SMBSCMD are passed in xact */
310 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
311
312 status = i801_wait_intr(priv);
313 return i801_check_post(priv, status);
ca8b9e32
OR		 314}
315
0cd96eb0
DW		 316static int i801_block_transaction_by_block(struct i801_priv *priv,
317 union i2c_smbus_data *data,
7edcb9ab
OR		 318 char read_write, int hwpec)
319{
320 int i, len;
97140342 321 int status;
7edcb9ab 322
0cd96eb0 323 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
7edcb9ab
OR		 324
325 /* Use 32-byte buffer to process this transaction */
326 if (read_write == I2C_SMBUS_WRITE) {
327 len = data->block[0];
0cd96eb0 328 outb_p(len, SMBHSTDAT0(priv));
7edcb9ab 329 for (i = 0; i < len; i++)
0cd96eb0 330 outb_p(data->block[i+1], SMBBLKDAT(priv));
7edcb9ab
OR		 331 }
332
37af8711 333 status = i801_transaction(priv, I801_BLOCK_DATA |
edbeea63 334 (hwpec ? SMBHSTCNT_PEC_EN : 0));
97140342
DB		 335 if (status)
336 return status;
7edcb9ab
OR		 337
338 if (read_write == I2C_SMBUS_READ) {
0cd96eb0 339 len = inb_p(SMBHSTDAT0(priv));
7edcb9ab 340 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
97140342 341 return -EPROTO;
7edcb9ab
OR		 342
343 data->block[0] = len;
344 for (i = 0; i < len; i++)
0cd96eb0 345 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
7edcb9ab
OR		 346 }
347 return 0;
348}
349
efa3cb15
DK		 350/*
351 * For "byte-by-byte" block transactions:
352 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
353 * I2C read uses cmd=I801_I2C_BLOCK_DATA
354 */
0cd96eb0
DW		 355static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
356 union i2c_smbus_data *data,
6342064c
JD		 357 char read_write, int command,
358 int hwpec)
1da177e4
LT		 359{
360 int i, len;
361 int smbcmd;
2b73809d 362 int status;
cf898dc5 363 int result;
cf898dc5 364
0cd96eb0 365 result = i801_check_pre(priv);
cf898dc5
JD		 366 if (result < 0)
367 return result;
1da177e4 368
7edcb9ab 369 len = data->block[0];
1da177e4
LT		 370
371 if (read_write == I2C_SMBUS_WRITE) {
0cd96eb0
DW		 372 outb_p(len, SMBHSTDAT0(priv));
373 outb_p(data->block[1], SMBBLKDAT(priv));
1da177e4
LT		 374 }
375
efa3cb15
DK		 376 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
377 read_write == I2C_SMBUS_READ)
378 smbcmd = I801_I2C_BLOCK_DATA;
379 else
380 smbcmd = I801_BLOCK_DATA;
381
1da177e4 382 for (i = 1; i <= len; i++) {
efa3cb15 383 if (i == len && read_write == I2C_SMBUS_READ)
edbeea63 384 smbcmd |= SMBHSTCNT_LAST_BYTE;
37af8711 385 outb_p(smbcmd, SMBHSTCNT(priv));
1da177e4 386
1da177e4 387 if (i == 1)
edbeea63 388 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
0cd96eb0 389 SMBHSTCNT(priv));
1da177e4 390
6cad93c4
JD		 391 status = i801_wait_byte_done(priv);
392 if (status)
393 goto exit;
1da177e4 394
6342064c
JD		 395 if (i == 1 && read_write == I2C_SMBUS_READ
396 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
0cd96eb0 397 len = inb_p(SMBHSTDAT0(priv));
cf898dc5 398 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
0cd96eb0 399 dev_err(&priv->pci_dev->dev,
cf898dc5
JD		 400 "Illegal SMBus block read size %d\n",
401 len);
402 /* Recover */
0cd96eb0
DW		 403 while (inb_p(SMBHSTSTS(priv)) &
404 SMBHSTSTS_HOST_BUSY)
405 outb_p(SMBHSTSTS_BYTE_DONE,
406 SMBHSTSTS(priv));
407 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
97140342 408 return -EPROTO;
cf898dc5 409 }
1da177e4
LT		 410 data->block[0] = len;
411 }
412
413 /* Retrieve/store value in SMBBLKDAT */
414 if (read_write == I2C_SMBUS_READ)
0cd96eb0 415 data->block[i] = inb_p(SMBBLKDAT(priv));
1da177e4 416 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
0cd96eb0 417 outb_p(data->block[i+1], SMBBLKDAT(priv));
1da177e4 418
cf898dc5 419 /* signals SMBBLKDAT ready */
6cad93c4 420 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
1da177e4 421 }
cf898dc5 422
6cad93c4
JD		 423 status = i801_wait_intr(priv);
424exit:
425 return i801_check_post(priv, status);
7edcb9ab 426}
1da177e4 427
0cd96eb0 428static int i801_set_block_buffer_mode(struct i801_priv *priv)
7edcb9ab 429{
0cd96eb0
DW		 430 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
431 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
97140342 432 return -EIO;
7edcb9ab
OR		 433 return 0;
434}
435
436/* Block transaction function */
0cd96eb0
DW		 437static int i801_block_transaction(struct i801_priv *priv,
438 union i2c_smbus_data *data, char read_write,
7edcb9ab
OR		 439 int command, int hwpec)
440{
441 int result = 0;
442 unsigned char hostc;
443
444 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
445 if (read_write == I2C_SMBUS_WRITE) {
446 /* set I2C_EN bit in configuration register */
0cd96eb0
DW		 447 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
448 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
7edcb9ab 449 hostc | SMBHSTCFG_I2C_EN);
0cd96eb0
DW		 450 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
451 dev_err(&priv->pci_dev->dev,
6342064c 452 "I2C block read is unsupported!\n");
97140342 453 return -EOPNOTSUPP;
7edcb9ab
OR		 454 }
455 }
456
6342064c
JD		 457 if (read_write == I2C_SMBUS_WRITE
458 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
7edcb9ab
OR		 459 if (data->block[0] < 1)
460 data->block[0] = 1;
461 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
462 data->block[0] = I2C_SMBUS_BLOCK_MAX;
463 } else {
6342064c 464 data->block[0] = 32; /* max for SMBus block reads */
7edcb9ab
OR		 465 }
466
c074c39d
JD		 467 /* Experience has shown that the block buffer can only be used for
468 SMBus (not I2C) block transactions, even though the datasheet
469 doesn't mention this limitation. */
0cd96eb0 470 if ((priv->features & FEATURE_BLOCK_BUFFER)
c074c39d 471 && command != I2C_SMBUS_I2C_BLOCK_DATA
0cd96eb0
DW		 472 && i801_set_block_buffer_mode(priv) == 0)
473 result = i801_block_transaction_by_block(priv, data,
474 read_write, hwpec);
7edcb9ab 475 else
0cd96eb0
DW		 476 result = i801_block_transaction_byte_by_byte(priv, data,
477 read_write,
6342064c 478 command, hwpec);
7edcb9ab 479
6342064c
JD		 480 if (command == I2C_SMBUS_I2C_BLOCK_DATA
481 && read_write == I2C_SMBUS_WRITE) {
1da177e4 482 /* restore saved configuration register value */
0cd96eb0 483 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
1da177e4
LT		 484 }
485 return result;
486}
487
97140342 488/* Return negative errno on error. */
3fb21c64 489static s32 i801_access(struct i2c_adapter *adap, u16 addr,
1da177e4 490 unsigned short flags, char read_write, u8 command,
3fb21c64 491 int size, union i2c_smbus_data *data)
1da177e4 492{
e8aac4a9 493 int hwpec;
1da177e4
LT		 494 int block = 0;
495 int ret, xact = 0;
0cd96eb0 496 struct i801_priv *priv = i2c_get_adapdata(adap);
1da177e4 497
0cd96eb0 498 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
e8aac4a9
JD		 499 && size != I2C_SMBUS_QUICK
500 && size != I2C_SMBUS_I2C_BLOCK_DATA;
1da177e4
LT		 501
502 switch (size) {
503 case I2C_SMBUS_QUICK:
504 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0 505 SMBHSTADD(priv));
1da177e4
LT		 506 xact = I801_QUICK;
507 break;
508 case I2C_SMBUS_BYTE:
509 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0 510 SMBHSTADD(priv));
1da177e4 511 if (read_write == I2C_SMBUS_WRITE)
0cd96eb0 512 outb_p(command, SMBHSTCMD(priv));
1da177e4
LT		 513 xact = I801_BYTE;
514 break;
515 case I2C_SMBUS_BYTE_DATA:
516 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0
DW		 517 SMBHSTADD(priv));
518 outb_p(command, SMBHSTCMD(priv));
1da177e4 519 if (read_write == I2C_SMBUS_WRITE)
0cd96eb0 520 outb_p(data->byte, SMBHSTDAT0(priv));
1da177e4
LT		 521 xact = I801_BYTE_DATA;
522 break;
523 case I2C_SMBUS_WORD_DATA:
524 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0
DW		 525 SMBHSTADD(priv));
526 outb_p(command, SMBHSTCMD(priv));
1da177e4 527 if (read_write == I2C_SMBUS_WRITE) {
0cd96eb0
DW		 528 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
529 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
1da177e4
LT		 530 }
531 xact = I801_WORD_DATA;
532 break;
533 case I2C_SMBUS_BLOCK_DATA:
1da177e4 534 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0
DW		 535 SMBHSTADD(priv));
536 outb_p(command, SMBHSTCMD(priv));
1da177e4
LT		 537 block = 1;
538 break;
6342064c
JD		 539 case I2C_SMBUS_I2C_BLOCK_DATA:
540 /* NB: page 240 of ICH5 datasheet shows that the R/#W
541 * bit should be cleared here, even when reading */
0cd96eb0 542 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
6342064c
JD		 543 if (read_write == I2C_SMBUS_READ) {
544 /* NB: page 240 of ICH5 datasheet also shows
545 * that DATA1 is the cmd field when reading */
0cd96eb0 546 outb_p(command, SMBHSTDAT1(priv));
6342064c 547 } else
0cd96eb0 548 outb_p(command, SMBHSTCMD(priv));
6342064c
JD		 549 block = 1;
550 break;
1da177e4 551 default:
0cd96eb0
DW		 552 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
553 size);
97140342 554 return -EOPNOTSUPP;
1da177e4
LT		 555 }
556
ca8b9e32 557 if (hwpec) /* enable/disable hardware PEC */
0cd96eb0 558 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
ca8b9e32 559 else
0cd96eb0
DW		 560 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
561 SMBAUXCTL(priv));
e8aac4a9 562
3fb21c64 563 if (block)
0cd96eb0
DW		 564 ret = i801_block_transaction(priv, data, read_write, size,
565 hwpec);
7edcb9ab 566 else
37af8711 567 ret = i801_transaction(priv, xact);
1da177e4 568
c79cfbac 569 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
7edcb9ab
OR		 570 time, so we forcibly disable it after every transaction. Turn off
571 E32B for the same reason. */
a0921b6c 572 if (hwpec || block)
0cd96eb0
DW		 573 outb_p(inb_p(SMBAUXCTL(priv)) &
574 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
c79cfbac 575
3fb21c64 576 if (block)
1da177e4 577 return ret;
3fb21c64 578 if (ret)
97140342 579 return ret;
1da177e4
LT		 580 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
581 return 0;
582
583 switch (xact & 0x7f) {
584 case I801_BYTE: /* Result put in SMBHSTDAT0 */
585 case I801_BYTE_DATA:
0cd96eb0 586 data->byte = inb_p(SMBHSTDAT0(priv));
1da177e4
LT		 587 break;
588 case I801_WORD_DATA:
0cd96eb0
DW		 589 data->word = inb_p(SMBHSTDAT0(priv)) +
590 (inb_p(SMBHSTDAT1(priv)) << 8);
1da177e4
LT		 591 break;
592 }
593 return 0;
594}
595
596
597static u32 i801_func(struct i2c_adapter *adapter)
598{
0cd96eb0
DW		 599 struct i801_priv *priv = i2c_get_adapdata(adapter);
600
1da177e4 601 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
369f6f4a
JD		 602 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
603 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
0cd96eb0
DW		 604 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
605 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
6342064c 606 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
1da177e4
LT		 607}
608
8f9082c5 609static const struct i2c_algorithm smbus_algorithm = {
1da177e4
LT		 610 .smbus_xfer = i801_access,
611 .functionality = i801_func,
612};
613
3527bd50 614static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
1da177e4
LT		 615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
b0a70b57 624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
8254fc4a 625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
adbc2a10 626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
cb04e95b 627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
d28dc711
GJ		 628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
cb04e95b
SH		 630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
e30d9859 632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
55fee8d7
DW		 633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
635 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
662cda8a 636 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
6e2a851e 637 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
062737fb 638 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1da177e4
LT		 639 { 0, }
640};
641
3fb21c64 642MODULE_DEVICE_TABLE(pci, i801_ids);
1da177e4 643
8eacfceb 644#if defined CONFIG_X86 && defined CONFIG_DMI
1561bfe5
JD		 645static unsigned char apanel_addr;
646
647/* Scan the system ROM for the signature "FJKEYINF" */
648static __init const void __iomem *bios_signature(const void __iomem *bios)
649{
650 ssize_t offset;
651 const unsigned char signature[] = "FJKEYINF";
652
653 for (offset = 0; offset < 0x10000; offset += 0x10) {
654 if (check_signature(bios + offset, signature,
655 sizeof(signature)-1))
656 return bios + offset;
657 }
658 return NULL;
659}
660
661static void __init input_apanel_init(void)
662{
663 void __iomem *bios;
664 const void __iomem *p;
665
666 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
667 p = bios_signature(bios);
668 if (p) {
669 /* just use the first address */
670 apanel_addr = readb(p + 8 + 3) >> 1;
671 }
672 iounmap(bios);
673}
1561bfe5 674
fa5bfab7
HG		 675struct dmi_onboard_device_info {
676 const char *name;
677 u8 type;
678 unsigned short i2c_addr;
679 const char *i2c_type;
680};
681
682static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
683 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
684 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
685 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
686};
687
688static void __devinit dmi_check_onboard_device(u8 type, const char *name,
689 struct i2c_adapter *adap)
690{
691 int i;
692 struct i2c_board_info info;
693
694 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
695 /* & ~0x80, ignore enabled/disabled bit */
696 if ((type & ~0x80) != dmi_devices[i].type)
697 continue;
faabd47f 698 if (strcasecmp(name, dmi_devices[i].name))
fa5bfab7
HG		 699 continue;
700
701 memset(&info, 0, sizeof(struct i2c_board_info));
702 info.addr = dmi_devices[i].i2c_addr;
703 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
704 i2c_new_device(adap, &info);
705 break;
706 }
707}
708
709/* We use our own function to check for onboard devices instead of
710 dmi_find_device() as some buggy BIOS's have the devices we are interested
711 in marked as disabled */
712static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
713 void *adap)
714{
715 int i, count;
716
717 if (dm->type != 10)
718 return;
719
720 count = (dm->length - sizeof(struct dmi_header)) / 2;
721 for (i = 0; i < count; i++) {
722 const u8 *d = (char *)(dm + 1) + (i * 2);
723 const char *name = ((char *) dm) + dm->length;
724 u8 type = d[0];
725 u8 s = d[1];
726
727 if (!s)
728 continue;
729 s--;
730 while (s > 0 && name[0]) {
731 name += strlen(name) + 1;
732 s--;
733 }
734 if (name[0] == 0) /* Bogus string reference */
735 continue;
736
737 dmi_check_onboard_device(type, name, adap);
738 }
739}
fa5bfab7 740
e7198fbf
JD		 741/* Register optional slaves */
742static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
743{
744 /* Only register slaves on main SMBus channel */
745 if (priv->features & FEATURE_IDF)
746 return;
747
e7198fbf
JD		 748 if (apanel_addr) {
749 struct i2c_board_info info;
750
751 memset(&info, 0, sizeof(struct i2c_board_info));
752 info.addr = apanel_addr;
753 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
754 i2c_new_device(&priv->adapter, &info);
755 }
8eacfceb 756
e7198fbf
JD		 757 if (dmi_name_in_vendors("FUJITSU"))
758 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
e7198fbf 759}
8eacfceb
JD		 760#else
761static void __init input_apanel_init(void) {}
762static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
763#endif /* CONFIG_X86 && CONFIG_DMI */
e7198fbf 764
3fb21c64
IM		 765static int __devinit i801_probe(struct pci_dev *dev,
766 const struct pci_device_id *id)
1da177e4 767{
02dd7ae2 768 unsigned char temp;
adff687d 769 int err, i;
0cd96eb0
DW		 770 struct i801_priv *priv;
771
772 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
773 if (!priv)
774 return -ENOMEM;
775
776 i2c_set_adapdata(&priv->adapter, priv);
777 priv->adapter.owner = THIS_MODULE;
778 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
779 priv->adapter.algo = &smbus_algorithm;
1da177e4 780
0cd96eb0 781 priv->pci_dev = dev;
250d1bd3 782 switch (dev->device) {
e7198fbf
JD		 783 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
784 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
785 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
786 priv->features |= FEATURE_IDF;
787 /* fall through */
e0e8398c 788 default:
0cd96eb0 789 priv->features |= FEATURE_I2C_BLOCK_READ;
6342064c
JD		 790 /* fall through */
791 case PCI_DEVICE_ID_INTEL_82801DB_3:
0cd96eb0
DW		 792 priv->features |= FEATURE_SMBUS_PEC;
793 priv->features |= FEATURE_BLOCK_BUFFER;
e0e8398c
JD		 794 /* fall through */
795 case PCI_DEVICE_ID_INTEL_82801CA_3:
796 case PCI_DEVICE_ID_INTEL_82801BA_2:
797 case PCI_DEVICE_ID_INTEL_82801AB_3:
798 case PCI_DEVICE_ID_INTEL_82801AA_3:
250d1bd3 799 break;
250d1bd3 800 }
02dd7ae2 801
adff687d
JD		 802 /* Disable features on user request */
803 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
0cd96eb0 804 if (priv->features & disable_features & (1 << i))
adff687d
JD		 805 dev_notice(&dev->dev, "%s disabled by user\n",
806 i801_feature_names[i]);
807 }
0cd96eb0 808 priv->features &= ~disable_features;
adff687d 809
02dd7ae2
JD		 810 err = pci_enable_device(dev);
811 if (err) {
812 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
813 err);
814 goto exit;
815 }
816
817 /* Determine the address of the SMBus area */
0cd96eb0
DW		 818 priv->smba = pci_resource_start(dev, SMBBAR);
819 if (!priv->smba) {
02dd7ae2
JD		 820 dev_err(&dev->dev, "SMBus base address uninitialized, "
821 "upgrade BIOS\n");
822 err = -ENODEV;
d6fcb3b9 823 goto exit;
02dd7ae2
JD		 824 }
825
54fb4a05 826 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
18669eab
JD		 827 if (err) {
828 err = -ENODEV;
54fb4a05 829 goto exit;
18669eab 830 }
54fb4a05 831
02dd7ae2
JD		 832 err = pci_request_region(dev, SMBBAR, i801_driver.name);
833 if (err) {
834 dev_err(&dev->dev, "Failed to request SMBus region "
0cd96eb0 835 "0x%lx-0x%Lx\n", priv->smba,
598736c5 836 (unsigned long long)pci_resource_end(dev, SMBBAR));
d6fcb3b9 837 goto exit;
02dd7ae2
JD		 838 }
839
0cd96eb0
DW		 840 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
841 priv->original_hstcfg = temp;
02dd7ae2
JD		 842 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
843 if (!(temp & SMBHSTCFG_HST_EN)) {
844 dev_info(&dev->dev, "Enabling SMBus device\n");
845 temp |= SMBHSTCFG_HST_EN;
846 }
0cd96eb0 847 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
02dd7ae2
JD		 848
849 if (temp & SMBHSTCFG_SMB_SMI_EN)
850 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
851 else
852 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
1da177e4 853
a0921b6c 854 /* Clear special mode bits */
0cd96eb0
DW		 855 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
856 outb_p(inb_p(SMBAUXCTL(priv)) &
857 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
a0921b6c 858
405ae7d3 859 /* set up the sysfs linkage to our parent device */
0cd96eb0 860 priv->adapter.dev.parent = &dev->dev;
1da177e4 861
7e2193a8 862 /* Retry up to 3 times on lost arbitration */
0cd96eb0 863 priv->adapter.retries = 3;
7e2193a8 864
0cd96eb0
DW		 865 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
866 "SMBus I801 adapter at %04lx", priv->smba);
867 err = i2c_add_adapter(&priv->adapter);
02dd7ae2
JD		 868 if (err) {
869 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
d6fcb3b9 870 goto exit_release;
02dd7ae2 871 }
1561bfe5 872
e7198fbf 873 i801_probe_optional_slaves(priv);
1561bfe5 874
0cd96eb0 875 pci_set_drvdata(dev, priv);
d6fcb3b9 876 return 0;
02dd7ae2 877
d6fcb3b9
DR		 878exit_release:
879 pci_release_region(dev, SMBBAR);
02dd7ae2 880exit:
0cd96eb0 881 kfree(priv);
02dd7ae2 882 return err;
1da177e4
LT		 883}
884
885static void __devexit i801_remove(struct pci_dev *dev)
886{
0cd96eb0
DW		 887 struct i801_priv *priv = pci_get_drvdata(dev);
888
889 i2c_del_adapter(&priv->adapter);
890 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
6dcc19df 891 pci_release_region(dev, SMBBAR);
0cd96eb0
DW		 892 pci_set_drvdata(dev, NULL);
893 kfree(priv);
d6fcb3b9
DR		 894 /*
895 * do not call pci_disable_device(dev) since it can cause hard hangs on
896 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
897 */
1da177e4
LT		 898}
899
a5aaea37
JD		 900#ifdef CONFIG_PM
901static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
902{
0cd96eb0
DW		 903 struct i801_priv *priv = pci_get_drvdata(dev);
904
a5aaea37 905 pci_save_state(dev);
0cd96eb0 906 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
a5aaea37
JD		 907 pci_set_power_state(dev, pci_choose_state(dev, mesg));
908 return 0;
909}
910
911static int i801_resume(struct pci_dev *dev)
912{
913 pci_set_power_state(dev, PCI_D0);
914 pci_restore_state(dev);
915 return pci_enable_device(dev);
916}
917#else
918#define i801_suspend NULL
919#define i801_resume NULL
920#endif
921
1da177e4
LT		 922static struct pci_driver i801_driver = {
923 .name = "i801_smbus",
924 .id_table = i801_ids,
925 .probe = i801_probe,
926 .remove = __devexit_p(i801_remove),
a5aaea37
JD		 927 .suspend = i801_suspend,
928 .resume = i801_resume,
1da177e4
LT		 929};
930
931static int __init i2c_i801_init(void)
932{
6aa1464d
JD		 933 if (dmi_name_in_vendors("FUJITSU"))
934 input_apanel_init();
1da177e4
LT		 935 return pci_register_driver(&i801_driver);
936}
937
938static void __exit i2c_i801_exit(void)
939{
940 pci_unregister_driver(&i801_driver);
941}
942
6342064c
JD		 943MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
944 "Jean Delvare <khali@linux-fr.org>");
1da177e4
LT		 945MODULE_DESCRIPTION("I801 SMBus driver");
946MODULE_LICENSE("GPL");
947
948module_init(i2c_i801_init);
949module_exit(i2c_i801_exit);
Linux 6.x block layer and io_uring tree(s)