Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
84c1af4c | 5 | Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | /* | |
ae7b0497 JD |
25 | Supports the following Intel I/O Controller Hubs (ICH): |
26 | ||
27 | I/O Block I2C | |
28 | region SMBus Block proc. block | |
29 | Chip name PCI ID size PEC buffer call read | |
30 | ---------------------------------------------------------------------- | |
31 | 82801AA (ICH) 0x2413 16 no no no no | |
32 | 82801AB (ICH0) 0x2423 16 no no no no | |
33 | 82801BA (ICH2) 0x2443 16 no no no no | |
34 | 82801CA (ICH3) 0x2483 32 soft no no no | |
35 | 82801DB (ICH4) 0x24c3 32 hard yes no no | |
36 | 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
37 | 6300ESB 0x25a4 32 hard yes yes yes | |
38 | 82801F (ICH6) 0x266a 32 hard yes yes yes | |
39 | 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
40 | 82801G (ICH7) 0x27da 32 hard yes yes yes | |
41 | 82801H (ICH8) 0x283e 32 hard yes yes yes | |
42 | 82801I (ICH9) 0x2930 32 hard yes yes yes | |
cb04e95b | 43 | EP80579 (Tolapai) 0x5032 32 hard yes yes yes |
d28dc711 GJ |
44 | ICH10 0x3a30 32 hard yes yes yes |
45 | ICH10 0x3a60 32 hard yes yes yes | |
cb04e95b | 46 | 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes |
662cda8a | 47 | 6 Series (PCH) 0x1c22 32 hard yes yes yes |
e30d9859 | 48 | Patsburg (PCH) 0x1d22 32 hard yes yes yes |
55fee8d7 DW |
49 | Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes |
50 | Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
51 | Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
662cda8a | 52 | DH89xxCC (PCH) 0x2330 32 hard yes yes yes |
6e2a851e | 53 | Panther Point (PCH) 0x1e22 32 hard yes yes yes |
062737fb | 54 | Lynx Point (PCH) 0x8c22 32 hard yes yes yes |
ae7b0497 JD |
55 | |
56 | Features supported by this driver: | |
57 | Software PEC no | |
58 | Hardware PEC yes | |
59 | Block buffer yes | |
60 | Block process call transaction no | |
6342064c | 61 | I2C block read transaction yes (doesn't use the block buffer) |
55fee8d7 | 62 | Slave mode no |
636752bc | 63 | Interrupt processing yes |
ae7b0497 JD |
64 | |
65 | See the file Documentation/i2c/busses/i2c-i801 for details. | |
1da177e4 LT |
66 | */ |
67 | ||
636752bc | 68 | #include <linux/interrupt.h> |
1da177e4 LT |
69 | #include <linux/module.h> |
70 | #include <linux/pci.h> | |
71 | #include <linux/kernel.h> | |
72 | #include <linux/stddef.h> | |
73 | #include <linux/delay.h> | |
1da177e4 LT |
74 | #include <linux/ioport.h> |
75 | #include <linux/init.h> | |
76 | #include <linux/i2c.h> | |
54fb4a05 | 77 | #include <linux/acpi.h> |
1561bfe5 | 78 | #include <linux/io.h> |
fa5bfab7 | 79 | #include <linux/dmi.h> |
665a96b7 | 80 | #include <linux/slab.h> |
636752bc | 81 | #include <linux/wait.h> |
1da177e4 | 82 | |
1da177e4 | 83 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
84 | #define SMBHSTSTS(p) (0 + (p)->smba) |
85 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
86 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
87 | #define SMBHSTADD(p) (4 + (p)->smba) | |
88 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
89 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
90 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
91 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
92 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
93 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
94 | |
95 | /* PCI Address Constants */ | |
6dcc19df | 96 | #define SMBBAR 4 |
636752bc | 97 | #define SMBPCISTS 0x006 |
1da177e4 | 98 | #define SMBHSTCFG 0x040 |
1da177e4 | 99 | |
636752bc DK |
100 | /* Host status bits for SMBPCISTS */ |
101 | #define SMBPCISTS_INTS 0x08 | |
102 | ||
1da177e4 LT |
103 | /* Host configuration bits for SMBHSTCFG */ |
104 | #define SMBHSTCFG_HST_EN 1 | |
105 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
106 | #define SMBHSTCFG_I2C_EN 4 | |
107 | ||
25985edc | 108 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
109 | #define SMBAUXCTL_CRC 1 |
110 | #define SMBAUXCTL_E32B 2 | |
111 | ||
1da177e4 | 112 | /* Other settings */ |
84c1af4c | 113 | #define MAX_RETRIES 400 |
1da177e4 LT |
114 | |
115 | /* I801 command constants */ | |
116 | #define I801_QUICK 0x00 | |
117 | #define I801_BYTE 0x04 | |
118 | #define I801_BYTE_DATA 0x08 | |
119 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 120 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 121 | #define I801_BLOCK_DATA 0x14 |
6342064c | 122 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
123 | |
124 | /* I801 Host Control register bits */ | |
125 | #define SMBHSTCNT_INTREN 0x01 | |
126 | #define SMBHSTCNT_KILL 0x02 | |
127 | #define SMBHSTCNT_LAST_BYTE 0x20 | |
128 | #define SMBHSTCNT_START 0x40 | |
129 | #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ | |
1da177e4 | 130 | |
ca8b9e32 OR |
131 | /* I801 Hosts Status register bits */ |
132 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
133 | #define SMBHSTSTS_INUSE_STS 0x40 | |
134 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
135 | #define SMBHSTSTS_FAILED 0x10 | |
136 | #define SMBHSTSTS_BUS_ERR 0x08 | |
137 | #define SMBHSTSTS_DEV_ERR 0x04 | |
138 | #define SMBHSTSTS_INTR 0x02 | |
139 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 140 | |
70a1cc19 DK |
141 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
142 | SMBHSTSTS_DEV_ERR) | |
143 | ||
144 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
145 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 146 | |
a6e5e2be JD |
147 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
148 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 | |
149 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 DW |
150 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
151 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 | |
152 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
153 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
6e2a851e | 154 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 |
a6e5e2be JD |
155 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 |
156 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
062737fb | 157 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 |
55fee8d7 | 158 | |
0cd96eb0 DW |
159 | struct i801_priv { |
160 | struct i2c_adapter adapter; | |
161 | unsigned long smba; | |
162 | unsigned char original_hstcfg; | |
163 | struct pci_dev *pci_dev; | |
164 | unsigned int features; | |
636752bc DK |
165 | |
166 | /* isr processing */ | |
167 | wait_queue_head_t waitq; | |
168 | u8 status; | |
0cd96eb0 DW |
169 | }; |
170 | ||
d6072f84 | 171 | static struct pci_driver i801_driver; |
369f6f4a JD |
172 | |
173 | #define FEATURE_SMBUS_PEC (1 << 0) | |
174 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
175 | #define FEATURE_BLOCK_PROC (1 << 2) | |
176 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
636752bc | 177 | #define FEATURE_IRQ (1 << 4) |
e7198fbf JD |
178 | /* Not really a feature, but it's convenient to handle it as such */ |
179 | #define FEATURE_IDF (1 << 15) | |
1da177e4 | 180 | |
adff687d JD |
181 | static const char *i801_feature_names[] = { |
182 | "SMBus PEC", | |
183 | "Block buffer", | |
184 | "Block process call", | |
185 | "I2C block read", | |
636752bc | 186 | "Interrupt", |
adff687d JD |
187 | }; |
188 | ||
189 | static unsigned int disable_features; | |
190 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
191 | MODULE_PARM_DESC(disable_features, "Disable selected driver features"); | |
192 | ||
cf898dc5 JD |
193 | /* Make sure the SMBus host is ready to start transmitting. |
194 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 195 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 196 | { |
2b73809d | 197 | int status; |
1da177e4 | 198 | |
0cd96eb0 | 199 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 200 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 201 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
202 | return -EBUSY; |
203 | } | |
204 | ||
205 | status &= STATUS_FLAGS; | |
206 | if (status) { | |
0cd96eb0 | 207 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 208 | status); |
0cd96eb0 DW |
209 | outb_p(status, SMBHSTSTS(priv)); |
210 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 211 | if (status) { |
0cd96eb0 | 212 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
213 | "Failed clearing status flags (%02x)\n", |
214 | status); | |
97140342 | 215 | return -EBUSY; |
1da177e4 LT |
216 | } |
217 | } | |
218 | ||
cf898dc5 JD |
219 | return 0; |
220 | } | |
1da177e4 | 221 | |
6cad93c4 JD |
222 | /* |
223 | * Convert the status register to an error code, and clear it. | |
224 | * Note that status only contains the bits we want to clear, not the | |
225 | * actual register value. | |
226 | */ | |
227 | static int i801_check_post(struct i801_priv *priv, int status) | |
cf898dc5 JD |
228 | { |
229 | int result = 0; | |
1da177e4 | 230 | |
636752bc DK |
231 | /* |
232 | * If the SMBus is still busy, we give up | |
233 | * Note: This timeout condition only happens when using polling | |
234 | * transactions. For interrupt operation, NAK/timeout is indicated by | |
235 | * DEV_ERR. | |
236 | */ | |
6cad93c4 | 237 | if (unlikely(status < 0)) { |
0cd96eb0 | 238 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 239 | /* try to stop the current command */ |
0cd96eb0 DW |
240 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
241 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
242 | SMBHSTCNT(priv)); | |
84c1af4c | 243 | usleep_range(1000, 2000); |
0cd96eb0 DW |
244 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
245 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
246 | |
247 | /* Check if it worked */ | |
0cd96eb0 | 248 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
249 | if ((status & SMBHSTSTS_HOST_BUSY) || |
250 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 251 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 252 | "Failed terminating the transaction\n"); |
0cd96eb0 | 253 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 254 | return -ETIMEDOUT; |
1da177e4 LT |
255 | } |
256 | ||
2b73809d | 257 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 258 | result = -EIO; |
0cd96eb0 | 259 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
260 | } |
261 | if (status & SMBHSTSTS_DEV_ERR) { | |
262 | result = -ENXIO; | |
0cd96eb0 | 263 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 264 | } |
2b73809d | 265 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 266 | result = -EAGAIN; |
0cd96eb0 | 267 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
268 | } |
269 | ||
6cad93c4 JD |
270 | /* Clear status flags except BYTE_DONE, to be cleared by caller */ |
271 | outb_p(status, SMBHSTSTS(priv)); | |
1da177e4 | 272 | |
1da177e4 LT |
273 | return result; |
274 | } | |
275 | ||
6cad93c4 JD |
276 | /* Wait for BUSY being cleared and either INTR or an error flag being set */ |
277 | static int i801_wait_intr(struct i801_priv *priv) | |
cf898dc5 | 278 | { |
cf898dc5 | 279 | int timeout = 0; |
6cad93c4 | 280 | int status; |
cf898dc5 JD |
281 | |
282 | /* We will always wait for a fraction of a second! */ | |
283 | do { | |
84c1af4c | 284 | usleep_range(250, 500); |
0cd96eb0 | 285 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
286 | } while (((status & SMBHSTSTS_HOST_BUSY) || |
287 | !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && | |
288 | (timeout++ < MAX_RETRIES)); | |
cf898dc5 | 289 | |
6cad93c4 JD |
290 | if (timeout > MAX_RETRIES) { |
291 | dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); | |
292 | return -ETIMEDOUT; | |
293 | } | |
294 | return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); | |
cf898dc5 JD |
295 | } |
296 | ||
6cad93c4 JD |
297 | /* Wait for either BYTE_DONE or an error flag being set */ |
298 | static int i801_wait_byte_done(struct i801_priv *priv) | |
ca8b9e32 OR |
299 | { |
300 | int timeout = 0; | |
2b73809d | 301 | int status; |
ca8b9e32 | 302 | |
6cad93c4 | 303 | /* We will always wait for a fraction of a second! */ |
ca8b9e32 | 304 | do { |
84c1af4c | 305 | usleep_range(250, 500); |
0cd96eb0 | 306 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
307 | } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && |
308 | (timeout++ < MAX_RETRIES)); | |
309 | ||
310 | if (timeout > MAX_RETRIES) { | |
311 | dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); | |
312 | return -ETIMEDOUT; | |
313 | } | |
314 | return status & STATUS_ERROR_FLAGS; | |
315 | } | |
316 | ||
317 | static int i801_transaction(struct i801_priv *priv, int xact) | |
318 | { | |
319 | int status; | |
320 | int result; | |
ca8b9e32 | 321 | |
6cad93c4 JD |
322 | result = i801_check_pre(priv); |
323 | if (result < 0) | |
324 | return result; | |
4ccc28f7 | 325 | |
636752bc DK |
326 | if (priv->features & FEATURE_IRQ) { |
327 | outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, | |
328 | SMBHSTCNT(priv)); | |
329 | wait_event(priv->waitq, (status = priv->status)); | |
330 | priv->status = 0; | |
331 | return i801_check_post(priv, status); | |
332 | } | |
333 | ||
6cad93c4 JD |
334 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
335 | * SMBSCMD are passed in xact */ | |
336 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
337 | ||
338 | status = i801_wait_intr(priv); | |
339 | return i801_check_post(priv, status); | |
ca8b9e32 OR |
340 | } |
341 | ||
0cd96eb0 DW |
342 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
343 | union i2c_smbus_data *data, | |
7edcb9ab OR |
344 | char read_write, int hwpec) |
345 | { | |
346 | int i, len; | |
97140342 | 347 | int status; |
7edcb9ab | 348 | |
0cd96eb0 | 349 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
350 | |
351 | /* Use 32-byte buffer to process this transaction */ | |
352 | if (read_write == I2C_SMBUS_WRITE) { | |
353 | len = data->block[0]; | |
0cd96eb0 | 354 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 355 | for (i = 0; i < len; i++) |
0cd96eb0 | 356 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
357 | } |
358 | ||
37af8711 | 359 | status = i801_transaction(priv, I801_BLOCK_DATA | |
edbeea63 | 360 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
361 | if (status) |
362 | return status; | |
7edcb9ab OR |
363 | |
364 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 365 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 366 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 367 | return -EPROTO; |
7edcb9ab OR |
368 | |
369 | data->block[0] = len; | |
370 | for (i = 0; i < len; i++) | |
0cd96eb0 | 371 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
372 | } |
373 | return 0; | |
374 | } | |
375 | ||
636752bc DK |
376 | /* |
377 | * i801 signals transaction completion with one of these interrupts: | |
378 | * INTR - Success | |
379 | * DEV_ERR - Invalid command, NAK or communication timeout | |
380 | * BUS_ERR - SMI# transaction collision | |
381 | * FAILED - transaction was canceled due to a KILL request | |
382 | * When any of these occur, update ->status and wake up the waitq. | |
383 | * ->status must be cleared before kicking off the next transaction. | |
384 | */ | |
385 | static irqreturn_t i801_isr(int irq, void *dev_id) | |
386 | { | |
387 | struct i801_priv *priv = dev_id; | |
388 | u16 pcists; | |
389 | u8 status; | |
390 | ||
391 | /* Confirm this is our interrupt */ | |
392 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
393 | if (!(pcists & SMBPCISTS_INTS)) | |
394 | return IRQ_NONE; | |
395 | ||
396 | status = inb_p(SMBHSTSTS(priv)); | |
397 | if (status != 0x42) | |
398 | dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status); | |
399 | ||
400 | /* | |
401 | * Clear irq sources and report transaction result. | |
402 | * ->status must be cleared before the next transaction is started. | |
403 | */ | |
404 | status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; | |
405 | if (status) { | |
406 | outb_p(status, SMBHSTSTS(priv)); | |
407 | priv->status |= status; | |
408 | wake_up(&priv->waitq); | |
409 | } | |
410 | ||
411 | return IRQ_HANDLED; | |
412 | } | |
413 | ||
efa3cb15 DK |
414 | /* |
415 | * For "byte-by-byte" block transactions: | |
416 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
417 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
418 | */ | |
0cd96eb0 DW |
419 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
420 | union i2c_smbus_data *data, | |
6342064c JD |
421 | char read_write, int command, |
422 | int hwpec) | |
1da177e4 LT |
423 | { |
424 | int i, len; | |
425 | int smbcmd; | |
2b73809d | 426 | int status; |
cf898dc5 | 427 | int result; |
cf898dc5 | 428 | |
0cd96eb0 | 429 | result = i801_check_pre(priv); |
cf898dc5 JD |
430 | if (result < 0) |
431 | return result; | |
1da177e4 | 432 | |
7edcb9ab | 433 | len = data->block[0]; |
1da177e4 LT |
434 | |
435 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
436 | outb_p(len, SMBHSTDAT0(priv)); |
437 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
438 | } |
439 | ||
efa3cb15 DK |
440 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
441 | read_write == I2C_SMBUS_READ) | |
442 | smbcmd = I801_I2C_BLOCK_DATA; | |
443 | else | |
444 | smbcmd = I801_BLOCK_DATA; | |
445 | ||
1da177e4 | 446 | for (i = 1; i <= len; i++) { |
efa3cb15 | 447 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 448 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
37af8711 | 449 | outb_p(smbcmd, SMBHSTCNT(priv)); |
1da177e4 | 450 | |
1da177e4 | 451 | if (i == 1) |
edbeea63 | 452 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 453 | SMBHSTCNT(priv)); |
1da177e4 | 454 | |
6cad93c4 JD |
455 | status = i801_wait_byte_done(priv); |
456 | if (status) | |
457 | goto exit; | |
1da177e4 | 458 | |
6342064c JD |
459 | if (i == 1 && read_write == I2C_SMBUS_READ |
460 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 461 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 462 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 463 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
464 | "Illegal SMBus block read size %d\n", |
465 | len); | |
466 | /* Recover */ | |
0cd96eb0 DW |
467 | while (inb_p(SMBHSTSTS(priv)) & |
468 | SMBHSTSTS_HOST_BUSY) | |
469 | outb_p(SMBHSTSTS_BYTE_DONE, | |
470 | SMBHSTSTS(priv)); | |
471 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 472 | return -EPROTO; |
cf898dc5 | 473 | } |
1da177e4 LT |
474 | data->block[0] = len; |
475 | } | |
476 | ||
477 | /* Retrieve/store value in SMBBLKDAT */ | |
478 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 479 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 480 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 481 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 482 | |
cf898dc5 | 483 | /* signals SMBBLKDAT ready */ |
6cad93c4 | 484 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); |
1da177e4 | 485 | } |
cf898dc5 | 486 | |
6cad93c4 JD |
487 | status = i801_wait_intr(priv); |
488 | exit: | |
489 | return i801_check_post(priv, status); | |
7edcb9ab | 490 | } |
1da177e4 | 491 | |
0cd96eb0 | 492 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 493 | { |
0cd96eb0 DW |
494 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
495 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 496 | return -EIO; |
7edcb9ab OR |
497 | return 0; |
498 | } | |
499 | ||
500 | /* Block transaction function */ | |
0cd96eb0 DW |
501 | static int i801_block_transaction(struct i801_priv *priv, |
502 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
503 | int command, int hwpec) |
504 | { | |
505 | int result = 0; | |
506 | unsigned char hostc; | |
507 | ||
508 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
509 | if (read_write == I2C_SMBUS_WRITE) { | |
510 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
511 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
512 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 513 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
514 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
515 | dev_err(&priv->pci_dev->dev, | |
6342064c | 516 | "I2C block read is unsupported!\n"); |
97140342 | 517 | return -EOPNOTSUPP; |
7edcb9ab OR |
518 | } |
519 | } | |
520 | ||
6342064c JD |
521 | if (read_write == I2C_SMBUS_WRITE |
522 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
523 | if (data->block[0] < 1) |
524 | data->block[0] = 1; | |
525 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
526 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
527 | } else { | |
6342064c | 528 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
529 | } |
530 | ||
c074c39d JD |
531 | /* Experience has shown that the block buffer can only be used for |
532 | SMBus (not I2C) block transactions, even though the datasheet | |
533 | doesn't mention this limitation. */ | |
0cd96eb0 | 534 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 535 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
536 | && i801_set_block_buffer_mode(priv) == 0) |
537 | result = i801_block_transaction_by_block(priv, data, | |
538 | read_write, hwpec); | |
7edcb9ab | 539 | else |
0cd96eb0 DW |
540 | result = i801_block_transaction_byte_by_byte(priv, data, |
541 | read_write, | |
6342064c | 542 | command, hwpec); |
7edcb9ab | 543 | |
6342064c JD |
544 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
545 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 546 | /* restore saved configuration register value */ |
0cd96eb0 | 547 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
548 | } |
549 | return result; | |
550 | } | |
551 | ||
97140342 | 552 | /* Return negative errno on error. */ |
3fb21c64 | 553 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 554 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 555 | int size, union i2c_smbus_data *data) |
1da177e4 | 556 | { |
e8aac4a9 | 557 | int hwpec; |
1da177e4 LT |
558 | int block = 0; |
559 | int ret, xact = 0; | |
0cd96eb0 | 560 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 561 | |
0cd96eb0 | 562 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
563 | && size != I2C_SMBUS_QUICK |
564 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
565 | |
566 | switch (size) { | |
567 | case I2C_SMBUS_QUICK: | |
568 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 569 | SMBHSTADD(priv)); |
1da177e4 LT |
570 | xact = I801_QUICK; |
571 | break; | |
572 | case I2C_SMBUS_BYTE: | |
573 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 574 | SMBHSTADD(priv)); |
1da177e4 | 575 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 576 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
577 | xact = I801_BYTE; |
578 | break; | |
579 | case I2C_SMBUS_BYTE_DATA: | |
580 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
581 | SMBHSTADD(priv)); |
582 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 583 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 584 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
585 | xact = I801_BYTE_DATA; |
586 | break; | |
587 | case I2C_SMBUS_WORD_DATA: | |
588 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
589 | SMBHSTADD(priv)); |
590 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 591 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
592 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
593 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
594 | } |
595 | xact = I801_WORD_DATA; | |
596 | break; | |
597 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 598 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
599 | SMBHSTADD(priv)); |
600 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
601 | block = 1; |
602 | break; | |
6342064c JD |
603 | case I2C_SMBUS_I2C_BLOCK_DATA: |
604 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
605 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 606 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
607 | if (read_write == I2C_SMBUS_READ) { |
608 | /* NB: page 240 of ICH5 datasheet also shows | |
609 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 610 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 611 | } else |
0cd96eb0 | 612 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
613 | block = 1; |
614 | break; | |
1da177e4 | 615 | default: |
0cd96eb0 DW |
616 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
617 | size); | |
97140342 | 618 | return -EOPNOTSUPP; |
1da177e4 LT |
619 | } |
620 | ||
ca8b9e32 | 621 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 622 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 623 | else |
0cd96eb0 DW |
624 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
625 | SMBAUXCTL(priv)); | |
e8aac4a9 | 626 | |
3fb21c64 | 627 | if (block) |
0cd96eb0 DW |
628 | ret = i801_block_transaction(priv, data, read_write, size, |
629 | hwpec); | |
7edcb9ab | 630 | else |
37af8711 | 631 | ret = i801_transaction(priv, xact); |
1da177e4 | 632 | |
c79cfbac | 633 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
634 | time, so we forcibly disable it after every transaction. Turn off |
635 | E32B for the same reason. */ | |
a0921b6c | 636 | if (hwpec || block) |
0cd96eb0 DW |
637 | outb_p(inb_p(SMBAUXCTL(priv)) & |
638 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 639 | |
3fb21c64 | 640 | if (block) |
1da177e4 | 641 | return ret; |
3fb21c64 | 642 | if (ret) |
97140342 | 643 | return ret; |
1da177e4 LT |
644 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
645 | return 0; | |
646 | ||
647 | switch (xact & 0x7f) { | |
648 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
649 | case I801_BYTE_DATA: | |
0cd96eb0 | 650 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
651 | break; |
652 | case I801_WORD_DATA: | |
0cd96eb0 DW |
653 | data->word = inb_p(SMBHSTDAT0(priv)) + |
654 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
655 | break; |
656 | } | |
657 | return 0; | |
658 | } | |
659 | ||
660 | ||
661 | static u32 i801_func(struct i2c_adapter *adapter) | |
662 | { | |
0cd96eb0 DW |
663 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
664 | ||
1da177e4 | 665 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
666 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
667 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
668 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
669 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 670 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
671 | } |
672 | ||
8f9082c5 | 673 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
674 | .smbus_xfer = i801_access, |
675 | .functionality = i801_func, | |
676 | }; | |
677 | ||
3527bd50 | 678 | static DEFINE_PCI_DEVICE_TABLE(i801_ids) = { |
1da177e4 LT |
679 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
680 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
681 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
682 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
683 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
684 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
685 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
686 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
687 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 688 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 689 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 690 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 691 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
692 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
693 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
694 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
695 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 696 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
697 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
698 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
699 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 700 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 701 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 702 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
1da177e4 LT |
703 | { 0, } |
704 | }; | |
705 | ||
3fb21c64 | 706 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 707 | |
8eacfceb | 708 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
709 | static unsigned char apanel_addr; |
710 | ||
711 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
712 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
713 | { | |
714 | ssize_t offset; | |
715 | const unsigned char signature[] = "FJKEYINF"; | |
716 | ||
717 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
718 | if (check_signature(bios + offset, signature, | |
719 | sizeof(signature)-1)) | |
720 | return bios + offset; | |
721 | } | |
722 | return NULL; | |
723 | } | |
724 | ||
725 | static void __init input_apanel_init(void) | |
726 | { | |
727 | void __iomem *bios; | |
728 | const void __iomem *p; | |
729 | ||
730 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
731 | p = bios_signature(bios); | |
732 | if (p) { | |
733 | /* just use the first address */ | |
734 | apanel_addr = readb(p + 8 + 3) >> 1; | |
735 | } | |
736 | iounmap(bios); | |
737 | } | |
1561bfe5 | 738 | |
fa5bfab7 HG |
739 | struct dmi_onboard_device_info { |
740 | const char *name; | |
741 | u8 type; | |
742 | unsigned short i2c_addr; | |
743 | const char *i2c_type; | |
744 | }; | |
745 | ||
746 | static struct dmi_onboard_device_info __devinitdata dmi_devices[] = { | |
747 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, | |
748 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
749 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
750 | }; | |
751 | ||
752 | static void __devinit dmi_check_onboard_device(u8 type, const char *name, | |
753 | struct i2c_adapter *adap) | |
754 | { | |
755 | int i; | |
756 | struct i2c_board_info info; | |
757 | ||
758 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
759 | /* & ~0x80, ignore enabled/disabled bit */ | |
760 | if ((type & ~0x80) != dmi_devices[i].type) | |
761 | continue; | |
faabd47f | 762 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
763 | continue; |
764 | ||
765 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
766 | info.addr = dmi_devices[i].i2c_addr; | |
767 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
768 | i2c_new_device(adap, &info); | |
769 | break; | |
770 | } | |
771 | } | |
772 | ||
773 | /* We use our own function to check for onboard devices instead of | |
774 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
775 | in marked as disabled */ | |
776 | static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm, | |
777 | void *adap) | |
778 | { | |
779 | int i, count; | |
780 | ||
781 | if (dm->type != 10) | |
782 | return; | |
783 | ||
784 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
785 | for (i = 0; i < count; i++) { | |
786 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
787 | const char *name = ((char *) dm) + dm->length; | |
788 | u8 type = d[0]; | |
789 | u8 s = d[1]; | |
790 | ||
791 | if (!s) | |
792 | continue; | |
793 | s--; | |
794 | while (s > 0 && name[0]) { | |
795 | name += strlen(name) + 1; | |
796 | s--; | |
797 | } | |
798 | if (name[0] == 0) /* Bogus string reference */ | |
799 | continue; | |
800 | ||
801 | dmi_check_onboard_device(type, name, adap); | |
802 | } | |
803 | } | |
fa5bfab7 | 804 | |
e7198fbf JD |
805 | /* Register optional slaves */ |
806 | static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) | |
807 | { | |
808 | /* Only register slaves on main SMBus channel */ | |
809 | if (priv->features & FEATURE_IDF) | |
810 | return; | |
811 | ||
e7198fbf JD |
812 | if (apanel_addr) { |
813 | struct i2c_board_info info; | |
814 | ||
815 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
816 | info.addr = apanel_addr; | |
817 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
818 | i2c_new_device(&priv->adapter, &info); | |
819 | } | |
8eacfceb | 820 | |
e7198fbf JD |
821 | if (dmi_name_in_vendors("FUJITSU")) |
822 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 823 | } |
8eacfceb JD |
824 | #else |
825 | static void __init input_apanel_init(void) {} | |
826 | static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {} | |
827 | #endif /* CONFIG_X86 && CONFIG_DMI */ | |
e7198fbf | 828 | |
3fb21c64 IM |
829 | static int __devinit i801_probe(struct pci_dev *dev, |
830 | const struct pci_device_id *id) | |
1da177e4 | 831 | { |
02dd7ae2 | 832 | unsigned char temp; |
adff687d | 833 | int err, i; |
0cd96eb0 DW |
834 | struct i801_priv *priv; |
835 | ||
836 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
837 | if (!priv) | |
838 | return -ENOMEM; | |
839 | ||
840 | i2c_set_adapdata(&priv->adapter, priv); | |
841 | priv->adapter.owner = THIS_MODULE; | |
842 | priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
843 | priv->adapter.algo = &smbus_algorithm; | |
1da177e4 | 844 | |
0cd96eb0 | 845 | priv->pci_dev = dev; |
250d1bd3 | 846 | switch (dev->device) { |
e7198fbf JD |
847 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
848 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
849 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
850 | priv->features |= FEATURE_IDF; | |
851 | /* fall through */ | |
e0e8398c | 852 | default: |
0cd96eb0 | 853 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6342064c JD |
854 | /* fall through */ |
855 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
856 | priv->features |= FEATURE_SMBUS_PEC; |
857 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
858 | /* fall through */ |
859 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
860 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
861 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
862 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 863 | break; |
250d1bd3 | 864 | } |
02dd7ae2 | 865 | |
636752bc DK |
866 | /* IRQ processing only tested on CougarPoint PCH */ |
867 | if (dev->device == PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) | |
868 | priv->features |= FEATURE_IRQ; | |
869 | ||
adff687d JD |
870 | /* Disable features on user request */ |
871 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 872 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
873 | dev_notice(&dev->dev, "%s disabled by user\n", |
874 | i801_feature_names[i]); | |
875 | } | |
0cd96eb0 | 876 | priv->features &= ~disable_features; |
adff687d | 877 | |
02dd7ae2 JD |
878 | err = pci_enable_device(dev); |
879 | if (err) { | |
880 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
881 | err); | |
882 | goto exit; | |
883 | } | |
884 | ||
885 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
886 | priv->smba = pci_resource_start(dev, SMBBAR); |
887 | if (!priv->smba) { | |
02dd7ae2 JD |
888 | dev_err(&dev->dev, "SMBus base address uninitialized, " |
889 | "upgrade BIOS\n"); | |
890 | err = -ENODEV; | |
d6fcb3b9 | 891 | goto exit; |
02dd7ae2 JD |
892 | } |
893 | ||
54fb4a05 | 894 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab JD |
895 | if (err) { |
896 | err = -ENODEV; | |
54fb4a05 | 897 | goto exit; |
18669eab | 898 | } |
54fb4a05 | 899 | |
02dd7ae2 JD |
900 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
901 | if (err) { | |
902 | dev_err(&dev->dev, "Failed to request SMBus region " | |
0cd96eb0 | 903 | "0x%lx-0x%Lx\n", priv->smba, |
598736c5 | 904 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
d6fcb3b9 | 905 | goto exit; |
02dd7ae2 JD |
906 | } |
907 | ||
0cd96eb0 DW |
908 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
909 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
910 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
911 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
912 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
913 | temp |= SMBHSTCFG_HST_EN; | |
914 | } | |
0cd96eb0 | 915 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 | 916 | |
636752bc | 917 | if (temp & SMBHSTCFG_SMB_SMI_EN) { |
02dd7ae2 | 918 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
636752bc DK |
919 | /* Disable SMBus interrupt feature if SMBus using SMI# */ |
920 | priv->features &= ~FEATURE_IRQ; | |
921 | } else { | |
02dd7ae2 | 922 | dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); |
636752bc | 923 | } |
1da177e4 | 924 | |
a0921b6c | 925 | /* Clear special mode bits */ |
0cd96eb0 DW |
926 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
927 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
928 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 929 | |
636752bc DK |
930 | if (priv->features & FEATURE_IRQ) { |
931 | init_waitqueue_head(&priv->waitq); | |
932 | ||
933 | err = request_irq(dev->irq, i801_isr, IRQF_SHARED, | |
934 | i801_driver.name, priv); | |
935 | if (err) { | |
936 | dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", | |
937 | dev->irq, err); | |
938 | goto exit_release; | |
939 | } | |
940 | } | |
941 | ||
405ae7d3 | 942 | /* set up the sysfs linkage to our parent device */ |
0cd96eb0 | 943 | priv->adapter.dev.parent = &dev->dev; |
1da177e4 | 944 | |
7e2193a8 | 945 | /* Retry up to 3 times on lost arbitration */ |
0cd96eb0 | 946 | priv->adapter.retries = 3; |
7e2193a8 | 947 | |
0cd96eb0 DW |
948 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
949 | "SMBus I801 adapter at %04lx", priv->smba); | |
950 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
951 | if (err) { |
952 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
636752bc | 953 | goto exit_free_irq; |
02dd7ae2 | 954 | } |
1561bfe5 | 955 | |
e7198fbf | 956 | i801_probe_optional_slaves(priv); |
1561bfe5 | 957 | |
0cd96eb0 | 958 | pci_set_drvdata(dev, priv); |
636752bc | 959 | |
d6fcb3b9 | 960 | return 0; |
02dd7ae2 | 961 | |
636752bc DK |
962 | exit_free_irq: |
963 | if (priv->features & FEATURE_IRQ) | |
964 | free_irq(dev->irq, priv); | |
d6fcb3b9 DR |
965 | exit_release: |
966 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 | 967 | exit: |
0cd96eb0 | 968 | kfree(priv); |
02dd7ae2 | 969 | return err; |
1da177e4 LT |
970 | } |
971 | ||
972 | static void __devexit i801_remove(struct pci_dev *dev) | |
973 | { | |
0cd96eb0 DW |
974 | struct i801_priv *priv = pci_get_drvdata(dev); |
975 | ||
976 | i2c_del_adapter(&priv->adapter); | |
977 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
636752bc DK |
978 | |
979 | if (priv->features & FEATURE_IRQ) | |
980 | free_irq(dev->irq, priv); | |
6dcc19df | 981 | pci_release_region(dev, SMBBAR); |
636752bc | 982 | |
0cd96eb0 DW |
983 | pci_set_drvdata(dev, NULL); |
984 | kfree(priv); | |
d6fcb3b9 DR |
985 | /* |
986 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
987 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
988 | */ | |
1da177e4 LT |
989 | } |
990 | ||
a5aaea37 JD |
991 | #ifdef CONFIG_PM |
992 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
993 | { | |
0cd96eb0 DW |
994 | struct i801_priv *priv = pci_get_drvdata(dev); |
995 | ||
a5aaea37 | 996 | pci_save_state(dev); |
0cd96eb0 | 997 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
998 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static int i801_resume(struct pci_dev *dev) | |
1003 | { | |
1004 | pci_set_power_state(dev, PCI_D0); | |
1005 | pci_restore_state(dev); | |
1006 | return pci_enable_device(dev); | |
1007 | } | |
1008 | #else | |
1009 | #define i801_suspend NULL | |
1010 | #define i801_resume NULL | |
1011 | #endif | |
1012 | ||
1da177e4 LT |
1013 | static struct pci_driver i801_driver = { |
1014 | .name = "i801_smbus", | |
1015 | .id_table = i801_ids, | |
1016 | .probe = i801_probe, | |
1017 | .remove = __devexit_p(i801_remove), | |
a5aaea37 JD |
1018 | .suspend = i801_suspend, |
1019 | .resume = i801_resume, | |
1da177e4 LT |
1020 | }; |
1021 | ||
1022 | static int __init i2c_i801_init(void) | |
1023 | { | |
6aa1464d JD |
1024 | if (dmi_name_in_vendors("FUJITSU")) |
1025 | input_apanel_init(); | |
1da177e4 LT |
1026 | return pci_register_driver(&i801_driver); |
1027 | } | |
1028 | ||
1029 | static void __exit i2c_i801_exit(void) | |
1030 | { | |
1031 | pci_unregister_driver(&i801_driver); | |
1032 | } | |
1033 | ||
6342064c JD |
1034 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, " |
1035 | "Jean Delvare <khali@linux-fr.org>"); | |
1da177e4 LT |
1036 | MODULE_DESCRIPTION("I801 SMBus driver"); |
1037 | MODULE_LICENSE("GPL"); | |
1038 | ||
1039 | module_init(i2c_i801_init); | |
1040 | module_exit(i2c_i801_exit); |