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i2c: i801: Instantiate SPD EEPROMs automatically
[linux-2.6-block.git] / drivers / i2c / busses / i2c-i801.c
CommitLineData
c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 2/*
1da177e4
LT		 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
b3b8df97 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
0cd96eb0
DW		 7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
1da177e4 9
1da177e4
LT		 10*/
11
12/*
ce316110
JD		 13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
b299de83 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
ce316110
JD		 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
15407798 53 * Braswell (SOC) 0x2292 32 hard yes yes yes
3e27a844 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
3eee1799 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
84d7f2eb 56 * DNV (SOC) 0x19df 32 hard yes yes yes
dd77f423 57 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
cdc5a311
AY		 58 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
59 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
31158763 60 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
9827f9eb 61 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
09a1de04
SP		 62 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
63 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
cb09d943 64 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
0bff2a86 65 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
5cd1c56c 66 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
07f047e3 67 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
9be1485a 68 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
051d769f 69 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
790591f4 70 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
f53938d2 71 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
ce316110
JD		 72 *
73 * Features supported by this driver:
74 * Software PEC no
75 * Hardware PEC yes
76 * Block buffer yes
315cd67c 77 * Block process call transaction yes
ce316110
JD		 78 * I2C block read transaction yes (doesn't use the block buffer)
79 * Slave mode no
7b0ed334 80 * SMBus Host Notify yes
ce316110
JD		 81 * Interrupt processing yes
82 *
ccf988b6 83 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
ce316110 84 */
1da177e4 85
636752bc 86#include <linux/interrupt.h>
1da177e4
LT		 87#include <linux/module.h>
88#include <linux/pci.h>
89#include <linux/kernel.h>
90#include <linux/stddef.h>
91#include <linux/delay.h>
1da177e4
LT		 92#include <linux/ioport.h>
93#include <linux/init.h>
94#include <linux/i2c.h>
7b0ed334 95#include <linux/i2c-smbus.h>
54fb4a05 96#include <linux/acpi.h>
1561bfe5 97#include <linux/io.h>
fa5bfab7 98#include <linux/dmi.h>
665a96b7 99#include <linux/slab.h>
af668d65 100#include <linux/string.h>
636752bc 101#include <linux/wait.h>
3ad7ea18 102#include <linux/err.h>
94246930
MW		 103#include <linux/platform_device.h>
104#include <linux/platform_data/itco_wdt.h>
a7401ca5 105#include <linux/pm_runtime.h>
3ad7ea18 106
175c7080 107#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
d308dfbf 108#include <linux/gpio/machine.h>
62ea22c4 109#include <linux/platform_data/i2c-mux-gpio.h>
3ad7ea18 110#endif
1da177e4 111
1da177e4 112/* I801 SMBus address offsets */
0cd96eb0
DW		 113#define SMBHSTSTS(p) (0 + (p)->smba)
114#define SMBHSTCNT(p) (2 + (p)->smba)
115#define SMBHSTCMD(p) (3 + (p)->smba)
116#define SMBHSTADD(p) (4 + (p)->smba)
117#define SMBHSTDAT0(p) (5 + (p)->smba)
118#define SMBHSTDAT1(p) (6 + (p)->smba)
119#define SMBBLKDAT(p) (7 + (p)->smba)
120#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
121#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
122#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
7b0ed334
BT		 123#define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
124#define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
125#define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
1da177e4
LT		 126
127/* PCI Address Constants */
6dcc19df 128#define SMBBAR 4
aeb8a3d1 129#define SMBPCICTL 0x004
636752bc 130#define SMBPCISTS 0x006
1da177e4 131#define SMBHSTCFG 0x040
94246930
MW		 132#define TCOBASE 0x050
133#define TCOCTL 0x054
134
94246930
MW		 135#define SBREG_BAR 0x10
136#define SBREG_SMBCTRL 0xc6000c
851a1511 137#define SBREG_SMBCTRL_DNV 0xcf000c
1da177e4 138
636752bc 139/* Host status bits for SMBPCISTS */
fe9ba3ec 140#define SMBPCISTS_INTS BIT(3)
636752bc 141
aeb8a3d1 142/* Control bits for SMBPCICTL */
fe9ba3ec 143#define SMBPCICTL_INTDIS BIT(10)
aeb8a3d1 144
1da177e4 145/* Host configuration bits for SMBHSTCFG */
fe9ba3ec
BT		 146#define SMBHSTCFG_HST_EN BIT(0)
147#define SMBHSTCFG_SMB_SMI_EN BIT(1)
148#define SMBHSTCFG_I2C_EN BIT(2)
149#define SMBHSTCFG_SPD_WD BIT(4)
1da177e4 150
94246930 151/* TCO configuration bits for TCOCTL */
fe9ba3ec 152#define TCOCTL_EN BIT(8)
94246930 153
97d34ec1 154/* Auxiliary status register bits, ICH4+ only */
fe9ba3ec
BT		 155#define SMBAUXSTS_CRCE BIT(0)
156#define SMBAUXSTS_STCO BIT(1)
97d34ec1 157
25985edc 158/* Auxiliary control register bits, ICH4+ only */
fe9ba3ec
BT		 159#define SMBAUXCTL_CRC BIT(0)
160#define SMBAUXCTL_E32B BIT(1)
ca8b9e32 161
1da177e4 162/* Other settings */
84c1af4c 163#define MAX_RETRIES 400
1da177e4
LT		 164
165/* I801 command constants */
166#define I801_QUICK 0x00
167#define I801_BYTE 0x04
168#define I801_BYTE_DATA 0x08
169#define I801_WORD_DATA 0x0C
ae7b0497 170#define I801_PROC_CALL 0x10 /* unimplemented */
1da177e4 171#define I801_BLOCK_DATA 0x14
6342064c 172#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
315cd67c 173#define I801_BLOCK_PROC_CALL 0x1C
edbeea63
DK		 174
175/* I801 Host Control register bits */
fe9ba3ec
BT		 176#define SMBHSTCNT_INTREN BIT(0)
177#define SMBHSTCNT_KILL BIT(1)
178#define SMBHSTCNT_LAST_BYTE BIT(5)
179#define SMBHSTCNT_START BIT(6)
180#define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
1da177e4 181
ca8b9e32 182/* I801 Hosts Status register bits */
fe9ba3ec
BT		 183#define SMBHSTSTS_BYTE_DONE BIT(7)
184#define SMBHSTSTS_INUSE_STS BIT(6)
185#define SMBHSTSTS_SMBALERT_STS BIT(5)
186#define SMBHSTSTS_FAILED BIT(4)
187#define SMBHSTSTS_BUS_ERR BIT(3)
188#define SMBHSTSTS_DEV_ERR BIT(2)
189#define SMBHSTSTS_INTR BIT(1)
190#define SMBHSTSTS_HOST_BUSY BIT(0)
1da177e4 191
9786b1f1 192/* Host Notify Status register bits */
fe9ba3ec 193#define SMBSLVSTS_HST_NTFY_STS BIT(0)
7b0ed334 194
9786b1f1 195/* Host Notify Command register bits */
fe9ba3ec 196#define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
7b0ed334 197
70a1cc19
DK		 198#define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
199 SMBHSTSTS_DEV_ERR)
200
201#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
202 STATUS_ERROR_FLAGS)
cf898dc5 203
a6e5e2be 204/* Older devices have their ID defined in <linux/pci_ids.h> */
856078bf 205#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
07f047e3 206#define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
ce316110 207#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
cb09d943 208#define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
34b57f40 209#define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
ce316110
JD		 210#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
211#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
55fee8d7 212/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
ce316110
JD		 213#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
214#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
215#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
216#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
217#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
34b57f40 218#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
ce316110
JD		 219#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
220#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
9827f9eb 221#define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
0bff2a86 222#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
ce316110 223#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
856078bf 224#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
790591f4 225#define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
34b57f40 226#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
ce316110 227#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
b299de83 228#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
ce316110
JD		 229#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
230#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
231#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
232#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
233#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
afc65924 234#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
3eee1799 235#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
09a1de04 236#define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
051d769f 237#define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
34b57f40 238#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
cdc5a311
AY		 239#define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
240#define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
31158763 241#define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
09a1de04 242#define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
f53938d2 243#define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
55fee8d7 244
3ad7ea18
JD		 245struct i801_mux_config {
246 char *gpio_chip;
247 unsigned values[3];
248 int n_values;
249 unsigned classes[3];
250 unsigned gpios[2]; /* Relative to gpio_chip->base */
251 int n_gpios;
252};
253
0cd96eb0
DW		 254struct i801_priv {
255 struct i2c_adapter adapter;
256 unsigned long smba;
257 unsigned char original_hstcfg;
22e94bd6 258 unsigned char original_slvcmd;
0cd96eb0
DW		 259 struct pci_dev *pci_dev;
260 unsigned int features;
636752bc
DK		 261
262 /* isr processing */
263 wait_queue_head_t waitq;
264 u8 status;
d3ff6ce4
DK		 265
266 /* Command state used by isr for byte-by-byte block transactions */
267 u8 cmd;
268 bool is_read;
269 int count;
270 int len;
271 u8 *data;
3ad7ea18 272
175c7080 273#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
3ad7ea18 274 const struct i801_mux_config *mux_drvdata;
3ad7ea18 275 struct platform_device *mux_pdev;
d308dfbf 276 struct gpiod_lookup_table *lookup;
3ad7ea18 277#endif
94246930 278 struct platform_device *tco_pdev;
a7ae8195
MW		 279
280 /*
281 * If set to true the host controller registers are reserved for
282 * ACPI AML use. Protected by acpi_lock.
283 */
284 bool acpi_reserved;
285 struct mutex acpi_lock;
0cd96eb0
DW		 286};
287
f91fba62
BT		 288#define FEATURE_SMBUS_PEC BIT(0)
289#define FEATURE_BLOCK_BUFFER BIT(1)
290#define FEATURE_BLOCK_PROC BIT(2)
291#define FEATURE_I2C_BLOCK_READ BIT(3)
292#define FEATURE_IRQ BIT(4)
293#define FEATURE_HOST_NOTIFY BIT(5)
e7198fbf 294/* Not really a feature, but it's convenient to handle it as such */
f91fba62 295#define FEATURE_IDF BIT(15)
b84398d6
MW		 296#define FEATURE_TCO_SPT BIT(16)
297#define FEATURE_TCO_CNL BIT(17)
1da177e4 298
adff687d
JD		 299static const char *i801_feature_names[] = {
300 "SMBus PEC",
301 "Block buffer",
302 "Block process call",
303 "I2C block read",
636752bc 304 "Interrupt",
7b0ed334 305 "SMBus Host Notify",
adff687d
JD		 306};
307
308static unsigned int disable_features;
309module_param(disable_features, uint, S_IRUGO | S_IWUSR);
53229345
JD		 310MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
311 "\t\t 0x01 disable SMBus PEC\n"
312 "\t\t 0x02 disable the block buffer\n"
313 "\t\t 0x08 disable the I2C block read functionality\n"
7b0ed334
BT		 314 "\t\t 0x10 don't use interrupts\n"
315 "\t\t 0x20 disable SMBus Host Notify ");
adff687d 316
cf898dc5
JD		 317/* Make sure the SMBus host is ready to start transmitting.
318 Return 0 if it is, -EBUSY if it is not. */
0cd96eb0 319static int i801_check_pre(struct i801_priv *priv)
1da177e4 320{
2b73809d 321 int status;
1da177e4 322
0cd96eb0 323 status = inb_p(SMBHSTSTS(priv));
cf898dc5 324 if (status & SMBHSTSTS_HOST_BUSY) {
0cd96eb0 325 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
cf898dc5
JD		 326 return -EBUSY;
327 }
328
329 status &= STATUS_FLAGS;
330 if (status) {
0cd96eb0 331 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
2b73809d 332 status);
0cd96eb0
DW		 333 outb_p(status, SMBHSTSTS(priv));
334 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
cf898dc5 335 if (status) {
0cd96eb0 336 dev_err(&priv->pci_dev->dev,
cf898dc5
JD		 337 "Failed clearing status flags (%02x)\n",
338 status);
97140342 339 return -EBUSY;
1da177e4
LT		 340 }
341 }
342
97d34ec1
EW		 343 /*
344 * Clear CRC status if needed.
345 * During normal operation, i801_check_post() takes care
346 * of it after every operation. We do it here only in case
347 * the hardware was already in this state when the driver
348 * started.
349 */
350 if (priv->features & FEATURE_SMBUS_PEC) {
351 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
352 if (status) {
353 dev_dbg(&priv->pci_dev->dev,
354 "Clearing aux status flags (%02x)\n", status);
355 outb_p(status, SMBAUXSTS(priv));
356 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
357 if (status) {
358 dev_err(&priv->pci_dev->dev,
359 "Failed clearing aux status flags (%02x)\n",
360 status);
361 return -EBUSY;
362 }
363 }
364 }
365
cf898dc5
JD		 366 return 0;
367}
1da177e4 368
6cad93c4
JD		 369/*
370 * Convert the status register to an error code, and clear it.
371 * Note that status only contains the bits we want to clear, not the
372 * actual register value.
373 */
374static int i801_check_post(struct i801_priv *priv, int status)
cf898dc5
JD		 375{
376 int result = 0;
1da177e4 377
636752bc
DK		 378 /*
379 * If the SMBus is still busy, we give up
380 * Note: This timeout condition only happens when using polling
381 * transactions. For interrupt operation, NAK/timeout is indicated by
382 * DEV_ERR.
383 */
6cad93c4 384 if (unlikely(status < 0)) {
0cd96eb0 385 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
ca8b9e32 386 /* try to stop the current command */
0cd96eb0
DW		 387 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
388 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
389 SMBHSTCNT(priv));
84c1af4c 390 usleep_range(1000, 2000);
0cd96eb0
DW		 391 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
392 SMBHSTCNT(priv));
cf898dc5
JD		 393
394 /* Check if it worked */
0cd96eb0 395 status = inb_p(SMBHSTSTS(priv));
cf898dc5
JD		 396 if ((status & SMBHSTSTS_HOST_BUSY) ||
397 !(status & SMBHSTSTS_FAILED))
0cd96eb0 398 dev_err(&priv->pci_dev->dev,
cf898dc5 399 "Failed terminating the transaction\n");
0cd96eb0 400 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
cf898dc5 401 return -ETIMEDOUT;
1da177e4
LT		 402 }
403
2b73809d 404 if (status & SMBHSTSTS_FAILED) {
97140342 405 result = -EIO;
0cd96eb0 406 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
cf898dc5
JD		 407 }
408 if (status & SMBHSTSTS_DEV_ERR) {
97d34ec1
EW		 409 /*
410 * This may be a PEC error, check and clear it.
411 *
412 * AUXSTS is handled differently from HSTSTS.
413 * For HSTSTS, i801_isr() or i801_wait_intr()
414 * has already cleared the error bits in hardware,
415 * and we are passed a copy of the original value
416 * in "status".
417 * For AUXSTS, the hardware register is left
418 * for us to handle here.
419 * This is asymmetric, slightly iffy, but safe,
420 * since all this code is serialized and the CRCE
421 * bit is harmless as long as it's cleared before
422 * the next operation.
423 */
424 if ((priv->features & FEATURE_SMBUS_PEC) &&
425 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
426 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
427 result = -EBADMSG;
428 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
429 } else {
430 result = -ENXIO;
431 dev_dbg(&priv->pci_dev->dev, "No response\n");
432 }
1da177e4 433 }
2b73809d 434 if (status & SMBHSTSTS_BUS_ERR) {
dcb5c923 435 result = -EAGAIN;
0cd96eb0 436 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
1da177e4
LT		 437 }
438
6cad93c4
JD		 439 /* Clear status flags except BYTE_DONE, to be cleared by caller */
440 outb_p(status, SMBHSTSTS(priv));
1da177e4 441
1da177e4
LT		 442 return result;
443}
444
6cad93c4
JD		 445/* Wait for BUSY being cleared and either INTR or an error flag being set */
446static int i801_wait_intr(struct i801_priv *priv)
cf898dc5 447{
cf898dc5 448 int timeout = 0;
6cad93c4 449 int status;
cf898dc5
JD		 450
451 /* We will always wait for a fraction of a second! */
452 do {
84c1af4c 453 usleep_range(250, 500);
0cd96eb0 454 status = inb_p(SMBHSTSTS(priv));
6cad93c4
JD		 455 } while (((status & SMBHSTSTS_HOST_BUSY) ||
456 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
457 (timeout++ < MAX_RETRIES));
cf898dc5 458
6cad93c4
JD		 459 if (timeout > MAX_RETRIES) {
460 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
461 return -ETIMEDOUT;
462 }
463 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
cf898dc5
JD		 464}
465
6cad93c4
JD		 466/* Wait for either BYTE_DONE or an error flag being set */
467static int i801_wait_byte_done(struct i801_priv *priv)
ca8b9e32
OR		 468{
469 int timeout = 0;
2b73809d 470 int status;
ca8b9e32 471
6cad93c4 472 /* We will always wait for a fraction of a second! */
ca8b9e32 473 do {
84c1af4c 474 usleep_range(250, 500);
0cd96eb0 475 status = inb_p(SMBHSTSTS(priv));
6cad93c4
JD		 476 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
477 (timeout++ < MAX_RETRIES));
478
479 if (timeout > MAX_RETRIES) {
480 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
481 return -ETIMEDOUT;
482 }
483 return status & STATUS_ERROR_FLAGS;
484}
485
486static int i801_transaction(struct i801_priv *priv, int xact)
487{
488 int status;
489 int result;
b3b8df97 490 const struct i2c_adapter *adap = &priv->adapter;
ca8b9e32 491
6cad93c4
JD		 492 result = i801_check_pre(priv);
493 if (result < 0)
494 return result;
4ccc28f7 495
636752bc
DK		 496 if (priv->features & FEATURE_IRQ) {
497 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
498 SMBHSTCNT(priv));
b3b8df97
JD		 499 result = wait_event_timeout(priv->waitq,
500 (status = priv->status),
501 adap->timeout);
502 if (!result) {
503 status = -ETIMEDOUT;
504 dev_warn(&priv->pci_dev->dev,
505 "Timeout waiting for interrupt!\n");
506 }
636752bc
DK		 507 priv->status = 0;
508 return i801_check_post(priv, status);
509 }
510
6cad93c4
JD		 511 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
512 * SMBSCMD are passed in xact */
513 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
514
515 status = i801_wait_intr(priv);
516 return i801_check_post(priv, status);
ca8b9e32
OR		 517}
518
0cd96eb0
DW		 519static int i801_block_transaction_by_block(struct i801_priv *priv,
520 union i2c_smbus_data *data,
315cd67c
AS		 521 char read_write, int command,
522 int hwpec)
7edcb9ab
OR		 523{
524 int i, len;
97140342 525 int status;
315cd67c
AS		 526 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
527
528 switch (command) {
529 case I2C_SMBUS_BLOCK_PROC_CALL:
530 xact |= I801_BLOCK_PROC_CALL;
531 break;
532 case I2C_SMBUS_BLOCK_DATA:
533 xact |= I801_BLOCK_DATA;
534 break;
535 default:
536 return -EOPNOTSUPP;
537 }
7edcb9ab 538
0cd96eb0 539 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
7edcb9ab
OR		 540
541 /* Use 32-byte buffer to process this transaction */
542 if (read_write == I2C_SMBUS_WRITE) {
543 len = data->block[0];
0cd96eb0 544 outb_p(len, SMBHSTDAT0(priv));
7edcb9ab 545 for (i = 0; i < len; i++)
0cd96eb0 546 outb_p(data->block[i+1], SMBBLKDAT(priv));
7edcb9ab
OR		 547 }
548
315cd67c 549 status = i801_transaction(priv, xact);
97140342
DB		 550 if (status)
551 return status;
7edcb9ab 552
315cd67c
AS		 553 if (read_write == I2C_SMBUS_READ ||
554 command == I2C_SMBUS_BLOCK_PROC_CALL) {
0cd96eb0 555 len = inb_p(SMBHSTDAT0(priv));
7edcb9ab 556 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
97140342 557 return -EPROTO;
7edcb9ab
OR		 558
559 data->block[0] = len;
560 for (i = 0; i < len; i++)
0cd96eb0 561 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
7edcb9ab
OR		 562 }
563 return 0;
564}
565
d3ff6ce4
DK		 566static void i801_isr_byte_done(struct i801_priv *priv)
567{
568 if (priv->is_read) {
569 /* For SMBus block reads, length is received with first byte */
570 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
571 (priv->count == 0)) {
572 priv->len = inb_p(SMBHSTDAT0(priv));
573 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
574 dev_err(&priv->pci_dev->dev,
575 "Illegal SMBus block read size %d\n",
576 priv->len);
577 /* FIXME: Recover */
578 priv->len = I2C_SMBUS_BLOCK_MAX;
579 } else {
580 dev_dbg(&priv->pci_dev->dev,
581 "SMBus block read size is %d\n",
582 priv->len);
583 }
584 priv->data[-1] = priv->len;
585 }
586
587 /* Read next byte */
588 if (priv->count < priv->len)
589 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
590 else
591 dev_dbg(&priv->pci_dev->dev,
592 "Discarding extra byte on block read\n");
593
594 /* Set LAST_BYTE for last byte of read transaction */
595 if (priv->count == priv->len - 1)
596 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
597 SMBHSTCNT(priv));
598 } else if (priv->count < priv->len - 1) {
599 /* Write next byte, except for IRQ after last byte */
600 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
601 }
602
603 /* Clear BYTE_DONE to continue with next byte */
604 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
605}
606
7b0ed334
BT		 607static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
608{
609 unsigned short addr;
7b0ed334
BT		 610
611 addr = inb_p(SMBNTFDADD(priv)) >> 1;
7b0ed334 612
c912a25a
BT		 613 /*
614 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
4d5538f5
BT		 615 * always returns 0. Our current implementation doesn't provide
616 * data, so we just ignore it.
c912a25a 617 */
4d5538f5 618 i2c_handle_smbus_host_notify(&priv->adapter, addr);
7b0ed334
BT		 619
620 /* clear Host Notify bit and return */
621 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
622 return IRQ_HANDLED;
623}
624
636752bc 625/*
7b0ed334 626 * There are three kinds of interrupts:
d3ff6ce4
DK		 627 *
628 * 1) i801 signals transaction completion with one of these interrupts:
629 * INTR - Success
630 * DEV_ERR - Invalid command, NAK or communication timeout
631 * BUS_ERR - SMI# transaction collision
632 * FAILED - transaction was canceled due to a KILL request
633 * When any of these occur, update ->status and wake up the waitq.
634 * ->status must be cleared before kicking off the next transaction.
635 *
636 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
637 * occurs for each byte of a byte-by-byte to prepare the next byte.
7b0ed334
BT		 638 *
639 * 3) Host Notify interrupts
636752bc
DK		 640 */
641static irqreturn_t i801_isr(int irq, void *dev_id)
642{
643 struct i801_priv *priv = dev_id;
644 u16 pcists;
645 u8 status;
646
647 /* Confirm this is our interrupt */
648 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
649 if (!(pcists & SMBPCISTS_INTS))
650 return IRQ_NONE;
651
7b0ed334
BT		 652 if (priv->features & FEATURE_HOST_NOTIFY) {
653 status = inb_p(SMBSLVSTS(priv));
654 if (status & SMBSLVSTS_HST_NTFY_STS)
655 return i801_host_notify_isr(priv);
656 }
657
636752bc 658 status = inb_p(SMBHSTSTS(priv));
d3ff6ce4
DK		 659 if (status & SMBHSTSTS_BYTE_DONE)
660 i801_isr_byte_done(priv);
661
636752bc
DK		 662 /*
663 * Clear irq sources and report transaction result.
664 * ->status must be cleared before the next transaction is started.
665 */
666 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
667 if (status) {
668 outb_p(status, SMBHSTSTS(priv));
a90bc5d9 669 priv->status = status;
636752bc
DK		 670 wake_up(&priv->waitq);
671 }
672
673 return IRQ_HANDLED;
674}
675
efa3cb15
DK		 676/*
677 * For "byte-by-byte" block transactions:
678 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
679 * I2C read uses cmd=I801_I2C_BLOCK_DATA
680 */
0cd96eb0
DW		 681static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
682 union i2c_smbus_data *data,
6342064c
JD		 683 char read_write, int command,
684 int hwpec)
1da177e4
LT		 685{
686 int i, len;
687 int smbcmd;
2b73809d 688 int status;
cf898dc5 689 int result;
b3b8df97 690 const struct i2c_adapter *adap = &priv->adapter;
cf898dc5 691
315cd67c
AS		 692 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
693 return -EOPNOTSUPP;
694
0cd96eb0 695 result = i801_check_pre(priv);
cf898dc5
JD		 696 if (result < 0)
697 return result;
1da177e4 698
7edcb9ab 699 len = data->block[0];
1da177e4
LT		 700
701 if (read_write == I2C_SMBUS_WRITE) {
0cd96eb0
DW		 702 outb_p(len, SMBHSTDAT0(priv));
703 outb_p(data->block[1], SMBBLKDAT(priv));
1da177e4
LT		 704 }
705
efa3cb15
DK		 706 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
707 read_write == I2C_SMBUS_READ)
708 smbcmd = I801_I2C_BLOCK_DATA;
709 else
710 smbcmd = I801_BLOCK_DATA;
711
d3ff6ce4
DK		 712 if (priv->features & FEATURE_IRQ) {
713 priv->is_read = (read_write == I2C_SMBUS_READ);
714 if (len == 1 && priv->is_read)
715 smbcmd |= SMBHSTCNT_LAST_BYTE;
716 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
717 priv->len = len;
718 priv->count = 0;
719 priv->data = &data->block[1];
720
721 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
b3b8df97
JD		 722 result = wait_event_timeout(priv->waitq,
723 (status = priv->status),
724 adap->timeout);
725 if (!result) {
726 status = -ETIMEDOUT;
727 dev_warn(&priv->pci_dev->dev,
728 "Timeout waiting for interrupt!\n");
729 }
d3ff6ce4
DK		 730 priv->status = 0;
731 return i801_check_post(priv, status);
732 }
733
1da177e4 734 for (i = 1; i <= len; i++) {
efa3cb15 735 if (i == len && read_write == I2C_SMBUS_READ)
edbeea63 736 smbcmd |= SMBHSTCNT_LAST_BYTE;
37af8711 737 outb_p(smbcmd, SMBHSTCNT(priv));
1da177e4 738
1da177e4 739 if (i == 1)
edbeea63 740 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
0cd96eb0 741 SMBHSTCNT(priv));
1da177e4 742
6cad93c4
JD		 743 status = i801_wait_byte_done(priv);
744 if (status)
745 goto exit;
1da177e4 746
6342064c
JD		 747 if (i == 1 && read_write == I2C_SMBUS_READ
748 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
0cd96eb0 749 len = inb_p(SMBHSTDAT0(priv));
cf898dc5 750 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
0cd96eb0 751 dev_err(&priv->pci_dev->dev,
cf898dc5
JD		 752 "Illegal SMBus block read size %d\n",
753 len);
754 /* Recover */
0cd96eb0
DW		 755 while (inb_p(SMBHSTSTS(priv)) &
756 SMBHSTSTS_HOST_BUSY)
757 outb_p(SMBHSTSTS_BYTE_DONE,
758 SMBHSTSTS(priv));
759 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
97140342 760 return -EPROTO;
cf898dc5 761 }
1da177e4
LT		 762 data->block[0] = len;
763 }
764
765 /* Retrieve/store value in SMBBLKDAT */
766 if (read_write == I2C_SMBUS_READ)
0cd96eb0 767 data->block[i] = inb_p(SMBBLKDAT(priv));
1da177e4 768 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
0cd96eb0 769 outb_p(data->block[i+1], SMBBLKDAT(priv));
1da177e4 770
cf898dc5 771 /* signals SMBBLKDAT ready */
6cad93c4 772 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
1da177e4 773 }
cf898dc5 774
6cad93c4
JD		 775 status = i801_wait_intr(priv);
776exit:
777 return i801_check_post(priv, status);
7edcb9ab 778}
1da177e4 779
0cd96eb0 780static int i801_set_block_buffer_mode(struct i801_priv *priv)
7edcb9ab 781{
0cd96eb0
DW		 782 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
783 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
97140342 784 return -EIO;
7edcb9ab
OR		 785 return 0;
786}
787
788/* Block transaction function */
0cd96eb0
DW		 789static int i801_block_transaction(struct i801_priv *priv,
790 union i2c_smbus_data *data, char read_write,
7edcb9ab
OR		 791 int command, int hwpec)
792{
793 int result = 0;
794 unsigned char hostc;
795
796 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
797 if (read_write == I2C_SMBUS_WRITE) {
798 /* set I2C_EN bit in configuration register */
0cd96eb0
DW		 799 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
800 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
7edcb9ab 801 hostc | SMBHSTCFG_I2C_EN);
0cd96eb0
DW		 802 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
803 dev_err(&priv->pci_dev->dev,
6342064c 804 "I2C block read is unsupported!\n");
97140342 805 return -EOPNOTSUPP;
7edcb9ab
OR		 806 }
807 }
808
6342064c
JD		 809 if (read_write == I2C_SMBUS_WRITE
810 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
7edcb9ab
OR		 811 if (data->block[0] < 1)
812 data->block[0] = 1;
813 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
814 data->block[0] = I2C_SMBUS_BLOCK_MAX;
815 } else {
6342064c 816 data->block[0] = 32; /* max for SMBus block reads */
7edcb9ab
OR		 817 }
818
c074c39d
JD		 819 /* Experience has shown that the block buffer can only be used for
820 SMBus (not I2C) block transactions, even though the datasheet
821 doesn't mention this limitation. */
0cd96eb0 822 if ((priv->features & FEATURE_BLOCK_BUFFER)
c074c39d 823 && command != I2C_SMBUS_I2C_BLOCK_DATA
0cd96eb0
DW		 824 && i801_set_block_buffer_mode(priv) == 0)
825 result = i801_block_transaction_by_block(priv, data,
315cd67c
AS		 826 read_write,
827 command, hwpec);
7edcb9ab 828 else
0cd96eb0
DW		 829 result = i801_block_transaction_byte_by_byte(priv, data,
830 read_write,
6342064c 831 command, hwpec);
7edcb9ab 832
6342064c
JD		 833 if (command == I2C_SMBUS_I2C_BLOCK_DATA
834 && read_write == I2C_SMBUS_WRITE) {
1da177e4 835 /* restore saved configuration register value */
0cd96eb0 836 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
1da177e4
LT		 837 }
838 return result;
839}
840
97140342 841/* Return negative errno on error. */
3fb21c64 842static s32 i801_access(struct i2c_adapter *adap, u16 addr,
1da177e4 843 unsigned short flags, char read_write, u8 command,
3fb21c64 844 int size, union i2c_smbus_data *data)
1da177e4 845{
e8aac4a9 846 int hwpec;
1da177e4 847 int block = 0;
a7401ca5 848 int ret = 0, xact = 0;
0cd96eb0 849 struct i801_priv *priv = i2c_get_adapdata(adap);
1da177e4 850
a7ae8195
MW		 851 mutex_lock(&priv->acpi_lock);
852 if (priv->acpi_reserved) {
853 mutex_unlock(&priv->acpi_lock);
854 return -EBUSY;
855 }
856
a7401ca5
JN		 857 pm_runtime_get_sync(&priv->pci_dev->dev);
858
0cd96eb0 859 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
e8aac4a9
JD		 860 && size != I2C_SMBUS_QUICK
861 && size != I2C_SMBUS_I2C_BLOCK_DATA;
1da177e4
LT		 862
863 switch (size) {
864 case I2C_SMBUS_QUICK:
865 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0 866 SMBHSTADD(priv));
1da177e4
LT		 867 xact = I801_QUICK;
868 break;
869 case I2C_SMBUS_BYTE:
870 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0 871 SMBHSTADD(priv));
1da177e4 872 if (read_write == I2C_SMBUS_WRITE)
0cd96eb0 873 outb_p(command, SMBHSTCMD(priv));
1da177e4
LT		 874 xact = I801_BYTE;
875 break;
876 case I2C_SMBUS_BYTE_DATA:
877 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0
DW		 878 SMBHSTADD(priv));
879 outb_p(command, SMBHSTCMD(priv));
1da177e4 880 if (read_write == I2C_SMBUS_WRITE)
0cd96eb0 881 outb_p(data->byte, SMBHSTDAT0(priv));
1da177e4
LT		 882 xact = I801_BYTE_DATA;
883 break;
884 case I2C_SMBUS_WORD_DATA:
885 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0
DW		 886 SMBHSTADD(priv));
887 outb_p(command, SMBHSTCMD(priv));
1da177e4 888 if (read_write == I2C_SMBUS_WRITE) {
0cd96eb0
DW		 889 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
890 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
1da177e4
LT		 891 }
892 xact = I801_WORD_DATA;
893 break;
894 case I2C_SMBUS_BLOCK_DATA:
1da177e4 895 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0cd96eb0
DW		 896 SMBHSTADD(priv));
897 outb_p(command, SMBHSTCMD(priv));
1da177e4
LT		 898 block = 1;
899 break;
6342064c 900 case I2C_SMBUS_I2C_BLOCK_DATA:
ba9ad2af
JD		 901 /*
902 * NB: page 240 of ICH5 datasheet shows that the R/#W
903 * bit should be cleared here, even when reading.
904 * However if SPD Write Disable is set (Lynx Point and later),
905 * the read will fail if we don't set the R/#W bit.
906 */
907 outb_p(((addr & 0x7f) << 1) |
908 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
909 (read_write & 0x01) : 0),
910 SMBHSTADD(priv));
6342064c
JD		 911 if (read_write == I2C_SMBUS_READ) {
912 /* NB: page 240 of ICH5 datasheet also shows
913 * that DATA1 is the cmd field when reading */
0cd96eb0 914 outb_p(command, SMBHSTDAT1(priv));
6342064c 915 } else
0cd96eb0 916 outb_p(command, SMBHSTCMD(priv));
6342064c
JD		 917 block = 1;
918 break;
315cd67c
AS		 919 case I2C_SMBUS_BLOCK_PROC_CALL:
920 /*
921 * Bit 0 of the slave address register always indicate a write
922 * command.
923 */
924 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
925 outb_p(command, SMBHSTCMD(priv));
926 block = 1;
927 break;
1da177e4 928 default:
0cd96eb0
DW		 929 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
930 size);
a7401ca5
JN		 931 ret = -EOPNOTSUPP;
932 goto out;
1da177e4
LT		 933 }
934
ca8b9e32 935 if (hwpec) /* enable/disable hardware PEC */
0cd96eb0 936 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
ca8b9e32 937 else
0cd96eb0
DW		 938 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
939 SMBAUXCTL(priv));
e8aac4a9 940
3fb21c64 941 if (block)
0cd96eb0
DW		 942 ret = i801_block_transaction(priv, data, read_write, size,
943 hwpec);
7edcb9ab 944 else
37af8711 945 ret = i801_transaction(priv, xact);
1da177e4 946
c79cfbac 947 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
7edcb9ab
OR		 948 time, so we forcibly disable it after every transaction. Turn off
949 E32B for the same reason. */
a0921b6c 950 if (hwpec || block)
0cd96eb0
DW		 951 outb_p(inb_p(SMBAUXCTL(priv)) &
952 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
c79cfbac 953
3fb21c64 954 if (block)
a7401ca5 955 goto out;
3fb21c64 956 if (ret)
a7401ca5 957 goto out;
1da177e4 958 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
a7401ca5 959 goto out;
1da177e4
LT		 960
961 switch (xact & 0x7f) {
962 case I801_BYTE: /* Result put in SMBHSTDAT0 */
963 case I801_BYTE_DATA:
0cd96eb0 964 data->byte = inb_p(SMBHSTDAT0(priv));
1da177e4
LT		 965 break;
966 case I801_WORD_DATA:
0cd96eb0
DW		 967 data->word = inb_p(SMBHSTDAT0(priv)) +
968 (inb_p(SMBHSTDAT1(priv)) << 8);
1da177e4
LT		 969 break;
970 }
a7401ca5
JN		 971
972out:
973 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
974 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
a7ae8195 975 mutex_unlock(&priv->acpi_lock);
a7401ca5 976 return ret;
1da177e4
LT		 977}
978
979
980static u32 i801_func(struct i2c_adapter *adapter)
981{
0cd96eb0
DW		 982 struct i801_priv *priv = i2c_get_adapdata(adapter);
983
1da177e4 984 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
369f6f4a
JD		 985 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
986 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
0cd96eb0 987 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
315cd67c
AS		 988 ((priv->features & FEATURE_BLOCK_PROC) ?
989 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
0cd96eb0 990 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
7b0ed334
BT		 991 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
992 ((priv->features & FEATURE_HOST_NOTIFY) ?
993 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
994}
995
4d5538f5 996static void i801_enable_host_notify(struct i2c_adapter *adapter)
7b0ed334
BT		 997{
998 struct i801_priv *priv = i2c_get_adapdata(adapter);
999
1000 if (!(priv->features & FEATURE_HOST_NOTIFY))
4d5538f5 1001 return;
7b0ed334 1002
22e94bd6
BT		 1003 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1004 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1005 SMBSLVCMD(priv));
1006
7b0ed334
BT		 1007 /* clear Host Notify bit to allow a new notification */
1008 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1da177e4
LT		 1009}
1010
22e94bd6
BT		 1011static void i801_disable_host_notify(struct i801_priv *priv)
1012{
1013 if (!(priv->features & FEATURE_HOST_NOTIFY))
1014 return;
1015
1016 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1017}
1018
8f9082c5 1019static const struct i2c_algorithm smbus_algorithm = {
1da177e4
LT		 1020 .smbus_xfer = i801_access,
1021 .functionality = i801_func,
1022};
1023
392debf1 1024static const struct pci_device_id i801_ids[] = {
1da177e4
LT		 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
b0a70b57 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
8254fc4a 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
adbc2a10 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
cb04e95b 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
d28dc711
GJ		 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
cb04e95b
SH		 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
e30d9859 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
55fee8d7
DW		 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
662cda8a 1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
6e2a851e 1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
062737fb 1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
4a8f1ddd 1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
c2db409c 1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
a3fc0ff0
JR		 1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
f39901c1 1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
9827f9eb 1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
b299de83 1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
afc65924 1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1b31e9b7 1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
39e8e30e 1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
3e27a844 1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
3eee1799 1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
cb09d943 1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
84d7f2eb 1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
dd77f423 1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
cdc5a311
AY		 1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
31158763 1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
09a1de04
SP		 1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
0bff2a86 1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
5cd1c56c 1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
07f047e3 1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
f53938d2 1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
9be1485a 1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
051d769f 1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
790591f4 1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1da177e4
LT		 1078 { 0, }
1079};
1080
3fb21c64 1081MODULE_DEVICE_TABLE(pci, i801_ids);
1da177e4 1082
8eacfceb 1083#if defined CONFIG_X86 && defined CONFIG_DMI
1561bfe5
JD		 1084static unsigned char apanel_addr;
1085
1086/* Scan the system ROM for the signature "FJKEYINF" */
1087static __init const void __iomem *bios_signature(const void __iomem *bios)
1088{
1089 ssize_t offset;
1090 const unsigned char signature[] = "FJKEYINF";
1091
1092 for (offset = 0; offset < 0x10000; offset += 0x10) {
1093 if (check_signature(bios + offset, signature,
1094 sizeof(signature)-1))
1095 return bios + offset;
1096 }
1097 return NULL;
1098}
1099
1100static void __init input_apanel_init(void)
1101{
1102 void __iomem *bios;
1103 const void __iomem *p;
1104
1105 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1106 p = bios_signature(bios);
1107 if (p) {
1108 /* just use the first address */
1109 apanel_addr = readb(p + 8 + 3) >> 1;
1110 }
1111 iounmap(bios);
1112}
1561bfe5 1113
fa5bfab7
HG		 1114struct dmi_onboard_device_info {
1115 const char *name;
1116 u8 type;
1117 unsigned short i2c_addr;
1118 const char *i2c_type;
1119};
1120
0b255e92 1121static const struct dmi_onboard_device_info dmi_devices[] = {
fa5bfab7
HG		 1122 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1123 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1124 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1125};
1126
0b255e92
BP		 1127static void dmi_check_onboard_device(u8 type, const char *name,
1128 struct i2c_adapter *adap)
fa5bfab7
HG		 1129{
1130 int i;
1131 struct i2c_board_info info;
1132
1133 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1134 /* & ~0x80, ignore enabled/disabled bit */
1135 if ((type & ~0x80) != dmi_devices[i].type)
1136 continue;
faabd47f 1137 if (strcasecmp(name, dmi_devices[i].name))
fa5bfab7
HG		 1138 continue;
1139
1140 memset(&info, 0, sizeof(struct i2c_board_info));
1141 info.addr = dmi_devices[i].i2c_addr;
1142 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
41d06630 1143 i2c_new_client_device(adap, &info);
fa5bfab7
HG		 1144 break;
1145 }
1146}
1147
1148/* We use our own function to check for onboard devices instead of
1149 dmi_find_device() as some buggy BIOS's have the devices we are interested
1150 in marked as disabled */
0b255e92 1151static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
fa5bfab7
HG		 1152{
1153 int i, count;
1154
1155 if (dm->type != 10)
1156 return;
1157
1158 count = (dm->length - sizeof(struct dmi_header)) / 2;
1159 for (i = 0; i < count; i++) {
1160 const u8 *d = (char *)(dm + 1) + (i * 2);
1161 const char *name = ((char *) dm) + dm->length;
1162 u8 type = d[0];
1163 u8 s = d[1];
1164
1165 if (!s)
1166 continue;
1167 s--;
1168 while (s > 0 && name[0]) {
1169 name += strlen(name) + 1;
1170 s--;
1171 }
1172 if (name[0] == 0) /* Bogus string reference */
1173 continue;
1174
1175 dmi_check_onboard_device(type, name, adap);
1176 }
1177}
fa5bfab7 1178
19b07cb4
PR		 1179/* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1180static const char *const acpi_smo8800_ids[] = {
1181 "SMO8800",
1182 "SMO8801",
1183 "SMO8810",
1184 "SMO8811",
1185 "SMO8820",
1186 "SMO8821",
1187 "SMO8830",
1188 "SMO8831",
1189};
1190
1191static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1192 u32 nesting_level,
1193 void *context,
1194 void **return_value)
1195{
1196 struct acpi_device_info *info;
1197 acpi_status status;
1198 char *hid;
1199 int i;
1200
1201 status = acpi_get_object_info(obj_handle, &info);
01641b26 1202 if (ACPI_FAILURE(status))
19b07cb4
PR		 1203 return AE_OK;
1204
01641b26
AS		 1205 if (!(info->valid & ACPI_VALID_HID))
1206 goto smo88xx_not_found;
1207
19b07cb4
PR		 1208 hid = info->hardware_id.string;
1209 if (!hid)
01641b26 1210 goto smo88xx_not_found;
19b07cb4 1211
af668d65
AS		 1212 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1213 if (i < 0)
01641b26
AS		 1214 goto smo88xx_not_found;
1215
1216 kfree(info);
19b07cb4 1217
af668d65
AS		 1218 *((bool *)return_value) = true;
1219 return AE_CTRL_TERMINATE;
01641b26
AS		 1220
1221smo88xx_not_found:
1222 kfree(info);
1223 return AE_OK;
19b07cb4
PR		 1224}
1225
1226static bool is_dell_system_with_lis3lv02d(void)
1227{
1228 bool found;
1229 const char *vendor;
1230
1231 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
aa5ae065 1232 if (!vendor || strcmp(vendor, "Dell Inc."))
19b07cb4
PR		 1233 return false;
1234
1235 /*
1236 * Check that ACPI device SMO88xx is present and is functioning.
1237 * Function acpi_get_devices() already filters all ACPI devices
1238 * which are not present or are not functioning.
1239 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1240 * accelerometer but unfortunately ACPI does not provide any other
1241 * information (like I2C address).
1242 */
1243 found = false;
1244 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1245 (void **)&found);
1246
1247 return found;
1248}
1249
1250/*
1251 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1252 * so it is needed to define mapping table based on DMI product names.
1253 */
1254static const struct {
1255 const char *dmi_product_name;
1256 unsigned short i2c_addr;
1257} dell_lis3lv02d_devices[] = {
1258 /*
1259 * Dell platform team told us that these Latitude devices have
1260 * ST microelectronics accelerometer at I2C address 0x29.
1261 */
1262 { "Latitude E5250", 0x29 },
1263 { "Latitude E5450", 0x29 },
1264 { "Latitude E5550", 0x29 },
1265 { "Latitude E6440", 0x29 },
1266 { "Latitude E6440 ATG", 0x29 },
1267 { "Latitude E6540", 0x29 },
1268 /*
1269 * Additional individual entries were added after verification.
1270 */
1271 { "Vostro V131", 0x1d },
1272};
1273
1274static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1275{
1276 struct i2c_board_info info;
1277 const char *dmi_product_name;
1278 int i;
1279
1280 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1281 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1282 if (strcmp(dmi_product_name,
1283 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1284 break;
1285 }
1286
1287 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1288 dev_warn(&priv->pci_dev->dev,
1289 "Accelerometer lis3lv02d is present on SMBus but its"
1290 " address is unknown, skipping registration\n");
1291 return;
1292 }
1293
1294 memset(&info, 0, sizeof(struct i2c_board_info));
1295 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1296 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
41d06630 1297 i2c_new_client_device(&priv->adapter, &info);
19b07cb4
PR		 1298}
1299
e7198fbf 1300/* Register optional slaves */
0b255e92 1301static void i801_probe_optional_slaves(struct i801_priv *priv)
e7198fbf
JD		 1302{
1303 /* Only register slaves on main SMBus channel */
1304 if (priv->features & FEATURE_IDF)
1305 return;
1306
e7198fbf
JD		 1307 if (apanel_addr) {
1308 struct i2c_board_info info;
1309
1310 memset(&info, 0, sizeof(struct i2c_board_info));
1311 info.addr = apanel_addr;
1312 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
41d06630 1313 i2c_new_client_device(&priv->adapter, &info);
e7198fbf 1314 }
8eacfceb 1315
e7198fbf
JD		 1316 if (dmi_name_in_vendors("FUJITSU"))
1317 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
19b07cb4
PR		 1318
1319 if (is_dell_system_with_lis3lv02d())
1320 register_dell_lis3lv02d_i2c_device(priv);
01590f36
JD		 1321
1322 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1323#if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1324 if (!priv->mux_drvdata)
1325#endif
1326 i2c_register_spd(&priv->adapter);
e7198fbf 1327}
8eacfceb
JD		 1328#else
1329static void __init input_apanel_init(void) {}
0b255e92 1330static void i801_probe_optional_slaves(struct i801_priv *priv) {}
8eacfceb 1331#endif /* CONFIG_X86 && CONFIG_DMI */
e7198fbf 1332
175c7080 1333#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
3ad7ea18
JD		 1334static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1335 .gpio_chip = "gpio_ich",
1336 .values = { 0x02, 0x03 },
1337 .n_values = 2,
1338 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1339 .gpios = { 52, 53 },
1340 .n_gpios = 2,
1341};
1342
1343static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1344 .gpio_chip = "gpio_ich",
1345 .values = { 0x02, 0x03, 0x01 },
1346 .n_values = 3,
1347 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1348 .gpios = { 52, 53 },
1349 .n_gpios = 2,
1350};
1351
0b255e92 1352static const struct dmi_system_id mux_dmi_table[] = {
3ad7ea18
JD		 1353 {
1354 .matches = {
1355 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1356 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1357 },
1358 .driver_data = &i801_mux_config_asus_z8_d12,
1359 },
1360 {
1361 .matches = {
1362 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1363 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1364 },
1365 .driver_data = &i801_mux_config_asus_z8_d12,
1366 },
1367 {
1368 .matches = {
1369 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1370 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1371 },
1372 .driver_data = &i801_mux_config_asus_z8_d12,
1373 },
1374 {
1375 .matches = {
1376 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1377 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1378 },
1379 .driver_data = &i801_mux_config_asus_z8_d12,
1380 },
1381 {
1382 .matches = {
1383 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1384 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1385 },
1386 .driver_data = &i801_mux_config_asus_z8_d12,
1387 },
1388 {
1389 .matches = {
1390 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1391 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1392 },
1393 .driver_data = &i801_mux_config_asus_z8_d12,
1394 },
1395 {
1396 .matches = {
1397 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1398 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1399 },
1400 .driver_data = &i801_mux_config_asus_z8_d18,
1401 },
1402 {
1403 .matches = {
1404 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1405 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1406 },
1407 .driver_data = &i801_mux_config_asus_z8_d18,
1408 },
1409 {
1410 .matches = {
1411 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1412 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1413 },
1414 .driver_data = &i801_mux_config_asus_z8_d12,
1415 },
1416 { }
1417};
1418
3ad7ea18 1419/* Setup multiplexing if needed */
0b255e92 1420static int i801_add_mux(struct i801_priv *priv)
3ad7ea18
JD		 1421{
1422 struct device *dev = &priv->adapter.dev;
1423 const struct i801_mux_config *mux_config;
3ad7ea18 1424 struct i2c_mux_gpio_platform_data gpio_data;
d308dfbf
LW		 1425 struct gpiod_lookup_table *lookup;
1426 int err, i;
3ad7ea18
JD		 1427
1428 if (!priv->mux_drvdata)
1429 return 0;
1430 mux_config = priv->mux_drvdata;
1431
3ad7ea18
JD		 1432 /* Prepare the platform data */
1433 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1434 gpio_data.parent = priv->adapter.nr;
1435 gpio_data.values = mux_config->values;
1436 gpio_data.n_values = mux_config->n_values;
1437 gpio_data.classes = mux_config->classes;
3ad7ea18
JD		 1438 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1439
d308dfbf
LW		 1440 /* Register GPIO descriptor lookup table */
1441 lookup = devm_kzalloc(dev,
1442 struct_size(lookup, table, mux_config->n_gpios),
1443 GFP_KERNEL);
1444 if (!lookup)
1445 return -ENOMEM;
1446 lookup->dev_id = "i2c-mux-gpio";
1447 for (i = 0; i < mux_config->n_gpios; i++) {
be1b92c1
GU		 1448 lookup->table[i] = (struct gpiod_lookup)
1449 GPIO_LOOKUP(mux_config->gpio_chip,
1450 mux_config->gpios[i], "mux", 0);
d308dfbf
LW		 1451 }
1452 gpiod_add_lookup_table(lookup);
1453 priv->lookup = lookup;
1454
1455 /*
1456 * Register the mux device, we use PLATFORM_DEVID_NONE here
1457 * because since we are referring to the GPIO chip by name we are
1458 * anyways in deep trouble if there is more than one of these
1459 * devices, and there should likely only be one platform controller
1460 * hub.
1461 */
3ad7ea18 1462 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
d308dfbf 1463 PLATFORM_DEVID_NONE, &gpio_data,
3ad7ea18
JD		 1464 sizeof(struct i2c_mux_gpio_platform_data));
1465 if (IS_ERR(priv->mux_pdev)) {
1466 err = PTR_ERR(priv->mux_pdev);
d308dfbf 1467 gpiod_remove_lookup_table(lookup);
3ad7ea18
JD		 1468 priv->mux_pdev = NULL;
1469 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1470 return err;
1471 }
1472
1473 return 0;
1474}
1475
0b255e92 1476static void i801_del_mux(struct i801_priv *priv)
3ad7ea18
JD		 1477{
1478 if (priv->mux_pdev)
1479 platform_device_unregister(priv->mux_pdev);
d308dfbf
LW		 1480 if (priv->lookup)
1481 gpiod_remove_lookup_table(priv->lookup);
3ad7ea18
JD		 1482}
1483
0b255e92 1484static unsigned int i801_get_adapter_class(struct i801_priv *priv)
3ad7ea18
JD		 1485{
1486 const struct dmi_system_id *id;
1487 const struct i801_mux_config *mux_config;
1488 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1489 int i;
1490
1491 id = dmi_first_match(mux_dmi_table);
1492 if (id) {
28901f57 1493 /* Remove branch classes from trunk */
3ad7ea18
JD		 1494 mux_config = id->driver_data;
1495 for (i = 0; i < mux_config->n_values; i++)
1496 class &= ~mux_config->classes[i];
1497
1498 /* Remember for later */
1499 priv->mux_drvdata = mux_config;
1500 }
1501
1502 return class;
1503}
1504#else
1505static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1506static inline void i801_del_mux(struct i801_priv *priv) { }
1507
1508static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1509{
1510 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1511}
1512#endif
1513
b84398d6 1514static const struct itco_wdt_platform_data spt_tco_platform_data = {
94246930
MW		 1515 .name = "Intel PCH",
1516 .version = 4,
1517};
1518
1519static DEFINE_SPINLOCK(p2sb_spinlock);
1520
b84398d6
MW		 1521static struct platform_device *
1522i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1523 struct resource *tco_res)
94246930 1524{
b84398d6 1525 struct resource *res;
94246930 1526 unsigned int devfn;
94246930 1527 u64 base64_addr;
b84398d6 1528 u32 base_addr;
bfd4473b 1529 u8 hidden;
94246930 1530
94246930
MW		 1531 /*
1532 * We must access the NO_REBOOT bit over the Primary to Sideband
1533 * bridge (P2SB). The BIOS prevents the P2SB device from being
1534 * enumerated by the PCI subsystem, so we need to unhide/hide it
1535 * to lookup the P2SB BAR.
1536 */
1537 spin_lock(&p2sb_spinlock);
1538
1539 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1540
bfd4473b
QZ		 1541 /* Unhide the P2SB device, if it is hidden */
1542 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1543 if (hidden)
1544 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
94246930
MW		 1545
1546 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1547 base64_addr = base_addr & 0xfffffff0;
1548
1549 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1550 base64_addr |= (u64)base_addr << 32;
1551
bfd4473b
QZ		 1552 /* Hide the P2SB device, if it was hidden before */
1553 if (hidden)
1554 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
94246930
MW		 1555 spin_unlock(&p2sb_spinlock);
1556
04bbb97d 1557 res = &tco_res[1];
851a1511
FB		 1558 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1559 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1560 else
1561 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1562
94246930
MW		 1563 res->end = res->start + 3;
1564 res->flags = IORESOURCE_MEM;
1565
b84398d6 1566 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
04bbb97d 1567 tco_res, 2, &spt_tco_platform_data,
b84398d6
MW		 1568 sizeof(spt_tco_platform_data));
1569}
1570
1571static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1572 .name = "Intel PCH",
1573 .version = 6,
1574};
1575
1576static struct platform_device *
1577i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1578 struct resource *tco_res)
1579{
04bbb97d
MW		 1580 return platform_device_register_resndata(&pci_dev->dev,
1581 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1582 sizeof(cnl_tco_platform_data));
b84398d6
MW		 1583}
1584
1585static void i801_add_tco(struct i801_priv *priv)
1586{
b84398d6 1587 struct pci_dev *pci_dev = priv->pci_dev;
04bbb97d
MW		 1588 struct resource tco_res[2], *res;
1589 u32 tco_base, tco_ctl;
b84398d6
MW		 1590
1591 /* If we have ACPI based watchdog use that instead */
1592 if (acpi_has_watchdog())
94246930 1593 return;
94246930 1594
b84398d6 1595 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
94246930 1596 return;
94246930 1597
b84398d6
MW		 1598 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1599 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1600 if (!(tco_ctl & TCOCTL_EN))
1601 return;
1602
1603 memset(tco_res, 0, sizeof(tco_res));
b84398d6 1604 /*
04bbb97d
MW		 1605 * Always populate the main iTCO IO resource here. The second entry
1606 * for NO_REBOOT MMIO is filled by the SPT specific function.
b84398d6 1607 */
04bbb97d
MW		 1608 res = &tco_res[0];
1609 res->start = tco_base & ~1;
1610 res->end = res->start + 32 - 1;
b84398d6
MW		 1611 res->flags = IORESOURCE_IO;
1612
b84398d6
MW		 1613 if (priv->features & FEATURE_TCO_CNL)
1614 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1615 else
1616 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1617
1618 if (IS_ERR(priv->tco_pdev))
1619 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
94246930
MW		 1620}
1621
a7ae8195 1622#ifdef CONFIG_ACPI
7fd6d98b
MW		 1623static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1624 acpi_physical_address address)
1625{
1626 return address >= priv->smba &&
1627 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1628}
1629
a7ae8195
MW		 1630static acpi_status
1631i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1632 u64 *value, void *handler_context, void *region_context)
1633{
1634 struct i801_priv *priv = handler_context;
1635 struct pci_dev *pdev = priv->pci_dev;
1636 acpi_status status;
1637
1638 /*
1639 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1640 * further access from the driver itself. This device is now owned
1641 * by the system firmware.
1642 */
1643 mutex_lock(&priv->acpi_lock);
1644
7fd6d98b 1645 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
a7ae8195
MW		 1646 priv->acpi_reserved = true;
1647
1648 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1649 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1650
1651 /*
1652 * BIOS is accessing the host controller so prevent it from
1653 * suspending automatically from now on.
1654 */
1655 pm_runtime_get_sync(&pdev->dev);
1656 }
1657
1658 if ((function & ACPI_IO_MASK) == ACPI_READ)
1659 status = acpi_os_read_port(address, (u32 *)value, bits);
1660 else
1661 status = acpi_os_write_port(address, (u32)*value, bits);
1662
1663 mutex_unlock(&priv->acpi_lock);
1664
1665 return status;
1666}
1667
1668static int i801_acpi_probe(struct i801_priv *priv)
1669{
1670 struct acpi_device *adev;
1671 acpi_status status;
1672
1673 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1674 if (adev) {
1675 status = acpi_install_address_space_handler(adev->handle,
1676 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1677 NULL, priv);
1678 if (ACPI_SUCCESS(status))
1679 return 0;
1680 }
1681
1682 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1683}
1684
1685static void i801_acpi_remove(struct i801_priv *priv)
1686{
1687 struct acpi_device *adev;
1688
1689 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1690 if (!adev)
1691 return;
1692
1693 acpi_remove_address_space_handler(adev->handle,
1694 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1695
1696 mutex_lock(&priv->acpi_lock);
1697 if (priv->acpi_reserved)
1698 pm_runtime_put(&priv->pci_dev->dev);
1699 mutex_unlock(&priv->acpi_lock);
1700}
1701#else
1702static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1703static inline void i801_acpi_remove(struct i801_priv *priv) { }
1704#endif
1705
0b255e92 1706static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1da177e4 1707{
02dd7ae2 1708 unsigned char temp;
adff687d 1709 int err, i;
0cd96eb0
DW		 1710 struct i801_priv *priv;
1711
1621c59d 1712 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
0cd96eb0
DW		 1713 if (!priv)
1714 return -ENOMEM;
1715
1716 i2c_set_adapdata(&priv->adapter, priv);
1717 priv->adapter.owner = THIS_MODULE;
3ad7ea18 1718 priv->adapter.class = i801_get_adapter_class(priv);
0cd96eb0 1719 priv->adapter.algo = &smbus_algorithm;
8eb5c87a
DB		 1720 priv->adapter.dev.parent = &dev->dev;
1721 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1722 priv->adapter.retries = 3;
a7ae8195 1723 mutex_init(&priv->acpi_lock);
1da177e4 1724
0cd96eb0 1725 priv->pci_dev = dev;
250d1bd3 1726 switch (dev->device) {
94246930
MW		 1727 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1728 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1a1503c5
AY		 1729 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1730 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
84d7f2eb 1731 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
31158763 1732 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
f53938d2 1733 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
fd4b204a 1734 priv->features |= FEATURE_BLOCK_PROC;
b84398d6
MW		 1735 priv->features |= FEATURE_I2C_BLOCK_READ;
1736 priv->features |= FEATURE_IRQ;
1737 priv->features |= FEATURE_SMBUS_PEC;
1738 priv->features |= FEATURE_BLOCK_BUFFER;
1739 priv->features |= FEATURE_TCO_SPT;
1740 priv->features |= FEATURE_HOST_NOTIFY;
1741 break;
1742
1743 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1744 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1745 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
0bff2a86 1746 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
5cd1c56c 1747 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
07f047e3 1748 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
9be1485a 1749 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
051d769f 1750 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
790591f4 1751 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
315cd67c 1752 priv->features |= FEATURE_BLOCK_PROC;
94246930
MW		 1753 priv->features |= FEATURE_I2C_BLOCK_READ;
1754 priv->features |= FEATURE_IRQ;
1755 priv->features |= FEATURE_SMBUS_PEC;
1756 priv->features |= FEATURE_BLOCK_BUFFER;
b84398d6 1757 priv->features |= FEATURE_TCO_CNL;
7b0ed334 1758 priv->features |= FEATURE_HOST_NOTIFY;
94246930
MW		 1759 break;
1760
e7198fbf
JD		 1761 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1762 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1763 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
a3fc0ff0
JR		 1764 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1765 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1766 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
e7198fbf
JD		 1767 priv->features |= FEATURE_IDF;
1768 /* fall through */
e0e8398c 1769 default:
315cd67c 1770 priv->features |= FEATURE_BLOCK_PROC;
0cd96eb0 1771 priv->features |= FEATURE_I2C_BLOCK_READ;
6676a847 1772 priv->features |= FEATURE_IRQ;
6342064c
JD		 1773 /* fall through */
1774 case PCI_DEVICE_ID_INTEL_82801DB_3:
0cd96eb0
DW		 1775 priv->features |= FEATURE_SMBUS_PEC;
1776 priv->features |= FEATURE_BLOCK_BUFFER;
e0e8398c
JD		 1777 /* fall through */
1778 case PCI_DEVICE_ID_INTEL_82801CA_3:
7b0ed334
BT		 1779 priv->features |= FEATURE_HOST_NOTIFY;
1780 /* fall through */
e0e8398c
JD		 1781 case PCI_DEVICE_ID_INTEL_82801BA_2:
1782 case PCI_DEVICE_ID_INTEL_82801AB_3:
1783 case PCI_DEVICE_ID_INTEL_82801AA_3:
250d1bd3 1784 break;
250d1bd3 1785 }
02dd7ae2 1786
adff687d
JD		 1787 /* Disable features on user request */
1788 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
0cd96eb0 1789 if (priv->features & disable_features & (1 << i))
adff687d
JD		 1790 dev_notice(&dev->dev, "%s disabled by user\n",
1791 i801_feature_names[i]);
1792 }
0cd96eb0 1793 priv->features &= ~disable_features;
adff687d 1794
fef220da 1795 err = pcim_enable_device(dev);
02dd7ae2
JD		 1796 if (err) {
1797 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1798 err);
fef220da 1799 return err;
02dd7ae2 1800 }
fef220da 1801 pcim_pin_device(dev);
02dd7ae2
JD		 1802
1803 /* Determine the address of the SMBus area */
0cd96eb0
DW		 1804 priv->smba = pci_resource_start(dev, SMBBAR);
1805 if (!priv->smba) {
9cbbf3dc
JN		 1806 dev_err(&dev->dev,
1807 "SMBus base address uninitialized, upgrade BIOS\n");
fef220da 1808 return -ENODEV;
02dd7ae2
JD		 1809 }
1810
a7ae8195 1811 if (i801_acpi_probe(priv))
fef220da 1812 return -ENODEV;
54fb4a05 1813
fef220da
JN		 1814 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1815 dev_driver_string(&dev->dev));
02dd7ae2 1816 if (err) {
9cbbf3dc
JN		 1817 dev_err(&dev->dev,
1818 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1819 priv->smba,
598736c5 1820 (unsigned long long)pci_resource_end(dev, SMBBAR));
a7ae8195 1821 i801_acpi_remove(priv);
fef220da 1822 return err;
02dd7ae2
JD		 1823 }
1824
0cd96eb0
DW		 1825 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1826 priv->original_hstcfg = temp;
02dd7ae2
JD		 1827 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1828 if (!(temp & SMBHSTCFG_HST_EN)) {
1829 dev_info(&dev->dev, "Enabling SMBus device\n");
1830 temp |= SMBHSTCFG_HST_EN;
1831 }
0cd96eb0 1832 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
02dd7ae2 1833
636752bc 1834 if (temp & SMBHSTCFG_SMB_SMI_EN) {
02dd7ae2 1835 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
636752bc
DK		 1836 /* Disable SMBus interrupt feature if SMBus using SMI# */
1837 priv->features &= ~FEATURE_IRQ;
636752bc 1838 }
ba9ad2af
JD		 1839 if (temp & SMBHSTCFG_SPD_WD)
1840 dev_info(&dev->dev, "SPD Write Disable is set\n");
1da177e4 1841
a0921b6c 1842 /* Clear special mode bits */
0cd96eb0
DW		 1843 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1844 outb_p(inb_p(SMBAUXCTL(priv)) &
1845 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
a0921b6c 1846
a086bb83
JD		 1847 /* Remember original Host Notify setting */
1848 if (priv->features & FEATURE_HOST_NOTIFY)
1849 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1850
b3b8df97
JD		 1851 /* Default timeout in interrupt mode: 200 ms */
1852 priv->adapter.timeout = HZ / 5;
1853
6e0c9507
HG		 1854 if (dev->irq == IRQ_NOTCONNECTED)
1855 priv->features &= ~FEATURE_IRQ;
1856
aeb8a3d1
JD		 1857 if (priv->features & FEATURE_IRQ) {
1858 u16 pcictl, pcists;
1859
1860 /* Complain if an interrupt is already pending */
1861 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1862 if (pcists & SMBPCISTS_INTS)
1863 dev_warn(&dev->dev, "An interrupt is pending!\n");
1864
1865 /* Check if interrupts have been disabled */
1866 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1867 if (pcictl & SMBPCICTL_INTDIS) {
1868 dev_info(&dev->dev, "Interrupts are disabled\n");
1869 priv->features &= ~FEATURE_IRQ;
1870 }
1871 }
1872
636752bc
DK		 1873 if (priv->features & FEATURE_IRQ) {
1874 init_waitqueue_head(&priv->waitq);
1875
1621c59d
JN		 1876 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1877 IRQF_SHARED,
1878 dev_driver_string(&dev->dev), priv);
636752bc
DK		 1879 if (err) {
1880 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1881 dev->irq, err);
ae944717 1882 priv->features &= ~FEATURE_IRQ;
636752bc
DK		 1883 }
1884 }
ae944717
JD		 1885 dev_info(&dev->dev, "SMBus using %s\n",
1886 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
636752bc 1887
94246930
MW		 1888 i801_add_tco(priv);
1889
0cd96eb0
DW		 1890 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1891 "SMBus I801 adapter at %04lx", priv->smba);
1892 err = i2c_add_adapter(&priv->adapter);
02dd7ae2 1893 if (err) {
a7ae8195 1894 i801_acpi_remove(priv);
fef220da 1895 return err;
02dd7ae2 1896 }
1561bfe5 1897
4d5538f5 1898 i801_enable_host_notify(&priv->adapter);
7b0ed334 1899
e7198fbf 1900 i801_probe_optional_slaves(priv);
3ad7ea18
JD		 1901 /* We ignore errors - multiplexing is optional */
1902 i801_add_mux(priv);
1561bfe5 1903
0cd96eb0 1904 pci_set_drvdata(dev, priv);
636752bc 1905
a7401ca5
JN		 1906 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1907 pm_runtime_use_autosuspend(&dev->dev);
1908 pm_runtime_put_autosuspend(&dev->dev);
1909 pm_runtime_allow(&dev->dev);
1910
d6fcb3b9 1911 return 0;
1da177e4
LT		 1912}
1913
0b255e92 1914static void i801_remove(struct pci_dev *dev)
1da177e4 1915{
0cd96eb0
DW		 1916 struct i801_priv *priv = pci_get_drvdata(dev);
1917
a7401ca5
JN		 1918 pm_runtime_forbid(&dev->dev);
1919 pm_runtime_get_noresume(&dev->dev);
1920
22e94bd6 1921 i801_disable_host_notify(priv);
3ad7ea18 1922 i801_del_mux(priv);
0cd96eb0 1923 i2c_del_adapter(&priv->adapter);
a7ae8195 1924 i801_acpi_remove(priv);
0cd96eb0 1925 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
636752bc 1926
94246930
MW		 1927 platform_device_unregister(priv->tco_pdev);
1928
d6fcb3b9
DR		 1929 /*
1930 * do not call pci_disable_device(dev) since it can cause hard hangs on
1931 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1932 */
1da177e4
LT		 1933}
1934
f7f6d915
JD		 1935static void i801_shutdown(struct pci_dev *dev)
1936{
1937 struct i801_priv *priv = pci_get_drvdata(dev);
1938
1939 /* Restore config registers to avoid hard hang on some systems */
1940 i801_disable_host_notify(priv);
1941 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1942}
1943
4b2f9bd5 1944#ifdef CONFIG_PM_SLEEP
2ee73c48 1945static int i801_suspend(struct device *dev)
a5aaea37 1946{
2ee73c48
JN		 1947 struct pci_dev *pci_dev = to_pci_dev(dev);
1948 struct i801_priv *priv = pci_get_drvdata(pci_dev);
0cd96eb0 1949
2ee73c48 1950 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
a5aaea37
JD		 1951 return 0;
1952}
1953
2ee73c48 1954static int i801_resume(struct device *dev)
a5aaea37 1955{
7735eeeb 1956 struct i801_priv *priv = dev_get_drvdata(dev);
7b0ed334 1957
4d5538f5 1958 i801_enable_host_notify(&priv->adapter);
7b0ed334 1959
f85da3f5 1960 return 0;
a5aaea37 1961}
a5aaea37
JD		 1962#endif
1963
a9c8088c 1964static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
2ee73c48 1965
1da177e4
LT		 1966static struct pci_driver i801_driver = {
1967 .name = "i801_smbus",
1968 .id_table = i801_ids,
1969 .probe = i801_probe,
0b255e92 1970 .remove = i801_remove,
f7f6d915 1971 .shutdown = i801_shutdown,
2ee73c48
JN		 1972 .driver = {
1973 .pm = &i801_pm_ops,
1974 },
1da177e4
LT		 1975};
1976
1977static int __init i2c_i801_init(void)
1978{
6aa1464d
JD		 1979 if (dmi_name_in_vendors("FUJITSU"))
1980 input_apanel_init();
1da177e4
LT		 1981 return pci_register_driver(&i801_driver);
1982}
1983
1984static void __exit i2c_i801_exit(void)
1985{
1986 pci_unregister_driver(&i801_driver);
1987}
1988
7c81c60f 1989MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1da177e4
LT		 1990MODULE_DESCRIPTION("I801 SMBus driver");
1991MODULE_LICENSE("GPL");
1992
1993module_init(i2c_i801_init);
1994module_exit(i2c_i801_exit);
Linux 6.x block layer and io_uring tree(s)