Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
84c1af4c | 5 | Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | /* | |
ae7b0497 JD |
25 | Supports the following Intel I/O Controller Hubs (ICH): |
26 | ||
27 | I/O Block I2C | |
28 | region SMBus Block proc. block | |
29 | Chip name PCI ID size PEC buffer call read | |
30 | ---------------------------------------------------------------------- | |
31 | 82801AA (ICH) 0x2413 16 no no no no | |
32 | 82801AB (ICH0) 0x2423 16 no no no no | |
33 | 82801BA (ICH2) 0x2443 16 no no no no | |
34 | 82801CA (ICH3) 0x2483 32 soft no no no | |
35 | 82801DB (ICH4) 0x24c3 32 hard yes no no | |
36 | 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
37 | 6300ESB 0x25a4 32 hard yes yes yes | |
38 | 82801F (ICH6) 0x266a 32 hard yes yes yes | |
39 | 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
40 | 82801G (ICH7) 0x27da 32 hard yes yes yes | |
41 | 82801H (ICH8) 0x283e 32 hard yes yes yes | |
42 | 82801I (ICH9) 0x2930 32 hard yes yes yes | |
cb04e95b | 43 | EP80579 (Tolapai) 0x5032 32 hard yes yes yes |
d28dc711 GJ |
44 | ICH10 0x3a30 32 hard yes yes yes |
45 | ICH10 0x3a60 32 hard yes yes yes | |
cb04e95b | 46 | 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes |
662cda8a | 47 | 6 Series (PCH) 0x1c22 32 hard yes yes yes |
e30d9859 | 48 | Patsburg (PCH) 0x1d22 32 hard yes yes yes |
55fee8d7 DW |
49 | Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes |
50 | Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
51 | Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
662cda8a | 52 | DH89xxCC (PCH) 0x2330 32 hard yes yes yes |
6e2a851e | 53 | Panther Point (PCH) 0x1e22 32 hard yes yes yes |
062737fb | 54 | Lynx Point (PCH) 0x8c22 32 hard yes yes yes |
4a8f1ddd | 55 | Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes |
c2db409c | 56 | Avoton (SOC) 0x1f3c 32 hard yes yes yes |
a3fc0ff0 JR |
57 | Wellsburg (PCH) 0x8d22 32 hard yes yes yes |
58 | Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes | |
59 | Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes | |
60 | Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes | |
ae7b0497 JD |
61 | |
62 | Features supported by this driver: | |
63 | Software PEC no | |
64 | Hardware PEC yes | |
65 | Block buffer yes | |
66 | Block process call transaction no | |
6342064c | 67 | I2C block read transaction yes (doesn't use the block buffer) |
55fee8d7 | 68 | Slave mode no |
636752bc | 69 | Interrupt processing yes |
ae7b0497 JD |
70 | |
71 | See the file Documentation/i2c/busses/i2c-i801 for details. | |
1da177e4 LT |
72 | */ |
73 | ||
636752bc | 74 | #include <linux/interrupt.h> |
1da177e4 LT |
75 | #include <linux/module.h> |
76 | #include <linux/pci.h> | |
77 | #include <linux/kernel.h> | |
78 | #include <linux/stddef.h> | |
79 | #include <linux/delay.h> | |
1da177e4 LT |
80 | #include <linux/ioport.h> |
81 | #include <linux/init.h> | |
82 | #include <linux/i2c.h> | |
54fb4a05 | 83 | #include <linux/acpi.h> |
1561bfe5 | 84 | #include <linux/io.h> |
fa5bfab7 | 85 | #include <linux/dmi.h> |
665a96b7 | 86 | #include <linux/slab.h> |
636752bc | 87 | #include <linux/wait.h> |
3ad7ea18 | 88 | #include <linux/err.h> |
f6afc8b1 | 89 | #include <linux/of_i2c.h> |
3ad7ea18 | 90 | |
79e3e5b8 JD |
91 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
92 | defined CONFIG_DMI | |
3ad7ea18 JD |
93 | #include <linux/gpio.h> |
94 | #include <linux/i2c-mux-gpio.h> | |
95 | #include <linux/platform_device.h> | |
96 | #endif | |
1da177e4 | 97 | |
1da177e4 | 98 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
99 | #define SMBHSTSTS(p) (0 + (p)->smba) |
100 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
101 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
102 | #define SMBHSTADD(p) (4 + (p)->smba) | |
103 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
104 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
105 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
106 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
107 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
108 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
109 | |
110 | /* PCI Address Constants */ | |
6dcc19df | 111 | #define SMBBAR 4 |
636752bc | 112 | #define SMBPCISTS 0x006 |
1da177e4 | 113 | #define SMBHSTCFG 0x040 |
1da177e4 | 114 | |
636752bc DK |
115 | /* Host status bits for SMBPCISTS */ |
116 | #define SMBPCISTS_INTS 0x08 | |
117 | ||
1da177e4 LT |
118 | /* Host configuration bits for SMBHSTCFG */ |
119 | #define SMBHSTCFG_HST_EN 1 | |
120 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
121 | #define SMBHSTCFG_I2C_EN 4 | |
122 | ||
25985edc | 123 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
124 | #define SMBAUXCTL_CRC 1 |
125 | #define SMBAUXCTL_E32B 2 | |
126 | ||
1da177e4 | 127 | /* Other settings */ |
84c1af4c | 128 | #define MAX_RETRIES 400 |
1da177e4 LT |
129 | |
130 | /* I801 command constants */ | |
131 | #define I801_QUICK 0x00 | |
132 | #define I801_BYTE 0x04 | |
133 | #define I801_BYTE_DATA 0x08 | |
134 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 135 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 136 | #define I801_BLOCK_DATA 0x14 |
6342064c | 137 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
138 | |
139 | /* I801 Host Control register bits */ | |
140 | #define SMBHSTCNT_INTREN 0x01 | |
141 | #define SMBHSTCNT_KILL 0x02 | |
142 | #define SMBHSTCNT_LAST_BYTE 0x20 | |
143 | #define SMBHSTCNT_START 0x40 | |
144 | #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ | |
1da177e4 | 145 | |
ca8b9e32 OR |
146 | /* I801 Hosts Status register bits */ |
147 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
148 | #define SMBHSTSTS_INUSE_STS 0x40 | |
149 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
150 | #define SMBHSTSTS_FAILED 0x10 | |
151 | #define SMBHSTSTS_BUS_ERR 0x08 | |
152 | #define SMBHSTSTS_DEV_ERR 0x04 | |
153 | #define SMBHSTSTS_INTR 0x02 | |
154 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 155 | |
70a1cc19 DK |
156 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
157 | SMBHSTSTS_DEV_ERR) | |
158 | ||
159 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
160 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 161 | |
a6e5e2be JD |
162 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
163 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 | |
164 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 DW |
165 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
166 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 | |
167 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
168 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
6e2a851e | 169 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 |
c2db409c | 170 | #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c |
a6e5e2be JD |
171 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 |
172 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
062737fb | 173 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 |
a3fc0ff0 JR |
174 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 |
175 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d | |
176 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e | |
177 | #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f | |
4a8f1ddd | 178 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 |
55fee8d7 | 179 | |
3ad7ea18 JD |
180 | struct i801_mux_config { |
181 | char *gpio_chip; | |
182 | unsigned values[3]; | |
183 | int n_values; | |
184 | unsigned classes[3]; | |
185 | unsigned gpios[2]; /* Relative to gpio_chip->base */ | |
186 | int n_gpios; | |
187 | }; | |
188 | ||
0cd96eb0 DW |
189 | struct i801_priv { |
190 | struct i2c_adapter adapter; | |
191 | unsigned long smba; | |
192 | unsigned char original_hstcfg; | |
193 | struct pci_dev *pci_dev; | |
194 | unsigned int features; | |
636752bc DK |
195 | |
196 | /* isr processing */ | |
197 | wait_queue_head_t waitq; | |
198 | u8 status; | |
d3ff6ce4 DK |
199 | |
200 | /* Command state used by isr for byte-by-byte block transactions */ | |
201 | u8 cmd; | |
202 | bool is_read; | |
203 | int count; | |
204 | int len; | |
205 | u8 *data; | |
3ad7ea18 | 206 | |
79e3e5b8 JD |
207 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
208 | defined CONFIG_DMI | |
3ad7ea18 | 209 | const struct i801_mux_config *mux_drvdata; |
3ad7ea18 JD |
210 | struct platform_device *mux_pdev; |
211 | #endif | |
0cd96eb0 DW |
212 | }; |
213 | ||
d6072f84 | 214 | static struct pci_driver i801_driver; |
369f6f4a JD |
215 | |
216 | #define FEATURE_SMBUS_PEC (1 << 0) | |
217 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
218 | #define FEATURE_BLOCK_PROC (1 << 2) | |
219 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
636752bc | 220 | #define FEATURE_IRQ (1 << 4) |
e7198fbf JD |
221 | /* Not really a feature, but it's convenient to handle it as such */ |
222 | #define FEATURE_IDF (1 << 15) | |
1da177e4 | 223 | |
adff687d JD |
224 | static const char *i801_feature_names[] = { |
225 | "SMBus PEC", | |
226 | "Block buffer", | |
227 | "Block process call", | |
228 | "I2C block read", | |
636752bc | 229 | "Interrupt", |
adff687d JD |
230 | }; |
231 | ||
232 | static unsigned int disable_features; | |
233 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
234 | MODULE_PARM_DESC(disable_features, "Disable selected driver features"); | |
235 | ||
cf898dc5 JD |
236 | /* Make sure the SMBus host is ready to start transmitting. |
237 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 238 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 239 | { |
2b73809d | 240 | int status; |
1da177e4 | 241 | |
0cd96eb0 | 242 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 243 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 244 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
245 | return -EBUSY; |
246 | } | |
247 | ||
248 | status &= STATUS_FLAGS; | |
249 | if (status) { | |
0cd96eb0 | 250 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 251 | status); |
0cd96eb0 DW |
252 | outb_p(status, SMBHSTSTS(priv)); |
253 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 254 | if (status) { |
0cd96eb0 | 255 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
256 | "Failed clearing status flags (%02x)\n", |
257 | status); | |
97140342 | 258 | return -EBUSY; |
1da177e4 LT |
259 | } |
260 | } | |
261 | ||
cf898dc5 JD |
262 | return 0; |
263 | } | |
1da177e4 | 264 | |
6cad93c4 JD |
265 | /* |
266 | * Convert the status register to an error code, and clear it. | |
267 | * Note that status only contains the bits we want to clear, not the | |
268 | * actual register value. | |
269 | */ | |
270 | static int i801_check_post(struct i801_priv *priv, int status) | |
cf898dc5 JD |
271 | { |
272 | int result = 0; | |
1da177e4 | 273 | |
636752bc DK |
274 | /* |
275 | * If the SMBus is still busy, we give up | |
276 | * Note: This timeout condition only happens when using polling | |
277 | * transactions. For interrupt operation, NAK/timeout is indicated by | |
278 | * DEV_ERR. | |
279 | */ | |
6cad93c4 | 280 | if (unlikely(status < 0)) { |
0cd96eb0 | 281 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 282 | /* try to stop the current command */ |
0cd96eb0 DW |
283 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
284 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
285 | SMBHSTCNT(priv)); | |
84c1af4c | 286 | usleep_range(1000, 2000); |
0cd96eb0 DW |
287 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
288 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
289 | |
290 | /* Check if it worked */ | |
0cd96eb0 | 291 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
292 | if ((status & SMBHSTSTS_HOST_BUSY) || |
293 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 294 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 295 | "Failed terminating the transaction\n"); |
0cd96eb0 | 296 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 297 | return -ETIMEDOUT; |
1da177e4 LT |
298 | } |
299 | ||
2b73809d | 300 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 301 | result = -EIO; |
0cd96eb0 | 302 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
303 | } |
304 | if (status & SMBHSTSTS_DEV_ERR) { | |
305 | result = -ENXIO; | |
0cd96eb0 | 306 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 307 | } |
2b73809d | 308 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 309 | result = -EAGAIN; |
0cd96eb0 | 310 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
311 | } |
312 | ||
6cad93c4 JD |
313 | /* Clear status flags except BYTE_DONE, to be cleared by caller */ |
314 | outb_p(status, SMBHSTSTS(priv)); | |
1da177e4 | 315 | |
1da177e4 LT |
316 | return result; |
317 | } | |
318 | ||
6cad93c4 JD |
319 | /* Wait for BUSY being cleared and either INTR or an error flag being set */ |
320 | static int i801_wait_intr(struct i801_priv *priv) | |
cf898dc5 | 321 | { |
cf898dc5 | 322 | int timeout = 0; |
6cad93c4 | 323 | int status; |
cf898dc5 JD |
324 | |
325 | /* We will always wait for a fraction of a second! */ | |
326 | do { | |
84c1af4c | 327 | usleep_range(250, 500); |
0cd96eb0 | 328 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
329 | } while (((status & SMBHSTSTS_HOST_BUSY) || |
330 | !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && | |
331 | (timeout++ < MAX_RETRIES)); | |
cf898dc5 | 332 | |
6cad93c4 JD |
333 | if (timeout > MAX_RETRIES) { |
334 | dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); | |
335 | return -ETIMEDOUT; | |
336 | } | |
337 | return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); | |
cf898dc5 JD |
338 | } |
339 | ||
6cad93c4 JD |
340 | /* Wait for either BYTE_DONE or an error flag being set */ |
341 | static int i801_wait_byte_done(struct i801_priv *priv) | |
ca8b9e32 OR |
342 | { |
343 | int timeout = 0; | |
2b73809d | 344 | int status; |
ca8b9e32 | 345 | |
6cad93c4 | 346 | /* We will always wait for a fraction of a second! */ |
ca8b9e32 | 347 | do { |
84c1af4c | 348 | usleep_range(250, 500); |
0cd96eb0 | 349 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
350 | } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && |
351 | (timeout++ < MAX_RETRIES)); | |
352 | ||
353 | if (timeout > MAX_RETRIES) { | |
354 | dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); | |
355 | return -ETIMEDOUT; | |
356 | } | |
357 | return status & STATUS_ERROR_FLAGS; | |
358 | } | |
359 | ||
360 | static int i801_transaction(struct i801_priv *priv, int xact) | |
361 | { | |
362 | int status; | |
363 | int result; | |
ca8b9e32 | 364 | |
6cad93c4 JD |
365 | result = i801_check_pre(priv); |
366 | if (result < 0) | |
367 | return result; | |
4ccc28f7 | 368 | |
636752bc DK |
369 | if (priv->features & FEATURE_IRQ) { |
370 | outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, | |
371 | SMBHSTCNT(priv)); | |
372 | wait_event(priv->waitq, (status = priv->status)); | |
373 | priv->status = 0; | |
374 | return i801_check_post(priv, status); | |
375 | } | |
376 | ||
6cad93c4 JD |
377 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
378 | * SMBSCMD are passed in xact */ | |
379 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
380 | ||
381 | status = i801_wait_intr(priv); | |
382 | return i801_check_post(priv, status); | |
ca8b9e32 OR |
383 | } |
384 | ||
0cd96eb0 DW |
385 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
386 | union i2c_smbus_data *data, | |
7edcb9ab OR |
387 | char read_write, int hwpec) |
388 | { | |
389 | int i, len; | |
97140342 | 390 | int status; |
7edcb9ab | 391 | |
0cd96eb0 | 392 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
393 | |
394 | /* Use 32-byte buffer to process this transaction */ | |
395 | if (read_write == I2C_SMBUS_WRITE) { | |
396 | len = data->block[0]; | |
0cd96eb0 | 397 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 398 | for (i = 0; i < len; i++) |
0cd96eb0 | 399 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
400 | } |
401 | ||
37af8711 | 402 | status = i801_transaction(priv, I801_BLOCK_DATA | |
edbeea63 | 403 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
404 | if (status) |
405 | return status; | |
7edcb9ab OR |
406 | |
407 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 408 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 409 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 410 | return -EPROTO; |
7edcb9ab OR |
411 | |
412 | data->block[0] = len; | |
413 | for (i = 0; i < len; i++) | |
0cd96eb0 | 414 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
415 | } |
416 | return 0; | |
417 | } | |
418 | ||
d3ff6ce4 DK |
419 | static void i801_isr_byte_done(struct i801_priv *priv) |
420 | { | |
421 | if (priv->is_read) { | |
422 | /* For SMBus block reads, length is received with first byte */ | |
423 | if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && | |
424 | (priv->count == 0)) { | |
425 | priv->len = inb_p(SMBHSTDAT0(priv)); | |
426 | if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { | |
427 | dev_err(&priv->pci_dev->dev, | |
428 | "Illegal SMBus block read size %d\n", | |
429 | priv->len); | |
430 | /* FIXME: Recover */ | |
431 | priv->len = I2C_SMBUS_BLOCK_MAX; | |
432 | } else { | |
433 | dev_dbg(&priv->pci_dev->dev, | |
434 | "SMBus block read size is %d\n", | |
435 | priv->len); | |
436 | } | |
437 | priv->data[-1] = priv->len; | |
438 | } | |
439 | ||
440 | /* Read next byte */ | |
441 | if (priv->count < priv->len) | |
442 | priv->data[priv->count++] = inb(SMBBLKDAT(priv)); | |
443 | else | |
444 | dev_dbg(&priv->pci_dev->dev, | |
445 | "Discarding extra byte on block read\n"); | |
446 | ||
447 | /* Set LAST_BYTE for last byte of read transaction */ | |
448 | if (priv->count == priv->len - 1) | |
449 | outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, | |
450 | SMBHSTCNT(priv)); | |
451 | } else if (priv->count < priv->len - 1) { | |
452 | /* Write next byte, except for IRQ after last byte */ | |
453 | outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); | |
454 | } | |
455 | ||
456 | /* Clear BYTE_DONE to continue with next byte */ | |
457 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); | |
458 | } | |
459 | ||
636752bc | 460 | /* |
d3ff6ce4 DK |
461 | * There are two kinds of interrupts: |
462 | * | |
463 | * 1) i801 signals transaction completion with one of these interrupts: | |
464 | * INTR - Success | |
465 | * DEV_ERR - Invalid command, NAK or communication timeout | |
466 | * BUS_ERR - SMI# transaction collision | |
467 | * FAILED - transaction was canceled due to a KILL request | |
468 | * When any of these occur, update ->status and wake up the waitq. | |
469 | * ->status must be cleared before kicking off the next transaction. | |
470 | * | |
471 | * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt | |
472 | * occurs for each byte of a byte-by-byte to prepare the next byte. | |
636752bc DK |
473 | */ |
474 | static irqreturn_t i801_isr(int irq, void *dev_id) | |
475 | { | |
476 | struct i801_priv *priv = dev_id; | |
477 | u16 pcists; | |
478 | u8 status; | |
479 | ||
480 | /* Confirm this is our interrupt */ | |
481 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
482 | if (!(pcists & SMBPCISTS_INTS)) | |
483 | return IRQ_NONE; | |
484 | ||
485 | status = inb_p(SMBHSTSTS(priv)); | |
486 | if (status != 0x42) | |
487 | dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status); | |
488 | ||
d3ff6ce4 DK |
489 | if (status & SMBHSTSTS_BYTE_DONE) |
490 | i801_isr_byte_done(priv); | |
491 | ||
636752bc DK |
492 | /* |
493 | * Clear irq sources and report transaction result. | |
494 | * ->status must be cleared before the next transaction is started. | |
495 | */ | |
496 | status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; | |
497 | if (status) { | |
498 | outb_p(status, SMBHSTSTS(priv)); | |
499 | priv->status |= status; | |
500 | wake_up(&priv->waitq); | |
501 | } | |
502 | ||
503 | return IRQ_HANDLED; | |
504 | } | |
505 | ||
efa3cb15 DK |
506 | /* |
507 | * For "byte-by-byte" block transactions: | |
508 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
509 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
510 | */ | |
0cd96eb0 DW |
511 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
512 | union i2c_smbus_data *data, | |
6342064c JD |
513 | char read_write, int command, |
514 | int hwpec) | |
1da177e4 LT |
515 | { |
516 | int i, len; | |
517 | int smbcmd; | |
2b73809d | 518 | int status; |
cf898dc5 | 519 | int result; |
cf898dc5 | 520 | |
0cd96eb0 | 521 | result = i801_check_pre(priv); |
cf898dc5 JD |
522 | if (result < 0) |
523 | return result; | |
1da177e4 | 524 | |
7edcb9ab | 525 | len = data->block[0]; |
1da177e4 LT |
526 | |
527 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
528 | outb_p(len, SMBHSTDAT0(priv)); |
529 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
530 | } |
531 | ||
efa3cb15 DK |
532 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
533 | read_write == I2C_SMBUS_READ) | |
534 | smbcmd = I801_I2C_BLOCK_DATA; | |
535 | else | |
536 | smbcmd = I801_BLOCK_DATA; | |
537 | ||
d3ff6ce4 DK |
538 | if (priv->features & FEATURE_IRQ) { |
539 | priv->is_read = (read_write == I2C_SMBUS_READ); | |
540 | if (len == 1 && priv->is_read) | |
541 | smbcmd |= SMBHSTCNT_LAST_BYTE; | |
542 | priv->cmd = smbcmd | SMBHSTCNT_INTREN; | |
543 | priv->len = len; | |
544 | priv->count = 0; | |
545 | priv->data = &data->block[1]; | |
546 | ||
547 | outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
548 | wait_event(priv->waitq, (status = priv->status)); | |
549 | priv->status = 0; | |
550 | return i801_check_post(priv, status); | |
551 | } | |
552 | ||
1da177e4 | 553 | for (i = 1; i <= len; i++) { |
efa3cb15 | 554 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 555 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
37af8711 | 556 | outb_p(smbcmd, SMBHSTCNT(priv)); |
1da177e4 | 557 | |
1da177e4 | 558 | if (i == 1) |
edbeea63 | 559 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 560 | SMBHSTCNT(priv)); |
1da177e4 | 561 | |
6cad93c4 JD |
562 | status = i801_wait_byte_done(priv); |
563 | if (status) | |
564 | goto exit; | |
1da177e4 | 565 | |
6342064c JD |
566 | if (i == 1 && read_write == I2C_SMBUS_READ |
567 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 568 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 569 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 570 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
571 | "Illegal SMBus block read size %d\n", |
572 | len); | |
573 | /* Recover */ | |
0cd96eb0 DW |
574 | while (inb_p(SMBHSTSTS(priv)) & |
575 | SMBHSTSTS_HOST_BUSY) | |
576 | outb_p(SMBHSTSTS_BYTE_DONE, | |
577 | SMBHSTSTS(priv)); | |
578 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 579 | return -EPROTO; |
cf898dc5 | 580 | } |
1da177e4 LT |
581 | data->block[0] = len; |
582 | } | |
583 | ||
584 | /* Retrieve/store value in SMBBLKDAT */ | |
585 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 586 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 587 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 588 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 589 | |
cf898dc5 | 590 | /* signals SMBBLKDAT ready */ |
6cad93c4 | 591 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); |
1da177e4 | 592 | } |
cf898dc5 | 593 | |
6cad93c4 JD |
594 | status = i801_wait_intr(priv); |
595 | exit: | |
596 | return i801_check_post(priv, status); | |
7edcb9ab | 597 | } |
1da177e4 | 598 | |
0cd96eb0 | 599 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 600 | { |
0cd96eb0 DW |
601 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
602 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 603 | return -EIO; |
7edcb9ab OR |
604 | return 0; |
605 | } | |
606 | ||
607 | /* Block transaction function */ | |
0cd96eb0 DW |
608 | static int i801_block_transaction(struct i801_priv *priv, |
609 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
610 | int command, int hwpec) |
611 | { | |
612 | int result = 0; | |
613 | unsigned char hostc; | |
614 | ||
615 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
616 | if (read_write == I2C_SMBUS_WRITE) { | |
617 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
618 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
619 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 620 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
621 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
622 | dev_err(&priv->pci_dev->dev, | |
6342064c | 623 | "I2C block read is unsupported!\n"); |
97140342 | 624 | return -EOPNOTSUPP; |
7edcb9ab OR |
625 | } |
626 | } | |
627 | ||
6342064c JD |
628 | if (read_write == I2C_SMBUS_WRITE |
629 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
630 | if (data->block[0] < 1) |
631 | data->block[0] = 1; | |
632 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
633 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
634 | } else { | |
6342064c | 635 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
636 | } |
637 | ||
c074c39d JD |
638 | /* Experience has shown that the block buffer can only be used for |
639 | SMBus (not I2C) block transactions, even though the datasheet | |
640 | doesn't mention this limitation. */ | |
0cd96eb0 | 641 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 642 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
643 | && i801_set_block_buffer_mode(priv) == 0) |
644 | result = i801_block_transaction_by_block(priv, data, | |
645 | read_write, hwpec); | |
7edcb9ab | 646 | else |
0cd96eb0 DW |
647 | result = i801_block_transaction_byte_by_byte(priv, data, |
648 | read_write, | |
6342064c | 649 | command, hwpec); |
7edcb9ab | 650 | |
6342064c JD |
651 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
652 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 653 | /* restore saved configuration register value */ |
0cd96eb0 | 654 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
655 | } |
656 | return result; | |
657 | } | |
658 | ||
97140342 | 659 | /* Return negative errno on error. */ |
3fb21c64 | 660 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 661 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 662 | int size, union i2c_smbus_data *data) |
1da177e4 | 663 | { |
e8aac4a9 | 664 | int hwpec; |
1da177e4 LT |
665 | int block = 0; |
666 | int ret, xact = 0; | |
0cd96eb0 | 667 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 668 | |
0cd96eb0 | 669 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
670 | && size != I2C_SMBUS_QUICK |
671 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
672 | |
673 | switch (size) { | |
674 | case I2C_SMBUS_QUICK: | |
675 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 676 | SMBHSTADD(priv)); |
1da177e4 LT |
677 | xact = I801_QUICK; |
678 | break; | |
679 | case I2C_SMBUS_BYTE: | |
680 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 681 | SMBHSTADD(priv)); |
1da177e4 | 682 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 683 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
684 | xact = I801_BYTE; |
685 | break; | |
686 | case I2C_SMBUS_BYTE_DATA: | |
687 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
688 | SMBHSTADD(priv)); |
689 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 690 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 691 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
692 | xact = I801_BYTE_DATA; |
693 | break; | |
694 | case I2C_SMBUS_WORD_DATA: | |
695 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
696 | SMBHSTADD(priv)); |
697 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 698 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
699 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
700 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
701 | } |
702 | xact = I801_WORD_DATA; | |
703 | break; | |
704 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 705 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
706 | SMBHSTADD(priv)); |
707 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
708 | block = 1; |
709 | break; | |
6342064c JD |
710 | case I2C_SMBUS_I2C_BLOCK_DATA: |
711 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
712 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 713 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
714 | if (read_write == I2C_SMBUS_READ) { |
715 | /* NB: page 240 of ICH5 datasheet also shows | |
716 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 717 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 718 | } else |
0cd96eb0 | 719 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
720 | block = 1; |
721 | break; | |
1da177e4 | 722 | default: |
0cd96eb0 DW |
723 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
724 | size); | |
97140342 | 725 | return -EOPNOTSUPP; |
1da177e4 LT |
726 | } |
727 | ||
ca8b9e32 | 728 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 729 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 730 | else |
0cd96eb0 DW |
731 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
732 | SMBAUXCTL(priv)); | |
e8aac4a9 | 733 | |
3fb21c64 | 734 | if (block) |
0cd96eb0 DW |
735 | ret = i801_block_transaction(priv, data, read_write, size, |
736 | hwpec); | |
7edcb9ab | 737 | else |
37af8711 | 738 | ret = i801_transaction(priv, xact); |
1da177e4 | 739 | |
c79cfbac | 740 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
741 | time, so we forcibly disable it after every transaction. Turn off |
742 | E32B for the same reason. */ | |
a0921b6c | 743 | if (hwpec || block) |
0cd96eb0 DW |
744 | outb_p(inb_p(SMBAUXCTL(priv)) & |
745 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 746 | |
3fb21c64 | 747 | if (block) |
1da177e4 | 748 | return ret; |
3fb21c64 | 749 | if (ret) |
97140342 | 750 | return ret; |
1da177e4 LT |
751 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
752 | return 0; | |
753 | ||
754 | switch (xact & 0x7f) { | |
755 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
756 | case I801_BYTE_DATA: | |
0cd96eb0 | 757 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
758 | break; |
759 | case I801_WORD_DATA: | |
0cd96eb0 DW |
760 | data->word = inb_p(SMBHSTDAT0(priv)) + |
761 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
762 | break; |
763 | } | |
764 | return 0; | |
765 | } | |
766 | ||
767 | ||
768 | static u32 i801_func(struct i2c_adapter *adapter) | |
769 | { | |
0cd96eb0 DW |
770 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
771 | ||
1da177e4 | 772 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
773 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
774 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
775 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
776 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 777 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
778 | } |
779 | ||
8f9082c5 | 780 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
781 | .smbus_xfer = i801_access, |
782 | .functionality = i801_func, | |
783 | }; | |
784 | ||
3527bd50 | 785 | static DEFINE_PCI_DEVICE_TABLE(i801_ids) = { |
1da177e4 LT |
786 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
787 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
788 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
789 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
790 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
791 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
792 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
793 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
794 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 795 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 796 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 797 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 798 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
799 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
800 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
801 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
802 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 803 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
804 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
805 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
806 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 807 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 808 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 809 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
4a8f1ddd | 810 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, |
c2db409c | 811 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, |
a3fc0ff0 JR |
812 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, |
813 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, | |
814 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, | |
815 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, | |
1da177e4 LT |
816 | { 0, } |
817 | }; | |
818 | ||
3fb21c64 | 819 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 820 | |
8eacfceb | 821 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
822 | static unsigned char apanel_addr; |
823 | ||
824 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
825 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
826 | { | |
827 | ssize_t offset; | |
828 | const unsigned char signature[] = "FJKEYINF"; | |
829 | ||
830 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
831 | if (check_signature(bios + offset, signature, | |
832 | sizeof(signature)-1)) | |
833 | return bios + offset; | |
834 | } | |
835 | return NULL; | |
836 | } | |
837 | ||
838 | static void __init input_apanel_init(void) | |
839 | { | |
840 | void __iomem *bios; | |
841 | const void __iomem *p; | |
842 | ||
843 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
844 | p = bios_signature(bios); | |
845 | if (p) { | |
846 | /* just use the first address */ | |
847 | apanel_addr = readb(p + 8 + 3) >> 1; | |
848 | } | |
849 | iounmap(bios); | |
850 | } | |
1561bfe5 | 851 | |
fa5bfab7 HG |
852 | struct dmi_onboard_device_info { |
853 | const char *name; | |
854 | u8 type; | |
855 | unsigned short i2c_addr; | |
856 | const char *i2c_type; | |
857 | }; | |
858 | ||
0b255e92 | 859 | static const struct dmi_onboard_device_info dmi_devices[] = { |
fa5bfab7 HG |
860 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, |
861 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
862 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
863 | }; | |
864 | ||
0b255e92 BP |
865 | static void dmi_check_onboard_device(u8 type, const char *name, |
866 | struct i2c_adapter *adap) | |
fa5bfab7 HG |
867 | { |
868 | int i; | |
869 | struct i2c_board_info info; | |
870 | ||
871 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
872 | /* & ~0x80, ignore enabled/disabled bit */ | |
873 | if ((type & ~0x80) != dmi_devices[i].type) | |
874 | continue; | |
faabd47f | 875 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
876 | continue; |
877 | ||
878 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
879 | info.addr = dmi_devices[i].i2c_addr; | |
880 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
881 | i2c_new_device(adap, &info); | |
882 | break; | |
883 | } | |
884 | } | |
885 | ||
886 | /* We use our own function to check for onboard devices instead of | |
887 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
888 | in marked as disabled */ | |
0b255e92 | 889 | static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) |
fa5bfab7 HG |
890 | { |
891 | int i, count; | |
892 | ||
893 | if (dm->type != 10) | |
894 | return; | |
895 | ||
896 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
897 | for (i = 0; i < count; i++) { | |
898 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
899 | const char *name = ((char *) dm) + dm->length; | |
900 | u8 type = d[0]; | |
901 | u8 s = d[1]; | |
902 | ||
903 | if (!s) | |
904 | continue; | |
905 | s--; | |
906 | while (s > 0 && name[0]) { | |
907 | name += strlen(name) + 1; | |
908 | s--; | |
909 | } | |
910 | if (name[0] == 0) /* Bogus string reference */ | |
911 | continue; | |
912 | ||
913 | dmi_check_onboard_device(type, name, adap); | |
914 | } | |
915 | } | |
fa5bfab7 | 916 | |
e7198fbf | 917 | /* Register optional slaves */ |
0b255e92 | 918 | static void i801_probe_optional_slaves(struct i801_priv *priv) |
e7198fbf JD |
919 | { |
920 | /* Only register slaves on main SMBus channel */ | |
921 | if (priv->features & FEATURE_IDF) | |
922 | return; | |
923 | ||
e7198fbf JD |
924 | if (apanel_addr) { |
925 | struct i2c_board_info info; | |
926 | ||
927 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
928 | info.addr = apanel_addr; | |
929 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
930 | i2c_new_device(&priv->adapter, &info); | |
931 | } | |
8eacfceb | 932 | |
e7198fbf JD |
933 | if (dmi_name_in_vendors("FUJITSU")) |
934 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 935 | } |
8eacfceb JD |
936 | #else |
937 | static void __init input_apanel_init(void) {} | |
0b255e92 | 938 | static void i801_probe_optional_slaves(struct i801_priv *priv) {} |
8eacfceb | 939 | #endif /* CONFIG_X86 && CONFIG_DMI */ |
e7198fbf | 940 | |
79e3e5b8 JD |
941 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
942 | defined CONFIG_DMI | |
3ad7ea18 JD |
943 | static struct i801_mux_config i801_mux_config_asus_z8_d12 = { |
944 | .gpio_chip = "gpio_ich", | |
945 | .values = { 0x02, 0x03 }, | |
946 | .n_values = 2, | |
947 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
948 | .gpios = { 52, 53 }, | |
949 | .n_gpios = 2, | |
950 | }; | |
951 | ||
952 | static struct i801_mux_config i801_mux_config_asus_z8_d18 = { | |
953 | .gpio_chip = "gpio_ich", | |
954 | .values = { 0x02, 0x03, 0x01 }, | |
955 | .n_values = 3, | |
956 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
957 | .gpios = { 52, 53 }, | |
958 | .n_gpios = 2, | |
959 | }; | |
960 | ||
0b255e92 | 961 | static const struct dmi_system_id mux_dmi_table[] = { |
3ad7ea18 JD |
962 | { |
963 | .matches = { | |
964 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
965 | DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), | |
966 | }, | |
967 | .driver_data = &i801_mux_config_asus_z8_d12, | |
968 | }, | |
969 | { | |
970 | .matches = { | |
971 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
972 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), | |
973 | }, | |
974 | .driver_data = &i801_mux_config_asus_z8_d12, | |
975 | }, | |
976 | { | |
977 | .matches = { | |
978 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
979 | DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), | |
980 | }, | |
981 | .driver_data = &i801_mux_config_asus_z8_d12, | |
982 | }, | |
983 | { | |
984 | .matches = { | |
985 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
986 | DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), | |
987 | }, | |
988 | .driver_data = &i801_mux_config_asus_z8_d12, | |
989 | }, | |
990 | { | |
991 | .matches = { | |
992 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
993 | DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), | |
994 | }, | |
995 | .driver_data = &i801_mux_config_asus_z8_d12, | |
996 | }, | |
997 | { | |
998 | .matches = { | |
999 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1000 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), | |
1001 | }, | |
1002 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1003 | }, | |
1004 | { | |
1005 | .matches = { | |
1006 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1007 | DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), | |
1008 | }, | |
1009 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1010 | }, | |
1011 | { | |
1012 | .matches = { | |
1013 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1014 | DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), | |
1015 | }, | |
1016 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1017 | }, | |
1018 | { | |
1019 | .matches = { | |
1020 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1021 | DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), | |
1022 | }, | |
1023 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1024 | }, | |
1025 | { } | |
1026 | }; | |
1027 | ||
3ad7ea18 | 1028 | /* Setup multiplexing if needed */ |
0b255e92 | 1029 | static int i801_add_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1030 | { |
1031 | struct device *dev = &priv->adapter.dev; | |
1032 | const struct i801_mux_config *mux_config; | |
3ad7ea18 | 1033 | struct i2c_mux_gpio_platform_data gpio_data; |
f82b8626 | 1034 | int err; |
3ad7ea18 JD |
1035 | |
1036 | if (!priv->mux_drvdata) | |
1037 | return 0; | |
1038 | mux_config = priv->mux_drvdata; | |
1039 | ||
3ad7ea18 JD |
1040 | /* Prepare the platform data */ |
1041 | memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); | |
1042 | gpio_data.parent = priv->adapter.nr; | |
1043 | gpio_data.values = mux_config->values; | |
1044 | gpio_data.n_values = mux_config->n_values; | |
1045 | gpio_data.classes = mux_config->classes; | |
f82b8626 JD |
1046 | gpio_data.gpio_chip = mux_config->gpio_chip; |
1047 | gpio_data.gpios = mux_config->gpios; | |
3ad7ea18 JD |
1048 | gpio_data.n_gpios = mux_config->n_gpios; |
1049 | gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; | |
1050 | ||
1051 | /* Register the mux device */ | |
1052 | priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", | |
f82b8626 | 1053 | PLATFORM_DEVID_AUTO, &gpio_data, |
3ad7ea18 JD |
1054 | sizeof(struct i2c_mux_gpio_platform_data)); |
1055 | if (IS_ERR(priv->mux_pdev)) { | |
1056 | err = PTR_ERR(priv->mux_pdev); | |
1057 | priv->mux_pdev = NULL; | |
1058 | dev_err(dev, "Failed to register i2c-mux-gpio device\n"); | |
1059 | return err; | |
1060 | } | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
0b255e92 | 1065 | static void i801_del_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1066 | { |
1067 | if (priv->mux_pdev) | |
1068 | platform_device_unregister(priv->mux_pdev); | |
1069 | } | |
1070 | ||
0b255e92 | 1071 | static unsigned int i801_get_adapter_class(struct i801_priv *priv) |
3ad7ea18 JD |
1072 | { |
1073 | const struct dmi_system_id *id; | |
1074 | const struct i801_mux_config *mux_config; | |
1075 | unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1076 | int i; | |
1077 | ||
1078 | id = dmi_first_match(mux_dmi_table); | |
1079 | if (id) { | |
28901f57 | 1080 | /* Remove branch classes from trunk */ |
3ad7ea18 JD |
1081 | mux_config = id->driver_data; |
1082 | for (i = 0; i < mux_config->n_values; i++) | |
1083 | class &= ~mux_config->classes[i]; | |
1084 | ||
1085 | /* Remember for later */ | |
1086 | priv->mux_drvdata = mux_config; | |
1087 | } | |
1088 | ||
1089 | return class; | |
1090 | } | |
1091 | #else | |
1092 | static inline int i801_add_mux(struct i801_priv *priv) { return 0; } | |
1093 | static inline void i801_del_mux(struct i801_priv *priv) { } | |
1094 | ||
1095 | static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) | |
1096 | { | |
1097 | return I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1098 | } | |
1099 | #endif | |
1100 | ||
0b255e92 | 1101 | static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 1102 | { |
02dd7ae2 | 1103 | unsigned char temp; |
adff687d | 1104 | int err, i; |
0cd96eb0 DW |
1105 | struct i801_priv *priv; |
1106 | ||
1107 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1108 | if (!priv) | |
1109 | return -ENOMEM; | |
1110 | ||
1111 | i2c_set_adapdata(&priv->adapter, priv); | |
1112 | priv->adapter.owner = THIS_MODULE; | |
3ad7ea18 | 1113 | priv->adapter.class = i801_get_adapter_class(priv); |
0cd96eb0 | 1114 | priv->adapter.algo = &smbus_algorithm; |
1da177e4 | 1115 | |
0cd96eb0 | 1116 | priv->pci_dev = dev; |
250d1bd3 | 1117 | switch (dev->device) { |
e7198fbf JD |
1118 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
1119 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
1120 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
a3fc0ff0 JR |
1121 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: |
1122 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: | |
1123 | case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: | |
e7198fbf JD |
1124 | priv->features |= FEATURE_IDF; |
1125 | /* fall through */ | |
e0e8398c | 1126 | default: |
0cd96eb0 | 1127 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6676a847 | 1128 | priv->features |= FEATURE_IRQ; |
6342064c JD |
1129 | /* fall through */ |
1130 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
1131 | priv->features |= FEATURE_SMBUS_PEC; |
1132 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
1133 | /* fall through */ |
1134 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
1135 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
1136 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
1137 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 1138 | break; |
250d1bd3 | 1139 | } |
02dd7ae2 | 1140 | |
adff687d JD |
1141 | /* Disable features on user request */ |
1142 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 1143 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
1144 | dev_notice(&dev->dev, "%s disabled by user\n", |
1145 | i801_feature_names[i]); | |
1146 | } | |
0cd96eb0 | 1147 | priv->features &= ~disable_features; |
adff687d | 1148 | |
02dd7ae2 JD |
1149 | err = pci_enable_device(dev); |
1150 | if (err) { | |
1151 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
1152 | err); | |
1153 | goto exit; | |
1154 | } | |
1155 | ||
1156 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
1157 | priv->smba = pci_resource_start(dev, SMBBAR); |
1158 | if (!priv->smba) { | |
02dd7ae2 JD |
1159 | dev_err(&dev->dev, "SMBus base address uninitialized, " |
1160 | "upgrade BIOS\n"); | |
1161 | err = -ENODEV; | |
d6fcb3b9 | 1162 | goto exit; |
02dd7ae2 JD |
1163 | } |
1164 | ||
54fb4a05 | 1165 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab JD |
1166 | if (err) { |
1167 | err = -ENODEV; | |
54fb4a05 | 1168 | goto exit; |
18669eab | 1169 | } |
54fb4a05 | 1170 | |
02dd7ae2 JD |
1171 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
1172 | if (err) { | |
1173 | dev_err(&dev->dev, "Failed to request SMBus region " | |
0cd96eb0 | 1174 | "0x%lx-0x%Lx\n", priv->smba, |
598736c5 | 1175 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
d6fcb3b9 | 1176 | goto exit; |
02dd7ae2 JD |
1177 | } |
1178 | ||
0cd96eb0 DW |
1179 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
1180 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
1181 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
1182 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
1183 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
1184 | temp |= SMBHSTCFG_HST_EN; | |
1185 | } | |
0cd96eb0 | 1186 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 | 1187 | |
636752bc | 1188 | if (temp & SMBHSTCFG_SMB_SMI_EN) { |
02dd7ae2 | 1189 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
636752bc DK |
1190 | /* Disable SMBus interrupt feature if SMBus using SMI# */ |
1191 | priv->features &= ~FEATURE_IRQ; | |
636752bc | 1192 | } |
1da177e4 | 1193 | |
a0921b6c | 1194 | /* Clear special mode bits */ |
0cd96eb0 DW |
1195 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
1196 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
1197 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 1198 | |
636752bc DK |
1199 | if (priv->features & FEATURE_IRQ) { |
1200 | init_waitqueue_head(&priv->waitq); | |
1201 | ||
1202 | err = request_irq(dev->irq, i801_isr, IRQF_SHARED, | |
1203 | i801_driver.name, priv); | |
1204 | if (err) { | |
1205 | dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", | |
1206 | dev->irq, err); | |
1207 | goto exit_release; | |
1208 | } | |
29b60854 | 1209 | dev_info(&dev->dev, "SMBus using PCI Interrupt\n"); |
636752bc DK |
1210 | } |
1211 | ||
405ae7d3 | 1212 | /* set up the sysfs linkage to our parent device */ |
0cd96eb0 | 1213 | priv->adapter.dev.parent = &dev->dev; |
1da177e4 | 1214 | |
7e2193a8 | 1215 | /* Retry up to 3 times on lost arbitration */ |
0cd96eb0 | 1216 | priv->adapter.retries = 3; |
7e2193a8 | 1217 | |
0cd96eb0 DW |
1218 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
1219 | "SMBus I801 adapter at %04lx", priv->smba); | |
1220 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
1221 | if (err) { |
1222 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
636752bc | 1223 | goto exit_free_irq; |
02dd7ae2 | 1224 | } |
1561bfe5 | 1225 | |
f6afc8b1 | 1226 | of_i2c_register_devices(&priv->adapter); |
e7198fbf | 1227 | i801_probe_optional_slaves(priv); |
3ad7ea18 JD |
1228 | /* We ignore errors - multiplexing is optional */ |
1229 | i801_add_mux(priv); | |
1561bfe5 | 1230 | |
0cd96eb0 | 1231 | pci_set_drvdata(dev, priv); |
636752bc | 1232 | |
d6fcb3b9 | 1233 | return 0; |
02dd7ae2 | 1234 | |
636752bc DK |
1235 | exit_free_irq: |
1236 | if (priv->features & FEATURE_IRQ) | |
1237 | free_irq(dev->irq, priv); | |
d6fcb3b9 DR |
1238 | exit_release: |
1239 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 | 1240 | exit: |
0cd96eb0 | 1241 | kfree(priv); |
02dd7ae2 | 1242 | return err; |
1da177e4 LT |
1243 | } |
1244 | ||
0b255e92 | 1245 | static void i801_remove(struct pci_dev *dev) |
1da177e4 | 1246 | { |
0cd96eb0 DW |
1247 | struct i801_priv *priv = pci_get_drvdata(dev); |
1248 | ||
3ad7ea18 | 1249 | i801_del_mux(priv); |
0cd96eb0 DW |
1250 | i2c_del_adapter(&priv->adapter); |
1251 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
636752bc DK |
1252 | |
1253 | if (priv->features & FEATURE_IRQ) | |
1254 | free_irq(dev->irq, priv); | |
6dcc19df | 1255 | pci_release_region(dev, SMBBAR); |
636752bc | 1256 | |
0cd96eb0 | 1257 | kfree(priv); |
d6fcb3b9 DR |
1258 | /* |
1259 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
1260 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
1261 | */ | |
1da177e4 LT |
1262 | } |
1263 | ||
a5aaea37 JD |
1264 | #ifdef CONFIG_PM |
1265 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
1266 | { | |
0cd96eb0 DW |
1267 | struct i801_priv *priv = pci_get_drvdata(dev); |
1268 | ||
a5aaea37 | 1269 | pci_save_state(dev); |
0cd96eb0 | 1270 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
1271 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | static int i801_resume(struct pci_dev *dev) | |
1276 | { | |
1277 | pci_set_power_state(dev, PCI_D0); | |
1278 | pci_restore_state(dev); | |
1279 | return pci_enable_device(dev); | |
1280 | } | |
1281 | #else | |
1282 | #define i801_suspend NULL | |
1283 | #define i801_resume NULL | |
1284 | #endif | |
1285 | ||
1da177e4 LT |
1286 | static struct pci_driver i801_driver = { |
1287 | .name = "i801_smbus", | |
1288 | .id_table = i801_ids, | |
1289 | .probe = i801_probe, | |
0b255e92 | 1290 | .remove = i801_remove, |
a5aaea37 JD |
1291 | .suspend = i801_suspend, |
1292 | .resume = i801_resume, | |
1da177e4 LT |
1293 | }; |
1294 | ||
1295 | static int __init i2c_i801_init(void) | |
1296 | { | |
6aa1464d JD |
1297 | if (dmi_name_in_vendors("FUJITSU")) |
1298 | input_apanel_init(); | |
1da177e4 LT |
1299 | return pci_register_driver(&i801_driver); |
1300 | } | |
1301 | ||
1302 | static void __exit i2c_i801_exit(void) | |
1303 | { | |
1304 | pci_unregister_driver(&i801_driver); | |
1305 | } | |
1306 | ||
6342064c JD |
1307 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, " |
1308 | "Jean Delvare <khali@linux-fr.org>"); | |
1da177e4 LT |
1309 | MODULE_DESCRIPTION("I801 SMBus driver"); |
1310 | MODULE_LICENSE("GPL"); | |
1311 | ||
1312 | module_init(i2c_i801_init); | |
1313 | module_exit(i2c_i801_exit); |