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i2c/busses: Use module_pci_driver
[linux-2.6-block.git] / drivers / i2c / busses / i2c-eg20t.c
CommitLineData
e9bc8fa5 1/*
8956dc10 2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
e9bc8fa5
TM		 3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/i2c.h>
24#include <linux/fs.h>
25#include <linux/io.h>
26#include <linux/types.h>
27#include <linux/interrupt.h>
28#include <linux/jiffies.h>
29#include <linux/pci.h>
30#include <linux/mutex.h>
31#include <linux/ktime.h>
6dbc2f35 32#include <linux/slab.h>
e9bc8fa5
TM		 33
34#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
35#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
36#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
37#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
38#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
39
40#define PCH_I2CSADR 0x00 /* I2C slave address register */
41#define PCH_I2CCTL 0x04 /* I2C control register */
42#define PCH_I2CSR 0x08 /* I2C status register */
43#define PCH_I2CDR 0x0C /* I2C data register */
44#define PCH_I2CMON 0x10 /* I2C bus monitor register */
45#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
46#define PCH_I2CMOD 0x18 /* I2C mode register */
47#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
48#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
49#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
50#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
51#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
52#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
53#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
54#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
55#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
56#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
57#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
58#define PCH_I2CTMR 0x48 /* I2C timer register */
59#define PCH_I2CSRST 0xFC /* I2C reset register */
60#define PCH_I2CNF 0xF8 /* I2C noise filter register */
61
62#define BUS_IDLE_TIMEOUT 20
63#define PCH_I2CCTL_I2CMEN 0x0080
64#define TEN_BIT_ADDR_DEFAULT 0xF000
65#define TEN_BIT_ADDR_MASK 0xF0
66#define PCH_START 0x0020
c249ac20 67#define PCH_RESTART 0x0004
e9bc8fa5
TM		 68#define PCH_ESR_START 0x0001
69#define PCH_BUFF_START 0x1
70#define PCH_REPSTART 0x0004
71#define PCH_ACK 0x0008
72#define PCH_GETACK 0x0001
73#define CLR_REG 0x0
74#define I2C_RD 0x1
75#define I2CMCF_BIT 0x0080
76#define I2CMIF_BIT 0x0002
77#define I2CMAL_BIT 0x0010
78#define I2CBMFI_BIT 0x0001
79#define I2CBMAL_BIT 0x0002
80#define I2CBMNA_BIT 0x0004
81#define I2CBMTO_BIT 0x0008
82#define I2CBMIS_BIT 0x0010
83#define I2CESRFI_BIT 0X0001
84#define I2CESRTO_BIT 0x0002
85#define I2CESRFIIE_BIT 0x1
86#define I2CESRTOIE_BIT 0x2
87#define I2CBMDZ_BIT 0x0040
88#define I2CBMAG_BIT 0x0020
89#define I2CMBB_BIT 0x0020
90#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
91 I2CBMTO_BIT | I2CBMIS_BIT)
92#define I2C_ADDR_MSK 0xFF
93#define I2C_MSB_2B_MSK 0x300
94#define FAST_MODE_CLK 400
95#define FAST_MODE_EN 0x0001
96#define SUB_ADDR_LEN_MAX 4
97#define BUF_LEN_MAX 32
98#define PCH_BUFFER_MODE 0x1
99#define EEPROM_SW_RST_MODE 0x0002
100#define NORMAL_INTR_ENBL 0x0300
101#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
102#define EEPROM_RST_INTR_DISBL 0x0
103#define BUFFER_MODE_INTR_ENBL 0x001F
104#define BUFFER_MODE_INTR_DISBL 0x0
105#define NORMAL_MODE 0x0
106#define BUFFER_MODE 0x1
107#define EEPROM_SR_MODE 0x2
108#define I2C_TX_MODE 0x0010
109#define PCH_BUF_TX 0xFFF7
110#define PCH_BUF_RD 0x0008
111#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
112 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
113#define I2CMAL_EVENT 0x0001
114#define I2CMCF_EVENT 0x0002
115#define I2CBMFI_EVENT 0x0004
116#define I2CBMAL_EVENT 0x0008
117#define I2CBMNA_EVENT 0x0010
118#define I2CBMTO_EVENT 0x0020
119#define I2CBMIS_EVENT 0x0040
120#define I2CESRFI_EVENT 0x0080
121#define I2CESRTO_EVENT 0x0100
122#define PCI_DEVICE_ID_PCH_I2C 0x8817
123
124#define pch_dbg(adap, fmt, arg...) \
125 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
126
127#define pch_err(adap, fmt, arg...) \
128 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
129
130#define pch_pci_err(pdev, fmt, arg...) \
131 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
132
133#define pch_pci_dbg(pdev, fmt, arg...) \
134 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
135
173442f2
TM		 136/*
137Set the number of I2C instance max
138Intel EG20T PCH : 1ch
8956dc10
TM		 139LAPIS Semiconductor ML7213 IOH : 2ch
140LAPIS Semiconductor ML7831 IOH : 1ch
173442f2
TM		 141*/
142#define PCH_I2C_MAX_DEV 2
143
e9bc8fa5
TM		 144/**
145 * struct i2c_algo_pch_data - for I2C driver functionalities
146 * @pch_adapter: stores the reference to i2c_adapter structure
147 * @p_adapter_info: stores the reference to adapter_info structure
148 * @pch_base_address: specifies the remapped base address
149 * @pch_buff_mode_en: specifies if buffer mode is enabled
150 * @pch_event_flag: specifies occurrence of interrupt events
151 * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
152 */
153struct i2c_algo_pch_data {
154 struct i2c_adapter pch_adapter;
155 struct adapter_info *p_adapter_info;
156 void __iomem *pch_base_address;
157 int pch_buff_mode_en;
158 u32 pch_event_flag;
159 bool pch_i2c_xfer_in_progress;
160};
161
162/**
163 * struct adapter_info - This structure holds the adapter information for the
164 PCH i2c controller
165 * @pch_data: stores a list of i2c_algo_pch_data
166 * @pch_i2c_suspended: specifies whether the system is suspended or not
167 * perhaps with more lines and words.
173442f2 168 * @ch_num: specifies the number of i2c instance
e9bc8fa5
TM		 169 *
170 * pch_data has as many elements as maximum I2C channels
171 */
172struct adapter_info {
173442f2 173 struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
e9bc8fa5 174 bool pch_i2c_suspended;
173442f2 175 int ch_num;
e9bc8fa5
TM		 176};
177
178
179static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
180static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
181static wait_queue_head_t pch_event;
182static DEFINE_MUTEX(pch_mutex);
183
8956dc10 184/* Definition for ML7213 by LAPIS Semiconductor */
173442f2
TM		 185#define PCI_VENDOR_ID_ROHM 0x10DB
186#define PCI_DEVICE_ID_ML7213_I2C 0x802D
efbe0f27 187#define PCI_DEVICE_ID_ML7223_I2C 0x8010
c3f4661f 188#define PCI_DEVICE_ID_ML7831_I2C 0x8817
173442f2 189
3527bd50 190static DEFINE_PCI_DEVICE_TABLE(pch_pcidev_id) = {
173442f2
TM		 191 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
192 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
efbe0f27 193 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
c3f4661f 194 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
e9bc8fa5
TM		 195 {0,}
196};
197
198static irqreturn_t pch_i2c_handler(int irq, void *pData);
199
200static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
201{
202 u32 val;
203 val = ioread32(addr + offset);
204 val |= bitmask;
205 iowrite32(val, addr + offset);
206}
207
208static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
209{
210 u32 val;
211 val = ioread32(addr + offset);
212 val &= (~bitmask);
213 iowrite32(val, addr + offset);
214}
215
216/**
217 * pch_i2c_init() - hardware initialization of I2C module
218 * @adap: Pointer to struct i2c_algo_pch_data.
219 */
220static void pch_i2c_init(struct i2c_algo_pch_data *adap)
221{
222 void __iomem *p = adap->pch_base_address;
223 u32 pch_i2cbc;
224 u32 pch_i2ctmr;
225 u32 reg_value;
226
227 /* reset I2C controller */
228 iowrite32(0x01, p + PCH_I2CSRST);
229 msleep(20);
230 iowrite32(0x0, p + PCH_I2CSRST);
231
232 /* Initialize I2C registers */
233 iowrite32(0x21, p + PCH_I2CNF);
234
173442f2 235 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
e9bc8fa5
TM		 236
237 if (pch_i2c_speed != 400)
238 pch_i2c_speed = 100;
239
240 reg_value = PCH_I2CCTL_I2CMEN;
241 if (pch_i2c_speed == FAST_MODE_CLK) {
242 reg_value |= FAST_MODE_EN;
243 pch_dbg(adap, "Fast mode enabled\n");
244 }
245
246 if (pch_clk > PCH_MAX_CLK)
247 pch_clk = 62500;
248
ff35e8b1 249 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
e9bc8fa5
TM		 250 /* Set transfer speed in I2CBC */
251 iowrite32(pch_i2cbc, p + PCH_I2CBC);
252
253 pch_i2ctmr = (pch_clk) / 8;
254 iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
255
256 reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
257 iowrite32(reg_value, p + PCH_I2CCTL);
258
259 pch_dbg(adap,
260 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
261 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
262
263 init_waitqueue_head(&pch_event);
264}
265
e9bc8fa5
TM		 266/**
267 * pch_i2c_wait_for_bus_idle() - check the status of bus.
268 * @adap: Pointer to struct i2c_algo_pch_data.
0836c809 269 * @timeout: waiting time counter (ms).
e9bc8fa5
TM		 270 */
271static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
173442f2 272 s32 timeout)
e9bc8fa5
TM		 273{
274 void __iomem *p = adap->pch_base_address;
0836c809
AS		 275 int schedule = 0;
276 unsigned long end = jiffies + msecs_to_jiffies(timeout);
277
278 while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
279 if (time_after(jiffies, end)) {
280 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
281 pch_err(adap, "%s: Timeout Error.return%d\n",
282 __func__, -ETIME);
283 pch_i2c_init(adap);
284
285 return -ETIME;
286 }
287
288 if (!schedule)
289 /* Retry after some usecs */
290 udelay(5);
291 else
292 /* Wait a bit more without consuming CPU */
293 usleep_range(20, 1000);
294
295 schedule = 1;
296 }
e9bc8fa5 297
0836c809 298 return 0;
e9bc8fa5
TM		 299}
300
301/**
302 * pch_i2c_start() - Generate I2C start condition in normal mode.
303 * @adap: Pointer to struct i2c_algo_pch_data.
304 *
305 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
306 */
307static void pch_i2c_start(struct i2c_algo_pch_data *adap)
308{
309 void __iomem *p = adap->pch_base_address;
310 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
311 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
312}
313
e9bc8fa5
TM		 314/**
315 * pch_i2c_getack() - to confirm ACK/NACK
316 * @adap: Pointer to struct i2c_algo_pch_data.
317 */
318static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
319{
320 u32 reg_val;
321 void __iomem *p = adap->pch_base_address;
322 reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
323
324 if (reg_val != 0) {
325 pch_err(adap, "return%d\n", -EPROTO);
326 return -EPROTO;
327 }
328
329 return 0;
330}
331
332/**
333 * pch_i2c_stop() - generate stop condition in normal mode.
334 * @adap: Pointer to struct i2c_algo_pch_data.
335 */
336static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
337{
338 void __iomem *p = adap->pch_base_address;
339 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
340 /* clear the start bit */
341 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
342}
343
5cc05632
TM		 344static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
345{
199bca2a
TM		 346 long ret;
347
348 ret = wait_event_timeout(pch_event,
349 (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
350 if (!ret) {
351 pch_err(adap, "%s:wait-event timeout\n", __func__);
352 adap->pch_event_flag = 0;
353 pch_i2c_stop(adap);
354 pch_i2c_init(adap);
355 return -ETIMEDOUT;
356 }
357
358 if (adap->pch_event_flag & I2C_ERROR_MASK) {
5cc05632 359 pch_err(adap, "Lost Arbitration\n");
199bca2a 360 adap->pch_event_flag = 0;
5cc05632
TM		 361 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
362 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
363 pch_i2c_init(adap);
364 return -EAGAIN;
199bca2a
TM		 365 }
366
367 adap->pch_event_flag = 0;
368
369 if (pch_i2c_getack(adap)) {
370 pch_dbg(adap, "Receive NACK for slave address"
371 "setting\n");
372 return -EIO;
5cc05632
TM		 373 }
374
375 return 0;
376}
377
e9bc8fa5
TM		 378/**
379 * pch_i2c_repstart() - generate repeated start condition in normal mode
380 * @adap: Pointer to struct i2c_algo_pch_data.
381 */
382static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
383{
384 void __iomem *p = adap->pch_base_address;
385 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
386 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
387}
388
389/**
390 * pch_i2c_writebytes() - write data to I2C bus in normal mode
391 * @i2c_adap: Pointer to the struct i2c_adapter.
392 * @last: specifies whether last message or not.
393 * In the case of compound mode it will be 1 for last message,
394 * otherwise 0.
395 * @first: specifies whether first message or not.
396 * 1 for first message otherwise 0.
397 */
398static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
399 struct i2c_msg *msgs, u32 last, u32 first)
400{
401 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
402 u8 *buf;
403 u32 length;
404 u32 addr;
405 u32 addr_2_msb;
406 u32 addr_8_lsb;
407 s32 wrcount;
12bd3146 408 s32 rtn;
e9bc8fa5
TM		 409 void __iomem *p = adap->pch_base_address;
410
411 length = msgs->len;
412 buf = msgs->buf;
413 addr = msgs->addr;
414
415 /* enable master tx */
416 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
417
418 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
419 length);
420
421 if (first) {
422 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
423 return -ETIME;
424 }
425
426 if (msgs->flags & I2C_M_TEN) {
c249ac20 427 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
e9bc8fa5
TM		 428 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
429 if (first)
430 pch_i2c_start(adap);
12bd3146 431
5cc05632
TM		 432 rtn = pch_i2c_wait_for_check_xfer(adap);
433 if (rtn)
434 return rtn;
435
436 addr_8_lsb = (addr & I2C_ADDR_MSK);
437 iowrite32(addr_8_lsb, p + PCH_I2CDR);
e9bc8fa5
TM		 438 } else {
439 /* set 7 bit slave address and R/W bit as 0 */
440 iowrite32(addr << 1, p + PCH_I2CDR);
441 if (first)
442 pch_i2c_start(adap);
443 }
444
5cc05632
TM		 445 rtn = pch_i2c_wait_for_check_xfer(adap);
446 if (rtn)
447 return rtn;
e9bc8fa5 448
12bd3146
TM		 449 for (wrcount = 0; wrcount < length; ++wrcount) {
450 /* write buffer value to I2C data register */
451 iowrite32(buf[wrcount], p + PCH_I2CDR);
452 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
e9bc8fa5 453
5cc05632
TM		 454 rtn = pch_i2c_wait_for_check_xfer(adap);
455 if (rtn)
456 return rtn;
457
458 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
459 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
12bd3146 460 }
e9bc8fa5 461
12bd3146
TM		 462 /* check if this is the last message */
463 if (last)
e9bc8fa5 464 pch_i2c_stop(adap);
12bd3146
TM		 465 else
466 pch_i2c_repstart(adap);
e9bc8fa5
TM		 467
468 pch_dbg(adap, "return=%d\n", wrcount);
469
470 return wrcount;
471}
472
473/**
474 * pch_i2c_sendack() - send ACK
475 * @adap: Pointer to struct i2c_algo_pch_data.
476 */
477static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
478{
479 void __iomem *p = adap->pch_base_address;
480 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
481 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
482}
483
484/**
485 * pch_i2c_sendnack() - send NACK
486 * @adap: Pointer to struct i2c_algo_pch_data.
487 */
488static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
489{
490 void __iomem *p = adap->pch_base_address;
491 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
492 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
493}
494
c249ac20
TM		 495/**
496 * pch_i2c_restart() - Generate I2C restart condition in normal mode.
497 * @adap: Pointer to struct i2c_algo_pch_data.
498 *
499 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
500 */
501static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
502{
503 void __iomem *p = adap->pch_base_address;
504 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
505 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
506}
507
e9bc8fa5
TM		 508/**
509 * pch_i2c_readbytes() - read data from I2C bus in normal mode.
510 * @i2c_adap: Pointer to the struct i2c_adapter.
511 * @msgs: Pointer to i2c_msg structure.
512 * @last: specifies whether last message or not.
513 * @first: specifies whether first message or not.
514 */
173442f2
TM		 515static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
516 u32 last, u32 first)
e9bc8fa5
TM		 517{
518 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
519
520 u8 *buf;
521 u32 count;
522 u32 length;
523 u32 addr;
524 u32 addr_2_msb;
c249ac20 525 u32 addr_8_lsb;
e9bc8fa5 526 void __iomem *p = adap->pch_base_address;
12bd3146 527 s32 rtn;
e9bc8fa5
TM		 528
529 length = msgs->len;
530 buf = msgs->buf;
531 addr = msgs->addr;
532
533 /* enable master reception */
534 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
535
536 if (first) {
537 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
538 return -ETIME;
539 }
540
541 if (msgs->flags & I2C_M_TEN) {
c249ac20 542 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
e9bc8fa5 543 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
c249ac20
TM		 544 if (first)
545 pch_i2c_start(adap);
e9bc8fa5 546
5cc05632
TM		 547 rtn = pch_i2c_wait_for_check_xfer(adap);
548 if (rtn)
549 return rtn;
550
551 addr_8_lsb = (addr & I2C_ADDR_MSK);
552 iowrite32(addr_8_lsb, p + PCH_I2CDR);
553
c249ac20 554 pch_i2c_restart(adap);
5cc05632
TM		 555
556 rtn = pch_i2c_wait_for_check_xfer(adap);
557 if (rtn)
558 return rtn;
559
560 addr_2_msb |= I2C_RD;
561 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
e9bc8fa5
TM		 562 } else {
563 /* 7 address bits + R/W bit */
564 addr = (((addr) << 1) | (I2C_RD));
565 iowrite32(addr, p + PCH_I2CDR);
566 }
567
568 /* check if it is the first message */
569 if (first)
570 pch_i2c_start(adap);
571
5cc05632
TM		 572 rtn = pch_i2c_wait_for_check_xfer(adap);
573 if (rtn)
574 return rtn;
e9bc8fa5 575
12bd3146
TM		 576 if (length == 0) {
577 pch_i2c_stop(adap);
578 ioread32(p + PCH_I2CDR); /* Dummy read needs */
e9bc8fa5 579
12bd3146
TM		 580 count = length;
581 } else {
582 int read_index;
583 int loop;
584 pch_i2c_sendack(adap);
e9bc8fa5 585
12bd3146
TM		 586 /* Dummy read */
587 for (loop = 1, read_index = 0; loop < length; loop++) {
588 buf[read_index] = ioread32(p + PCH_I2CDR);
e9bc8fa5 589
12bd3146
TM		 590 if (loop != 1)
591 read_index++;
e9bc8fa5 592
5cc05632
TM		 593 rtn = pch_i2c_wait_for_check_xfer(adap);
594 if (rtn)
595 return rtn;
12bd3146 596 } /* end for */
e9bc8fa5 597
12bd3146 598 pch_i2c_sendnack(adap);
e9bc8fa5 599
12bd3146 600 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
e9bc8fa5 601
12bd3146
TM		 602 if (length != 1)
603 read_index++;
e9bc8fa5 604
5cc05632
TM		 605 rtn = pch_i2c_wait_for_check_xfer(adap);
606 if (rtn)
607 return rtn;
12bd3146
TM		 608
609 if (last)
610 pch_i2c_stop(adap);
611 else
612 pch_i2c_repstart(adap);
613
614 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
615 count = read_index;
e9bc8fa5
TM		 616 }
617
618 return count;
619}
620
621/**
173442f2 622 * pch_i2c_cb() - Interrupt handler Call back function
e9bc8fa5
TM		 623 * @adap: Pointer to struct i2c_algo_pch_data.
624 */
173442f2 625static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
e9bc8fa5
TM		 626{
627 u32 sts;
628 void __iomem *p = adap->pch_base_address;
629
630 sts = ioread32(p + PCH_I2CSR);
631 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
632 if (sts & I2CMAL_BIT)
633 adap->pch_event_flag |= I2CMAL_EVENT;
634
635 if (sts & I2CMCF_BIT)
636 adap->pch_event_flag |= I2CMCF_EVENT;
637
638 /* clear the applicable bits */
639 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
640
641 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
642
643 wake_up(&pch_event);
644}
645
646/**
647 * pch_i2c_handler() - interrupt handler for the PCH I2C controller
648 * @irq: irq number.
649 * @pData: cookie passed back to the handler function.
650 */
651static irqreturn_t pch_i2c_handler(int irq, void *pData)
652{
173442f2
TM		 653 u32 reg_val;
654 int flag;
655 int i;
656 struct adapter_info *adap_info = pData;
657 void __iomem *p;
658 u32 mode;
659
660 for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
661 p = adap_info->pch_data[i].pch_base_address;
662 mode = ioread32(p + PCH_I2CMOD);
663 mode &= BUFFER_MODE | EEPROM_SR_MODE;
664 if (mode != NORMAL_MODE) {
665 pch_err(adap_info->pch_data,
666 "I2C-%d mode(%d) is not supported\n", mode, i);
667 continue;
668 }
669 reg_val = ioread32(p + PCH_I2CSR);
670 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
671 pch_i2c_cb(&adap_info->pch_data[i]);
672 flag = 1;
673 }
e9bc8fa5
TM		 674 }
675
173442f2 676 return flag ? IRQ_HANDLED : IRQ_NONE;
e9bc8fa5
TM		 677}
678
679/**
680 * pch_i2c_xfer() - Reading adnd writing data through I2C bus
681 * @i2c_adap: Pointer to the struct i2c_adapter.
682 * @msgs: Pointer to i2c_msg structure.
683 * @num: number of messages.
684 */
685static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
173442f2 686 struct i2c_msg *msgs, s32 num)
e9bc8fa5
TM		 687{
688 struct i2c_msg *pmsg;
689 u32 i = 0;
690 u32 status;
e9bc8fa5
TM		 691 s32 ret;
692
693 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
694
695 ret = mutex_lock_interruptible(&pch_mutex);
696 if (ret)
772ae99c 697 return ret;
e9bc8fa5
TM		 698
699 if (adap->p_adapter_info->pch_i2c_suspended) {
700 mutex_unlock(&pch_mutex);
701 return -EBUSY;
702 }
703
704 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
705 adap->p_adapter_info->pch_i2c_suspended);
706 /* transfer not completed */
707 adap->pch_i2c_xfer_in_progress = true;
708
07e729ce 709 for (i = 0; i < num && ret >= 0; i++) {
7a9c42cc
TM		 710 pmsg = &msgs[i];
711 pmsg->flags |= adap->pch_buff_mode_en;
712 status = pmsg->flags;
713 pch_dbg(adap,
714 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
7a9c42cc
TM		 715
716 if ((status & (I2C_M_RD)) != false) {
717 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
718 (i == 0));
719 } else {
720 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
721 (i == 0));
722 }
e9bc8fa5
TM		 723 }
724
725 adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
726
727 mutex_unlock(&pch_mutex);
728
07e729ce 729 return (ret < 0) ? ret : num;
e9bc8fa5
TM		 730}
731
732/**
733 * pch_i2c_func() - return the functionality of the I2C driver
734 * @adap: Pointer to struct i2c_algo_pch_data.
735 */
736static u32 pch_i2c_func(struct i2c_adapter *adap)
737{
738 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
739}
740
741static struct i2c_algorithm pch_algorithm = {
742 .master_xfer = pch_i2c_xfer,
743 .functionality = pch_i2c_func
744};
745
746/**
747 * pch_i2c_disbl_int() - Disable PCH I2C interrupts
748 * @adap: Pointer to struct i2c_algo_pch_data.
749 */
750static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
751{
752 void __iomem *p = adap->pch_base_address;
753
754 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
755
756 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
757
758 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
759}
760
761static int __devinit pch_i2c_probe(struct pci_dev *pdev,
173442f2 762 const struct pci_device_id *id)
e9bc8fa5
TM		 763{
764 void __iomem *base_addr;
173442f2
TM		 765 int ret;
766 int i, j;
e9bc8fa5 767 struct adapter_info *adap_info;
173442f2 768 struct i2c_adapter *pch_adap;
e9bc8fa5
TM		 769
770 pch_pci_dbg(pdev, "Entered.\n");
771
772 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
773 if (adap_info == NULL) {
774 pch_pci_err(pdev, "Memory allocation FAILED\n");
775 return -ENOMEM;
776 }
777
778 ret = pci_enable_device(pdev);
779 if (ret) {
780 pch_pci_err(pdev, "pci_enable_device FAILED\n");
781 goto err_pci_enable;
782 }
783
784 ret = pci_request_regions(pdev, KBUILD_MODNAME);
785 if (ret) {
786 pch_pci_err(pdev, "pci_request_regions FAILED\n");
787 goto err_pci_req;
788 }
789
790 base_addr = pci_iomap(pdev, 1, 0);
791
792 if (base_addr == NULL) {
793 pch_pci_err(pdev, "pci_iomap FAILED\n");
794 ret = -ENOMEM;
795 goto err_pci_iomap;
796 }
797
173442f2
TM		 798 /* Set the number of I2C channel instance */
799 adap_info->ch_num = id->driver_data;
e9bc8fa5 800
0d5fb5ea
FT		 801 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
802 KBUILD_MODNAME, adap_info);
803 if (ret) {
804 pch_pci_err(pdev, "request_irq FAILED\n");
805 goto err_request_irq;
806 }
807
173442f2
TM		 808 for (i = 0; i < adap_info->ch_num; i++) {
809 pch_adap = &adap_info->pch_data[i].pch_adapter;
810 adap_info->pch_i2c_suspended = false;
e9bc8fa5 811
173442f2 812 adap_info->pch_data[i].p_adapter_info = adap_info;
e9bc8fa5 813
173442f2
TM		 814 pch_adap->owner = THIS_MODULE;
815 pch_adap->class = I2C_CLASS_HWMON;
6188a376 816 strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
173442f2
TM		 817 pch_adap->algo = &pch_algorithm;
818 pch_adap->algo_data = &adap_info->pch_data[i];
e9bc8fa5 819
173442f2
TM		 820 /* base_addr + offset; */
821 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
e9bc8fa5 822
173442f2 823 pch_adap->dev.parent = &pdev->dev;
e9bc8fa5 824
0d5fb5ea 825 pch_i2c_init(&adap_info->pch_data[i]);
07e8a51f
FT		 826
827 pch_adap->nr = i;
828 ret = i2c_add_numbered_adapter(pch_adap);
173442f2
TM		 829 if (ret) {
830 pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
0d5fb5ea 831 goto err_add_adapter;
173442f2 832 }
e9bc8fa5
TM		 833 }
834
835 pci_set_drvdata(pdev, adap_info);
836 pch_pci_dbg(pdev, "returns %d.\n", ret);
837 return 0;
838
0d5fb5ea 839err_add_adapter:
173442f2
TM		 840 for (j = 0; j < i; j++)
841 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
0d5fb5ea
FT		 842 free_irq(pdev->irq, adap_info);
843err_request_irq:
e9bc8fa5
TM		 844 pci_iounmap(pdev, base_addr);
845err_pci_iomap:
846 pci_release_regions(pdev);
847err_pci_req:
848 pci_disable_device(pdev);
849err_pci_enable:
850 kfree(adap_info);
851 return ret;
852}
853
854static void __devexit pch_i2c_remove(struct pci_dev *pdev)
855{
173442f2 856 int i;
e9bc8fa5
TM		 857 struct adapter_info *adap_info = pci_get_drvdata(pdev);
858
173442f2 859 free_irq(pdev->irq, adap_info);
e9bc8fa5 860
173442f2
TM		 861 for (i = 0; i < adap_info->ch_num; i++) {
862 pch_i2c_disbl_int(&adap_info->pch_data[i]);
863 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
e9bc8fa5
TM		 864 }
865
173442f2
TM		 866 if (adap_info->pch_data[0].pch_base_address)
867 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
868
869 for (i = 0; i < adap_info->ch_num; i++)
75fb1f25 870 adap_info->pch_data[i].pch_base_address = NULL;
173442f2 871
e9bc8fa5
TM		 872 pci_set_drvdata(pdev, NULL);
873
874 pci_release_regions(pdev);
875
876 pci_disable_device(pdev);
877 kfree(adap_info);
878}
879
880#ifdef CONFIG_PM
881static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
882{
883 int ret;
173442f2 884 int i;
e9bc8fa5 885 struct adapter_info *adap_info = pci_get_drvdata(pdev);
173442f2 886 void __iomem *p = adap_info->pch_data[0].pch_base_address;
e9bc8fa5
TM		 887
888 adap_info->pch_i2c_suspended = true;
889
173442f2
TM		 890 for (i = 0; i < adap_info->ch_num; i++) {
891 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
892 /* Wait until all channel transfers are completed */
893 msleep(20);
894 }
e9bc8fa5 895 }
173442f2 896
e9bc8fa5 897 /* Disable the i2c interrupts */
173442f2
TM		 898 for (i = 0; i < adap_info->ch_num; i++)
899 pch_i2c_disbl_int(&adap_info->pch_data[i]);
e9bc8fa5
TM		 900
901 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
902 "invoked function pch_i2c_disbl_int successfully\n",
903 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
904 ioread32(p + PCH_I2CESRSTA));
905
906 ret = pci_save_state(pdev);
907
908 if (ret) {
909 pch_pci_err(pdev, "pci_save_state\n");
910 return ret;
911 }
912
913 pci_enable_wake(pdev, PCI_D3hot, 0);
914 pci_disable_device(pdev);
915 pci_set_power_state(pdev, pci_choose_state(pdev, state));
916
917 return 0;
918}
919
920static int pch_i2c_resume(struct pci_dev *pdev)
921{
173442f2 922 int i;
e9bc8fa5
TM		 923 struct adapter_info *adap_info = pci_get_drvdata(pdev);
924
925 pci_set_power_state(pdev, PCI_D0);
926 pci_restore_state(pdev);
927
928 if (pci_enable_device(pdev) < 0) {
929 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
930 return -EIO;
931 }
932
933 pci_enable_wake(pdev, PCI_D3hot, 0);
934
173442f2
TM		 935 for (i = 0; i < adap_info->ch_num; i++)
936 pch_i2c_init(&adap_info->pch_data[i]);
e9bc8fa5
TM		 937
938 adap_info->pch_i2c_suspended = false;
939
940 return 0;
941}
942#else
943#define pch_i2c_suspend NULL
944#define pch_i2c_resume NULL
945#endif
946
947static struct pci_driver pch_pcidriver = {
948 .name = KBUILD_MODNAME,
949 .id_table = pch_pcidev_id,
950 .probe = pch_i2c_probe,
951 .remove = __devexit_p(pch_i2c_remove),
952 .suspend = pch_i2c_suspend,
953 .resume = pch_i2c_resume
954};
955
56f21788 956module_pci_driver(pch_pcidriver);
e9bc8fa5 957
8956dc10 958MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
e9bc8fa5 959MODULE_LICENSE("GPL");
09640713 960MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
e9bc8fa5
TM		 961module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
962module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
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