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1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * ---------------------------------------------------------------------------- | |
26 | * | |
27 | */ | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/i2c.h> | |
32 | #include <linux/clk.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/io.h> | |
5a0e3ad6 | 39 | #include <linux/slab.h> |
1ab52cf9 BS |
40 | |
41 | /* | |
42 | * Registers offset | |
43 | */ | |
44 | #define DW_IC_CON 0x0 | |
45 | #define DW_IC_TAR 0x4 | |
46 | #define DW_IC_DATA_CMD 0x10 | |
47 | #define DW_IC_SS_SCL_HCNT 0x14 | |
48 | #define DW_IC_SS_SCL_LCNT 0x18 | |
49 | #define DW_IC_FS_SCL_HCNT 0x1c | |
50 | #define DW_IC_FS_SCL_LCNT 0x20 | |
51 | #define DW_IC_INTR_STAT 0x2c | |
52 | #define DW_IC_INTR_MASK 0x30 | |
e28000a3 | 53 | #define DW_IC_RAW_INTR_STAT 0x34 |
4cb6d1d6 SK |
54 | #define DW_IC_RX_TL 0x38 |
55 | #define DW_IC_TX_TL 0x3c | |
1ab52cf9 | 56 | #define DW_IC_CLR_INTR 0x40 |
e28000a3 SK |
57 | #define DW_IC_CLR_RX_UNDER 0x44 |
58 | #define DW_IC_CLR_RX_OVER 0x48 | |
59 | #define DW_IC_CLR_TX_OVER 0x4c | |
60 | #define DW_IC_CLR_RD_REQ 0x50 | |
61 | #define DW_IC_CLR_TX_ABRT 0x54 | |
62 | #define DW_IC_CLR_RX_DONE 0x58 | |
63 | #define DW_IC_CLR_ACTIVITY 0x5c | |
64 | #define DW_IC_CLR_STOP_DET 0x60 | |
65 | #define DW_IC_CLR_START_DET 0x64 | |
66 | #define DW_IC_CLR_GEN_CALL 0x68 | |
1ab52cf9 BS |
67 | #define DW_IC_ENABLE 0x6c |
68 | #define DW_IC_STATUS 0x70 | |
69 | #define DW_IC_TXFLR 0x74 | |
70 | #define DW_IC_RXFLR 0x78 | |
71 | #define DW_IC_COMP_PARAM_1 0xf4 | |
4ff895bc | 72 | #define DW_IC_COMP_TYPE 0xfc |
1ab52cf9 BS |
73 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
74 | ||
75 | #define DW_IC_CON_MASTER 0x1 | |
76 | #define DW_IC_CON_SPEED_STD 0x2 | |
77 | #define DW_IC_CON_SPEED_FAST 0x4 | |
78 | #define DW_IC_CON_10BITADDR_MASTER 0x10 | |
79 | #define DW_IC_CON_RESTART_EN 0x20 | |
80 | #define DW_IC_CON_SLAVE_DISABLE 0x40 | |
81 | ||
e28000a3 SK |
82 | #define DW_IC_INTR_RX_UNDER 0x001 |
83 | #define DW_IC_INTR_RX_OVER 0x002 | |
84 | #define DW_IC_INTR_RX_FULL 0x004 | |
85 | #define DW_IC_INTR_TX_OVER 0x008 | |
86 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
87 | #define DW_IC_INTR_RD_REQ 0x020 | |
88 | #define DW_IC_INTR_TX_ABRT 0x040 | |
89 | #define DW_IC_INTR_RX_DONE 0x080 | |
90 | #define DW_IC_INTR_ACTIVITY 0x100 | |
1ab52cf9 | 91 | #define DW_IC_INTR_STOP_DET 0x200 |
e28000a3 SK |
92 | #define DW_IC_INTR_START_DET 0x400 |
93 | #define DW_IC_INTR_GEN_CALL 0x800 | |
1ab52cf9 | 94 | |
201d6a70 SK |
95 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ |
96 | DW_IC_INTR_TX_EMPTY | \ | |
97 | DW_IC_INTR_TX_ABRT | \ | |
98 | DW_IC_INTR_STOP_DET) | |
99 | ||
1ab52cf9 BS |
100 | #define DW_IC_STATUS_ACTIVITY 0x1 |
101 | ||
102 | #define DW_IC_ERR_TX_ABRT 0x1 | |
103 | ||
104 | /* | |
105 | * status codes | |
106 | */ | |
107 | #define STATUS_IDLE 0x0 | |
108 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
109 | #define STATUS_READ_IN_PROGRESS 0x2 | |
110 | ||
111 | #define TIMEOUT 20 /* ms */ | |
112 | ||
113 | /* | |
114 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
115 | * | |
116 | * only expected abort codes are listed here | |
117 | * refer to the datasheet for the full list | |
118 | */ | |
119 | #define ABRT_7B_ADDR_NOACK 0 | |
120 | #define ABRT_10ADDR1_NOACK 1 | |
121 | #define ABRT_10ADDR2_NOACK 2 | |
122 | #define ABRT_TXDATA_NOACK 3 | |
123 | #define ABRT_GCALL_NOACK 4 | |
124 | #define ABRT_GCALL_READ 5 | |
125 | #define ABRT_SBYTE_ACKDET 7 | |
126 | #define ABRT_SBYTE_NORSTRT 9 | |
127 | #define ABRT_10B_RD_NORSTRT 10 | |
ce6eb574 | 128 | #define ABRT_MASTER_DIS 11 |
1ab52cf9 BS |
129 | #define ARB_LOST 12 |
130 | ||
ce6eb574 SK |
131 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) |
132 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | |
133 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | |
134 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | |
135 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | |
136 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | |
137 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | |
138 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | |
139 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | |
140 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | |
141 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | |
142 | ||
143 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | |
144 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | |
145 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | |
146 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | |
147 | DW_IC_TX_ABRT_GCALL_NOACK) | |
148 | ||
1ab52cf9 | 149 | static char *abort_sources[] = { |
a0e06ea6 | 150 | [ABRT_7B_ADDR_NOACK] = |
1ab52cf9 | 151 | "slave address not acknowledged (7bit mode)", |
a0e06ea6 | 152 | [ABRT_10ADDR1_NOACK] = |
1ab52cf9 | 153 | "first address byte not acknowledged (10bit mode)", |
a0e06ea6 | 154 | [ABRT_10ADDR2_NOACK] = |
1ab52cf9 | 155 | "second address byte not acknowledged (10bit mode)", |
a0e06ea6 | 156 | [ABRT_TXDATA_NOACK] = |
1ab52cf9 | 157 | "data not acknowledged", |
a0e06ea6 | 158 | [ABRT_GCALL_NOACK] = |
1ab52cf9 | 159 | "no acknowledgement for a general call", |
a0e06ea6 | 160 | [ABRT_GCALL_READ] = |
1ab52cf9 | 161 | "read after general call", |
a0e06ea6 | 162 | [ABRT_SBYTE_ACKDET] = |
1ab52cf9 | 163 | "start byte acknowledged", |
a0e06ea6 | 164 | [ABRT_SBYTE_NORSTRT] = |
1ab52cf9 | 165 | "trying to send start byte when restart is disabled", |
a0e06ea6 | 166 | [ABRT_10B_RD_NORSTRT] = |
1ab52cf9 | 167 | "trying to read when restart is disabled (10bit mode)", |
a0e06ea6 | 168 | [ABRT_MASTER_DIS] = |
1ab52cf9 | 169 | "trying to use disabled adapter", |
a0e06ea6 | 170 | [ARB_LOST] = |
1ab52cf9 BS |
171 | "lost arbitration", |
172 | }; | |
173 | ||
174 | /** | |
175 | * struct dw_i2c_dev - private i2c-designware data | |
176 | * @dev: driver model device node | |
177 | * @base: IO registers pointer | |
178 | * @cmd_complete: tx completion indicator | |
1ab52cf9 BS |
179 | * @lock: protect this struct and IO registers |
180 | * @clk: input reference clock | |
181 | * @cmd_err: run time hadware error code | |
25985edc | 182 | * @msgs: points to an array of messages currently being transferred |
1ab52cf9 BS |
183 | * @msgs_num: the number of elements in msgs |
184 | * @msg_write_idx: the element index of the current tx message in the msgs | |
185 | * array | |
186 | * @tx_buf_len: the length of the current tx buffer | |
187 | * @tx_buf: the current tx buffer | |
188 | * @msg_read_idx: the element index of the current rx message in the msgs | |
189 | * array | |
190 | * @rx_buf_len: the length of the current rx buffer | |
191 | * @rx_buf: the current rx buffer | |
192 | * @msg_err: error status of the current transfer | |
193 | * @status: i2c master status, one of STATUS_* | |
194 | * @abort_source: copy of the TX_ABRT_SOURCE register | |
195 | * @irq: interrupt number for the i2c master | |
196 | * @adapter: i2c subsystem adapter node | |
197 | * @tx_fifo_depth: depth of the hardware tx fifo | |
198 | * @rx_fifo_depth: depth of the hardware rx fifo | |
199 | */ | |
200 | struct dw_i2c_dev { | |
201 | struct device *dev; | |
202 | void __iomem *base; | |
203 | struct completion cmd_complete; | |
1ab52cf9 BS |
204 | struct mutex lock; |
205 | struct clk *clk; | |
206 | int cmd_err; | |
207 | struct i2c_msg *msgs; | |
208 | int msgs_num; | |
209 | int msg_write_idx; | |
ed5e1dd5 | 210 | u32 tx_buf_len; |
1ab52cf9 BS |
211 | u8 *tx_buf; |
212 | int msg_read_idx; | |
ed5e1dd5 | 213 | u32 rx_buf_len; |
1ab52cf9 BS |
214 | u8 *rx_buf; |
215 | int msg_err; | |
216 | unsigned int status; | |
ed5e1dd5 | 217 | u32 abort_source; |
1ab52cf9 BS |
218 | int irq; |
219 | struct i2c_adapter adapter; | |
220 | unsigned int tx_fifo_depth; | |
221 | unsigned int rx_fifo_depth; | |
222 | }; | |
223 | ||
7f279601 JHD |
224 | static u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
225 | { | |
226 | return readl(dev->base + offset); | |
227 | } | |
228 | ||
229 | static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) | |
230 | { | |
231 | writel(b, dev->base + offset); | |
232 | } | |
233 | ||
d60c7e81 SK |
234 | static u32 |
235 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
236 | { | |
237 | /* | |
238 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
239 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
240 | * will result in violation of the tHD;STA spec. | |
241 | */ | |
242 | if (cond) | |
243 | /* | |
244 | * Conditional expression: | |
245 | * | |
246 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
247 | * | |
248 | * This is based on the DW manuals, and represents an ideal | |
249 | * configuration. The resulting I2C bus speed will be | |
250 | * faster than any of the others. | |
251 | * | |
252 | * If your hardware is free from tHD;STA issue, try this one. | |
253 | */ | |
254 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; | |
255 | else | |
256 | /* | |
257 | * Conditional expression: | |
258 | * | |
259 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
260 | * | |
261 | * This is just experimental rule; the tHD;STA period turned | |
262 | * out to be proportinal to (_HCNT + 3). With this setting, | |
263 | * we could meet both tHIGH and tHD;STA timing specs. | |
264 | * | |
265 | * If unsure, you'd better to take this alternative. | |
266 | * | |
267 | * The reason why we need to take into account "tf" here, | |
268 | * is the same as described in i2c_dw_scl_lcnt(). | |
269 | */ | |
270 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; | |
271 | } | |
272 | ||
273 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
274 | { | |
275 | /* | |
276 | * Conditional expression: | |
277 | * | |
278 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
279 | * | |
280 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
281 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
282 | * In order to meet the tLOW timing spec, we need to take into | |
283 | * account the fall time of SCL signal (tf). Default tf value | |
284 | * should be 0.3 us, for safety. | |
285 | */ | |
286 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; | |
287 | } | |
288 | ||
1ab52cf9 BS |
289 | /** |
290 | * i2c_dw_init() - initialize the designware i2c master hardware | |
291 | * @dev: device private data | |
292 | * | |
293 | * This functions configures and enables the I2C master. | |
294 | * This function is called during I2C init function, and in case of timeout at | |
295 | * run time. | |
296 | */ | |
297 | static void i2c_dw_init(struct dw_i2c_dev *dev) | |
298 | { | |
299 | u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; | |
d60c7e81 | 300 | u32 ic_con, hcnt, lcnt; |
1ab52cf9 BS |
301 | |
302 | /* Disable the adapter */ | |
7f279601 | 303 | dw_writel(dev, 0, DW_IC_ENABLE); |
1ab52cf9 BS |
304 | |
305 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 SK |
306 | |
307 | /* Standard-mode */ | |
308 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
309 | 40, /* tHD;STA = tHIGH = 4.0 us */ | |
310 | 3, /* tf = 0.3 us */ | |
311 | 0, /* 0: DW default, 1: Ideal */ | |
312 | 0); /* No offset */ | |
313 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
314 | 47, /* tLOW = 4.7 us */ | |
315 | 3, /* tf = 0.3 us */ | |
316 | 0); /* No offset */ | |
7f279601 JHD |
317 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
318 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); | |
d60c7e81 SK |
319 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
320 | ||
321 | /* Fast-mode */ | |
322 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
323 | 6, /* tHD;STA = tHIGH = 0.6 us */ | |
324 | 3, /* tf = 0.3 us */ | |
325 | 0, /* 0: DW default, 1: Ideal */ | |
326 | 0); /* No offset */ | |
327 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
328 | 13, /* tLOW = 1.3 us */ | |
329 | 3, /* tf = 0.3 us */ | |
330 | 0); /* No offset */ | |
7f279601 JHD |
331 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
332 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); | |
d60c7e81 | 333 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
1ab52cf9 | 334 | |
4cb6d1d6 | 335 | /* Configure Tx/Rx FIFO threshold levels */ |
7f279601 JHD |
336 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
337 | dw_writel(dev, 0, DW_IC_RX_TL); | |
4cb6d1d6 | 338 | |
1ab52cf9 BS |
339 | /* configure the i2c master */ |
340 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | | |
341 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; | |
7f279601 | 342 | dw_writel(dev, ic_con, DW_IC_CON); |
1ab52cf9 BS |
343 | } |
344 | ||
345 | /* | |
346 | * Waiting for bus not busy | |
347 | */ | |
348 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
349 | { | |
350 | int timeout = TIMEOUT; | |
351 | ||
7f279601 | 352 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
353 | if (timeout <= 0) { |
354 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
355 | return -ETIMEDOUT; | |
356 | } | |
357 | timeout--; | |
358 | mdelay(1); | |
359 | } | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
81e798b7 SK |
364 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
365 | { | |
366 | struct i2c_msg *msgs = dev->msgs; | |
367 | u32 ic_con; | |
368 | ||
369 | /* Disable the adapter */ | |
7f279601 | 370 | dw_writel(dev, 0, DW_IC_ENABLE); |
81e798b7 SK |
371 | |
372 | /* set the slave (target) address */ | |
7f279601 | 373 | dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); |
81e798b7 SK |
374 | |
375 | /* if the slave address is ten bit address, enable 10BITADDR */ | |
7f279601 | 376 | ic_con = dw_readl(dev, DW_IC_CON); |
81e798b7 SK |
377 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
378 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
379 | else | |
380 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
7f279601 | 381 | dw_writel(dev, ic_con, DW_IC_CON); |
81e798b7 SK |
382 | |
383 | /* Enable the adapter */ | |
7f279601 | 384 | dw_writel(dev, 1, DW_IC_ENABLE); |
201d6a70 SK |
385 | |
386 | /* Enable interrupts */ | |
7f279601 | 387 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
81e798b7 SK |
388 | } |
389 | ||
1ab52cf9 | 390 | /* |
201d6a70 SK |
391 | * Initiate (and continue) low level master read/write transaction. |
392 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
393 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
394 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 BS |
395 | */ |
396 | static void | |
e77cf232 | 397 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 398 | { |
1ab52cf9 | 399 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 400 | u32 intr_mask; |
ae72222d | 401 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
402 | u32 addr = msgs[dev->msg_write_idx].addr; |
403 | u32 buf_len = dev->tx_buf_len; | |
69932487 | 404 | u8 *buf = dev->tx_buf; |
1ab52cf9 | 405 | |
201d6a70 | 406 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
c70c5cd3 | 407 | |
6d2ea487 | 408 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
a0e06ea6 SK |
409 | /* |
410 | * if target address has changed, we need to | |
1ab52cf9 BS |
411 | * reprogram the target address in the i2c |
412 | * adapter when we are done with this transfer | |
413 | */ | |
8f588e40 SK |
414 | if (msgs[dev->msg_write_idx].addr != addr) { |
415 | dev_err(dev->dev, | |
416 | "%s: invalid target address\n", __func__); | |
417 | dev->msg_err = -EINVAL; | |
418 | break; | |
419 | } | |
1ab52cf9 BS |
420 | |
421 | if (msgs[dev->msg_write_idx].len == 0) { | |
422 | dev_err(dev->dev, | |
423 | "%s: invalid message length\n", __func__); | |
424 | dev->msg_err = -EINVAL; | |
8f588e40 | 425 | break; |
1ab52cf9 BS |
426 | } |
427 | ||
428 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
429 | /* new i2c_msg */ | |
26ea15b1 | 430 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 BS |
431 | buf_len = msgs[dev->msg_write_idx].len; |
432 | } | |
433 | ||
7f279601 JHD |
434 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
435 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); | |
ae72222d | 436 | |
1ab52cf9 BS |
437 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
438 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { | |
7f279601 | 439 | dw_writel(dev, 0x100, DW_IC_DATA_CMD); |
1ab52cf9 BS |
440 | rx_limit--; |
441 | } else | |
7f279601 | 442 | dw_writel(dev, *buf++, DW_IC_DATA_CMD); |
1ab52cf9 BS |
443 | tx_limit--; buf_len--; |
444 | } | |
c70c5cd3 | 445 | |
26ea15b1 | 446 | dev->tx_buf = buf; |
c70c5cd3 SK |
447 | dev->tx_buf_len = buf_len; |
448 | ||
449 | if (buf_len > 0) { | |
450 | /* more bytes to be written */ | |
c70c5cd3 SK |
451 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
452 | break; | |
69151e53 | 453 | } else |
c70c5cd3 | 454 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
455 | } |
456 | ||
69151e53 SK |
457 | /* |
458 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
459 | * interrupt any more. | |
460 | */ | |
461 | if (dev->msg_write_idx == dev->msgs_num) | |
462 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
463 | ||
8f588e40 SK |
464 | if (dev->msg_err) |
465 | intr_mask = 0; | |
466 | ||
7f279601 | 467 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
1ab52cf9 BS |
468 | } |
469 | ||
470 | static void | |
78839bd0 | 471 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 472 | { |
1ab52cf9 | 473 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 474 | int rx_valid; |
1ab52cf9 | 475 | |
6d2ea487 | 476 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 477 | u32 len; |
1ab52cf9 BS |
478 | u8 *buf; |
479 | ||
480 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
481 | continue; | |
482 | ||
1ab52cf9 BS |
483 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
484 | len = msgs[dev->msg_read_idx].len; | |
485 | buf = msgs[dev->msg_read_idx].buf; | |
486 | } else { | |
487 | len = dev->rx_buf_len; | |
488 | buf = dev->rx_buf; | |
489 | } | |
490 | ||
7f279601 | 491 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
ae72222d | 492 | |
1ab52cf9 | 493 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
7f279601 | 494 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
1ab52cf9 BS |
495 | |
496 | if (len > 0) { | |
497 | dev->status |= STATUS_READ_IN_PROGRESS; | |
498 | dev->rx_buf_len = len; | |
499 | dev->rx_buf = buf; | |
500 | return; | |
501 | } else | |
502 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
503 | } | |
504 | } | |
505 | ||
ce6eb574 SK |
506 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
507 | { | |
508 | unsigned long abort_source = dev->abort_source; | |
509 | int i; | |
510 | ||
6d1ea0f6 | 511 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
984b3f57 | 512 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
6d1ea0f6 SK |
513 | dev_dbg(dev->dev, |
514 | "%s: %s\n", __func__, abort_sources[i]); | |
515 | return -EREMOTEIO; | |
516 | } | |
517 | ||
984b3f57 | 518 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
ce6eb574 SK |
519 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
520 | ||
521 | if (abort_source & DW_IC_TX_ARB_LOST) | |
522 | return -EAGAIN; | |
ce6eb574 SK |
523 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
524 | return -EINVAL; /* wrong msgs[] data */ | |
525 | else | |
526 | return -EIO; | |
527 | } | |
528 | ||
1ab52cf9 BS |
529 | /* |
530 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
531 | */ | |
532 | static int | |
533 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
534 | { | |
535 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
536 | int ret; | |
537 | ||
538 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
539 | ||
540 | mutex_lock(&dev->lock); | |
541 | ||
542 | INIT_COMPLETION(dev->cmd_complete); | |
543 | dev->msgs = msgs; | |
544 | dev->msgs_num = num; | |
545 | dev->cmd_err = 0; | |
546 | dev->msg_write_idx = 0; | |
547 | dev->msg_read_idx = 0; | |
548 | dev->msg_err = 0; | |
549 | dev->status = STATUS_IDLE; | |
ce6eb574 | 550 | dev->abort_source = 0; |
1ab52cf9 BS |
551 | |
552 | ret = i2c_dw_wait_bus_not_busy(dev); | |
553 | if (ret < 0) | |
554 | goto done; | |
555 | ||
556 | /* start the transfers */ | |
81e798b7 | 557 | i2c_dw_xfer_init(dev); |
1ab52cf9 BS |
558 | |
559 | /* wait for tx to complete */ | |
560 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); | |
561 | if (ret == 0) { | |
562 | dev_err(dev->dev, "controller timed out\n"); | |
563 | i2c_dw_init(dev); | |
564 | ret = -ETIMEDOUT; | |
565 | goto done; | |
566 | } else if (ret < 0) | |
567 | goto done; | |
568 | ||
569 | if (dev->msg_err) { | |
570 | ret = dev->msg_err; | |
571 | goto done; | |
572 | } | |
573 | ||
574 | /* no error */ | |
575 | if (likely(!dev->cmd_err)) { | |
07745399 | 576 | /* Disable the adapter */ |
7f279601 | 577 | dw_writel(dev, 0, DW_IC_ENABLE); |
1ab52cf9 BS |
578 | ret = num; |
579 | goto done; | |
580 | } | |
581 | ||
582 | /* We have an error */ | |
583 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
584 | ret = i2c_dw_handle_tx_abort(dev); |
585 | goto done; | |
1ab52cf9 BS |
586 | } |
587 | ret = -EIO; | |
588 | ||
589 | done: | |
590 | mutex_unlock(&dev->lock); | |
591 | ||
592 | return ret; | |
593 | } | |
594 | ||
595 | static u32 i2c_dw_func(struct i2c_adapter *adap) | |
596 | { | |
52d7e430 SK |
597 | return I2C_FUNC_I2C | |
598 | I2C_FUNC_10BIT_ADDR | | |
599 | I2C_FUNC_SMBUS_BYTE | | |
600 | I2C_FUNC_SMBUS_BYTE_DATA | | |
601 | I2C_FUNC_SMBUS_WORD_DATA | | |
602 | I2C_FUNC_SMBUS_I2C_BLOCK; | |
1ab52cf9 BS |
603 | } |
604 | ||
e28000a3 SK |
605 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
606 | { | |
607 | u32 stat; | |
608 | ||
609 | /* | |
610 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
611 | * Ths unmasked raw version of interrupt status bits are available | |
612 | * in the IC_RAW_INTR_STAT register. | |
613 | * | |
614 | * That is, | |
615 | * stat = readl(IC_INTR_STAT); | |
616 | * equals to, | |
617 | * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); | |
618 | * | |
619 | * The raw version might be useful for debugging purposes. | |
620 | */ | |
7f279601 | 621 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
e28000a3 SK |
622 | |
623 | /* | |
624 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
625 | * you'll miss some interrupts, triggered during the period from | |
626 | * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). | |
627 | * | |
628 | * Instead, use the separately-prepared IC_CLR_* registers. | |
629 | */ | |
630 | if (stat & DW_IC_INTR_RX_UNDER) | |
7f279601 | 631 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
e28000a3 | 632 | if (stat & DW_IC_INTR_RX_OVER) |
7f279601 | 633 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
e28000a3 | 634 | if (stat & DW_IC_INTR_TX_OVER) |
7f279601 | 635 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
e28000a3 | 636 | if (stat & DW_IC_INTR_RD_REQ) |
7f279601 | 637 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
e28000a3 SK |
638 | if (stat & DW_IC_INTR_TX_ABRT) { |
639 | /* | |
640 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
641 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
642 | */ | |
7f279601 JHD |
643 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
644 | dw_readl(dev, DW_IC_CLR_TX_ABRT); | |
e28000a3 SK |
645 | } |
646 | if (stat & DW_IC_INTR_RX_DONE) | |
7f279601 | 647 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
e28000a3 | 648 | if (stat & DW_IC_INTR_ACTIVITY) |
7f279601 | 649 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
e28000a3 | 650 | if (stat & DW_IC_INTR_STOP_DET) |
7f279601 | 651 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
e28000a3 | 652 | if (stat & DW_IC_INTR_START_DET) |
7f279601 | 653 | dw_readl(dev, DW_IC_CLR_START_DET); |
e28000a3 | 654 | if (stat & DW_IC_INTR_GEN_CALL) |
7f279601 | 655 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
e28000a3 SK |
656 | |
657 | return stat; | |
658 | } | |
659 | ||
1ab52cf9 BS |
660 | /* |
661 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
662 | * occurs. | |
663 | */ | |
664 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) | |
665 | { | |
666 | struct dw_i2c_dev *dev = dev_id; | |
ed5e1dd5 | 667 | u32 stat; |
1ab52cf9 | 668 | |
e28000a3 | 669 | stat = i2c_dw_read_clear_intrbits(dev); |
1ab52cf9 | 670 | dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); |
e28000a3 | 671 | |
1ab52cf9 | 672 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
673 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
674 | dev->status = STATUS_IDLE; | |
597fe310 SK |
675 | |
676 | /* | |
677 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
678 | * buffers are flushed. Make sure to skip them. | |
679 | */ | |
7f279601 | 680 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
597fe310 | 681 | goto tx_aborted; |
07745399 SK |
682 | } |
683 | ||
21a89d41 | 684 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 685 | i2c_dw_read(dev); |
21a89d41 SK |
686 | |
687 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 688 | i2c_dw_xfer_msg(dev); |
07745399 SK |
689 | |
690 | /* | |
691 | * No need to modify or disable the interrupt mask here. | |
692 | * i2c_dw_xfer_msg() will take care of it according to | |
693 | * the current transmit status. | |
694 | */ | |
1ab52cf9 | 695 | |
597fe310 | 696 | tx_aborted: |
8f588e40 | 697 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 BS |
698 | complete(&dev->cmd_complete); |
699 | ||
700 | return IRQ_HANDLED; | |
701 | } | |
702 | ||
703 | static struct i2c_algorithm i2c_dw_algo = { | |
704 | .master_xfer = i2c_dw_xfer, | |
705 | .functionality = i2c_dw_func, | |
706 | }; | |
707 | ||
708 | static int __devinit dw_i2c_probe(struct platform_device *pdev) | |
709 | { | |
710 | struct dw_i2c_dev *dev; | |
711 | struct i2c_adapter *adap; | |
91b52cae SK |
712 | struct resource *mem, *ioarea; |
713 | int irq, r; | |
4ff895bc | 714 | u32 reg; |
1ab52cf9 BS |
715 | |
716 | /* NOTE: driver uses the static register mapping */ | |
717 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
718 | if (!mem) { | |
719 | dev_err(&pdev->dev, "no mem resource?\n"); | |
720 | return -EINVAL; | |
721 | } | |
722 | ||
91b52cae SK |
723 | irq = platform_get_irq(pdev, 0); |
724 | if (irq < 0) { | |
1ab52cf9 | 725 | dev_err(&pdev->dev, "no irq resource?\n"); |
91b52cae | 726 | return irq; /* -ENXIO */ |
1ab52cf9 BS |
727 | } |
728 | ||
729 | ioarea = request_mem_region(mem->start, resource_size(mem), | |
730 | pdev->name); | |
731 | if (!ioarea) { | |
732 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
733 | return -EBUSY; | |
734 | } | |
735 | ||
736 | dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL); | |
737 | if (!dev) { | |
738 | r = -ENOMEM; | |
739 | goto err_release_region; | |
740 | } | |
741 | ||
742 | init_completion(&dev->cmd_complete); | |
1ab52cf9 BS |
743 | mutex_init(&dev->lock); |
744 | dev->dev = get_device(&pdev->dev); | |
91b52cae | 745 | dev->irq = irq; |
1ab52cf9 BS |
746 | platform_set_drvdata(pdev, dev); |
747 | ||
748 | dev->clk = clk_get(&pdev->dev, NULL); | |
749 | if (IS_ERR(dev->clk)) { | |
750 | r = -ENODEV; | |
751 | goto err_free_mem; | |
752 | } | |
753 | clk_enable(dev->clk); | |
754 | ||
755 | dev->base = ioremap(mem->start, resource_size(mem)); | |
756 | if (dev->base == NULL) { | |
757 | dev_err(&pdev->dev, "failure mapping io resources\n"); | |
758 | r = -EBUSY; | |
759 | goto err_unuse_clocks; | |
760 | } | |
1ab52cf9 | 761 | |
4ff895bc JHD |
762 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
763 | if (reg != 0x44570140) { | |
764 | dev_err(&pdev->dev, "Unknown Synopsys component type: " | |
765 | "0x%08x\n", reg); | |
766 | r = -ENODEV; | |
767 | goto err_iounmap; | |
1ab52cf9 | 768 | } |
4ff895bc JHD |
769 | |
770 | reg = dw_readl(dev, DW_IC_COMP_PARAM_1); | |
771 | dev->tx_fifo_depth = ((reg >> 16) & 0xff) + 1; | |
772 | dev->rx_fifo_depth = ((reg >> 8) & 0xff) + 1; | |
773 | ||
1ab52cf9 BS |
774 | i2c_dw_init(dev); |
775 | ||
7f279601 | 776 | dw_writel(dev, 0, DW_IC_INTR_MASK); /* disable IRQ */ |
201d6a70 | 777 | r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev); |
1ab52cf9 BS |
778 | if (r) { |
779 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); | |
780 | goto err_iounmap; | |
781 | } | |
782 | ||
783 | adap = &dev->adapter; | |
784 | i2c_set_adapdata(adap, dev); | |
785 | adap->owner = THIS_MODULE; | |
786 | adap->class = I2C_CLASS_HWMON; | |
787 | strlcpy(adap->name, "Synopsys DesignWare I2C adapter", | |
788 | sizeof(adap->name)); | |
789 | adap->algo = &i2c_dw_algo; | |
790 | adap->dev.parent = &pdev->dev; | |
791 | ||
792 | adap->nr = pdev->id; | |
793 | r = i2c_add_numbered_adapter(adap); | |
794 | if (r) { | |
795 | dev_err(&pdev->dev, "failure adding adapter\n"); | |
796 | goto err_free_irq; | |
797 | } | |
798 | ||
799 | return 0; | |
800 | ||
801 | err_free_irq: | |
802 | free_irq(dev->irq, dev); | |
803 | err_iounmap: | |
804 | iounmap(dev->base); | |
805 | err_unuse_clocks: | |
806 | clk_disable(dev->clk); | |
807 | clk_put(dev->clk); | |
808 | dev->clk = NULL; | |
809 | err_free_mem: | |
810 | platform_set_drvdata(pdev, NULL); | |
811 | put_device(&pdev->dev); | |
812 | kfree(dev); | |
813 | err_release_region: | |
814 | release_mem_region(mem->start, resource_size(mem)); | |
815 | ||
816 | return r; | |
817 | } | |
818 | ||
819 | static int __devexit dw_i2c_remove(struct platform_device *pdev) | |
820 | { | |
821 | struct dw_i2c_dev *dev = platform_get_drvdata(pdev); | |
822 | struct resource *mem; | |
823 | ||
824 | platform_set_drvdata(pdev, NULL); | |
825 | i2c_del_adapter(&dev->adapter); | |
826 | put_device(&pdev->dev); | |
827 | ||
828 | clk_disable(dev->clk); | |
829 | clk_put(dev->clk); | |
830 | dev->clk = NULL; | |
831 | ||
7f279601 | 832 | dw_writel(dev, 0, DW_IC_ENABLE); |
1ab52cf9 BS |
833 | free_irq(dev->irq, dev); |
834 | kfree(dev); | |
835 | ||
836 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
837 | release_mem_region(mem->start, resource_size(mem)); | |
838 | return 0; | |
839 | } | |
840 | ||
841 | /* work with hotplug and coldplug */ | |
842 | MODULE_ALIAS("platform:i2c_designware"); | |
843 | ||
844 | static struct platform_driver dw_i2c_driver = { | |
845 | .remove = __devexit_p(dw_i2c_remove), | |
846 | .driver = { | |
847 | .name = "i2c_designware", | |
848 | .owner = THIS_MODULE, | |
849 | }, | |
850 | }; | |
851 | ||
852 | static int __init dw_i2c_init_driver(void) | |
853 | { | |
854 | return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); | |
855 | } | |
856 | module_init(dw_i2c_init_driver); | |
857 | ||
858 | static void __exit dw_i2c_exit_driver(void) | |
859 | { | |
860 | platform_driver_unregister(&dw_i2c_driver); | |
861 | } | |
862 | module_exit(dw_i2c_exit_driver); | |
863 | ||
864 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); | |
865 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter"); | |
866 | MODULE_LICENSE("GPL"); |