[linux-2.6-block.git] / drivers / i2c / busses / i2c-designware-pcidrv.c

/*
 * Synopsys DesignWare I2C adapter driver (master only).
 *
 * Based on the TI DAVINCI I2C adapter driver.
 *
 * Copyright (C) 2006 Texas Instruments.
 * Copyright (C) 2007 MontaVista Software Inc.
 * Copyright (C) 2009 Provigent Ltd.
 * Copyright (C) 2011, 2015, 2016 Intel Corporation.
 *
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * ----------------------------------------------------------------------------
 *
 */

#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include <linux/sched.h>
#include <linux/slab.h>

#include "i2c-designware-core.h"

#define DRIVER_NAME "i2c-designware-pci"

enum dw_pci_ctl_id_t {
	medfield,
	merrifield,
	baytrail,
	cherrytrail,
	haswell,
};

struct dw_scl_sda_cfg {
	u32 ss_hcnt;
	u32 fs_hcnt;
	u32 ss_lcnt;
	u32 fs_lcnt;
	u32 sda_hold;
};

struct dw_pci_controller {
	u32 bus_num;
	u32 bus_cfg;
	u32 tx_fifo_depth;
	u32 rx_fifo_depth;
	u32 clk_khz;
	u32 functionality;
	u32 flags;
	struct dw_scl_sda_cfg *scl_sda_cfg;
	int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
};

#define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER |			\
				DW_IC_CON_SLAVE_DISABLE |	\
				DW_IC_CON_RESTART_EN)

/* Merrifield HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg mrfld_config = {
	.ss_hcnt = 0x2f8,
	.fs_hcnt = 0x87,
	.ss_lcnt = 0x37b,
	.fs_lcnt = 0x10a,
};

/* BayTrail HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg byt_config = {
	.ss_hcnt = 0x200,
	.fs_hcnt = 0x55,
	.ss_lcnt = 0x200,
	.fs_lcnt = 0x99,
	.sda_hold = 0x6,
};

/* Haswell HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg hsw_config = {
	.ss_hcnt = 0x01b0,
	.fs_hcnt = 0x48,
	.ss_lcnt = 0x01fb,
	.fs_lcnt = 0xa0,
	.sda_hold = 0x9,
};

static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
{
	switch (pdev->device) {
	case 0x0817:
		c->bus_cfg &= ~DW_IC_CON_SPEED_MASK;
		c->bus_cfg |= DW_IC_CON_SPEED_STD;
	case 0x0818:
	case 0x0819:
		c->bus_num = pdev->device - 0x817 + 3;
		return 0;
	case 0x082C:
	case 0x082D:
	case 0x082E:
		c->bus_num = pdev->device - 0x82C + 0;
		return 0;
	}
	return -ENODEV;
}

static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
{
	/*
	 * On Intel Merrifield the user visible i2c busses are enumerated
	 * [1..7]. So, we add 1 to shift the default range. Besides that the
	 * first PCI slot provides 4 functions, that's why we have to add 0 to
	 * the first slot and 4 to the next one.
	 */
	switch (PCI_SLOT(pdev->devfn)) {
	case 8:
		c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
		return 0;
	case 9:
		c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
		return 0;
	}
	return -ENODEV;
}

static struct dw_pci_controller dw_pci_controllers[] = {
	[medfield] = {
		.bus_num = -1,
		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.functionality = I2C_FUNC_10BIT_ADDR,
		.clk_khz      = 25000,
		.setup = mfld_setup,
	},
	[merrifield] = {
		.bus_num = -1,
		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 64,
		.rx_fifo_depth = 64,
		.functionality = I2C_FUNC_10BIT_ADDR,
		.scl_sda_cfg = &mrfld_config,
		.setup = mrfld_setup,
	},
	[baytrail] = {
		.bus_num = -1,
		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.functionality = I2C_FUNC_10BIT_ADDR,
		.scl_sda_cfg = &byt_config,
	},
	[haswell] = {
		.bus_num = -1,
		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.functionality = I2C_FUNC_10BIT_ADDR,
		.scl_sda_cfg = &hsw_config,
	},
	[cherrytrail] = {
		.bus_num = -1,
		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
		.tx_fifo_depth = 32,
		.rx_fifo_depth = 32,
		.functionality = I2C_FUNC_10BIT_ADDR,
		.flags = MODEL_CHERRYTRAIL,
		.scl_sda_cfg = &byt_config,
	},
};

#ifdef CONFIG_PM
static int i2c_dw_pci_suspend(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);

	i_dev->disable(i_dev);

	return 0;
}

static int i2c_dw_pci_resume(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);

	return i_dev->init(i_dev);
}
#endif

static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
			    i2c_dw_pci_resume, NULL);

static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
{
	return dev->controller->clk_khz;
}

static int i2c_dw_pci_probe(struct pci_dev *pdev,
			    const struct pci_device_id *id)
{
	struct dw_i2c_dev *dev;
	struct i2c_adapter *adap;
	int r;
	struct dw_pci_controller *controller;
	struct dw_scl_sda_cfg *cfg;

	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
		dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
			id->driver_data);
		return -EINVAL;
	}

	controller = &dw_pci_controllers[id->driver_data];

	r = pcim_enable_device(pdev);
	if (r) {
		dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
			r);
		return r;
	}

	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
	if (r) {
		dev_err(&pdev->dev, "I/O memory remapping failed\n");
		return r;
	}

	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
	if (!dev)
		return -ENOMEM;

	dev->clk = NULL;
	dev->controller = controller;
	dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
	dev->base = pcim_iomap_table(pdev)[0];
	dev->dev = &pdev->dev;
	dev->irq = pdev->irq;
	dev->flags |= controller->flags;

	if (controller->setup) {
		r = controller->setup(pdev, controller);
		if (r)
			return r;
	}

	dev->functionality = controller->functionality |
				DW_IC_DEFAULT_FUNCTIONALITY;

	dev->master_cfg = controller->bus_cfg;
	if (controller->scl_sda_cfg) {
		cfg = controller->scl_sda_cfg;
		dev->ss_hcnt = cfg->ss_hcnt;
		dev->fs_hcnt = cfg->fs_hcnt;
		dev->ss_lcnt = cfg->ss_lcnt;
		dev->fs_lcnt = cfg->fs_lcnt;
		dev->sda_hold_time = cfg->sda_hold;
	}

	pci_set_drvdata(pdev, dev);

	dev->tx_fifo_depth = controller->tx_fifo_depth;
	dev->rx_fifo_depth = controller->rx_fifo_depth;

	adap = &dev->adapter;
	adap->owner = THIS_MODULE;
	adap->class = 0;
	ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
	adap->nr = controller->bus_num;

	r = i2c_dw_probe(dev);
	if (r)
		return r;

	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_put_autosuspend(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static void i2c_dw_pci_remove(struct pci_dev *pdev)
{
	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);

	dev->disable(dev);
	pm_runtime_forbid(&pdev->dev);
	pm_runtime_get_noresume(&pdev->dev);

	i2c_del_adapter(&dev->adapter);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("i2c_designware-pci");

static const struct pci_device_id i2_designware_pci_ids[] = {
	/* Medfield */
	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
	{ PCI_VDEVICE(INTEL, 0x082C), medfield },
	{ PCI_VDEVICE(INTEL, 0x082D), medfield },
	{ PCI_VDEVICE(INTEL, 0x082E), medfield },
	/* Merrifield */
	{ PCI_VDEVICE(INTEL, 0x1195), merrifield },
	{ PCI_VDEVICE(INTEL, 0x1196), merrifield },
	/* Baytrail */
	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
	/* Haswell */
	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
	/* Braswell / Cherrytrail */
	{ PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
	{ PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
	{ PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
	{ PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
	{ PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
	{ PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
	{ PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
	{ 0,}
};
MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);

static struct pci_driver dw_i2c_driver = {
	.name		= DRIVER_NAME,
	.id_table	= i2_designware_pci_ids,
	.probe		= i2c_dw_pci_probe,
	.remove		= i2c_dw_pci_remove,
	.driver         = {
		.pm     = &i2c_dw_pm_ops,
	},
};

module_pci_driver(dw_i2c_driver);

MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
MODULE_LICENSE("GPL");
Commit	Line	Data
fe20ff5c DB	1	/*
	2	* Synopsys DesignWare I2C adapter driver (master only).
	3	*
	4	* Based on the TI DAVINCI I2C adapter driver.
	5	*
	6	* Copyright (C) 2006 Texas Instruments.
	7	* Copyright (C) 2007 MontaVista Software Inc.
	8	* Copyright (C) 2009 Provigent Ltd.
45bc35ef	9	* Copyright (C) 2011, 2015, 2016 Intel Corporation.
fe20ff5c DB	10	*
	11	* ----------------------------------------------------------------------------
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2 of the License, or
	16	* (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
fe20ff5c DB	22	* ----------------------------------------------------------------------------
	23	*
	24	*/
	25
45bc35ef	26	#include <linux/acpi.h>
fe20ff5c	27	#include <linux/delay.h>
fe20ff5c	28	#include <linux/err.h>
45bc35ef AS	29	#include <linux/errno.h>
45bc35ef AS	30	#include <linux/i2c.h>
fe20ff5c DB	31	#include <linux/interrupt.h>
fe20ff5c DB	32	#include <linux/io.h>
45bc35ef AS	33	#include <linux/kernel.h>
45bc35ef AS	34	#include <linux/module.h>
fe20ff5c	35	#include <linux/pci.h>
18dbdda8	36	#include <linux/pm_runtime.h>
45bc35ef AS	37	#include <linux/sched.h>
	38	#include <linux/slab.h>
	39
fe20ff5c DB	40	#include "i2c-designware-core.h"
	41
	42	#define DRIVER_NAME "i2c-designware-pci"
	43
	44	enum dw_pci_ctl_id_t {
ed1bf034	45	medfield,
b20551c1	46	merrifield,
089c729a	47	baytrail,
fd476fa2	48	cherrytrail,
157a801e	49	haswell,
fe20ff5c DB	50	};
fe20ff5c DB	51
8efd1e9e CCE	52	struct dw_scl_sda_cfg {
	53	u32 ss_hcnt;
	54	u32 fs_hcnt;
	55	u32 ss_lcnt;
	56	u32 fs_lcnt;
	57	u32 sda_hold;
	58	};
	59
fe20ff5c DB	60	struct dw_pci_controller {
	61	u32 bus_num;
	62	u32 bus_cfg;
	63	u32 tx_fifo_depth;
	64	u32 rx_fifo_depth;
	65	u32 clk_khz;
ceccd298	66	u32 functionality;
fd476fa2	67	u32 flags;
8efd1e9e	68	struct dw_scl_sda_cfg *scl_sda_cfg;
ed1bf034	69	int (setup)(struct pci_dev pdev, struct dw_pci_controller *c);
fe20ff5c DB	70	};
	71
	72	#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER \| \
	73	DW_IC_CON_SLAVE_DISABLE \| \
	74	DW_IC_CON_RESTART_EN)
	75
b20551c1 AS	76	/* Merrifield HCNT/LCNT/SDA hold time */
	77	static struct dw_scl_sda_cfg mrfld_config = {
	78	.ss_hcnt = 0x2f8,
	79	.fs_hcnt = 0x87,
	80	.ss_lcnt = 0x37b,
	81	.fs_lcnt = 0x10a,
	82	};
	83
8efd1e9e CCE	84	/* BayTrail HCNT/LCNT/SDA hold time */
	85	static struct dw_scl_sda_cfg byt_config = {
	86	.ss_hcnt = 0x200,
	87	.fs_hcnt = 0x55,
	88	.ss_lcnt = 0x200,
	89	.fs_lcnt = 0x99,
	90	.sda_hold = 0x6,
	91	};
	92
157a801e MW	93	/* Haswell HCNT/LCNT/SDA hold time */
	94	static struct dw_scl_sda_cfg hsw_config = {
	95	.ss_hcnt = 0x01b0,
	96	.fs_hcnt = 0x48,
	97	.ss_lcnt = 0x01fb,
	98	.fs_lcnt = 0xa0,
	99	.sda_hold = 0x9,
	100	};
	101
ed1bf034 AS	102	static int mfld_setup(struct pci_dev pdev, struct dw_pci_controller c)
	103	{
	104	switch (pdev->device) {
	105	case 0x0817:
	106	c->bus_cfg &= ~DW_IC_CON_SPEED_MASK;
	107	c->bus_cfg \|= DW_IC_CON_SPEED_STD;
	108	case 0x0818:
	109	case 0x0819:
	110	c->bus_num = pdev->device - 0x817 + 3;
	111	return 0;
	112	case 0x082C:
	113	case 0x082D:
	114	case 0x082E:
	115	c->bus_num = pdev->device - 0x82C + 0;
	116	return 0;
	117	}
	118	return -ENODEV;
	119	}
	120
b20551c1 AS	121	static int mrfld_setup(struct pci_dev pdev, struct dw_pci_controller c)
	122	{
	123	/*
ec2790e9 AS	124	* On Intel Merrifield the user visible i2c busses are enumerated
	125	* [1..7]. So, we add 1 to shift the default range. Besides that the
	126	* first PCI slot provides 4 functions, that's why we have to add 0 to
	127	* the first slot and 4 to the next one.
b20551c1 AS	128	*/
	129	switch (PCI_SLOT(pdev->devfn)) {
	130	case 8:
	131	c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
	132	return 0;
	133	case 9:
	134	c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
	135	return 0;
	136	}
	137	return -ENODEV;
	138	}
	139
a93ac578	140	static struct dw_pci_controller dw_pci_controllers[] = {
ed1bf034 AS	141	[medfield] = {
ed1bf034 AS	142	.bus_num = -1,
fe20ff5c DB	143	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	144	.tx_fifo_depth = 32,
	145	.rx_fifo_depth = 32,
531ccabb	146	.functionality = I2C_FUNC_10BIT_ADDR,
fe20ff5c	147	.clk_khz = 25000,
ed1bf034	148	.setup = mfld_setup,
fe20ff5c	149	},
b20551c1 AS	150	[merrifield] = {
	151	.bus_num = -1,
	152	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	153	.tx_fifo_depth = 64,
	154	.rx_fifo_depth = 64,
531ccabb	155	.functionality = I2C_FUNC_10BIT_ADDR,
b20551c1 AS	156	.scl_sda_cfg = &mrfld_config,
	157	.setup = mrfld_setup,
	158	},
089c729a MW	159	[baytrail] = {
	160	.bus_num = -1,
	161	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	162	.tx_fifo_depth = 32,
	163	.rx_fifo_depth = 32,
ceccd298	164	.functionality = I2C_FUNC_10BIT_ADDR,
8efd1e9e	165	.scl_sda_cfg = &byt_config,
089c729a	166	},
157a801e MW	167	[haswell] = {
	168	.bus_num = -1,
	169	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	170	.tx_fifo_depth = 32,
	171	.rx_fifo_depth = 32,
157a801e MW	172	.functionality = I2C_FUNC_10BIT_ADDR,
	173	.scl_sda_cfg = &hsw_config,
	174	},
fd476fa2 HG	175	[cherrytrail] = {
	176	.bus_num = -1,
	177	.bus_cfg = INTEL_MID_STD_CFG \| DW_IC_CON_SPEED_FAST,
	178	.tx_fifo_depth = 32,
	179	.rx_fifo_depth = 32,
	180	.functionality = I2C_FUNC_10BIT_ADDR,
	181	.flags = MODEL_CHERRYTRAIL,
	182	.scl_sda_cfg = &byt_config,
	183	},
fe20ff5c	184	};
0409516a	185
be58eda7	186	#ifdef CONFIG_PM
52c28433	187	static int i2c_dw_pci_suspend(struct device *dev)
18dbdda8	188	{
238c44a7	189	struct pci_dev *pdev = to_pci_dev(dev);
90312351 LO	190	struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
	191
	192	i_dev->disable(i_dev);
18dbdda8 DB	193
	194	return 0;
	195	}
	196
52c28433	197	static int i2c_dw_pci_resume(struct device *dev)
18dbdda8	198	{
238c44a7	199	struct pci_dev *pdev = to_pci_dev(dev);
90312351	200	struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
18dbdda8	201
90312351	202	return i_dev->init(i_dev);
18dbdda8	203	}
be58eda7	204	#endif
18dbdda8	205
be58eda7 MW	206	static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
be58eda7 MW	207	i2c_dw_pci_resume, NULL);
18dbdda8	208
fe20ff5c DB	209	static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
	210	{
	211	return dev->controller->clk_khz;
	212	}
	213
0b255e92	214	static int i2c_dw_pci_probe(struct pci_dev *pdev,
ca0c1ff5	215	const struct pci_device_id *id)
fe20ff5c DB	216	{
	217	struct dw_i2c_dev *dev;
	218	struct i2c_adapter *adap;
fe20ff5c	219	int r;
45bc35ef	220	struct dw_pci_controller *controller;
8efd1e9e	221	struct dw_scl_sda_cfg *cfg;
fe20ff5c DB	222
fe20ff5c DB	223	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
ca0c1ff5	224	dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
fe20ff5c DB	225	id->driver_data);
	226	return -EINVAL;
	227	}
	228
	229	controller = &dw_pci_controllers[id->driver_data];
	230
76cf3fc8	231	r = pcim_enable_device(pdev);
fe20ff5c DB	232	if (r) {
	233	dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
	234	r);
76cf3fc8	235	return r;
fe20ff5c DB	236	}
fe20ff5c DB	237
76cf3fc8	238	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
fe20ff5c	239	if (r) {
fe20ff5c	240	dev_err(&pdev->dev, "I/O memory remapping failed\n");
76cf3fc8	241	return r;
fe20ff5c DB	242	}
fe20ff5c DB	243
76cf3fc8 AS	244	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
	245	if (!dev)
	246	return -ENOMEM;
fe20ff5c	247
fe20ff5c DB	248	dev->clk = NULL;
	249	dev->controller = controller;
	250	dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
76cf3fc8 AS	251	dev->base = pcim_iomap_table(pdev)[0];
76cf3fc8 AS	252	dev->dev = &pdev->dev;
d80d1341	253	dev->irq = pdev->irq;
fd476fa2	254	dev->flags \|= controller->flags;
ed1bf034 AS	255
	256	if (controller->setup) {
	257	r = controller->setup(pdev, controller);
	258	if (r)
	259	return r;
	260	}
	261
ceccd298	262	dev->functionality = controller->functionality \|
f06122f0	263	DW_IC_DEFAULT_FUNCTIONALITY;
ceccd298	264
a93ac578	265	dev->master_cfg = controller->bus_cfg;
8efd1e9e CCE	266	if (controller->scl_sda_cfg) {
	267	cfg = controller->scl_sda_cfg;
	268	dev->ss_hcnt = cfg->ss_hcnt;
	269	dev->fs_hcnt = cfg->fs_hcnt;
	270	dev->ss_lcnt = cfg->ss_lcnt;
	271	dev->fs_lcnt = cfg->fs_lcnt;
	272	dev->sda_hold_time = cfg->sda_hold;
	273	}
fe20ff5c DB	274
	275	pci_set_drvdata(pdev, dev);
	276
	277	dev->tx_fifo_depth = controller->tx_fifo_depth;
	278	dev->rx_fifo_depth = controller->rx_fifo_depth;
fe20ff5c DB	279
fe20ff5c DB	280	adap = &dev->adapter;
fe20ff5c DB	281	adap->owner = THIS_MODULE;
fe20ff5c DB	282	adap->class = 0;
8eb5c87a	283	ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
fe20ff5c	284	adap->nr = controller->bus_num;
089c729a	285
d80d1341 JN	286	r = i2c_dw_probe(dev);
d80d1341 JN	287	if (r)
76cf3fc8	288	return r;
fe20ff5c	289
43452335 MW	290	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
43452335 MW	291	pm_runtime_use_autosuspend(&pdev->dev);
be58eda7	292	pm_runtime_put_autosuspend(&pdev->dev);
18dbdda8 DB	293	pm_runtime_allow(&pdev->dev);
18dbdda8 DB	294
fe20ff5c	295	return 0;
fe20ff5c DB	296	}
fe20ff5c DB	297
0b255e92	298	static void i2c_dw_pci_remove(struct pci_dev *pdev)
fe20ff5c DB	299	{
	300	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
	301
90312351	302	dev->disable(dev);
18dbdda8 DB	303	pm_runtime_forbid(&pdev->dev);
	304	pm_runtime_get_noresume(&pdev->dev);
	305
fe20ff5c	306	i2c_del_adapter(&dev->adapter);
fe20ff5c DB	307	}
	308
	309	/* work with hotplug and coldplug */
	310	MODULE_ALIAS("i2c_designware-pci");
	311
392debf1	312	static const struct pci_device_id i2_designware_pci_ids[] = {
fe20ff5c	313	/* Medfield */
ed1bf034 AS	314	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
	315	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
	316	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
	317	{ PCI_VDEVICE(INTEL, 0x082C), medfield },
	318	{ PCI_VDEVICE(INTEL, 0x082D), medfield },
	319	{ PCI_VDEVICE(INTEL, 0x082E), medfield },
b20551c1 AS	320	/* Merrifield */
	321	{ PCI_VDEVICE(INTEL, 0x1195), merrifield },
	322	{ PCI_VDEVICE(INTEL, 0x1196), merrifield },
089c729a MW	323	/* Baytrail */
	324	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
	325	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
	326	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
	327	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
	328	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
	329	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
	330	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
157a801e MW	331	/* Haswell */
	332	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
	333	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
0409516a	334	/* Braswell / Cherrytrail */
fd476fa2 HG	335	{ PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
	336	{ PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
	337	{ PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
	338	{ PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
	339	{ PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
	340	{ PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
	341	{ PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
fe20ff5c DB	342	{ 0,}
	343	};
	344	MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
	345
	346	static struct pci_driver dw_i2c_driver = {
	347	.name = DRIVER_NAME,
	348	.id_table = i2_designware_pci_ids,
	349	.probe = i2c_dw_pci_probe,
0b255e92	350	.remove = i2c_dw_pci_remove,
18dbdda8 DB	351	.driver = {
	352	.pm = &i2c_dw_pm_ops,
	353	},
fe20ff5c DB	354	};
fe20ff5c DB	355
56f21788	356	module_pci_driver(dw_i2c_driver);
fe20ff5c DB	357
	358	MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
	359	MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
	360	MODULE_LICENSE("GPL");