Commit | Line | Data |
---|---|---|
1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
1ab52cf9 BS |
21 | * ---------------------------------------------------------------------------- |
22 | * | |
23 | */ | |
e393f674 | 24 | #include <linux/delay.h> |
1ab52cf9 | 25 | #include <linux/err.h> |
90312351 LO |
26 | #include <linux/errno.h> |
27 | #include <linux/export.h> | |
ca382f5b | 28 | #include <linux/gpio/consumer.h> |
2373f6b9 | 29 | #include <linux/i2c.h> |
1ab52cf9 | 30 | #include <linux/interrupt.h> |
1ab52cf9 | 31 | #include <linux/io.h> |
9dd3162d | 32 | #include <linux/module.h> |
e393f674 | 33 | #include <linux/pm_runtime.h> |
ca382f5b | 34 | #include <linux/reset.h> |
ce6eb574 | 35 | |
e393f674 | 36 | #include "i2c-designware-core.h" |
7f279601 | 37 | |
89a1e1bd LO |
38 | static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev) |
39 | { | |
40 | /* Configure Tx/Rx FIFO threshold levels */ | |
41 | dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL); | |
42 | dw_writel(dev, 0, DW_IC_RX_TL); | |
43 | ||
44 | /* Configure the I2C master */ | |
45 | dw_writel(dev, dev->master_cfg, DW_IC_CON); | |
46 | } | |
47 | ||
1ab52cf9 | 48 | /** |
e393f674 | 49 | * i2c_dw_init() - Initialize the designware I2C master hardware |
1ab52cf9 BS |
50 | * @dev: device private data |
51 | * | |
52 | * This functions configures and enables the I2C master. | |
53 | * This function is called during I2C init function, and in case of timeout at | |
54 | * run time. | |
55 | */ | |
21bf440c | 56 | static int i2c_dw_init_master(struct dw_i2c_dev *dev) |
1ab52cf9 | 57 | { |
e18563fc | 58 | u32 hcnt, lcnt; |
b6e67145 | 59 | u32 reg, comp_param1; |
6468276b | 60 | u32 sda_falling_time, scl_falling_time; |
c0601d28 DB |
61 | int ret; |
62 | ||
8c5660bb LDM |
63 | ret = i2c_dw_acquire_lock(dev); |
64 | if (ret) | |
65 | return ret; | |
4a423a8c | 66 | |
4a423a8c DB |
67 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
68 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { | |
a8a9f3fe | 69 | /* Configure register endianess access */ |
86524e54 | 70 | dev->flags |= ACCESS_SWAP; |
a8a9f3fe SR |
71 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { |
72 | /* Configure register access mode 16bit */ | |
86524e54 | 73 | dev->flags |= ACCESS_16BIT; |
a8a9f3fe | 74 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { |
e393f674 LO |
75 | dev_err(dev->dev, |
76 | "Unknown Synopsys component type: 0x%08x\n", reg); | |
8c5660bb | 77 | i2c_dw_release_lock(dev); |
4a423a8c DB |
78 | return -ENODEV; |
79 | } | |
1ab52cf9 | 80 | |
b6e67145 WV |
81 | comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1); |
82 | ||
1ab52cf9 | 83 | /* Disable the adapter */ |
2702ea7d | 84 | __i2c_dw_enable_and_wait(dev, false); |
1ab52cf9 | 85 | |
e393f674 | 86 | /* Set standard and fast speed deviders for high/low periods */ |
d60c7e81 | 87 | |
6468276b RB |
88 | sda_falling_time = dev->sda_falling_time ?: 300; /* ns */ |
89 | scl_falling_time = dev->scl_falling_time ?: 300; /* ns */ | |
90 | ||
42ffd390 | 91 | /* Set SCL timing parameters for standard-mode */ |
defc0b2f MW |
92 | if (dev->ss_hcnt && dev->ss_lcnt) { |
93 | hcnt = dev->ss_hcnt; | |
94 | lcnt = dev->ss_lcnt; | |
42ffd390 | 95 | } else { |
b33af11d | 96 | hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
97 | 4000, /* tHD;STA = tHIGH = 4.0 us */ |
98 | sda_falling_time, | |
99 | 0, /* 0: DW default, 1: Ideal */ | |
100 | 0); /* No offset */ | |
b33af11d | 101 | lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
102 | 4700, /* tLOW = 4.7 us */ |
103 | scl_falling_time, | |
104 | 0); /* No offset */ | |
defc0b2f | 105 | } |
7f279601 JHD |
106 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
107 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); | |
d60c7e81 SK |
108 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
109 | ||
d608c3d9 WV |
110 | /* Set SCL timing parameters for fast-mode or fast-mode plus */ |
111 | if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) { | |
112 | hcnt = dev->fp_hcnt; | |
113 | lcnt = dev->fp_lcnt; | |
114 | } else if (dev->fs_hcnt && dev->fs_lcnt) { | |
defc0b2f MW |
115 | hcnt = dev->fs_hcnt; |
116 | lcnt = dev->fs_lcnt; | |
42ffd390 | 117 | } else { |
b33af11d | 118 | hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
119 | 600, /* tHD;STA = tHIGH = 0.6 us */ |
120 | sda_falling_time, | |
121 | 0, /* 0: DW default, 1: Ideal */ | |
122 | 0); /* No offset */ | |
b33af11d | 123 | lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), |
42ffd390 JN |
124 | 1300, /* tLOW = 1.3 us */ |
125 | scl_falling_time, | |
126 | 0); /* No offset */ | |
defc0b2f | 127 | } |
7f279601 JHD |
128 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
129 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); | |
d60c7e81 | 130 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
1ab52cf9 | 131 | |
b6e67145 WV |
132 | if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == |
133 | DW_IC_CON_SPEED_HIGH) { | |
134 | if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) | |
135 | != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) { | |
136 | dev_err(dev->dev, "High Speed not supported!\n"); | |
137 | dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; | |
138 | dev->master_cfg |= DW_IC_CON_SPEED_FAST; | |
139 | } else if (dev->hs_hcnt && dev->hs_lcnt) { | |
140 | hcnt = dev->hs_hcnt; | |
141 | lcnt = dev->hs_lcnt; | |
142 | dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT); | |
143 | dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT); | |
144 | dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n", | |
145 | hcnt, lcnt); | |
146 | } | |
147 | } | |
148 | ||
9803f868 | 149 | /* Configure SDA Hold Time if required */ |
664d58bf ZL |
150 | reg = dw_readl(dev, DW_IC_COMP_VERSION); |
151 | if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { | |
171e23e1 | 152 | if (!dev->sda_hold_time) { |
664d58bf ZL |
153 | /* Keep previous hold time setting if no one set it */ |
154 | dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD); | |
155 | } | |
171e23e1 JN |
156 | /* |
157 | * Workaround for avoiding TX arbitration lost in case I2C | |
158 | * slave pulls SDA down "too quickly" after falling egde of | |
159 | * SCL by enabling non-zero SDA RX hold. Specification says it | |
160 | * extends incoming SDA low to high transition while SCL is | |
161 | * high but it apprears to help also above issue. | |
162 | */ | |
163 | if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) | |
164 | dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; | |
165 | dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD); | |
664d58bf ZL |
166 | } else { |
167 | dev_warn(dev->dev, | |
168 | "Hardware too old to adjust SDA hold time.\n"); | |
9803f868 CR |
169 | } |
170 | ||
89a1e1bd | 171 | i2c_dw_configure_fifo_master(dev); |
8c5660bb LDM |
172 | i2c_dw_release_lock(dev); |
173 | ||
4a423a8c | 174 | return 0; |
1ab52cf9 BS |
175 | } |
176 | ||
81e798b7 SK |
177 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
178 | { | |
179 | struct i2c_msg *msgs = dev->msgs; | |
12688dc2 | 180 | u32 ic_con, ic_tar = 0; |
81e798b7 | 181 | |
89119f08 JN |
182 | /* Disable the adapter */ |
183 | __i2c_dw_enable_and_wait(dev, false); | |
81e798b7 | 184 | |
e393f674 | 185 | /* If the slave address is ten bit address, enable 10BITADDR */ |
12688dc2 JN |
186 | ic_con = dw_readl(dev, DW_IC_CON); |
187 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { | |
188 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
bd63ace4 CCE |
189 | /* |
190 | * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing | |
12688dc2 JN |
191 | * mode has to be enabled via bit 12 of IC_TAR register. |
192 | * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be | |
193 | * detected from registers. | |
bd63ace4 | 194 | */ |
12688dc2 | 195 | ic_tar = DW_IC_TAR_10BITADDR_MASTER; |
bd63ace4 | 196 | } else { |
12688dc2 | 197 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
63d0f0a6 | 198 | } |
81e798b7 | 199 | |
12688dc2 JN |
200 | dw_writel(dev, ic_con, DW_IC_CON); |
201 | ||
bd63ace4 CCE |
202 | /* |
203 | * Set the slave (target) address and enable 10-bit addressing mode | |
204 | * if applicable. | |
205 | */ | |
206 | dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR); | |
207 | ||
e393f674 | 208 | /* Enforce disabled interrupts (due to HW issues) */ |
47bb27e7 DW |
209 | i2c_dw_disable_int(dev); |
210 | ||
89119f08 | 211 | /* Enable the adapter */ |
fba4adbb | 212 | __i2c_dw_enable_and_wait(dev, true); |
201d6a70 | 213 | |
2a2d95e9 | 214 | /* Clear and enable interrupts */ |
c335631a | 215 | dw_readl(dev, DW_IC_CLR_INTR); |
89a1e1bd | 216 | dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK); |
81e798b7 SK |
217 | } |
218 | ||
1ab52cf9 | 219 | /* |
201d6a70 SK |
220 | * Initiate (and continue) low level master read/write transaction. |
221 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
222 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
223 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 | 224 | */ |
bccd780f | 225 | static void |
e77cf232 | 226 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 227 | { |
1ab52cf9 | 228 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 229 | u32 intr_mask; |
ae72222d | 230 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
231 | u32 addr = msgs[dev->msg_write_idx].addr; |
232 | u32 buf_len = dev->tx_buf_len; | |
69932487 | 233 | u8 *buf = dev->tx_buf; |
82564245 | 234 | bool need_restart = false; |
1ab52cf9 | 235 | |
89a1e1bd | 236 | intr_mask = DW_IC_INTR_MASTER_MASK; |
c70c5cd3 | 237 | |
6d2ea487 | 238 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
c3ae1060 TH |
239 | u32 flags = msgs[dev->msg_write_idx].flags; |
240 | ||
a0e06ea6 | 241 | /* |
e393f674 LO |
242 | * If target address has changed, we need to |
243 | * reprogram the target address in the I2C | |
244 | * adapter when we are done with this transfer. | |
1ab52cf9 | 245 | */ |
8f588e40 SK |
246 | if (msgs[dev->msg_write_idx].addr != addr) { |
247 | dev_err(dev->dev, | |
248 | "%s: invalid target address\n", __func__); | |
249 | dev->msg_err = -EINVAL; | |
250 | break; | |
251 | } | |
1ab52cf9 BS |
252 | |
253 | if (msgs[dev->msg_write_idx].len == 0) { | |
254 | dev_err(dev->dev, | |
255 | "%s: invalid message length\n", __func__); | |
256 | dev->msg_err = -EINVAL; | |
8f588e40 | 257 | break; |
1ab52cf9 BS |
258 | } |
259 | ||
260 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
261 | /* new i2c_msg */ | |
26ea15b1 | 262 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 | 263 | buf_len = msgs[dev->msg_write_idx].len; |
82564245 CCE |
264 | |
265 | /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and | |
266 | * IC_RESTART_EN are set, we must manually | |
267 | * set restart bit between messages. | |
268 | */ | |
269 | if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && | |
270 | (dev->msg_write_idx > 0)) | |
271 | need_restart = true; | |
1ab52cf9 BS |
272 | } |
273 | ||
7f279601 JHD |
274 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
275 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); | |
ae72222d | 276 | |
1ab52cf9 | 277 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
17a76b4b MW |
278 | u32 cmd = 0; |
279 | ||
280 | /* | |
281 | * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must | |
282 | * manually set the stop bit. However, it cannot be | |
283 | * detected from the registers so we set it always | |
284 | * when writing/reading the last byte. | |
285 | */ | |
c3ae1060 TH |
286 | |
287 | /* | |
91ed5349 | 288 | * i2c-core always sets the buffer length of |
c3ae1060 TH |
289 | * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will |
290 | * be adjusted when receiving the first byte. | |
291 | * Thus we can't stop the transaction here. | |
292 | */ | |
17a76b4b | 293 | if (dev->msg_write_idx == dev->msgs_num - 1 && |
c3ae1060 | 294 | buf_len == 1 && !(flags & I2C_M_RECV_LEN)) |
17a76b4b MW |
295 | cmd |= BIT(9); |
296 | ||
82564245 CCE |
297 | if (need_restart) { |
298 | cmd |= BIT(10); | |
299 | need_restart = false; | |
300 | } | |
301 | ||
1ab52cf9 | 302 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
e6f34cea | 303 | |
e393f674 | 304 | /* Avoid rx buffer overrun */ |
4d6d5f1d | 305 | if (dev->rx_outstanding >= dev->rx_fifo_depth) |
e6f34cea JA |
306 | break; |
307 | ||
17a76b4b | 308 | dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); |
1ab52cf9 | 309 | rx_limit--; |
e6f34cea | 310 | dev->rx_outstanding++; |
1ab52cf9 | 311 | } else |
17a76b4b | 312 | dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); |
1ab52cf9 BS |
313 | tx_limit--; buf_len--; |
314 | } | |
c70c5cd3 | 315 | |
26ea15b1 | 316 | dev->tx_buf = buf; |
c70c5cd3 SK |
317 | dev->tx_buf_len = buf_len; |
318 | ||
c3ae1060 TH |
319 | /* |
320 | * Because we don't know the buffer length in the | |
321 | * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop | |
322 | * the transaction here. | |
323 | */ | |
324 | if (buf_len > 0 || flags & I2C_M_RECV_LEN) { | |
c70c5cd3 | 325 | /* more bytes to be written */ |
c70c5cd3 SK |
326 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
327 | break; | |
69151e53 | 328 | } else |
c70c5cd3 | 329 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
330 | } |
331 | ||
69151e53 SK |
332 | /* |
333 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
334 | * interrupt any more. | |
335 | */ | |
336 | if (dev->msg_write_idx == dev->msgs_num) | |
337 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
338 | ||
8f588e40 SK |
339 | if (dev->msg_err) |
340 | intr_mask = 0; | |
341 | ||
2373f6b9 | 342 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
1ab52cf9 BS |
343 | } |
344 | ||
c3ae1060 TH |
345 | static u8 |
346 | i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len) | |
347 | { | |
348 | struct i2c_msg *msgs = dev->msgs; | |
349 | u32 flags = msgs[dev->msg_read_idx].flags; | |
350 | ||
351 | /* | |
352 | * Adjust the buffer length and mask the flag | |
353 | * after receiving the first byte. | |
354 | */ | |
355 | len += (flags & I2C_CLIENT_PEC) ? 2 : 1; | |
356 | dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); | |
357 | msgs[dev->msg_read_idx].len = len; | |
358 | msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; | |
359 | ||
360 | return len; | |
361 | } | |
362 | ||
1ab52cf9 | 363 | static void |
78839bd0 | 364 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 365 | { |
1ab52cf9 | 366 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 367 | int rx_valid; |
1ab52cf9 | 368 | |
6d2ea487 | 369 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 370 | u32 len; |
1ab52cf9 BS |
371 | u8 *buf; |
372 | ||
373 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
374 | continue; | |
375 | ||
1ab52cf9 BS |
376 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
377 | len = msgs[dev->msg_read_idx].len; | |
378 | buf = msgs[dev->msg_read_idx].buf; | |
379 | } else { | |
380 | len = dev->rx_buf_len; | |
381 | buf = dev->rx_buf; | |
382 | } | |
383 | ||
7f279601 | 384 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
ae72222d | 385 | |
e6f34cea | 386 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) { |
c3ae1060 TH |
387 | u32 flags = msgs[dev->msg_read_idx].flags; |
388 | ||
389 | *buf = dw_readl(dev, DW_IC_DATA_CMD); | |
390 | /* Ensure length byte is a valid value */ | |
391 | if (flags & I2C_M_RECV_LEN && | |
392 | *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) { | |
393 | len = i2c_dw_recv_len(dev, *buf); | |
394 | } | |
395 | buf++; | |
e6f34cea JA |
396 | dev->rx_outstanding--; |
397 | } | |
1ab52cf9 BS |
398 | |
399 | if (len > 0) { | |
400 | dev->status |= STATUS_READ_IN_PROGRESS; | |
401 | dev->rx_buf_len = len; | |
402 | dev->rx_buf = buf; | |
403 | return; | |
404 | } else | |
405 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
406 | } | |
407 | } | |
408 | ||
409 | /* | |
e393f674 | 410 | * Prepare controller for a transaction and call i2c_dw_xfer_msg. |
1ab52cf9 | 411 | */ |
d80d1341 | 412 | static int |
1ab52cf9 BS |
413 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
414 | { | |
415 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
416 | int ret; | |
417 | ||
418 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
419 | ||
18dbdda8 | 420 | pm_runtime_get_sync(dev->dev); |
1ab52cf9 | 421 | |
16735d02 | 422 | reinit_completion(&dev->cmd_complete); |
1ab52cf9 BS |
423 | dev->msgs = msgs; |
424 | dev->msgs_num = num; | |
425 | dev->cmd_err = 0; | |
426 | dev->msg_write_idx = 0; | |
427 | dev->msg_read_idx = 0; | |
428 | dev->msg_err = 0; | |
429 | dev->status = STATUS_IDLE; | |
ce6eb574 | 430 | dev->abort_source = 0; |
e6f34cea | 431 | dev->rx_outstanding = 0; |
1ab52cf9 | 432 | |
8c5660bb LDM |
433 | ret = i2c_dw_acquire_lock(dev); |
434 | if (ret) | |
435 | goto done_nolock; | |
c0601d28 | 436 | |
1ab52cf9 BS |
437 | ret = i2c_dw_wait_bus_not_busy(dev); |
438 | if (ret < 0) | |
439 | goto done; | |
440 | ||
e393f674 | 441 | /* Start the transfers */ |
81e798b7 | 442 | i2c_dw_xfer_init(dev); |
1ab52cf9 | 443 | |
e393f674 | 444 | /* Wait for tx to complete */ |
d0bcd8df | 445 | if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) { |
1ab52cf9 | 446 | dev_err(dev->dev, "controller timed out\n"); |
38d7fade | 447 | /* i2c_dw_init implicitly disables the adapter */ |
ca382f5b | 448 | i2c_recover_bus(&dev->adapter); |
21bf440c | 449 | i2c_dw_init_master(dev); |
1ab52cf9 BS |
450 | ret = -ETIMEDOUT; |
451 | goto done; | |
e42dba56 | 452 | } |
1ab52cf9 | 453 | |
89119f08 JN |
454 | /* |
455 | * We must disable the adapter before returning and signaling the end | |
456 | * of the current transfer. Otherwise the hardware might continue | |
457 | * generating interrupts which in turn causes a race condition with | |
458 | * the following transfer. Needs some more investigation if the | |
459 | * additional interrupts are a hardware bug or this driver doesn't | |
460 | * handle them correctly yet. | |
461 | */ | |
462 | __i2c_dw_enable(dev, false); | |
463 | ||
1ab52cf9 BS |
464 | if (dev->msg_err) { |
465 | ret = dev->msg_err; | |
466 | goto done; | |
467 | } | |
468 | ||
e393f674 | 469 | /* No error */ |
2bf413d5 | 470 | if (likely(!dev->cmd_err && !dev->status)) { |
1ab52cf9 BS |
471 | ret = num; |
472 | goto done; | |
473 | } | |
474 | ||
475 | /* We have an error */ | |
476 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
477 | ret = i2c_dw_handle_tx_abort(dev); |
478 | goto done; | |
1ab52cf9 | 479 | } |
2bf413d5 RK |
480 | |
481 | if (dev->status) | |
482 | dev_err(dev->dev, | |
483 | "transfer terminated early - interrupt latency too high?\n"); | |
484 | ||
1ab52cf9 BS |
485 | ret = -EIO; |
486 | ||
487 | done: | |
8c5660bb | 488 | i2c_dw_release_lock(dev); |
c0601d28 DB |
489 | |
490 | done_nolock: | |
43452335 MW |
491 | pm_runtime_mark_last_busy(dev->dev); |
492 | pm_runtime_put_autosuspend(dev->dev); | |
1ab52cf9 BS |
493 | |
494 | return ret; | |
495 | } | |
496 | ||
92d9d0df | 497 | static const struct i2c_algorithm i2c_dw_algo = { |
e393f674 LO |
498 | .master_xfer = i2c_dw_xfer, |
499 | .functionality = i2c_dw_func, | |
d80d1341 | 500 | }; |
1ab52cf9 | 501 | |
e28000a3 SK |
502 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
503 | { | |
504 | u32 stat; | |
505 | ||
506 | /* | |
507 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
508 | * Ths unmasked raw version of interrupt status bits are available | |
509 | * in the IC_RAW_INTR_STAT register. | |
510 | * | |
511 | * That is, | |
2373f6b9 | 512 | * stat = dw_readl(IC_INTR_STAT); |
e28000a3 | 513 | * equals to, |
2373f6b9 | 514 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
e28000a3 SK |
515 | * |
516 | * The raw version might be useful for debugging purposes. | |
517 | */ | |
7f279601 | 518 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
e28000a3 SK |
519 | |
520 | /* | |
521 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
522 | * you'll miss some interrupts, triggered during the period from | |
2373f6b9 | 523 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
e28000a3 SK |
524 | * |
525 | * Instead, use the separately-prepared IC_CLR_* registers. | |
526 | */ | |
527 | if (stat & DW_IC_INTR_RX_UNDER) | |
7f279601 | 528 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
e28000a3 | 529 | if (stat & DW_IC_INTR_RX_OVER) |
7f279601 | 530 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
e28000a3 | 531 | if (stat & DW_IC_INTR_TX_OVER) |
7f279601 | 532 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
e28000a3 | 533 | if (stat & DW_IC_INTR_RD_REQ) |
7f279601 | 534 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
e28000a3 SK |
535 | if (stat & DW_IC_INTR_TX_ABRT) { |
536 | /* | |
537 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
538 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
539 | */ | |
7f279601 JHD |
540 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
541 | dw_readl(dev, DW_IC_CLR_TX_ABRT); | |
e28000a3 SK |
542 | } |
543 | if (stat & DW_IC_INTR_RX_DONE) | |
7f279601 | 544 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
e28000a3 | 545 | if (stat & DW_IC_INTR_ACTIVITY) |
7f279601 | 546 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
e28000a3 | 547 | if (stat & DW_IC_INTR_STOP_DET) |
7f279601 | 548 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
e28000a3 | 549 | if (stat & DW_IC_INTR_START_DET) |
7f279601 | 550 | dw_readl(dev, DW_IC_CLR_START_DET); |
e28000a3 | 551 | if (stat & DW_IC_INTR_GEN_CALL) |
7f279601 | 552 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
e28000a3 SK |
553 | |
554 | return stat; | |
555 | } | |
556 | ||
1ab52cf9 | 557 | /* |
89a1e1bd | 558 | * Interrupt service routine. This gets called whenever an I2C master interrupt |
1ab52cf9 BS |
559 | * occurs. |
560 | */ | |
89a1e1bd | 561 | static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev) |
1ab52cf9 | 562 | { |
89a1e1bd | 563 | u32 stat; |
1ab52cf9 | 564 | |
e28000a3 | 565 | stat = i2c_dw_read_clear_intrbits(dev); |
1ab52cf9 | 566 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
567 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
568 | dev->status = STATUS_IDLE; | |
597fe310 SK |
569 | |
570 | /* | |
571 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
e393f674 | 572 | * buffers are flushed. Make sure to skip them. |
597fe310 | 573 | */ |
7f279601 | 574 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
597fe310 | 575 | goto tx_aborted; |
07745399 SK |
576 | } |
577 | ||
21a89d41 | 578 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 579 | i2c_dw_read(dev); |
21a89d41 SK |
580 | |
581 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 582 | i2c_dw_xfer_msg(dev); |
07745399 SK |
583 | |
584 | /* | |
585 | * No need to modify or disable the interrupt mask here. | |
586 | * i2c_dw_xfer_msg() will take care of it according to | |
587 | * the current transmit status. | |
588 | */ | |
1ab52cf9 | 589 | |
597fe310 | 590 | tx_aborted: |
89119f08 | 591 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 | 592 | complete(&dev->cmd_complete); |
86524e54 | 593 | else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { |
e393f674 | 594 | /* Workaround to trigger pending interrupt */ |
2d244c81 XY |
595 | stat = dw_readl(dev, DW_IC_INTR_MASK); |
596 | i2c_dw_disable_int(dev); | |
597 | dw_writel(dev, stat, DW_IC_INTR_MASK); | |
598 | } | |
1ab52cf9 | 599 | |
89a1e1bd LO |
600 | return 0; |
601 | } | |
602 | ||
603 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) | |
604 | { | |
605 | struct dw_i2c_dev *dev = dev_id; | |
606 | u32 stat, enabled; | |
607 | ||
608 | enabled = dw_readl(dev, DW_IC_ENABLE); | |
609 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); | |
610 | dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); | |
611 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) | |
612 | return IRQ_NONE; | |
613 | ||
614 | i2c_dw_irq_handler_master(dev); | |
615 | ||
1ab52cf9 BS |
616 | return IRQ_HANDLED; |
617 | } | |
f3fa9f3d | 618 | |
ca382f5b TS |
619 | static void i2c_dw_prepare_recovery(struct i2c_adapter *adap) |
620 | { | |
621 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
622 | ||
623 | i2c_dw_disable(dev); | |
624 | reset_control_assert(dev->rst); | |
625 | i2c_dw_prepare_clk(dev, false); | |
626 | } | |
627 | ||
628 | static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap) | |
629 | { | |
630 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
631 | ||
632 | i2c_dw_prepare_clk(dev, true); | |
633 | reset_control_deassert(dev->rst); | |
634 | i2c_dw_init_master(dev); | |
635 | } | |
636 | ||
637 | static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev) | |
638 | { | |
639 | struct i2c_bus_recovery_info *rinfo = &dev->rinfo; | |
640 | struct i2c_adapter *adap = &dev->adapter; | |
641 | struct gpio_desc *gpio; | |
642 | int r; | |
643 | ||
644 | gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH); | |
645 | if (IS_ERR(gpio)) { | |
646 | r = PTR_ERR(gpio); | |
d1fa7452 | 647 | if (r == -ENOENT || r == -ENOSYS) |
ca382f5b TS |
648 | return 0; |
649 | return r; | |
650 | } | |
651 | rinfo->scl_gpiod = gpio; | |
652 | ||
653 | gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); | |
654 | if (IS_ERR(gpio)) | |
655 | return PTR_ERR(gpio); | |
656 | rinfo->sda_gpiod = gpio; | |
657 | ||
658 | rinfo->recover_bus = i2c_generic_scl_recovery; | |
659 | rinfo->prepare_recovery = i2c_dw_prepare_recovery; | |
660 | rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; | |
661 | adap->bus_recovery_info = rinfo; | |
662 | ||
663 | dev_info(dev->dev, "running with gpio recovery mode! scl%s", | |
664 | rinfo->sda_gpiod ? ",sda" : ""); | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
d80d1341 JN |
669 | int i2c_dw_probe(struct dw_i2c_dev *dev) |
670 | { | |
671 | struct i2c_adapter *adap = &dev->adapter; | |
41c80b8a | 672 | unsigned long irq_flags; |
e393f674 | 673 | int ret; |
d80d1341 JN |
674 | |
675 | init_completion(&dev->cmd_complete); | |
d80d1341 | 676 | |
21bf440c | 677 | dev->init = i2c_dw_init_master; |
90312351 LO |
678 | dev->disable = i2c_dw_disable; |
679 | dev->disable_int = i2c_dw_disable_int; | |
680 | ||
681 | ret = dev->init(dev); | |
e393f674 LO |
682 | if (ret) |
683 | return ret; | |
d80d1341 JN |
684 | |
685 | snprintf(adap->name, sizeof(adap->name), | |
686 | "Synopsys DesignWare I2C adapter"); | |
8d22f309 | 687 | adap->retries = 3; |
d80d1341 JN |
688 | adap->algo = &i2c_dw_algo; |
689 | adap->dev.parent = dev->dev; | |
690 | i2c_set_adapdata(adap, dev); | |
691 | ||
41c80b8a HG |
692 | if (dev->pm_disabled) { |
693 | dev_pm_syscore_device(dev->dev, true); | |
694 | irq_flags = IRQF_NO_SUSPEND; | |
695 | } else { | |
696 | irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND; | |
697 | } | |
698 | ||
d80d1341 | 699 | i2c_dw_disable_int(dev); |
e393f674 LO |
700 | ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags, |
701 | dev_name(dev->dev), dev); | |
702 | if (ret) { | |
d80d1341 | 703 | dev_err(dev->dev, "failure requesting irq %i: %d\n", |
e393f674 LO |
704 | dev->irq, ret); |
705 | return ret; | |
d80d1341 JN |
706 | } |
707 | ||
ca382f5b TS |
708 | ret = i2c_dw_init_recovery_info(dev); |
709 | if (ret) | |
710 | return ret; | |
711 | ||
cd998ded JN |
712 | /* |
713 | * Increment PM usage count during adapter registration in order to | |
714 | * avoid possible spurious runtime suspend when adapter device is | |
715 | * registered to the device core and immediate resume in case bus has | |
716 | * registered I2C slaves that do I2C transfers in their probe. | |
717 | */ | |
718 | pm_runtime_get_noresume(dev->dev); | |
e393f674 LO |
719 | ret = i2c_add_numbered_adapter(adap); |
720 | if (ret) | |
721 | dev_err(dev->dev, "failure adding adapter: %d\n", ret); | |
cd998ded | 722 | pm_runtime_put_noidle(dev->dev); |
d80d1341 | 723 | |
e393f674 | 724 | return ret; |
d80d1341 JN |
725 | } |
726 | EXPORT_SYMBOL_GPL(i2c_dw_probe); | |
727 | ||
90312351 | 728 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter"); |
9dd3162d | 729 | MODULE_LICENSE("GPL"); |