Commit | Line | Data |
---|---|---|
1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * ---------------------------------------------------------------------------- | |
26 | * | |
27 | */ | |
e68bb91b | 28 | #include <linux/export.h> |
1ab52cf9 BS |
29 | #include <linux/clk.h> |
30 | #include <linux/errno.h> | |
1ab52cf9 | 31 | #include <linux/err.h> |
2373f6b9 | 32 | #include <linux/i2c.h> |
1ab52cf9 | 33 | #include <linux/interrupt.h> |
1ab52cf9 | 34 | #include <linux/io.h> |
18dbdda8 | 35 | #include <linux/pm_runtime.h> |
2373f6b9 | 36 | #include <linux/delay.h> |
9dd3162d | 37 | #include <linux/module.h> |
2373f6b9 | 38 | #include "i2c-designware-core.h" |
ce6eb574 | 39 | |
f3fa9f3d DB |
40 | /* |
41 | * Registers offset | |
42 | */ | |
43 | #define DW_IC_CON 0x0 | |
44 | #define DW_IC_TAR 0x4 | |
45 | #define DW_IC_DATA_CMD 0x10 | |
46 | #define DW_IC_SS_SCL_HCNT 0x14 | |
47 | #define DW_IC_SS_SCL_LCNT 0x18 | |
48 | #define DW_IC_FS_SCL_HCNT 0x1c | |
49 | #define DW_IC_FS_SCL_LCNT 0x20 | |
50 | #define DW_IC_INTR_STAT 0x2c | |
51 | #define DW_IC_INTR_MASK 0x30 | |
52 | #define DW_IC_RAW_INTR_STAT 0x34 | |
53 | #define DW_IC_RX_TL 0x38 | |
54 | #define DW_IC_TX_TL 0x3c | |
55 | #define DW_IC_CLR_INTR 0x40 | |
56 | #define DW_IC_CLR_RX_UNDER 0x44 | |
57 | #define DW_IC_CLR_RX_OVER 0x48 | |
58 | #define DW_IC_CLR_TX_OVER 0x4c | |
59 | #define DW_IC_CLR_RD_REQ 0x50 | |
60 | #define DW_IC_CLR_TX_ABRT 0x54 | |
61 | #define DW_IC_CLR_RX_DONE 0x58 | |
62 | #define DW_IC_CLR_ACTIVITY 0x5c | |
63 | #define DW_IC_CLR_STOP_DET 0x60 | |
64 | #define DW_IC_CLR_START_DET 0x64 | |
65 | #define DW_IC_CLR_GEN_CALL 0x68 | |
66 | #define DW_IC_ENABLE 0x6c | |
67 | #define DW_IC_STATUS 0x70 | |
68 | #define DW_IC_TXFLR 0x74 | |
69 | #define DW_IC_RXFLR 0x78 | |
9803f868 | 70 | #define DW_IC_SDA_HOLD 0x7c |
f3fa9f3d | 71 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
3ca4ed87 | 72 | #define DW_IC_ENABLE_STATUS 0x9c |
f3fa9f3d | 73 | #define DW_IC_COMP_PARAM_1 0xf4 |
9803f868 CR |
74 | #define DW_IC_COMP_VERSION 0xf8 |
75 | #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A | |
f3fa9f3d DB |
76 | #define DW_IC_COMP_TYPE 0xfc |
77 | #define DW_IC_COMP_TYPE_VALUE 0x44570140 | |
78 | ||
79 | #define DW_IC_INTR_RX_UNDER 0x001 | |
80 | #define DW_IC_INTR_RX_OVER 0x002 | |
81 | #define DW_IC_INTR_RX_FULL 0x004 | |
82 | #define DW_IC_INTR_TX_OVER 0x008 | |
83 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
84 | #define DW_IC_INTR_RD_REQ 0x020 | |
85 | #define DW_IC_INTR_TX_ABRT 0x040 | |
86 | #define DW_IC_INTR_RX_DONE 0x080 | |
87 | #define DW_IC_INTR_ACTIVITY 0x100 | |
88 | #define DW_IC_INTR_STOP_DET 0x200 | |
89 | #define DW_IC_INTR_START_DET 0x400 | |
90 | #define DW_IC_INTR_GEN_CALL 0x800 | |
91 | ||
92 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ | |
93 | DW_IC_INTR_TX_EMPTY | \ | |
94 | DW_IC_INTR_TX_ABRT | \ | |
95 | DW_IC_INTR_STOP_DET) | |
96 | ||
97 | #define DW_IC_STATUS_ACTIVITY 0x1 | |
98 | ||
99 | #define DW_IC_ERR_TX_ABRT 0x1 | |
100 | ||
101 | /* | |
102 | * status codes | |
103 | */ | |
104 | #define STATUS_IDLE 0x0 | |
105 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
106 | #define STATUS_READ_IN_PROGRESS 0x2 | |
107 | ||
108 | #define TIMEOUT 20 /* ms */ | |
109 | ||
110 | /* | |
111 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
112 | * | |
113 | * only expected abort codes are listed here | |
114 | * refer to the datasheet for the full list | |
115 | */ | |
116 | #define ABRT_7B_ADDR_NOACK 0 | |
117 | #define ABRT_10ADDR1_NOACK 1 | |
118 | #define ABRT_10ADDR2_NOACK 2 | |
119 | #define ABRT_TXDATA_NOACK 3 | |
120 | #define ABRT_GCALL_NOACK 4 | |
121 | #define ABRT_GCALL_READ 5 | |
122 | #define ABRT_SBYTE_ACKDET 7 | |
123 | #define ABRT_SBYTE_NORSTRT 9 | |
124 | #define ABRT_10B_RD_NORSTRT 10 | |
125 | #define ABRT_MASTER_DIS 11 | |
126 | #define ARB_LOST 12 | |
127 | ||
128 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) | |
129 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | |
130 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | |
131 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | |
132 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | |
133 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | |
134 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | |
135 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | |
136 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | |
137 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | |
138 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | |
139 | ||
140 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | |
141 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | |
142 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | |
143 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | |
144 | DW_IC_TX_ABRT_GCALL_NOACK) | |
145 | ||
1ab52cf9 | 146 | static char *abort_sources[] = { |
a0e06ea6 | 147 | [ABRT_7B_ADDR_NOACK] = |
1ab52cf9 | 148 | "slave address not acknowledged (7bit mode)", |
a0e06ea6 | 149 | [ABRT_10ADDR1_NOACK] = |
1ab52cf9 | 150 | "first address byte not acknowledged (10bit mode)", |
a0e06ea6 | 151 | [ABRT_10ADDR2_NOACK] = |
1ab52cf9 | 152 | "second address byte not acknowledged (10bit mode)", |
a0e06ea6 | 153 | [ABRT_TXDATA_NOACK] = |
1ab52cf9 | 154 | "data not acknowledged", |
a0e06ea6 | 155 | [ABRT_GCALL_NOACK] = |
1ab52cf9 | 156 | "no acknowledgement for a general call", |
a0e06ea6 | 157 | [ABRT_GCALL_READ] = |
1ab52cf9 | 158 | "read after general call", |
a0e06ea6 | 159 | [ABRT_SBYTE_ACKDET] = |
1ab52cf9 | 160 | "start byte acknowledged", |
a0e06ea6 | 161 | [ABRT_SBYTE_NORSTRT] = |
1ab52cf9 | 162 | "trying to send start byte when restart is disabled", |
a0e06ea6 | 163 | [ABRT_10B_RD_NORSTRT] = |
1ab52cf9 | 164 | "trying to read when restart is disabled (10bit mode)", |
a0e06ea6 | 165 | [ABRT_MASTER_DIS] = |
1ab52cf9 | 166 | "trying to use disabled adapter", |
a0e06ea6 | 167 | [ARB_LOST] = |
1ab52cf9 BS |
168 | "lost arbitration", |
169 | }; | |
170 | ||
2373f6b9 | 171 | u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
7f279601 | 172 | { |
a8a9f3fe | 173 | u32 value; |
18c4089e | 174 | |
a8a9f3fe SR |
175 | if (dev->accessor_flags & ACCESS_16BIT) |
176 | value = readw(dev->base + offset) | | |
177 | (readw(dev->base + offset + 2) << 16); | |
178 | else | |
179 | value = readl(dev->base + offset); | |
180 | ||
181 | if (dev->accessor_flags & ACCESS_SWAP) | |
18c4089e JHD |
182 | return swab32(value); |
183 | else | |
184 | return value; | |
7f279601 JHD |
185 | } |
186 | ||
2373f6b9 | 187 | void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
7f279601 | 188 | { |
a8a9f3fe | 189 | if (dev->accessor_flags & ACCESS_SWAP) |
18c4089e JHD |
190 | b = swab32(b); |
191 | ||
a8a9f3fe SR |
192 | if (dev->accessor_flags & ACCESS_16BIT) { |
193 | writew((u16)b, dev->base + offset); | |
194 | writew((u16)(b >> 16), dev->base + offset + 2); | |
195 | } else { | |
196 | writel(b, dev->base + offset); | |
197 | } | |
7f279601 JHD |
198 | } |
199 | ||
d60c7e81 SK |
200 | static u32 |
201 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
202 | { | |
203 | /* | |
204 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
205 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
206 | * will result in violation of the tHD;STA spec. | |
207 | */ | |
208 | if (cond) | |
209 | /* | |
210 | * Conditional expression: | |
211 | * | |
212 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
213 | * | |
214 | * This is based on the DW manuals, and represents an ideal | |
215 | * configuration. The resulting I2C bus speed will be | |
216 | * faster than any of the others. | |
217 | * | |
218 | * If your hardware is free from tHD;STA issue, try this one. | |
219 | */ | |
220 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; | |
221 | else | |
222 | /* | |
223 | * Conditional expression: | |
224 | * | |
225 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
226 | * | |
227 | * This is just experimental rule; the tHD;STA period turned | |
228 | * out to be proportinal to (_HCNT + 3). With this setting, | |
229 | * we could meet both tHIGH and tHD;STA timing specs. | |
230 | * | |
231 | * If unsure, you'd better to take this alternative. | |
232 | * | |
233 | * The reason why we need to take into account "tf" here, | |
234 | * is the same as described in i2c_dw_scl_lcnt(). | |
235 | */ | |
236 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; | |
237 | } | |
238 | ||
239 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
240 | { | |
241 | /* | |
242 | * Conditional expression: | |
243 | * | |
244 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
245 | * | |
246 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
247 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
248 | * In order to meet the tLOW timing spec, we need to take into | |
249 | * account the fall time of SCL signal (tf). Default tf value | |
250 | * should be 0.3 us, for safety. | |
251 | */ | |
252 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; | |
253 | } | |
254 | ||
3ca4ed87 MW |
255 | static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable) |
256 | { | |
257 | int timeout = 100; | |
258 | ||
259 | do { | |
260 | dw_writel(dev, enable, DW_IC_ENABLE); | |
261 | if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable) | |
262 | return; | |
263 | ||
264 | /* | |
265 | * Wait 10 times the signaling period of the highest I2C | |
266 | * transfer supported by the driver (for 400KHz this is | |
267 | * 25us) as described in the DesignWare I2C databook. | |
268 | */ | |
269 | usleep_range(25, 250); | |
270 | } while (timeout--); | |
271 | ||
272 | dev_warn(dev->dev, "timeout in %sabling adapter\n", | |
273 | enable ? "en" : "dis"); | |
274 | } | |
275 | ||
1ab52cf9 BS |
276 | /** |
277 | * i2c_dw_init() - initialize the designware i2c master hardware | |
278 | * @dev: device private data | |
279 | * | |
280 | * This functions configures and enables the I2C master. | |
281 | * This function is called during I2C init function, and in case of timeout at | |
282 | * run time. | |
283 | */ | |
2373f6b9 | 284 | int i2c_dw_init(struct dw_i2c_dev *dev) |
1ab52cf9 | 285 | { |
1d31b58f | 286 | u32 input_clock_khz; |
e18563fc | 287 | u32 hcnt, lcnt; |
4a423a8c DB |
288 | u32 reg; |
289 | ||
1d31b58f DB |
290 | input_clock_khz = dev->get_clk_rate_khz(dev); |
291 | ||
4a423a8c DB |
292 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
293 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { | |
a8a9f3fe SR |
294 | /* Configure register endianess access */ |
295 | dev->accessor_flags |= ACCESS_SWAP; | |
296 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { | |
297 | /* Configure register access mode 16bit */ | |
298 | dev->accessor_flags |= ACCESS_16BIT; | |
299 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { | |
4a423a8c DB |
300 | dev_err(dev->dev, "Unknown Synopsys component type: " |
301 | "0x%08x\n", reg); | |
302 | return -ENODEV; | |
303 | } | |
1ab52cf9 BS |
304 | |
305 | /* Disable the adapter */ | |
3ca4ed87 | 306 | __i2c_dw_enable(dev, false); |
1ab52cf9 BS |
307 | |
308 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 SK |
309 | |
310 | /* Standard-mode */ | |
311 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
312 | 40, /* tHD;STA = tHIGH = 4.0 us */ | |
313 | 3, /* tf = 0.3 us */ | |
314 | 0, /* 0: DW default, 1: Ideal */ | |
315 | 0); /* No offset */ | |
316 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
317 | 47, /* tLOW = 4.7 us */ | |
318 | 3, /* tf = 0.3 us */ | |
319 | 0); /* No offset */ | |
7f279601 JHD |
320 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
321 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); | |
d60c7e81 SK |
322 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
323 | ||
324 | /* Fast-mode */ | |
325 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
326 | 6, /* tHD;STA = tHIGH = 0.6 us */ | |
327 | 3, /* tf = 0.3 us */ | |
328 | 0, /* 0: DW default, 1: Ideal */ | |
329 | 0); /* No offset */ | |
330 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
331 | 13, /* tLOW = 1.3 us */ | |
332 | 3, /* tf = 0.3 us */ | |
333 | 0); /* No offset */ | |
7f279601 JHD |
334 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
335 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); | |
d60c7e81 | 336 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
1ab52cf9 | 337 | |
9803f868 CR |
338 | /* Configure SDA Hold Time if required */ |
339 | if (dev->sda_hold_time) { | |
340 | reg = dw_readl(dev, DW_IC_COMP_VERSION); | |
341 | if (reg >= DW_IC_SDA_HOLD_MIN_VERS) | |
342 | dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD); | |
343 | else | |
344 | dev_warn(dev->dev, | |
345 | "Hardware too old to adjust SDA hold time."); | |
346 | } | |
347 | ||
4cb6d1d6 | 348 | /* Configure Tx/Rx FIFO threshold levels */ |
7f279601 JHD |
349 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
350 | dw_writel(dev, 0, DW_IC_RX_TL); | |
4cb6d1d6 | 351 | |
1ab52cf9 | 352 | /* configure the i2c master */ |
e18563fc | 353 | dw_writel(dev, dev->master_cfg , DW_IC_CON); |
4a423a8c | 354 | return 0; |
1ab52cf9 | 355 | } |
e68bb91b | 356 | EXPORT_SYMBOL_GPL(i2c_dw_init); |
1ab52cf9 BS |
357 | |
358 | /* | |
359 | * Waiting for bus not busy | |
360 | */ | |
361 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
362 | { | |
363 | int timeout = TIMEOUT; | |
364 | ||
7f279601 | 365 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
366 | if (timeout <= 0) { |
367 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
368 | return -ETIMEDOUT; | |
369 | } | |
370 | timeout--; | |
1451b91f | 371 | usleep_range(1000, 1100); |
1ab52cf9 BS |
372 | } |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
81e798b7 SK |
377 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
378 | { | |
379 | struct i2c_msg *msgs = dev->msgs; | |
380 | u32 ic_con; | |
381 | ||
382 | /* Disable the adapter */ | |
3ca4ed87 | 383 | __i2c_dw_enable(dev, false); |
81e798b7 SK |
384 | |
385 | /* set the slave (target) address */ | |
7f279601 | 386 | dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); |
81e798b7 SK |
387 | |
388 | /* if the slave address is ten bit address, enable 10BITADDR */ | |
7f279601 | 389 | ic_con = dw_readl(dev, DW_IC_CON); |
81e798b7 SK |
390 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
391 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
392 | else | |
393 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
7f279601 | 394 | dw_writel(dev, ic_con, DW_IC_CON); |
81e798b7 SK |
395 | |
396 | /* Enable the adapter */ | |
3ca4ed87 | 397 | __i2c_dw_enable(dev, true); |
201d6a70 | 398 | |
2a2d95e9 MW |
399 | /* Clear and enable interrupts */ |
400 | i2c_dw_clear_int(dev); | |
7f279601 | 401 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
81e798b7 SK |
402 | } |
403 | ||
1ab52cf9 | 404 | /* |
201d6a70 SK |
405 | * Initiate (and continue) low level master read/write transaction. |
406 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
407 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
408 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 | 409 | */ |
bccd780f | 410 | static void |
e77cf232 | 411 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 412 | { |
1ab52cf9 | 413 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 414 | u32 intr_mask; |
ae72222d | 415 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
416 | u32 addr = msgs[dev->msg_write_idx].addr; |
417 | u32 buf_len = dev->tx_buf_len; | |
69932487 | 418 | u8 *buf = dev->tx_buf; |
1ab52cf9 | 419 | |
201d6a70 | 420 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
c70c5cd3 | 421 | |
6d2ea487 | 422 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
a0e06ea6 SK |
423 | /* |
424 | * if target address has changed, we need to | |
1ab52cf9 BS |
425 | * reprogram the target address in the i2c |
426 | * adapter when we are done with this transfer | |
427 | */ | |
8f588e40 SK |
428 | if (msgs[dev->msg_write_idx].addr != addr) { |
429 | dev_err(dev->dev, | |
430 | "%s: invalid target address\n", __func__); | |
431 | dev->msg_err = -EINVAL; | |
432 | break; | |
433 | } | |
1ab52cf9 BS |
434 | |
435 | if (msgs[dev->msg_write_idx].len == 0) { | |
436 | dev_err(dev->dev, | |
437 | "%s: invalid message length\n", __func__); | |
438 | dev->msg_err = -EINVAL; | |
8f588e40 | 439 | break; |
1ab52cf9 BS |
440 | } |
441 | ||
442 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
443 | /* new i2c_msg */ | |
26ea15b1 | 444 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 BS |
445 | buf_len = msgs[dev->msg_write_idx].len; |
446 | } | |
447 | ||
7f279601 JHD |
448 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
449 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); | |
ae72222d | 450 | |
1ab52cf9 | 451 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
17a76b4b MW |
452 | u32 cmd = 0; |
453 | ||
454 | /* | |
455 | * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must | |
456 | * manually set the stop bit. However, it cannot be | |
457 | * detected from the registers so we set it always | |
458 | * when writing/reading the last byte. | |
459 | */ | |
460 | if (dev->msg_write_idx == dev->msgs_num - 1 && | |
461 | buf_len == 1) | |
462 | cmd |= BIT(9); | |
463 | ||
1ab52cf9 | 464 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
e6f34cea JA |
465 | |
466 | /* avoid rx buffer overrun */ | |
467 | if (rx_limit - dev->rx_outstanding <= 0) | |
468 | break; | |
469 | ||
17a76b4b | 470 | dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); |
1ab52cf9 | 471 | rx_limit--; |
e6f34cea | 472 | dev->rx_outstanding++; |
1ab52cf9 | 473 | } else |
17a76b4b | 474 | dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); |
1ab52cf9 BS |
475 | tx_limit--; buf_len--; |
476 | } | |
c70c5cd3 | 477 | |
26ea15b1 | 478 | dev->tx_buf = buf; |
c70c5cd3 SK |
479 | dev->tx_buf_len = buf_len; |
480 | ||
481 | if (buf_len > 0) { | |
482 | /* more bytes to be written */ | |
c70c5cd3 SK |
483 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
484 | break; | |
69151e53 | 485 | } else |
c70c5cd3 | 486 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
487 | } |
488 | ||
69151e53 SK |
489 | /* |
490 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
491 | * interrupt any more. | |
492 | */ | |
493 | if (dev->msg_write_idx == dev->msgs_num) | |
494 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
495 | ||
8f588e40 SK |
496 | if (dev->msg_err) |
497 | intr_mask = 0; | |
498 | ||
2373f6b9 | 499 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
1ab52cf9 BS |
500 | } |
501 | ||
502 | static void | |
78839bd0 | 503 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 504 | { |
1ab52cf9 | 505 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 506 | int rx_valid; |
1ab52cf9 | 507 | |
6d2ea487 | 508 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 509 | u32 len; |
1ab52cf9 BS |
510 | u8 *buf; |
511 | ||
512 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
513 | continue; | |
514 | ||
1ab52cf9 BS |
515 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
516 | len = msgs[dev->msg_read_idx].len; | |
517 | buf = msgs[dev->msg_read_idx].buf; | |
518 | } else { | |
519 | len = dev->rx_buf_len; | |
520 | buf = dev->rx_buf; | |
521 | } | |
522 | ||
7f279601 | 523 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
ae72222d | 524 | |
e6f34cea | 525 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) { |
7f279601 | 526 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
e6f34cea JA |
527 | dev->rx_outstanding--; |
528 | } | |
1ab52cf9 BS |
529 | |
530 | if (len > 0) { | |
531 | dev->status |= STATUS_READ_IN_PROGRESS; | |
532 | dev->rx_buf_len = len; | |
533 | dev->rx_buf = buf; | |
534 | return; | |
535 | } else | |
536 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
537 | } | |
538 | } | |
539 | ||
ce6eb574 SK |
540 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
541 | { | |
542 | unsigned long abort_source = dev->abort_source; | |
543 | int i; | |
544 | ||
6d1ea0f6 | 545 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
984b3f57 | 546 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
6d1ea0f6 SK |
547 | dev_dbg(dev->dev, |
548 | "%s: %s\n", __func__, abort_sources[i]); | |
549 | return -EREMOTEIO; | |
550 | } | |
551 | ||
984b3f57 | 552 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
ce6eb574 SK |
553 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
554 | ||
555 | if (abort_source & DW_IC_TX_ARB_LOST) | |
556 | return -EAGAIN; | |
ce6eb574 SK |
557 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
558 | return -EINVAL; /* wrong msgs[] data */ | |
559 | else | |
560 | return -EIO; | |
561 | } | |
562 | ||
1ab52cf9 BS |
563 | /* |
564 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
565 | */ | |
2373f6b9 | 566 | int |
1ab52cf9 BS |
567 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
568 | { | |
569 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
570 | int ret; | |
571 | ||
572 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
573 | ||
574 | mutex_lock(&dev->lock); | |
18dbdda8 | 575 | pm_runtime_get_sync(dev->dev); |
1ab52cf9 BS |
576 | |
577 | INIT_COMPLETION(dev->cmd_complete); | |
578 | dev->msgs = msgs; | |
579 | dev->msgs_num = num; | |
580 | dev->cmd_err = 0; | |
581 | dev->msg_write_idx = 0; | |
582 | dev->msg_read_idx = 0; | |
583 | dev->msg_err = 0; | |
584 | dev->status = STATUS_IDLE; | |
ce6eb574 | 585 | dev->abort_source = 0; |
e6f34cea | 586 | dev->rx_outstanding = 0; |
1ab52cf9 BS |
587 | |
588 | ret = i2c_dw_wait_bus_not_busy(dev); | |
589 | if (ret < 0) | |
590 | goto done; | |
591 | ||
592 | /* start the transfers */ | |
81e798b7 | 593 | i2c_dw_xfer_init(dev); |
1ab52cf9 BS |
594 | |
595 | /* wait for tx to complete */ | |
e42dba56 | 596 | ret = wait_for_completion_timeout(&dev->cmd_complete, HZ); |
1ab52cf9 BS |
597 | if (ret == 0) { |
598 | dev_err(dev->dev, "controller timed out\n"); | |
38d7fade | 599 | /* i2c_dw_init implicitly disables the adapter */ |
1ab52cf9 BS |
600 | i2c_dw_init(dev); |
601 | ret = -ETIMEDOUT; | |
602 | goto done; | |
e42dba56 | 603 | } |
1ab52cf9 | 604 | |
38d7fade CR |
605 | /* |
606 | * We must disable the adapter before unlocking the &dev->lock mutex | |
607 | * below. Otherwise the hardware might continue generating interrupts | |
608 | * which in turn causes a race condition with the following transfer. | |
609 | * Needs some more investigation if the additional interrupts are | |
610 | * a hardware bug or this driver doesn't handle them correctly yet. | |
611 | */ | |
612 | __i2c_dw_enable(dev, false); | |
613 | ||
1ab52cf9 BS |
614 | if (dev->msg_err) { |
615 | ret = dev->msg_err; | |
616 | goto done; | |
617 | } | |
618 | ||
619 | /* no error */ | |
620 | if (likely(!dev->cmd_err)) { | |
1ab52cf9 BS |
621 | ret = num; |
622 | goto done; | |
623 | } | |
624 | ||
625 | /* We have an error */ | |
626 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
627 | ret = i2c_dw_handle_tx_abort(dev); |
628 | goto done; | |
1ab52cf9 BS |
629 | } |
630 | ret = -EIO; | |
631 | ||
632 | done: | |
43452335 MW |
633 | pm_runtime_mark_last_busy(dev->dev); |
634 | pm_runtime_put_autosuspend(dev->dev); | |
1ab52cf9 BS |
635 | mutex_unlock(&dev->lock); |
636 | ||
637 | return ret; | |
638 | } | |
e68bb91b | 639 | EXPORT_SYMBOL_GPL(i2c_dw_xfer); |
1ab52cf9 | 640 | |
2373f6b9 | 641 | u32 i2c_dw_func(struct i2c_adapter *adap) |
1ab52cf9 | 642 | { |
2fa8326b DB |
643 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
644 | return dev->functionality; | |
1ab52cf9 | 645 | } |
e68bb91b | 646 | EXPORT_SYMBOL_GPL(i2c_dw_func); |
1ab52cf9 | 647 | |
e28000a3 SK |
648 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
649 | { | |
650 | u32 stat; | |
651 | ||
652 | /* | |
653 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
654 | * Ths unmasked raw version of interrupt status bits are available | |
655 | * in the IC_RAW_INTR_STAT register. | |
656 | * | |
657 | * That is, | |
2373f6b9 | 658 | * stat = dw_readl(IC_INTR_STAT); |
e28000a3 | 659 | * equals to, |
2373f6b9 | 660 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
e28000a3 SK |
661 | * |
662 | * The raw version might be useful for debugging purposes. | |
663 | */ | |
7f279601 | 664 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
e28000a3 SK |
665 | |
666 | /* | |
667 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
668 | * you'll miss some interrupts, triggered during the period from | |
2373f6b9 | 669 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
e28000a3 SK |
670 | * |
671 | * Instead, use the separately-prepared IC_CLR_* registers. | |
672 | */ | |
673 | if (stat & DW_IC_INTR_RX_UNDER) | |
7f279601 | 674 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
e28000a3 | 675 | if (stat & DW_IC_INTR_RX_OVER) |
7f279601 | 676 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
e28000a3 | 677 | if (stat & DW_IC_INTR_TX_OVER) |
7f279601 | 678 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
e28000a3 | 679 | if (stat & DW_IC_INTR_RD_REQ) |
7f279601 | 680 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
e28000a3 SK |
681 | if (stat & DW_IC_INTR_TX_ABRT) { |
682 | /* | |
683 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
684 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
685 | */ | |
7f279601 JHD |
686 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
687 | dw_readl(dev, DW_IC_CLR_TX_ABRT); | |
e28000a3 SK |
688 | } |
689 | if (stat & DW_IC_INTR_RX_DONE) | |
7f279601 | 690 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
e28000a3 | 691 | if (stat & DW_IC_INTR_ACTIVITY) |
7f279601 | 692 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
e28000a3 | 693 | if (stat & DW_IC_INTR_STOP_DET) |
7f279601 | 694 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
e28000a3 | 695 | if (stat & DW_IC_INTR_START_DET) |
7f279601 | 696 | dw_readl(dev, DW_IC_CLR_START_DET); |
e28000a3 | 697 | if (stat & DW_IC_INTR_GEN_CALL) |
7f279601 | 698 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
e28000a3 SK |
699 | |
700 | return stat; | |
701 | } | |
702 | ||
1ab52cf9 BS |
703 | /* |
704 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
705 | * occurs. | |
706 | */ | |
2373f6b9 | 707 | irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
1ab52cf9 BS |
708 | { |
709 | struct dw_i2c_dev *dev = dev_id; | |
af06cf6c DB |
710 | u32 stat, enabled; |
711 | ||
712 | enabled = dw_readl(dev, DW_IC_ENABLE); | |
713 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); | |
714 | dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__, | |
715 | dev->adapter.name, enabled, stat); | |
716 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) | |
717 | return IRQ_NONE; | |
1ab52cf9 | 718 | |
e28000a3 | 719 | stat = i2c_dw_read_clear_intrbits(dev); |
e28000a3 | 720 | |
1ab52cf9 | 721 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
722 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
723 | dev->status = STATUS_IDLE; | |
597fe310 SK |
724 | |
725 | /* | |
726 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
727 | * buffers are flushed. Make sure to skip them. | |
728 | */ | |
7f279601 | 729 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
597fe310 | 730 | goto tx_aborted; |
07745399 SK |
731 | } |
732 | ||
21a89d41 | 733 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 734 | i2c_dw_read(dev); |
21a89d41 SK |
735 | |
736 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 737 | i2c_dw_xfer_msg(dev); |
07745399 SK |
738 | |
739 | /* | |
740 | * No need to modify or disable the interrupt mask here. | |
741 | * i2c_dw_xfer_msg() will take care of it according to | |
742 | * the current transmit status. | |
743 | */ | |
1ab52cf9 | 744 | |
597fe310 | 745 | tx_aborted: |
8f588e40 | 746 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 BS |
747 | complete(&dev->cmd_complete); |
748 | ||
749 | return IRQ_HANDLED; | |
750 | } | |
e68bb91b | 751 | EXPORT_SYMBOL_GPL(i2c_dw_isr); |
f3fa9f3d DB |
752 | |
753 | void i2c_dw_enable(struct dw_i2c_dev *dev) | |
754 | { | |
755 | /* Enable the adapter */ | |
3ca4ed87 | 756 | __i2c_dw_enable(dev, true); |
f3fa9f3d | 757 | } |
e68bb91b | 758 | EXPORT_SYMBOL_GPL(i2c_dw_enable); |
f3fa9f3d | 759 | |
18dbdda8 | 760 | u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev) |
f3fa9f3d | 761 | { |
18dbdda8 DB |
762 | return dw_readl(dev, DW_IC_ENABLE); |
763 | } | |
e68bb91b | 764 | EXPORT_SYMBOL_GPL(i2c_dw_is_enabled); |
f3fa9f3d | 765 | |
18dbdda8 DB |
766 | void i2c_dw_disable(struct dw_i2c_dev *dev) |
767 | { | |
f3fa9f3d | 768 | /* Disable controller */ |
3ca4ed87 | 769 | __i2c_dw_enable(dev, false); |
f3fa9f3d DB |
770 | |
771 | /* Disable all interupts */ | |
772 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
773 | dw_readl(dev, DW_IC_CLR_INTR); | |
774 | } | |
e68bb91b | 775 | EXPORT_SYMBOL_GPL(i2c_dw_disable); |
f3fa9f3d DB |
776 | |
777 | void i2c_dw_clear_int(struct dw_i2c_dev *dev) | |
778 | { | |
779 | dw_readl(dev, DW_IC_CLR_INTR); | |
780 | } | |
e68bb91b | 781 | EXPORT_SYMBOL_GPL(i2c_dw_clear_int); |
f3fa9f3d DB |
782 | |
783 | void i2c_dw_disable_int(struct dw_i2c_dev *dev) | |
784 | { | |
785 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
786 | } | |
e68bb91b | 787 | EXPORT_SYMBOL_GPL(i2c_dw_disable_int); |
f3fa9f3d DB |
788 | |
789 | u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) | |
790 | { | |
791 | return dw_readl(dev, DW_IC_COMP_PARAM_1); | |
792 | } | |
e68bb91b | 793 | EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); |
9dd3162d MW |
794 | |
795 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); | |
796 | MODULE_LICENSE("GPL"); |