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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
61045dbe JF |
2 | /* |
3 | * Freescale CPM1/CPM2 I2C interface. | |
4 | * Copyright (c) 1999 Dan Malek (dmalek@jlc.net). | |
5 | * | |
6 | * moved into proper i2c interface; | |
7 | * Brad Parker (brad@heeltoe.com) | |
8 | * | |
9 | * Parts from dbox2_i2c.c (cvs.tuxbox.org) | |
10 | * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net) | |
11 | * | |
12 | * (C) 2007 Montavista Software, Inc. | |
13 | * Vitaly Bordug <vitb@kernel.crashing.org> | |
14 | * | |
15 | * Converted to of_platform_device. Renamed to i2c-cpm.c. | |
16 | * (C) 2007,2008 Jochen Friedrich <jochen@scram.de> | |
61045dbe JF |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/slab.h> | |
61045dbe JF |
23 | #include <linux/interrupt.h> |
24 | #include <linux/errno.h> | |
25 | #include <linux/stddef.h> | |
26 | #include <linux/i2c.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/dma-mapping.h> | |
5f12c5ec | 29 | #include <linux/of_address.h> |
61045dbe | 30 | #include <linux/of_device.h> |
5f12c5ec | 31 | #include <linux/of_irq.h> |
61045dbe | 32 | #include <linux/of_platform.h> |
61045dbe JF |
33 | #include <sysdev/fsl_soc.h> |
34 | #include <asm/cpm.h> | |
35 | ||
36 | /* Try to define this if you have an older CPU (earlier than rev D4) */ | |
37 | /* However, better use a GPIO based bitbang driver in this case :/ */ | |
38 | #undef I2C_CHIP_ERRATA | |
39 | ||
40 | #define CPM_MAX_READ 513 | |
41 | #define CPM_MAXBD 4 | |
42 | ||
43 | #define I2C_EB (0x10) /* Big endian mode */ | |
44 | #define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */ | |
45 | ||
46 | #define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0)) | |
47 | ||
48 | /* I2C parameter RAM. */ | |
49 | struct i2c_ram { | |
50 | ushort rbase; /* Rx Buffer descriptor base address */ | |
51 | ushort tbase; /* Tx Buffer descriptor base address */ | |
52 | u_char rfcr; /* Rx function code */ | |
53 | u_char tfcr; /* Tx function code */ | |
54 | ushort mrblr; /* Max receive buffer length */ | |
55 | uint rstate; /* Internal */ | |
56 | uint rdp; /* Internal */ | |
57 | ushort rbptr; /* Rx Buffer descriptor pointer */ | |
58 | ushort rbc; /* Internal */ | |
59 | uint rxtmp; /* Internal */ | |
60 | uint tstate; /* Internal */ | |
61 | uint tdp; /* Internal */ | |
62 | ushort tbptr; /* Tx Buffer descriptor pointer */ | |
63 | ushort tbc; /* Internal */ | |
64 | uint txtmp; /* Internal */ | |
65 | char res1[4]; /* Reserved */ | |
66 | ushort rpbase; /* Relocation pointer */ | |
67 | char res2[2]; /* Reserved */ | |
68 | }; | |
69 | ||
70 | #define I2COM_START 0x80 | |
71 | #define I2COM_MASTER 0x01 | |
72 | #define I2CER_TXE 0x10 | |
73 | #define I2CER_BUSY 0x04 | |
74 | #define I2CER_TXB 0x02 | |
75 | #define I2CER_RXB 0x01 | |
76 | #define I2MOD_EN 0x01 | |
77 | ||
78 | /* I2C Registers */ | |
79 | struct i2c_reg { | |
80 | u8 i2mod; | |
81 | u8 res1[3]; | |
82 | u8 i2add; | |
83 | u8 res2[3]; | |
84 | u8 i2brg; | |
85 | u8 res3[3]; | |
86 | u8 i2com; | |
87 | u8 res4[3]; | |
88 | u8 i2cer; | |
89 | u8 res5[3]; | |
90 | u8 i2cmr; | |
91 | }; | |
92 | ||
93 | struct cpm_i2c { | |
94 | char *base; | |
2dc11581 | 95 | struct platform_device *ofdev; |
61045dbe JF |
96 | struct i2c_adapter adap; |
97 | uint dp_addr; | |
98 | int version; /* CPM1=1, CPM2=2 */ | |
99 | int irq; | |
100 | int cp_command; | |
101 | int freq; | |
102 | struct i2c_reg __iomem *i2c_reg; | |
103 | struct i2c_ram __iomem *i2c_ram; | |
104 | u16 i2c_addr; | |
105 | wait_queue_head_t i2c_wait; | |
106 | cbd_t __iomem *tbase; | |
107 | cbd_t __iomem *rbase; | |
108 | u_char *txbuf[CPM_MAXBD]; | |
109 | u_char *rxbuf[CPM_MAXBD]; | |
609d5a1b ME |
110 | dma_addr_t txdma[CPM_MAXBD]; |
111 | dma_addr_t rxdma[CPM_MAXBD]; | |
61045dbe JF |
112 | }; |
113 | ||
114 | static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id) | |
115 | { | |
116 | struct cpm_i2c *cpm; | |
117 | struct i2c_reg __iomem *i2c_reg; | |
118 | struct i2c_adapter *adap = dev_id; | |
119 | int i; | |
120 | ||
121 | cpm = i2c_get_adapdata(dev_id); | |
122 | i2c_reg = cpm->i2c_reg; | |
123 | ||
124 | /* Clear interrupt. */ | |
125 | i = in_8(&i2c_reg->i2cer); | |
126 | out_8(&i2c_reg->i2cer, i); | |
127 | ||
128 | dev_dbg(&adap->dev, "Interrupt: %x\n", i); | |
129 | ||
dc1972d0 | 130 | wake_up(&cpm->i2c_wait); |
61045dbe JF |
131 | |
132 | return i ? IRQ_HANDLED : IRQ_NONE; | |
133 | } | |
134 | ||
135 | static void cpm_reset_i2c_params(struct cpm_i2c *cpm) | |
136 | { | |
137 | struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram; | |
138 | ||
139 | /* Set up the I2C parameters in the parameter ram. */ | |
140 | out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE); | |
141 | out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE); | |
142 | ||
143 | if (cpm->version == 1) { | |
144 | out_8(&i2c_ram->tfcr, I2C_EB); | |
145 | out_8(&i2c_ram->rfcr, I2C_EB); | |
146 | } else { | |
147 | out_8(&i2c_ram->tfcr, I2C_EB_CPM2); | |
148 | out_8(&i2c_ram->rfcr, I2C_EB_CPM2); | |
149 | } | |
150 | ||
151 | out_be16(&i2c_ram->mrblr, CPM_MAX_READ); | |
152 | ||
153 | out_be32(&i2c_ram->rstate, 0); | |
154 | out_be32(&i2c_ram->rdp, 0); | |
155 | out_be16(&i2c_ram->rbptr, 0); | |
156 | out_be16(&i2c_ram->rbc, 0); | |
157 | out_be32(&i2c_ram->rxtmp, 0); | |
158 | out_be32(&i2c_ram->tstate, 0); | |
159 | out_be32(&i2c_ram->tdp, 0); | |
160 | out_be16(&i2c_ram->tbptr, 0); | |
161 | out_be16(&i2c_ram->tbc, 0); | |
162 | out_be32(&i2c_ram->txtmp, 0); | |
163 | } | |
164 | ||
165 | static void cpm_i2c_force_close(struct i2c_adapter *adap) | |
166 | { | |
167 | struct cpm_i2c *cpm = i2c_get_adapdata(adap); | |
168 | struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg; | |
169 | ||
170 | dev_dbg(&adap->dev, "cpm_i2c_force_close()\n"); | |
171 | ||
172 | cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD); | |
173 | ||
174 | out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */ | |
175 | out_8(&i2c_reg->i2cer, 0xff); | |
176 | } | |
177 | ||
178 | static void cpm_i2c_parse_message(struct i2c_adapter *adap, | |
179 | struct i2c_msg *pmsg, int num, int tx, int rx) | |
180 | { | |
181 | cbd_t __iomem *tbdf; | |
182 | cbd_t __iomem *rbdf; | |
183 | u_char addr; | |
184 | u_char *tb; | |
185 | u_char *rb; | |
186 | struct cpm_i2c *cpm = i2c_get_adapdata(adap); | |
187 | ||
188 | tbdf = cpm->tbase + tx; | |
189 | rbdf = cpm->rbase + rx; | |
190 | ||
949d0c5b | 191 | addr = i2c_8bit_addr_from_msg(pmsg); |
61045dbe JF |
192 | |
193 | tb = cpm->txbuf[tx]; | |
194 | rb = cpm->rxbuf[rx]; | |
195 | ||
196 | /* Align read buffer */ | |
197 | rb = (u_char *) (((ulong) rb + 1) & ~1); | |
198 | ||
199 | tb[0] = addr; /* Device address byte w/rw flag */ | |
200 | ||
201 | out_be16(&tbdf->cbd_datlen, pmsg->len + 1); | |
202 | out_be16(&tbdf->cbd_sc, 0); | |
203 | ||
204 | if (!(pmsg->flags & I2C_M_NOSTART)) | |
205 | setbits16(&tbdf->cbd_sc, BD_I2C_START); | |
206 | ||
207 | if (tx + 1 == num) | |
208 | setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP); | |
209 | ||
210 | if (pmsg->flags & I2C_M_RD) { | |
211 | /* | |
212 | * To read, we need an empty buffer of the proper length. | |
213 | * All that is used is the first byte for address, the remainder | |
214 | * is just used for timing (and doesn't really have to exist). | |
215 | */ | |
216 | ||
217 | dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr); | |
218 | ||
219 | out_be16(&rbdf->cbd_datlen, 0); | |
220 | out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); | |
221 | ||
222 | if (rx + 1 == CPM_MAXBD) | |
223 | setbits16(&rbdf->cbd_sc, BD_SC_WRAP); | |
224 | ||
225 | eieio(); | |
226 | setbits16(&tbdf->cbd_sc, BD_SC_READY); | |
227 | } else { | |
3b270804 | 228 | dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr); |
61045dbe JF |
229 | |
230 | memcpy(tb+1, pmsg->buf, pmsg->len); | |
231 | ||
232 | eieio(); | |
233 | setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT); | |
234 | } | |
235 | } | |
236 | ||
237 | static int cpm_i2c_check_message(struct i2c_adapter *adap, | |
238 | struct i2c_msg *pmsg, int tx, int rx) | |
239 | { | |
240 | cbd_t __iomem *tbdf; | |
241 | cbd_t __iomem *rbdf; | |
242 | u_char *tb; | |
243 | u_char *rb; | |
244 | struct cpm_i2c *cpm = i2c_get_adapdata(adap); | |
245 | ||
246 | tbdf = cpm->tbase + tx; | |
247 | rbdf = cpm->rbase + rx; | |
248 | ||
249 | tb = cpm->txbuf[tx]; | |
250 | rb = cpm->rxbuf[rx]; | |
251 | ||
252 | /* Align read buffer */ | |
253 | rb = (u_char *) (((uint) rb + 1) & ~1); | |
254 | ||
255 | eieio(); | |
256 | if (pmsg->flags & I2C_M_RD) { | |
257 | dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n", | |
258 | in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc)); | |
259 | ||
260 | if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) { | |
261 | dev_dbg(&adap->dev, "I2C read; No ack\n"); | |
262 | return -ENXIO; | |
263 | } | |
264 | if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) { | |
265 | dev_err(&adap->dev, | |
266 | "I2C read; complete but rbuf empty\n"); | |
267 | return -EREMOTEIO; | |
268 | } | |
269 | if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) { | |
270 | dev_err(&adap->dev, "I2C read; Overrun\n"); | |
271 | return -EREMOTEIO; | |
272 | } | |
273 | memcpy(pmsg->buf, rb, pmsg->len); | |
274 | } else { | |
275 | dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx, | |
276 | in_be16(&tbdf->cbd_sc)); | |
277 | ||
278 | if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) { | |
279 | dev_dbg(&adap->dev, "I2C write; No ack\n"); | |
280 | return -ENXIO; | |
281 | } | |
282 | if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) { | |
283 | dev_err(&adap->dev, "I2C write; Underrun\n"); | |
284 | return -EIO; | |
285 | } | |
286 | if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) { | |
287 | dev_err(&adap->dev, "I2C write; Collision\n"); | |
288 | return -EIO; | |
289 | } | |
290 | } | |
291 | return 0; | |
292 | } | |
293 | ||
294 | static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
295 | { | |
296 | struct cpm_i2c *cpm = i2c_get_adapdata(adap); | |
297 | struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg; | |
298 | struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram; | |
299 | struct i2c_msg *pmsg; | |
b94c820f | 300 | int ret; |
61045dbe JF |
301 | int tptr; |
302 | int rptr; | |
303 | cbd_t __iomem *tbdf; | |
304 | cbd_t __iomem *rbdf; | |
305 | ||
61045dbe JF |
306 | /* Reset to use first buffer */ |
307 | out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase)); | |
308 | out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase)); | |
309 | ||
310 | tbdf = cpm->tbase; | |
311 | rbdf = cpm->rbase; | |
312 | ||
313 | tptr = 0; | |
314 | rptr = 0; | |
315 | ||
a16d8aa4 SS |
316 | /* |
317 | * If there was a collision in the last i2c transaction, | |
318 | * Set I2COM_MASTER as it was cleared during collision. | |
319 | */ | |
320 | if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) { | |
321 | out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); | |
322 | } | |
323 | ||
61045dbe JF |
324 | while (tptr < num) { |
325 | pmsg = &msgs[tptr]; | |
326 | dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr); | |
327 | ||
328 | cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr); | |
329 | if (pmsg->flags & I2C_M_RD) | |
330 | rptr++; | |
331 | tptr++; | |
332 | } | |
333 | /* Start transfer now */ | |
334 | /* Enable RX/TX/Error interupts */ | |
3b270804 | 335 | out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB); |
61045dbe JF |
336 | out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */ |
337 | /* Chip bug, set enable here */ | |
338 | setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */ | |
339 | /* Begin transmission */ | |
340 | setbits8(&i2c_reg->i2com, I2COM_START); | |
341 | ||
342 | tptr = 0; | |
343 | rptr = 0; | |
344 | ||
345 | while (tptr < num) { | |
346 | /* Check for outstanding messages */ | |
347 | dev_dbg(&adap->dev, "test ready.\n"); | |
348 | pmsg = &msgs[tptr]; | |
349 | if (pmsg->flags & I2C_M_RD) | |
dc1972d0 | 350 | ret = wait_event_timeout(cpm->i2c_wait, |
a804644a | 351 | (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) || |
61045dbe JF |
352 | !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY), |
353 | 1 * HZ); | |
354 | else | |
dc1972d0 | 355 | ret = wait_event_timeout(cpm->i2c_wait, |
61045dbe JF |
356 | !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY), |
357 | 1 * HZ); | |
358 | if (ret == 0) { | |
359 | ret = -EREMOTEIO; | |
360 | dev_err(&adap->dev, "I2C transfer: timeout\n"); | |
361 | goto out_err; | |
362 | } | |
363 | if (ret > 0) { | |
364 | dev_dbg(&adap->dev, "ready.\n"); | |
365 | ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr); | |
366 | tptr++; | |
367 | if (pmsg->flags & I2C_M_RD) | |
368 | rptr++; | |
369 | if (ret) | |
370 | goto out_err; | |
371 | } | |
372 | } | |
373 | #ifdef I2C_CHIP_ERRATA | |
374 | /* | |
375 | * Chip errata, clear enable. This is not needed on rev D4 CPUs. | |
376 | * Disabling I2C too early may cause too short stop condition | |
377 | */ | |
378 | udelay(4); | |
379 | clrbits8(&i2c_reg->i2mod, I2MOD_EN); | |
380 | #endif | |
381 | return (num); | |
382 | ||
383 | out_err: | |
384 | cpm_i2c_force_close(adap); | |
385 | #ifdef I2C_CHIP_ERRATA | |
386 | /* | |
387 | * Chip errata, clear enable. This is not needed on rev D4 CPUs. | |
388 | */ | |
389 | clrbits8(&i2c_reg->i2mod, I2MOD_EN); | |
390 | #endif | |
391 | return ret; | |
392 | } | |
393 | ||
394 | static u32 cpm_i2c_func(struct i2c_adapter *adap) | |
395 | { | |
396 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
397 | } | |
398 | ||
399 | /* -----exported algorithm data: ------------------------------------- */ | |
400 | ||
401 | static const struct i2c_algorithm cpm_i2c_algo = { | |
402 | .master_xfer = cpm_i2c_xfer, | |
403 | .functionality = cpm_i2c_func, | |
404 | }; | |
405 | ||
b94c820f | 406 | /* CPM_MAX_READ is also limiting writes according to the code! */ |
ae3923a2 | 407 | static const struct i2c_adapter_quirks cpm_i2c_quirks = { |
b94c820f WS |
408 | .max_num_msgs = CPM_MAXBD, |
409 | .max_read_len = CPM_MAX_READ, | |
410 | .max_write_len = CPM_MAX_READ, | |
411 | }; | |
412 | ||
61045dbe JF |
413 | static const struct i2c_adapter cpm_ops = { |
414 | .owner = THIS_MODULE, | |
415 | .name = "i2c-cpm", | |
416 | .algo = &cpm_i2c_algo, | |
b94c820f | 417 | .quirks = &cpm_i2c_quirks, |
61045dbe JF |
418 | }; |
419 | ||
0b255e92 | 420 | static int cpm_i2c_setup(struct cpm_i2c *cpm) |
61045dbe | 421 | { |
2dc11581 | 422 | struct platform_device *ofdev = cpm->ofdev; |
61045dbe JF |
423 | const u32 *data; |
424 | int len, ret, i; | |
425 | void __iomem *i2c_base; | |
426 | cbd_t __iomem *tbdf; | |
427 | cbd_t __iomem *rbdf; | |
428 | unsigned char brg; | |
429 | ||
430 | dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n"); | |
431 | ||
432 | init_waitqueue_head(&cpm->i2c_wait); | |
433 | ||
f7578496 | 434 | cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); |
b865a4e7 | 435 | if (!cpm->irq) |
61045dbe JF |
436 | return -EINVAL; |
437 | ||
438 | /* Install interrupt handler. */ | |
439 | ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c", | |
440 | &cpm->adap); | |
441 | if (ret) | |
442 | return ret; | |
443 | ||
444 | /* I2C parameter RAM */ | |
61c7a080 | 445 | i2c_base = of_iomap(ofdev->dev.of_node, 1); |
61045dbe JF |
446 | if (i2c_base == NULL) { |
447 | ret = -EINVAL; | |
448 | goto out_irq; | |
449 | } | |
450 | ||
61c7a080 | 451 | if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) { |
61045dbe JF |
452 | |
453 | /* Check for and use a microcode relocation patch. */ | |
454 | cpm->i2c_ram = i2c_base; | |
455 | cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase); | |
456 | ||
457 | /* | |
458 | * Maybe should use cpm_muram_alloc instead of hardcoding | |
459 | * this in micropatch.c | |
460 | */ | |
461 | if (cpm->i2c_addr) { | |
462 | cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr); | |
463 | iounmap(i2c_base); | |
464 | } | |
465 | ||
466 | cpm->version = 1; | |
467 | ||
61c7a080 | 468 | } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) { |
61045dbe JF |
469 | cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64); |
470 | cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr); | |
471 | out_be16(i2c_base, cpm->i2c_addr); | |
472 | iounmap(i2c_base); | |
473 | ||
474 | cpm->version = 2; | |
475 | ||
476 | } else { | |
477 | iounmap(i2c_base); | |
478 | ret = -EINVAL; | |
479 | goto out_irq; | |
480 | } | |
481 | ||
482 | /* I2C control/status registers */ | |
61c7a080 | 483 | cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0); |
61045dbe JF |
484 | if (cpm->i2c_reg == NULL) { |
485 | ret = -EINVAL; | |
486 | goto out_ram; | |
487 | } | |
488 | ||
61c7a080 | 489 | data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len); |
61045dbe JF |
490 | if (!data || len != 4) { |
491 | ret = -EINVAL; | |
492 | goto out_reg; | |
493 | } | |
494 | cpm->cp_command = *data; | |
495 | ||
61c7a080 | 496 | data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len); |
61045dbe JF |
497 | if (data && len == 4) |
498 | cpm->adap.class = *data; | |
499 | ||
61c7a080 | 500 | data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len); |
61045dbe JF |
501 | if (data && len == 4) |
502 | cpm->freq = *data; | |
503 | else | |
504 | cpm->freq = 60000; /* use 60kHz i2c clock by default */ | |
505 | ||
506 | /* | |
507 | * Allocate space for CPM_MAXBD transmit and receive buffer | |
508 | * descriptors in the DP ram. | |
509 | */ | |
510 | cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8); | |
511 | if (!cpm->dp_addr) { | |
512 | ret = -ENOMEM; | |
513 | goto out_reg; | |
514 | } | |
515 | ||
516 | cpm->tbase = cpm_muram_addr(cpm->dp_addr); | |
517 | cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD); | |
518 | ||
519 | /* Allocate TX and RX buffers */ | |
520 | ||
521 | tbdf = cpm->tbase; | |
522 | rbdf = cpm->rbase; | |
523 | ||
524 | for (i = 0; i < CPM_MAXBD; i++) { | |
36521c27 MW |
525 | cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev, |
526 | CPM_MAX_READ + 1, | |
527 | &cpm->rxdma[i], GFP_KERNEL); | |
61045dbe JF |
528 | if (!cpm->rxbuf[i]) { |
529 | ret = -ENOMEM; | |
530 | goto out_muram; | |
531 | } | |
532 | out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1)); | |
533 | ||
36521c27 | 534 | cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL); |
61045dbe JF |
535 | if (!cpm->txbuf[i]) { |
536 | ret = -ENOMEM; | |
537 | goto out_muram; | |
538 | } | |
539 | out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]); | |
540 | } | |
541 | ||
542 | /* Initialize Tx/Rx parameters. */ | |
543 | ||
544 | cpm_reset_i2c_params(cpm); | |
545 | ||
3b270804 WS |
546 | dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n", |
547 | cpm->i2c_ram, cpm->i2c_addr, cpm->freq); | |
61045dbe JF |
548 | dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n", |
549 | (u8 __iomem *)cpm->tbase - DPRAM_BASE, | |
550 | (u8 __iomem *)cpm->rbase - DPRAM_BASE); | |
551 | ||
552 | cpm_command(cpm->cp_command, CPM_CR_INIT_TRX); | |
553 | ||
554 | /* | |
555 | * Select an invalid address. Just make sure we don't use loopback mode | |
556 | */ | |
557 | out_8(&cpm->i2c_reg->i2add, 0x7f << 1); | |
558 | ||
559 | /* | |
560 | * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the | |
561 | * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get | |
562 | * the actual i2c bus frequency. | |
563 | */ | |
564 | brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3; | |
565 | out_8(&cpm->i2c_reg->i2brg, brg); | |
566 | ||
567 | out_8(&cpm->i2c_reg->i2mod, 0x00); | |
568 | out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */ | |
569 | ||
570 | /* Disable interrupts. */ | |
571 | out_8(&cpm->i2c_reg->i2cmr, 0); | |
572 | out_8(&cpm->i2c_reg->i2cer, 0xff); | |
573 | ||
574 | return 0; | |
575 | ||
576 | out_muram: | |
577 | for (i = 0; i < CPM_MAXBD; i++) { | |
578 | if (cpm->rxbuf[i]) | |
36521c27 | 579 | dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, |
61045dbe JF |
580 | cpm->rxbuf[i], cpm->rxdma[i]); |
581 | if (cpm->txbuf[i]) | |
36521c27 | 582 | dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, |
61045dbe JF |
583 | cpm->txbuf[i], cpm->txdma[i]); |
584 | } | |
585 | cpm_muram_free(cpm->dp_addr); | |
586 | out_reg: | |
587 | iounmap(cpm->i2c_reg); | |
588 | out_ram: | |
589 | if ((cpm->version == 1) && (!cpm->i2c_addr)) | |
590 | iounmap(cpm->i2c_ram); | |
591 | if (cpm->version == 2) | |
592 | cpm_muram_free(cpm->i2c_addr); | |
593 | out_irq: | |
594 | free_irq(cpm->irq, &cpm->adap); | |
595 | return ret; | |
596 | } | |
597 | ||
598 | static void cpm_i2c_shutdown(struct cpm_i2c *cpm) | |
599 | { | |
600 | int i; | |
601 | ||
602 | /* Shut down I2C. */ | |
603 | clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN); | |
604 | ||
605 | /* Disable interrupts */ | |
606 | out_8(&cpm->i2c_reg->i2cmr, 0); | |
607 | out_8(&cpm->i2c_reg->i2cer, 0xff); | |
608 | ||
609 | free_irq(cpm->irq, &cpm->adap); | |
610 | ||
611 | /* Free all memory */ | |
612 | for (i = 0; i < CPM_MAXBD; i++) { | |
36521c27 | 613 | dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, |
61045dbe | 614 | cpm->rxbuf[i], cpm->rxdma[i]); |
36521c27 | 615 | dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, |
61045dbe JF |
616 | cpm->txbuf[i], cpm->txdma[i]); |
617 | } | |
618 | ||
619 | cpm_muram_free(cpm->dp_addr); | |
620 | iounmap(cpm->i2c_reg); | |
621 | ||
622 | if ((cpm->version == 1) && (!cpm->i2c_addr)) | |
623 | iounmap(cpm->i2c_ram); | |
624 | if (cpm->version == 2) | |
625 | cpm_muram_free(cpm->i2c_addr); | |
626 | } | |
627 | ||
0b255e92 | 628 | static int cpm_i2c_probe(struct platform_device *ofdev) |
61045dbe JF |
629 | { |
630 | int result, len; | |
631 | struct cpm_i2c *cpm; | |
632 | const u32 *data; | |
633 | ||
634 | cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL); | |
635 | if (!cpm) | |
636 | return -ENOMEM; | |
637 | ||
638 | cpm->ofdev = ofdev; | |
639 | ||
c2c64954 | 640 | platform_set_drvdata(ofdev, cpm); |
61045dbe JF |
641 | |
642 | cpm->adap = cpm_ops; | |
643 | i2c_set_adapdata(&cpm->adap, cpm); | |
644 | cpm->adap.dev.parent = &ofdev->dev; | |
9fd04992 | 645 | cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node); |
61045dbe JF |
646 | |
647 | result = cpm_i2c_setup(cpm); | |
648 | if (result) { | |
649 | dev_err(&ofdev->dev, "Unable to init hardware\n"); | |
650 | goto out_free; | |
651 | } | |
652 | ||
653 | /* register new adapter to i2c module... */ | |
654 | ||
61c7a080 | 655 | data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len); |
488bf314 GL |
656 | cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1; |
657 | result = i2c_add_numbered_adapter(&cpm->adap); | |
61045dbe | 658 | |
ea734404 | 659 | if (result < 0) |
61045dbe | 660 | goto out_shut; |
61045dbe JF |
661 | |
662 | dev_dbg(&ofdev->dev, "hw routines for %s registered.\n", | |
663 | cpm->adap.name); | |
664 | ||
61045dbe JF |
665 | return 0; |
666 | out_shut: | |
667 | cpm_i2c_shutdown(cpm); | |
668 | out_free: | |
61045dbe JF |
669 | kfree(cpm); |
670 | ||
671 | return result; | |
672 | } | |
673 | ||
0b255e92 | 674 | static int cpm_i2c_remove(struct platform_device *ofdev) |
61045dbe | 675 | { |
c2c64954 | 676 | struct cpm_i2c *cpm = platform_get_drvdata(ofdev); |
61045dbe JF |
677 | |
678 | i2c_del_adapter(&cpm->adap); | |
679 | ||
680 | cpm_i2c_shutdown(cpm); | |
681 | ||
61045dbe JF |
682 | kfree(cpm); |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | static const struct of_device_id cpm_i2c_match[] = { | |
688 | { | |
689 | .compatible = "fsl,cpm1-i2c", | |
690 | }, | |
691 | { | |
692 | .compatible = "fsl,cpm2-i2c", | |
693 | }, | |
694 | {}, | |
695 | }; | |
696 | ||
697 | MODULE_DEVICE_TABLE(of, cpm_i2c_match); | |
698 | ||
1c48a5c9 | 699 | static struct platform_driver cpm_i2c_driver = { |
61045dbe | 700 | .probe = cpm_i2c_probe, |
0b255e92 | 701 | .remove = cpm_i2c_remove, |
4018294b GL |
702 | .driver = { |
703 | .name = "fsl-i2c-cpm", | |
4018294b GL |
704 | .of_match_table = cpm_i2c_match, |
705 | }, | |
61045dbe JF |
706 | }; |
707 | ||
a3664b51 | 708 | module_platform_driver(cpm_i2c_driver); |
61045dbe JF |
709 | |
710 | MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>"); | |
711 | MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards"); | |
712 | MODULE_LICENSE("GPL"); |