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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
df8eb569 SB |
2 | /* |
3 | * I2C bus driver for the Cadence I2C controller. | |
4 | * | |
5 | * Copyright (C) 2009 - 2014 Xilinx, Inc. | |
df8eb569 SB |
6 | */ |
7 | ||
8 | #include <linux/clk.h> | |
9 | #include <linux/delay.h> | |
10 | #include <linux/i2c.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/platform_device.h> | |
63cab195 | 15 | #include <linux/of.h> |
7fa32329 | 16 | #include <linux/pm_runtime.h> |
df8eb569 SB |
17 | |
18 | /* Register offsets for the I2C device. */ | |
19 | #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */ | |
20 | #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */ | |
21 | #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */ | |
22 | #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */ | |
23 | #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */ | |
24 | #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */ | |
25 | #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */ | |
1a351b10 | 26 | #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */ |
df8eb569 SB |
27 | #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */ |
28 | #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */ | |
29 | ||
30 | /* Control Register Bit mask definitions */ | |
31 | #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */ | |
32 | #define CDNS_I2C_CR_ACK_EN BIT(3) | |
33 | #define CDNS_I2C_CR_NEA BIT(2) | |
34 | #define CDNS_I2C_CR_MS BIT(1) | |
35 | /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */ | |
36 | #define CDNS_I2C_CR_RW BIT(0) | |
37 | /* 1 = Auto init FIFO to zeroes */ | |
38 | #define CDNS_I2C_CR_CLR_FIFO BIT(6) | |
39 | #define CDNS_I2C_CR_DIVA_SHIFT 14 | |
40 | #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT) | |
41 | #define CDNS_I2C_CR_DIVB_SHIFT 8 | |
42 | #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT) | |
43 | ||
1a351b10 RP |
44 | #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \ |
45 | CDNS_I2C_CR_ACK_EN | \ | |
46 | CDNS_I2C_CR_MS) | |
47 | ||
48 | #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK | |
49 | ||
df8eb569 SB |
50 | /* Status Register Bit mask definitions */ |
51 | #define CDNS_I2C_SR_BA BIT(8) | |
1a351b10 | 52 | #define CDNS_I2C_SR_TXDV BIT(6) |
df8eb569 | 53 | #define CDNS_I2C_SR_RXDV BIT(5) |
1a351b10 | 54 | #define CDNS_I2C_SR_RXRW BIT(3) |
df8eb569 SB |
55 | |
56 | /* | |
57 | * I2C Address Register Bit mask definitions | |
58 | * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0] | |
59 | * bits. A write access to this register always initiates a transfer if the I2C | |
60 | * is in master mode. | |
61 | */ | |
62 | #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */ | |
63 | ||
64 | /* | |
65 | * I2C Interrupt Registers Bit mask definitions | |
66 | * All the four interrupt registers (Status/Mask/Enable/Disable) have the same | |
67 | * bit definitions. | |
68 | */ | |
69 | #define CDNS_I2C_IXR_ARB_LOST BIT(9) | |
70 | #define CDNS_I2C_IXR_RX_UNF BIT(7) | |
71 | #define CDNS_I2C_IXR_TX_OVF BIT(6) | |
72 | #define CDNS_I2C_IXR_RX_OVF BIT(5) | |
73 | #define CDNS_I2C_IXR_SLV_RDY BIT(4) | |
74 | #define CDNS_I2C_IXR_TO BIT(3) | |
75 | #define CDNS_I2C_IXR_NACK BIT(2) | |
76 | #define CDNS_I2C_IXR_DATA BIT(1) | |
77 | #define CDNS_I2C_IXR_COMP BIT(0) | |
78 | ||
79 | #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ | |
80 | CDNS_I2C_IXR_RX_UNF | \ | |
81 | CDNS_I2C_IXR_TX_OVF | \ | |
82 | CDNS_I2C_IXR_RX_OVF | \ | |
83 | CDNS_I2C_IXR_SLV_RDY | \ | |
84 | CDNS_I2C_IXR_TO | \ | |
85 | CDNS_I2C_IXR_NACK | \ | |
86 | CDNS_I2C_IXR_DATA | \ | |
87 | CDNS_I2C_IXR_COMP) | |
88 | ||
89 | #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ | |
90 | CDNS_I2C_IXR_RX_UNF | \ | |
91 | CDNS_I2C_IXR_TX_OVF | \ | |
92 | CDNS_I2C_IXR_RX_OVF | \ | |
93 | CDNS_I2C_IXR_NACK) | |
94 | ||
95 | #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ | |
96 | CDNS_I2C_IXR_RX_UNF | \ | |
97 | CDNS_I2C_IXR_TX_OVF | \ | |
98 | CDNS_I2C_IXR_RX_OVF | \ | |
99 | CDNS_I2C_IXR_NACK | \ | |
100 | CDNS_I2C_IXR_DATA | \ | |
101 | CDNS_I2C_IXR_COMP) | |
102 | ||
1a351b10 RP |
103 | #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \ |
104 | CDNS_I2C_IXR_TX_OVF | \ | |
105 | CDNS_I2C_IXR_RX_OVF | \ | |
106 | CDNS_I2C_IXR_TO | \ | |
107 | CDNS_I2C_IXR_NACK | \ | |
108 | CDNS_I2C_IXR_DATA | \ | |
109 | CDNS_I2C_IXR_COMP) | |
110 | ||
df8eb569 | 111 | #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000) |
7fa32329 SD |
112 | /* timeout for pm runtime autosuspend */ |
113 | #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */ | |
df8eb569 SB |
114 | |
115 | #define CDNS_I2C_FIFO_DEPTH 16 | |
116 | /* FIFO depth at which the DATA interrupt occurs */ | |
117 | #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2) | |
118 | #define CDNS_I2C_MAX_TRANSFER_SIZE 255 | |
119 | /* Transfer size in multiples of data interrupt depth */ | |
120 | #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3) | |
121 | ||
122 | #define DRIVER_NAME "cdns-i2c" | |
123 | ||
df8eb569 SB |
124 | #define CDNS_I2C_DIVA_MAX 4 |
125 | #define CDNS_I2C_DIVB_MAX 64 | |
126 | ||
681d15a0 VM |
127 | #define CDNS_I2C_TIMEOUT_MAX 0xFF |
128 | ||
63cab195 AKV |
129 | #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) |
130 | ||
df8eb569 SB |
131 | #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) |
132 | #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) | |
133 | ||
1a351b10 RP |
134 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
135 | /** | |
136 | * enum cdns_i2c_mode - I2C Controller current operating mode | |
137 | * | |
138 | * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode | |
139 | * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode | |
140 | */ | |
141 | enum cdns_i2c_mode { | |
142 | CDNS_I2C_MODE_SLAVE, | |
143 | CDNS_I2C_MODE_MASTER, | |
144 | }; | |
145 | ||
146 | /** | |
6eb8a473 | 147 | * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode |
1a351b10 RP |
148 | * |
149 | * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle | |
150 | * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master | |
151 | * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master | |
152 | */ | |
153 | enum cdns_i2c_slave_state { | |
154 | CDNS_I2C_SLAVE_STATE_IDLE, | |
155 | CDNS_I2C_SLAVE_STATE_SEND, | |
156 | CDNS_I2C_SLAVE_STATE_RECV, | |
157 | }; | |
158 | #endif | |
159 | ||
df8eb569 SB |
160 | /** |
161 | * struct cdns_i2c - I2C device private data structure | |
30e31a1f SD |
162 | * |
163 | * @dev: Pointer to device structure | |
df8eb569 SB |
164 | * @membase: Base address of the I2C device |
165 | * @adap: I2C adapter instance | |
166 | * @p_msg: Message pointer | |
167 | * @err_status: Error status in Interrupt Status Register | |
168 | * @xfer_done: Transfer complete status | |
169 | * @p_send_buf: Pointer to transmit buffer | |
170 | * @p_recv_buf: Pointer to receive buffer | |
df8eb569 SB |
171 | * @send_count: Number of bytes still expected to send |
172 | * @recv_count: Number of bytes still expected to receive | |
9fae82e1 | 173 | * @curr_recv_count: Number of bytes to be received in current transfer |
df8eb569 SB |
174 | * @irq: IRQ number |
175 | * @input_clk: Input clock to I2C controller | |
176 | * @i2c_clk: Maximum I2C clock speed | |
177 | * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit | |
178 | * @clk: Pointer to struct clk | |
179 | * @clk_rate_change_nb: Notifier block for clock rate changes | |
63cab195 | 180 | * @quirks: flag for broken hold bit usage in r1p10 |
8b51a8e6 | 181 | * @ctrl_reg: Cached value of the control register. |
1a351b10 RP |
182 | * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register |
183 | * @slave: Registered slave instance. | |
184 | * @dev_mode: I2C operating role(master/slave). | |
185 | * @slave_state: I2C Slave state(idle/read/write). | |
df8eb569 SB |
186 | */ |
187 | struct cdns_i2c { | |
7fa32329 | 188 | struct device *dev; |
df8eb569 SB |
189 | void __iomem *membase; |
190 | struct i2c_adapter adap; | |
191 | struct i2c_msg *p_msg; | |
192 | int err_status; | |
193 | struct completion xfer_done; | |
194 | unsigned char *p_send_buf; | |
195 | unsigned char *p_recv_buf; | |
df8eb569 SB |
196 | unsigned int send_count; |
197 | unsigned int recv_count; | |
9fae82e1 | 198 | unsigned int curr_recv_count; |
df8eb569 SB |
199 | int irq; |
200 | unsigned long input_clk; | |
201 | unsigned int i2c_clk; | |
202 | unsigned int bus_hold_flag; | |
203 | struct clk *clk; | |
204 | struct notifier_block clk_rate_change_nb; | |
63cab195 | 205 | u32 quirks; |
8b51a8e6 | 206 | u32 ctrl_reg; |
1a351b10 RP |
207 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
208 | u16 ctrl_reg_diva_divb; | |
209 | struct i2c_client *slave; | |
210 | enum cdns_i2c_mode dev_mode; | |
211 | enum cdns_i2c_slave_state slave_state; | |
212 | #endif | |
63cab195 AKV |
213 | }; |
214 | ||
215 | struct cdns_platform_data { | |
216 | u32 quirks; | |
df8eb569 SB |
217 | }; |
218 | ||
219 | #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \ | |
220 | clk_rate_change_nb) | |
221 | ||
222 | /** | |
30e31a1f | 223 | * cdns_i2c_clear_bus_hold - Clear bus hold bit |
df8eb569 SB |
224 | * @id: Pointer to driver data struct |
225 | * | |
226 | * Helper to clear the controller's bus hold bit. | |
227 | */ | |
228 | static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) | |
229 | { | |
230 | u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
231 | if (reg & CDNS_I2C_CR_HOLD) | |
232 | cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET); | |
233 | } | |
234 | ||
63cab195 AKV |
235 | static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) |
236 | { | |
237 | return (hold_wrkaround && | |
238 | (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)); | |
239 | } | |
240 | ||
1a351b10 RP |
241 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
242 | static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) | |
243 | { | |
244 | /* Disable all interrupts */ | |
245 | cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); | |
246 | ||
247 | /* Clear FIFO and transfer size */ | |
248 | cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); | |
249 | ||
250 | /* Update device mode and state */ | |
251 | id->dev_mode = mode; | |
252 | id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; | |
253 | ||
254 | switch (mode) { | |
255 | case CDNS_I2C_MODE_MASTER: | |
256 | /* Enable i2c master */ | |
257 | cdns_i2c_writereg(id->ctrl_reg_diva_divb | | |
258 | CDNS_I2C_CR_MASTER_EN_MASK, | |
259 | CDNS_I2C_CR_OFFSET); | |
260 | /* | |
261 | * This delay is needed to give the IP some time to switch to | |
262 | * the master mode. With lower values(like 110 us) i2cdetect | |
263 | * will not detect any slave and without this delay, the IP will | |
264 | * trigger a timeout interrupt. | |
265 | */ | |
266 | usleep_range(115, 125); | |
267 | break; | |
268 | case CDNS_I2C_MODE_SLAVE: | |
269 | /* Enable i2c slave */ | |
270 | cdns_i2c_writereg(id->ctrl_reg_diva_divb & | |
271 | CDNS_I2C_CR_SLAVE_EN_MASK, | |
272 | CDNS_I2C_CR_OFFSET); | |
273 | ||
274 | /* Setting slave address */ | |
275 | cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK, | |
276 | CDNS_I2C_ADDR_OFFSET); | |
277 | ||
278 | /* Enable slave send/receive interrupts */ | |
279 | cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK, | |
280 | CDNS_I2C_IER_OFFSET); | |
281 | break; | |
282 | } | |
283 | } | |
284 | ||
285 | static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) | |
286 | { | |
287 | u8 bytes; | |
288 | unsigned char data; | |
289 | ||
290 | /* Prepare backend for data reception */ | |
291 | if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { | |
292 | id->slave_state = CDNS_I2C_SLAVE_STATE_RECV; | |
293 | i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL); | |
294 | } | |
295 | ||
296 | /* Fetch number of bytes to receive */ | |
297 | bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); | |
298 | ||
299 | /* Read data and send to backend */ | |
300 | while (bytes--) { | |
301 | data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); | |
302 | i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data); | |
303 | } | |
304 | } | |
305 | ||
306 | static void cdns_i2c_slave_send_data(struct cdns_i2c *id) | |
307 | { | |
308 | u8 data; | |
309 | ||
310 | /* Prepare backend for data transmission */ | |
311 | if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { | |
312 | id->slave_state = CDNS_I2C_SLAVE_STATE_SEND; | |
313 | i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data); | |
314 | } else { | |
315 | i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data); | |
316 | } | |
317 | ||
318 | /* Send data over bus */ | |
319 | cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET); | |
320 | } | |
321 | ||
df8eb569 | 322 | /** |
1a351b10 RP |
323 | * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role |
324 | * @ptr: Pointer to I2C device private data | |
325 | * | |
326 | * This function handles the data interrupt and transfer complete interrupt of | |
327 | * the I2C device in slave role. | |
328 | * | |
329 | * Return: IRQ_HANDLED always | |
330 | */ | |
331 | static irqreturn_t cdns_i2c_slave_isr(void *ptr) | |
332 | { | |
333 | struct cdns_i2c *id = ptr; | |
334 | unsigned int isr_status, i2c_status; | |
335 | ||
336 | /* Fetch the interrupt status */ | |
337 | isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); | |
338 | cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); | |
339 | ||
340 | /* Ignore masked interrupts */ | |
341 | isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET); | |
342 | ||
343 | /* Fetch transfer mode (send/receive) */ | |
344 | i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); | |
345 | ||
346 | /* Handle data send/receive */ | |
347 | if (i2c_status & CDNS_I2C_SR_RXRW) { | |
348 | /* Send data to master */ | |
349 | if (isr_status & CDNS_I2C_IXR_DATA) | |
350 | cdns_i2c_slave_send_data(id); | |
351 | ||
352 | if (isr_status & CDNS_I2C_IXR_COMP) { | |
353 | id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; | |
354 | i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); | |
355 | } | |
356 | } else { | |
357 | /* Receive data from master */ | |
358 | if (isr_status & CDNS_I2C_IXR_DATA) | |
359 | cdns_i2c_slave_rcv_data(id); | |
360 | ||
361 | if (isr_status & CDNS_I2C_IXR_COMP) { | |
362 | cdns_i2c_slave_rcv_data(id); | |
363 | id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; | |
364 | i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); | |
365 | } | |
366 | } | |
367 | ||
368 | /* Master indicated xfer stop or fifo underflow/overflow */ | |
369 | if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF | | |
370 | CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) { | |
371 | id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; | |
372 | i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); | |
373 | cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); | |
374 | } | |
375 | ||
376 | return IRQ_HANDLED; | |
377 | } | |
378 | #endif | |
379 | ||
380 | /** | |
381 | * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role | |
382 | * @ptr: Pointer to I2C device private data | |
df8eb569 SB |
383 | * |
384 | * This function handles the data interrupt, transfer complete interrupt and | |
1a351b10 | 385 | * the error interrupts of the I2C device in master role. |
df8eb569 SB |
386 | * |
387 | * Return: IRQ_HANDLED always | |
388 | */ | |
1a351b10 | 389 | static irqreturn_t cdns_i2c_master_isr(void *ptr) |
df8eb569 | 390 | { |
4ca8ca87 | 391 | unsigned int isr_status, avail_bytes; |
9fae82e1 | 392 | unsigned int bytes_to_send; |
4ca8ca87 | 393 | bool updatetx; |
df8eb569 SB |
394 | struct cdns_i2c *id = ptr; |
395 | /* Signal completion only after everything is updated */ | |
396 | int done_flag = 0; | |
397 | irqreturn_t status = IRQ_NONE; | |
398 | ||
399 | isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); | |
9fae82e1 | 400 | cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); |
bbf967b2 | 401 | id->err_status = 0; |
df8eb569 SB |
402 | |
403 | /* Handling nack and arbitration lost interrupt */ | |
404 | if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { | |
405 | done_flag = 1; | |
406 | status = IRQ_HANDLED; | |
407 | } | |
408 | ||
9fae82e1 HK |
409 | /* |
410 | * Check if transfer size register needs to be updated again for a | |
411 | * large data receive operation. | |
412 | */ | |
4ca8ca87 | 413 | updatetx = id->recv_count > id->curr_recv_count; |
63cab195 | 414 | |
9fae82e1 HK |
415 | /* When receiving, handle data interrupt and completion interrupt */ |
416 | if (id->p_recv_buf && | |
417 | ((isr_status & CDNS_I2C_IXR_COMP) || | |
418 | (isr_status & CDNS_I2C_IXR_DATA))) { | |
419 | /* Read data if receive data valid is set */ | |
420 | while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & | |
421 | CDNS_I2C_SR_RXDV) { | |
bbf967b2 AW |
422 | if (id->recv_count > 0) { |
423 | *(id->p_recv_buf)++ = | |
424 | cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); | |
425 | id->recv_count--; | |
426 | id->curr_recv_count--; | |
12d4d9ec RN |
427 | |
428 | /* | |
429 | * Clear hold bit that was set for FIFO control | |
430 | * if RX data left is less than or equal to | |
431 | * FIFO DEPTH unless repeated start is selected | |
432 | */ | |
433 | if (id->recv_count <= CDNS_I2C_FIFO_DEPTH && | |
434 | !id->bus_hold_flag) | |
435 | cdns_i2c_clear_bus_hold(id); | |
436 | ||
bbf967b2 AW |
437 | } else { |
438 | dev_err(id->adap.dev.parent, | |
439 | "xfer_size reg rollover. xfer aborted!\n"); | |
440 | id->err_status |= CDNS_I2C_IXR_TO; | |
441 | break; | |
442 | } | |
df8eb569 | 443 | |
4ca8ca87 | 444 | if (cdns_is_holdquirk(id, updatetx)) |
9fae82e1 HK |
445 | break; |
446 | } | |
df8eb569 | 447 | |
9fae82e1 HK |
448 | /* |
449 | * The controller sends NACK to the slave when transfer size | |
450 | * register reaches zero without considering the HOLD bit. | |
451 | * This workaround is implemented for large data transfers to | |
452 | * maintain transfer size non-zero while performing a large | |
453 | * receive operation. | |
454 | */ | |
4ca8ca87 | 455 | if (cdns_is_holdquirk(id, updatetx)) { |
9fae82e1 HK |
456 | /* wait while fifo is full */ |
457 | while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != | |
458 | (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH)) | |
459 | ; | |
df8eb569 | 460 | |
df8eb569 | 461 | /* |
9fae82e1 HK |
462 | * Check number of bytes to be received against maximum |
463 | * transfer size and update register accordingly. | |
df8eb569 | 464 | */ |
9fae82e1 HK |
465 | if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) > |
466 | CDNS_I2C_TRANSFER_SIZE) { | |
467 | cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, | |
468 | CDNS_I2C_XFER_SIZE_OFFSET); | |
469 | id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE + | |
470 | CDNS_I2C_FIFO_DEPTH; | |
df8eb569 | 471 | } else { |
9fae82e1 HK |
472 | cdns_i2c_writereg(id->recv_count - |
473 | CDNS_I2C_FIFO_DEPTH, | |
474 | CDNS_I2C_XFER_SIZE_OFFSET); | |
475 | id->curr_recv_count = id->recv_count; | |
df8eb569 | 476 | } |
9fae82e1 HK |
477 | } |
478 | ||
479 | /* Clear hold (if not repeated start) and signal completion */ | |
480 | if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) { | |
df8eb569 SB |
481 | if (!id->bus_hold_flag) |
482 | cdns_i2c_clear_bus_hold(id); | |
9fae82e1 HK |
483 | done_flag = 1; |
484 | } | |
485 | ||
486 | status = IRQ_HANDLED; | |
487 | } | |
488 | ||
489 | /* When sending, handle transfer complete interrupt */ | |
490 | if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) { | |
491 | /* | |
492 | * If there is more data to be sent, calculate the | |
493 | * space available in FIFO and fill with that many bytes. | |
494 | */ | |
495 | if (id->send_count) { | |
496 | avail_bytes = CDNS_I2C_FIFO_DEPTH - | |
497 | cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); | |
498 | if (id->send_count > avail_bytes) | |
499 | bytes_to_send = avail_bytes; | |
500 | else | |
501 | bytes_to_send = id->send_count; | |
502 | ||
503 | while (bytes_to_send--) { | |
504 | cdns_i2c_writereg( | |
505 | (*(id->p_send_buf)++), | |
506 | CDNS_I2C_DATA_OFFSET); | |
507 | id->send_count--; | |
508 | } | |
509 | } else { | |
df8eb569 | 510 | /* |
9fae82e1 HK |
511 | * Signal the completion of transaction and |
512 | * clear the hold bus bit if there are no | |
513 | * further messages to be processed. | |
df8eb569 | 514 | */ |
df8eb569 SB |
515 | done_flag = 1; |
516 | } | |
9fae82e1 HK |
517 | if (!id->send_count && !id->bus_hold_flag) |
518 | cdns_i2c_clear_bus_hold(id); | |
df8eb569 SB |
519 | |
520 | status = IRQ_HANDLED; | |
521 | } | |
522 | ||
523 | /* Update the status for errors */ | |
bbf967b2 | 524 | id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; |
df8eb569 SB |
525 | if (id->err_status) |
526 | status = IRQ_HANDLED; | |
527 | ||
df8eb569 SB |
528 | if (done_flag) |
529 | complete(&id->xfer_done); | |
530 | ||
531 | return status; | |
532 | } | |
533 | ||
1a351b10 RP |
534 | /** |
535 | * cdns_i2c_isr - Interrupt handler for the I2C device | |
536 | * @irq: irq number for the I2C device | |
537 | * @ptr: void pointer to cdns_i2c structure | |
538 | * | |
539 | * This function passes the control to slave/master based on current role of | |
540 | * i2c controller. | |
541 | * | |
542 | * Return: IRQ_HANDLED always | |
543 | */ | |
544 | static irqreturn_t cdns_i2c_isr(int irq, void *ptr) | |
545 | { | |
546 | #if IS_ENABLED(CONFIG_I2C_SLAVE) | |
547 | struct cdns_i2c *id = ptr; | |
548 | ||
549 | if (id->dev_mode == CDNS_I2C_MODE_SLAVE) | |
550 | return cdns_i2c_slave_isr(ptr); | |
551 | #endif | |
552 | return cdns_i2c_master_isr(ptr); | |
553 | } | |
554 | ||
df8eb569 SB |
555 | /** |
556 | * cdns_i2c_mrecv - Prepare and start a master receive operation | |
557 | * @id: pointer to the i2c device structure | |
558 | */ | |
559 | static void cdns_i2c_mrecv(struct cdns_i2c *id) | |
560 | { | |
561 | unsigned int ctrl_reg; | |
562 | unsigned int isr_status; | |
dd66b39f RN |
563 | unsigned long flags; |
564 | bool hold_clear = false; | |
565 | bool irq_save = false; | |
566 | ||
567 | u32 addr; | |
df8eb569 SB |
568 | |
569 | id->p_recv_buf = id->p_msg->buf; | |
570 | id->recv_count = id->p_msg->len; | |
571 | ||
572 | /* Put the controller in master receive mode and clear the FIFO */ | |
573 | ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
574 | ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; | |
575 | ||
576 | if (id->p_msg->flags & I2C_M_RECV_LEN) | |
577 | id->recv_count = I2C_SMBUS_BLOCK_MAX + 1; | |
578 | ||
9fae82e1 HK |
579 | id->curr_recv_count = id->recv_count; |
580 | ||
df8eb569 SB |
581 | /* |
582 | * Check for the message size against FIFO depth and set the | |
583 | * 'hold bus' bit if it is greater than FIFO depth. | |
584 | */ | |
0db9254d | 585 | if (id->recv_count > CDNS_I2C_FIFO_DEPTH) |
df8eb569 SB |
586 | ctrl_reg |= CDNS_I2C_CR_HOLD; |
587 | ||
588 | cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); | |
589 | ||
590 | /* Clear the interrupts in interrupt status register */ | |
591 | isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); | |
592 | cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); | |
593 | ||
594 | /* | |
595 | * The no. of bytes to receive is checked against the limit of | |
596 | * max transfer size. Set transfer size register with no of bytes | |
597 | * receive if it is less than transfer size and transfer size if | |
598 | * it is more. Enable the interrupts. | |
599 | */ | |
9fae82e1 | 600 | if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { |
df8eb569 SB |
601 | cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, |
602 | CDNS_I2C_XFER_SIZE_OFFSET); | |
9fae82e1 HK |
603 | id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; |
604 | } else { | |
df8eb569 | 605 | cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); |
9fae82e1 HK |
606 | } |
607 | ||
dd66b39f | 608 | /* Determine hold_clear based on number of bytes to receive and hold flag */ |
df8eb569 | 609 | if (!id->bus_hold_flag && |
dd66b39f RN |
610 | ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && |
611 | (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) { | |
612 | if (cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & CDNS_I2C_CR_HOLD) { | |
613 | hold_clear = true; | |
614 | if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) | |
615 | irq_save = true; | |
616 | } | |
617 | } | |
618 | ||
619 | addr = id->p_msg->addr; | |
620 | addr &= CDNS_I2C_ADDR_MASK; | |
621 | ||
622 | if (hold_clear) { | |
623 | ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & ~CDNS_I2C_CR_HOLD; | |
624 | /* | |
625 | * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size | |
626 | * register reaches '0'. This is an IP bug which causes transfer size | |
627 | * register overflow to 0xFF. To satisfy this timing requirement, | |
628 | * disable the interrupts on current processor core between register | |
629 | * writes to slave address register and control register. | |
630 | */ | |
631 | if (irq_save) | |
632 | local_irq_save(flags); | |
633 | ||
634 | cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); | |
635 | cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); | |
636 | /* Read it back to avoid bufferring and make sure write happens */ | |
637 | cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
638 | ||
639 | if (irq_save) | |
640 | local_irq_restore(flags); | |
641 | } else { | |
642 | cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); | |
643 | } | |
644 | ||
df8eb569 SB |
645 | cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); |
646 | } | |
647 | ||
648 | /** | |
649 | * cdns_i2c_msend - Prepare and start a master send operation | |
650 | * @id: pointer to the i2c device | |
651 | */ | |
652 | static void cdns_i2c_msend(struct cdns_i2c *id) | |
653 | { | |
654 | unsigned int avail_bytes; | |
655 | unsigned int bytes_to_send; | |
656 | unsigned int ctrl_reg; | |
657 | unsigned int isr_status; | |
658 | ||
659 | id->p_recv_buf = NULL; | |
660 | id->p_send_buf = id->p_msg->buf; | |
661 | id->send_count = id->p_msg->len; | |
662 | ||
663 | /* Set the controller in Master transmit mode and clear the FIFO. */ | |
664 | ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
665 | ctrl_reg &= ~CDNS_I2C_CR_RW; | |
666 | ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; | |
667 | ||
668 | /* | |
669 | * Check for the message size against FIFO depth and set the | |
670 | * 'hold bus' bit if it is greater than FIFO depth. | |
671 | */ | |
0db9254d | 672 | if (id->send_count > CDNS_I2C_FIFO_DEPTH) |
df8eb569 SB |
673 | ctrl_reg |= CDNS_I2C_CR_HOLD; |
674 | cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); | |
675 | ||
676 | /* Clear the interrupts in interrupt status register. */ | |
677 | isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); | |
678 | cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); | |
679 | ||
680 | /* | |
681 | * Calculate the space available in FIFO. Check the message length | |
682 | * against the space available, and fill the FIFO accordingly. | |
683 | * Enable the interrupts. | |
684 | */ | |
685 | avail_bytes = CDNS_I2C_FIFO_DEPTH - | |
686 | cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); | |
687 | ||
688 | if (id->send_count > avail_bytes) | |
689 | bytes_to_send = avail_bytes; | |
690 | else | |
691 | bytes_to_send = id->send_count; | |
692 | ||
693 | while (bytes_to_send--) { | |
694 | cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET); | |
695 | id->send_count--; | |
696 | } | |
697 | ||
698 | /* | |
699 | * Clear the bus hold flag if there is no more data | |
700 | * and if it is the last message. | |
701 | */ | |
702 | if (!id->bus_hold_flag && !id->send_count) | |
703 | cdns_i2c_clear_bus_hold(id); | |
704 | /* Set the slave address in address register - triggers operation. */ | |
705 | cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, | |
706 | CDNS_I2C_ADDR_OFFSET); | |
707 | ||
708 | cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); | |
709 | } | |
710 | ||
711 | /** | |
712 | * cdns_i2c_master_reset - Reset the interface | |
713 | * @adap: pointer to the i2c adapter driver instance | |
714 | * | |
715 | * This function cleanup the fifos, clear the hold bit and status | |
716 | * and disable the interrupts. | |
717 | */ | |
718 | static void cdns_i2c_master_reset(struct i2c_adapter *adap) | |
719 | { | |
720 | struct cdns_i2c *id = adap->algo_data; | |
721 | u32 regval; | |
722 | ||
723 | /* Disable the interrupts */ | |
724 | cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); | |
725 | /* Clear the hold bit and fifos */ | |
726 | regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
727 | regval &= ~CDNS_I2C_CR_HOLD; | |
728 | regval |= CDNS_I2C_CR_CLR_FIFO; | |
729 | cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); | |
730 | /* Update the transfercount register to zero */ | |
731 | cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET); | |
9253975b | 732 | /* Clear the interrupt status register */ |
df8eb569 SB |
733 | regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); |
734 | cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); | |
735 | /* Clear the status register */ | |
736 | regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); | |
737 | cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); | |
738 | } | |
739 | ||
740 | static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, | |
741 | struct i2c_adapter *adap) | |
742 | { | |
96789dce | 743 | unsigned long time_left, msg_timeout; |
df8eb569 SB |
744 | u32 reg; |
745 | ||
746 | id->p_msg = msg; | |
747 | id->err_status = 0; | |
748 | reinit_completion(&id->xfer_done); | |
749 | ||
750 | /* Check for the TEN Bit mode on each msg */ | |
751 | reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
752 | if (msg->flags & I2C_M_TEN) { | |
753 | if (reg & CDNS_I2C_CR_NEA) | |
754 | cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA, | |
755 | CDNS_I2C_CR_OFFSET); | |
756 | } else { | |
757 | if (!(reg & CDNS_I2C_CR_NEA)) | |
758 | cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA, | |
759 | CDNS_I2C_CR_OFFSET); | |
760 | } | |
761 | ||
762 | /* Check for the R/W flag on each msg */ | |
763 | if (msg->flags & I2C_M_RD) | |
764 | cdns_i2c_mrecv(id); | |
765 | else | |
766 | cdns_i2c_msend(id); | |
767 | ||
96789dce LT |
768 | /* Minimal time to execute this message */ |
769 | msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk); | |
770 | /* Plus some wiggle room */ | |
771 | msg_timeout += msecs_to_jiffies(500); | |
772 | ||
773 | if (msg_timeout < adap->timeout) | |
774 | msg_timeout = adap->timeout; | |
775 | ||
df8eb569 | 776 | /* Wait for the signal of completion */ |
96789dce | 777 | time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout); |
e2efb897 | 778 | if (time_left == 0) { |
df8eb569 SB |
779 | cdns_i2c_master_reset(adap); |
780 | dev_err(id->adap.dev.parent, | |
781 | "timeout waiting on completion\n"); | |
782 | return -ETIMEDOUT; | |
783 | } | |
784 | ||
785 | cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, | |
786 | CDNS_I2C_IDR_OFFSET); | |
787 | ||
788 | /* If it is bus arbitration error, try again */ | |
789 | if (id->err_status & CDNS_I2C_IXR_ARB_LOST) | |
790 | return -EAGAIN; | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
795 | /** | |
796 | * cdns_i2c_master_xfer - The main i2c transfer function | |
797 | * @adap: pointer to the i2c adapter driver instance | |
798 | * @msgs: pointer to the i2c message structure | |
799 | * @num: the number of messages to transfer | |
800 | * | |
801 | * Initiates the send/recv activity based on the transfer message received. | |
802 | * | |
803 | * Return: number of msgs processed on success, negative error otherwise | |
804 | */ | |
805 | static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, | |
806 | int num) | |
807 | { | |
808 | int ret, count; | |
809 | u32 reg; | |
810 | struct cdns_i2c *id = adap->algo_data; | |
63cab195 | 811 | bool hold_quirk; |
1a351b10 RP |
812 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
813 | bool change_role = false; | |
814 | #endif | |
df8eb569 | 815 | |
23ceb846 | 816 | ret = pm_runtime_resume_and_get(id->dev); |
7fa32329 SD |
817 | if (ret < 0) |
818 | return ret; | |
1a351b10 RP |
819 | |
820 | #if IS_ENABLED(CONFIG_I2C_SLAVE) | |
821 | /* Check i2c operating mode and switch if possible */ | |
822 | if (id->dev_mode == CDNS_I2C_MODE_SLAVE) { | |
823 | if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE) | |
824 | return -EAGAIN; | |
825 | ||
826 | /* Set mode to master */ | |
827 | cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); | |
828 | ||
829 | /* Mark flag to change role once xfer is completed */ | |
830 | change_role = true; | |
831 | } | |
832 | #endif | |
833 | ||
df8eb569 | 834 | /* Check if the bus is free */ |
7fa32329 SD |
835 | if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) { |
836 | ret = -EAGAIN; | |
837 | goto out; | |
838 | } | |
df8eb569 | 839 | |
63cab195 | 840 | hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); |
df8eb569 SB |
841 | /* |
842 | * Set the flag to one when multiple messages are to be | |
843 | * processed with a repeated start. | |
844 | */ | |
845 | if (num > 1) { | |
8a86c3ae HK |
846 | /* |
847 | * This controller does not give completion interrupt after a | |
848 | * master receive message if HOLD bit is set (repeated start), | |
849 | * resulting in SW timeout. Hence, if a receive message is | |
850 | * followed by any other message, an error is returned | |
851 | * indicating that this sequence is not supported. | |
852 | */ | |
63cab195 | 853 | for (count = 0; (count < num - 1 && hold_quirk); count++) { |
8a86c3ae HK |
854 | if (msgs[count].flags & I2C_M_RD) { |
855 | dev_warn(adap->dev.parent, | |
856 | "Can't do repeated start after a receive message\n"); | |
7fa32329 SD |
857 | ret = -EOPNOTSUPP; |
858 | goto out; | |
8a86c3ae HK |
859 | } |
860 | } | |
df8eb569 SB |
861 | id->bus_hold_flag = 1; |
862 | reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); | |
863 | reg |= CDNS_I2C_CR_HOLD; | |
864 | cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET); | |
865 | } else { | |
866 | id->bus_hold_flag = 0; | |
867 | } | |
868 | ||
869 | /* Process the msg one by one */ | |
870 | for (count = 0; count < num; count++, msgs++) { | |
871 | if (count == (num - 1)) | |
872 | id->bus_hold_flag = 0; | |
873 | ||
874 | ret = cdns_i2c_process_msg(id, msgs, adap); | |
875 | if (ret) | |
7fa32329 | 876 | goto out; |
df8eb569 SB |
877 | |
878 | /* Report the other error interrupts to application */ | |
879 | if (id->err_status) { | |
880 | cdns_i2c_master_reset(adap); | |
881 | ||
7fa32329 SD |
882 | if (id->err_status & CDNS_I2C_IXR_NACK) { |
883 | ret = -ENXIO; | |
884 | goto out; | |
885 | } | |
886 | ret = -EIO; | |
887 | goto out; | |
df8eb569 SB |
888 | } |
889 | } | |
890 | ||
7fa32329 | 891 | ret = num; |
1a351b10 | 892 | |
7fa32329 | 893 | out: |
1a351b10 RP |
894 | |
895 | #if IS_ENABLED(CONFIG_I2C_SLAVE) | |
896 | /* Switch i2c mode to slave */ | |
897 | if (change_role) | |
898 | cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); | |
899 | #endif | |
900 | ||
7fa32329 SD |
901 | pm_runtime_mark_last_busy(id->dev); |
902 | pm_runtime_put_autosuspend(id->dev); | |
903 | return ret; | |
df8eb569 SB |
904 | } |
905 | ||
906 | /** | |
907 | * cdns_i2c_func - Returns the supported features of the I2C driver | |
908 | * @adap: pointer to the i2c adapter structure | |
909 | * | |
910 | * Return: 32 bit value, each bit corresponding to a feature | |
911 | */ | |
912 | static u32 cdns_i2c_func(struct i2c_adapter *adap) | |
913 | { | |
1a351b10 RP |
914 | u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | |
915 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | | |
916 | I2C_FUNC_SMBUS_BLOCK_DATA; | |
917 | ||
918 | #if IS_ENABLED(CONFIG_I2C_SLAVE) | |
919 | func |= I2C_FUNC_SLAVE; | |
920 | #endif | |
921 | ||
922 | return func; | |
df8eb569 SB |
923 | } |
924 | ||
1a351b10 RP |
925 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
926 | static int cdns_reg_slave(struct i2c_client *slave) | |
927 | { | |
928 | int ret; | |
929 | struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, | |
930 | adap); | |
931 | ||
932 | if (id->slave) | |
933 | return -EBUSY; | |
934 | ||
935 | if (slave->flags & I2C_CLIENT_TEN) | |
936 | return -EAFNOSUPPORT; | |
937 | ||
23ceb846 | 938 | ret = pm_runtime_resume_and_get(id->dev); |
1a351b10 RP |
939 | if (ret < 0) |
940 | return ret; | |
941 | ||
942 | /* Store slave information */ | |
943 | id->slave = slave; | |
944 | ||
945 | /* Enable I2C slave */ | |
946 | cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
951 | static int cdns_unreg_slave(struct i2c_client *slave) | |
952 | { | |
953 | struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, | |
954 | adap); | |
955 | ||
956 | pm_runtime_put(id->dev); | |
957 | ||
958 | /* Remove slave information */ | |
959 | id->slave = NULL; | |
960 | ||
961 | /* Enable I2C master */ | |
962 | cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); | |
963 | ||
964 | return 0; | |
965 | } | |
966 | #endif | |
967 | ||
df8eb569 SB |
968 | static const struct i2c_algorithm cdns_i2c_algo = { |
969 | .master_xfer = cdns_i2c_master_xfer, | |
970 | .functionality = cdns_i2c_func, | |
1a351b10 RP |
971 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
972 | .reg_slave = cdns_reg_slave, | |
973 | .unreg_slave = cdns_unreg_slave, | |
974 | #endif | |
df8eb569 SB |
975 | }; |
976 | ||
977 | /** | |
978 | * cdns_i2c_calc_divs - Calculate clock dividers | |
979 | * @f: I2C clock frequency | |
980 | * @input_clk: Input clock frequency | |
981 | * @a: First divider (return value) | |
982 | * @b: Second divider (return value) | |
983 | * | |
984 | * f is used as input and output variable. As input it is used as target I2C | |
985 | * frequency. On function exit f holds the actually resulting I2C frequency. | |
986 | * | |
987 | * Return: 0 on success, negative errno otherwise. | |
988 | */ | |
989 | static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, | |
990 | unsigned int *a, unsigned int *b) | |
991 | { | |
992 | unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; | |
993 | unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; | |
994 | unsigned int last_error, current_error; | |
995 | ||
996 | /* calculate (divisor_a+1) x (divisor_b+1) */ | |
997 | temp = input_clk / (22 * fscl); | |
998 | ||
999 | /* | |
1000 | * If the calculated value is negative or 0, the fscl input is out of | |
1001 | * range. Return error. | |
1002 | */ | |
1003 | if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) | |
1004 | return -EINVAL; | |
1005 | ||
1006 | last_error = -1; | |
1007 | for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { | |
1008 | div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); | |
1009 | ||
1010 | if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) | |
1011 | continue; | |
1012 | div_b--; | |
1013 | ||
1014 | actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); | |
1015 | ||
1016 | if (actual_fscl > fscl) | |
1017 | continue; | |
1018 | ||
1019 | current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : | |
1020 | (fscl - actual_fscl)); | |
1021 | ||
1022 | if (last_error > current_error) { | |
1023 | calc_div_a = div_a; | |
1024 | calc_div_b = div_b; | |
1025 | best_fscl = actual_fscl; | |
1026 | last_error = current_error; | |
1027 | } | |
1028 | } | |
1029 | ||
1030 | *a = calc_div_a; | |
1031 | *b = calc_div_b; | |
1032 | *f = best_fscl; | |
1033 | ||
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | /** | |
1038 | * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device | |
1039 | * @clk_in: I2C clock input frequency in Hz | |
1040 | * @id: Pointer to the I2C device structure | |
1041 | * | |
1042 | * The device must be idle rather than busy transferring data before setting | |
1043 | * these device options. | |
1044 | * The data rate is set by values in the control register. | |
1045 | * The formula for determining the correct register values is | |
1046 | * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) | |
1047 | * See the hardware data sheet for a full explanation of setting the serial | |
1048 | * clock rate. The clock can not be faster than the input clock divide by 22. | |
1049 | * The two most common clock rates are 100KHz and 400KHz. | |
1050 | * | |
1051 | * Return: 0 on success, negative error otherwise | |
1052 | */ | |
1053 | static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id) | |
1054 | { | |
1055 | unsigned int div_a, div_b; | |
1056 | unsigned int ctrl_reg; | |
1057 | int ret = 0; | |
1058 | unsigned long fscl = id->i2c_clk; | |
1059 | ||
1060 | ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b); | |
1061 | if (ret) | |
1062 | return ret; | |
1063 | ||
8b51a8e6 | 1064 | ctrl_reg = id->ctrl_reg; |
df8eb569 SB |
1065 | ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK); |
1066 | ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) | | |
1067 | (div_b << CDNS_I2C_CR_DIVB_SHIFT)); | |
8b51a8e6 | 1068 | id->ctrl_reg = ctrl_reg; |
df8eb569 | 1069 | cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); |
1a351b10 RP |
1070 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
1071 | id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK | | |
1072 | CDNS_I2C_CR_DIVB_MASK); | |
1073 | #endif | |
df8eb569 SB |
1074 | return 0; |
1075 | } | |
1076 | ||
1077 | /** | |
1078 | * cdns_i2c_clk_notifier_cb - Clock rate change callback | |
1079 | * @nb: Pointer to notifier block | |
1080 | * @event: Notification reason | |
1081 | * @data: Pointer to notification data object | |
1082 | * | |
1083 | * This function is called when the cdns_i2c input clock frequency changes. | |
1084 | * The callback checks whether a valid bus frequency can be generated after the | |
1085 | * change. If so, the change is acknowledged, otherwise the change is aborted. | |
1086 | * New dividers are written to the HW in the pre- or post change notification | |
1087 | * depending on the scaling direction. | |
1088 | * | |
1089 | * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK | |
e0603c8d | 1090 | * to acknowledge the change, NOTIFY_DONE if the notification is |
df8eb569 SB |
1091 | * considered irrelevant. |
1092 | */ | |
1093 | static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long | |
1094 | event, void *data) | |
1095 | { | |
1096 | struct clk_notifier_data *ndata = data; | |
1097 | struct cdns_i2c *id = to_cdns_i2c(nb); | |
1098 | ||
948c58a0 | 1099 | if (pm_runtime_suspended(id->dev)) |
df8eb569 SB |
1100 | return NOTIFY_OK; |
1101 | ||
1102 | switch (event) { | |
1103 | case PRE_RATE_CHANGE: | |
1104 | { | |
1105 | unsigned long input_clk = ndata->new_rate; | |
1106 | unsigned long fscl = id->i2c_clk; | |
1107 | unsigned int div_a, div_b; | |
1108 | int ret; | |
1109 | ||
1110 | ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); | |
1111 | if (ret) { | |
1112 | dev_warn(id->adap.dev.parent, | |
1113 | "clock rate change rejected\n"); | |
1114 | return NOTIFY_STOP; | |
1115 | } | |
1116 | ||
1117 | /* scale up */ | |
1118 | if (ndata->new_rate > ndata->old_rate) | |
1119 | cdns_i2c_setclk(ndata->new_rate, id); | |
1120 | ||
1121 | return NOTIFY_OK; | |
1122 | } | |
1123 | case POST_RATE_CHANGE: | |
1124 | id->input_clk = ndata->new_rate; | |
1125 | /* scale down */ | |
1126 | if (ndata->new_rate < ndata->old_rate) | |
1127 | cdns_i2c_setclk(ndata->new_rate, id); | |
1128 | return NOTIFY_OK; | |
1129 | case ABORT_RATE_CHANGE: | |
1130 | /* scale up */ | |
1131 | if (ndata->new_rate > ndata->old_rate) | |
1132 | cdns_i2c_setclk(ndata->old_rate, id); | |
1133 | return NOTIFY_OK; | |
1134 | default: | |
1135 | return NOTIFY_DONE; | |
1136 | } | |
1137 | } | |
1138 | ||
1139 | /** | |
30e31a1f SD |
1140 | * cdns_i2c_runtime_suspend - Runtime suspend method for the driver |
1141 | * @dev: Address of the platform_device structure | |
df8eb569 SB |
1142 | * |
1143 | * Put the driver into low power mode. | |
1144 | * | |
1145 | * Return: 0 always | |
1146 | */ | |
7fa32329 | 1147 | static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) |
df8eb569 | 1148 | { |
9242e72a | 1149 | struct cdns_i2c *xi2c = dev_get_drvdata(dev); |
df8eb569 SB |
1150 | |
1151 | clk_disable(xi2c->clk); | |
df8eb569 SB |
1152 | |
1153 | return 0; | |
1154 | } | |
1155 | ||
8b51a8e6 SD |
1156 | /** |
1157 | * cdns_i2c_init - Controller initialisation | |
1158 | * @id: Device private data structure | |
1159 | * | |
1160 | * Initialise the i2c controller. | |
1161 | * | |
1162 | */ | |
1163 | static void cdns_i2c_init(struct cdns_i2c *id) | |
1164 | { | |
1165 | cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET); | |
1166 | /* | |
1167 | * Cadence I2C controller has a bug wherein it generates | |
1168 | * invalid read transaction after HW timeout in master receiver mode. | |
1169 | * HW timeout is not used by this driver and the interrupt is disabled. | |
1170 | * But the feature itself cannot be disabled. Hence maximum value | |
1171 | * is written to this register to reduce the chances of error. | |
1172 | */ | |
1173 | cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); | |
1174 | } | |
1175 | ||
df8eb569 | 1176 | /** |
30e31a1f SD |
1177 | * cdns_i2c_runtime_resume - Runtime resume |
1178 | * @dev: Address of the platform_device structure | |
df8eb569 | 1179 | * |
30e31a1f | 1180 | * Runtime resume callback. |
df8eb569 SB |
1181 | * |
1182 | * Return: 0 on success and error value on error | |
1183 | */ | |
7fa32329 | 1184 | static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) |
df8eb569 | 1185 | { |
9242e72a | 1186 | struct cdns_i2c *xi2c = dev_get_drvdata(dev); |
df8eb569 SB |
1187 | int ret; |
1188 | ||
1189 | ret = clk_enable(xi2c->clk); | |
1190 | if (ret) { | |
7fa32329 | 1191 | dev_err(dev, "Cannot enable clock.\n"); |
df8eb569 SB |
1192 | return ret; |
1193 | } | |
8b51a8e6 | 1194 | cdns_i2c_init(xi2c); |
df8eb569 | 1195 | |
df8eb569 SB |
1196 | return 0; |
1197 | } | |
1198 | ||
7fa32329 SD |
1199 | static const struct dev_pm_ops cdns_i2c_dev_pm_ops = { |
1200 | SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, | |
1201 | cdns_i2c_runtime_resume, NULL) | |
1202 | }; | |
df8eb569 | 1203 | |
63cab195 AKV |
1204 | static const struct cdns_platform_data r1p10_i2c_def = { |
1205 | .quirks = CDNS_I2C_BROKEN_HOLD_BIT, | |
1206 | }; | |
1207 | ||
1208 | static const struct of_device_id cdns_i2c_of_match[] = { | |
1209 | { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def }, | |
1210 | { .compatible = "cdns,i2c-r1p14",}, | |
1211 | { /* end of table */ } | |
1212 | }; | |
1213 | MODULE_DEVICE_TABLE(of, cdns_i2c_of_match); | |
1214 | ||
df8eb569 SB |
1215 | /** |
1216 | * cdns_i2c_probe - Platform registration call | |
1217 | * @pdev: Handle to the platform device structure | |
1218 | * | |
1219 | * This function does all the memory allocation and registration for the i2c | |
1220 | * device. User can modify the address mode to 10 bit address mode using the | |
1221 | * ioctl call with option I2C_TENBIT. | |
1222 | * | |
1223 | * Return: 0 on success, negative error otherwise | |
1224 | */ | |
1225 | static int cdns_i2c_probe(struct platform_device *pdev) | |
1226 | { | |
1227 | struct resource *r_mem; | |
1228 | struct cdns_i2c *id; | |
1229 | int ret; | |
63cab195 | 1230 | const struct of_device_id *match; |
df8eb569 SB |
1231 | |
1232 | id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL); | |
1233 | if (!id) | |
1234 | return -ENOMEM; | |
1235 | ||
7fa32329 | 1236 | id->dev = &pdev->dev; |
df8eb569 SB |
1237 | platform_set_drvdata(pdev, id); |
1238 | ||
63cab195 AKV |
1239 | match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node); |
1240 | if (match && match->data) { | |
1241 | const struct cdns_platform_data *data = match->data; | |
1242 | id->quirks = data->quirks; | |
1243 | } | |
1244 | ||
c02fb2b8 | 1245 | id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem); |
df8eb569 SB |
1246 | if (IS_ERR(id->membase)) |
1247 | return PTR_ERR(id->membase); | |
1248 | ||
5581c2c5 SS |
1249 | ret = platform_get_irq(pdev, 0); |
1250 | if (ret < 0) | |
1251 | return ret; | |
1252 | id->irq = ret; | |
df8eb569 | 1253 | |
a1f64317 | 1254 | id->adap.owner = THIS_MODULE; |
df8eb569 SB |
1255 | id->adap.dev.of_node = pdev->dev.of_node; |
1256 | id->adap.algo = &cdns_i2c_algo; | |
1257 | id->adap.timeout = CDNS_I2C_TIMEOUT; | |
1258 | id->adap.retries = 3; /* Default retry value. */ | |
1259 | id->adap.algo_data = id; | |
1260 | id->adap.dev.parent = &pdev->dev; | |
1261 | init_completion(&id->xfer_done); | |
1262 | snprintf(id->adap.name, sizeof(id->adap.name), | |
1263 | "Cadence I2C at %08lx", (unsigned long)r_mem->start); | |
1264 | ||
1265 | id->clk = devm_clk_get(&pdev->dev, NULL); | |
2d1a83a4 KK |
1266 | if (IS_ERR(id->clk)) |
1267 | return dev_err_probe(&pdev->dev, PTR_ERR(id->clk), | |
1268 | "input clock not found.\n"); | |
1269 | ||
df8eb569 | 1270 | ret = clk_prepare_enable(id->clk); |
7fa32329 | 1271 | if (ret) |
df8eb569 | 1272 | dev_err(&pdev->dev, "Unable to enable clock.\n"); |
7fa32329 | 1273 | |
7fa32329 SD |
1274 | pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT); |
1275 | pm_runtime_use_autosuspend(id->dev); | |
1276 | pm_runtime_set_active(id->dev); | |
db3fad84 | 1277 | pm_runtime_enable(id->dev); |
7fa32329 | 1278 | |
df8eb569 SB |
1279 | id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb; |
1280 | if (clk_notifier_register(id->clk, &id->clk_rate_change_nb)) | |
1281 | dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); | |
1282 | id->input_clk = clk_get_rate(id->clk); | |
1283 | ||
1284 | ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", | |
1285 | &id->i2c_clk); | |
90224e64 AS |
1286 | if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ)) |
1287 | id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ; | |
df8eb569 | 1288 | |
1a351b10 RP |
1289 | #if IS_ENABLED(CONFIG_I2C_SLAVE) |
1290 | /* Set initial mode to master */ | |
1291 | id->dev_mode = CDNS_I2C_MODE_MASTER; | |
1292 | id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; | |
1293 | #endif | |
8b51a8e6 | 1294 | id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS; |
df8eb569 SB |
1295 | |
1296 | ret = cdns_i2c_setclk(id->input_clk, id); | |
1297 | if (ret) { | |
1298 | dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk); | |
1299 | ret = -EINVAL; | |
1300 | goto err_clk_dis; | |
1301 | } | |
1302 | ||
1303 | ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0, | |
1304 | DRIVER_NAME, id); | |
1305 | if (ret) { | |
1306 | dev_err(&pdev->dev, "cannot get irq %d\n", id->irq); | |
1307 | goto err_clk_dis; | |
1308 | } | |
8b51a8e6 | 1309 | cdns_i2c_init(id); |
681d15a0 | 1310 | |
0e1929de ML |
1311 | ret = i2c_add_adapter(&id->adap); |
1312 | if (ret < 0) | |
1313 | goto err_clk_dis; | |
1314 | ||
df8eb569 SB |
1315 | dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", |
1316 | id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq); | |
1317 | ||
1318 | return 0; | |
1319 | ||
1320 | err_clk_dis: | |
3501f0c6 | 1321 | clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); |
df8eb569 | 1322 | clk_disable_unprepare(id->clk); |
7fa32329 | 1323 | pm_runtime_disable(&pdev->dev); |
db3fad84 | 1324 | pm_runtime_set_suspended(&pdev->dev); |
df8eb569 SB |
1325 | return ret; |
1326 | } | |
1327 | ||
1328 | /** | |
1329 | * cdns_i2c_remove - Unregister the device after releasing the resources | |
1330 | * @pdev: Handle to the platform device structure | |
1331 | * | |
1332 | * This function frees all the resources allocated to the device. | |
1333 | * | |
1334 | * Return: 0 always | |
1335 | */ | |
1336 | static int cdns_i2c_remove(struct platform_device *pdev) | |
1337 | { | |
1338 | struct cdns_i2c *id = platform_get_drvdata(pdev); | |
1339 | ||
db3fad84 TK |
1340 | pm_runtime_disable(&pdev->dev); |
1341 | pm_runtime_set_suspended(&pdev->dev); | |
1342 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
1343 | ||
df8eb569 SB |
1344 | i2c_del_adapter(&id->adap); |
1345 | clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); | |
1346 | clk_disable_unprepare(id->clk); | |
1347 | ||
1348 | return 0; | |
1349 | } | |
1350 | ||
df8eb569 SB |
1351 | static struct platform_driver cdns_i2c_drv = { |
1352 | .driver = { | |
1353 | .name = DRIVER_NAME, | |
df8eb569 SB |
1354 | .of_match_table = cdns_i2c_of_match, |
1355 | .pm = &cdns_i2c_dev_pm_ops, | |
1356 | }, | |
1357 | .probe = cdns_i2c_probe, | |
1358 | .remove = cdns_i2c_remove, | |
1359 | }; | |
1360 | ||
1361 | module_platform_driver(cdns_i2c_drv); | |
1362 | ||
1363 | MODULE_AUTHOR("Xilinx Inc."); | |
1364 | MODULE_DESCRIPTION("Cadence I2C bus driver"); | |
1365 | MODULE_LICENSE("GPL"); |