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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-block.git] / drivers / i2c / busses / i2c-bfin-twi.c
CommitLineData
d24ecfcc 1/*
bd584996 2 * Blackfin On-Chip Two Wire Interface Driver
d24ecfcc 3 *
bd584996 4 * Copyright 2005-2007 Analog Devices Inc.
d24ecfcc 5 *
bd584996 6 * Enter bugs at http://blackfin.uclinux.org/
d24ecfcc 7 *
bd584996 8 * Licensed under the GPL-2 or later.
d24ecfcc
BW		 9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
5a0e3ad6 15#include <linux/slab.h>
6df263cf 16#include <linux/io.h>
d24ecfcc
BW		 17#include <linux/mm.h>
18#include <linux/timer.h>
19#include <linux/spinlock.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23
24#include <asm/blackfin.h>
74d362e0 25#include <asm/portmux.h>
d24ecfcc
BW		 26#include <asm/irq.h>
27
28#define POLL_TIMEOUT (2 * HZ)
29
30/* SMBus mode*/
4dd39bb1
SZ		 31#define TWI_I2C_MODE_STANDARD 1
32#define TWI_I2C_MODE_STANDARDSUB 2
33#define TWI_I2C_MODE_COMBINED 3
34#define TWI_I2C_MODE_REPEAT 4
d24ecfcc
BW		 35
36struct bfin_twi_iface {
d24ecfcc
BW		 37 int irq;
38 spinlock_t lock;
39 char read_write;
40 u8 command;
41 u8 *transPtr;
42 int readNum;
43 int writeNum;
44 int cur_mode;
45 int manual_stop;
46 int result;
47 int timeout_count;
48 struct timer_list timeout_timer;
49 struct i2c_adapter adap;
50 struct completion complete;
4dd39bb1
SZ		 51 struct i2c_msg *pmsg;
52 int msg_num;
53 int cur_msg;
958585f5
MH		 54 u16 saved_clkdiv;
55 u16 saved_control;
aa3d0209 56 void __iomem *regs_base;
d24ecfcc
BW		 57};
58
aa3d0209
BW		 59
60#define DEFINE_TWI_REG(reg, off) \
61static inline u16 read_##reg(struct bfin_twi_iface *iface) \
62 { return bfin_read16(iface->regs_base + (off)); } \
63static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
64 { bfin_write16(iface->regs_base + (off), v); }
65
66DEFINE_TWI_REG(CLKDIV, 0x00)
67DEFINE_TWI_REG(CONTROL, 0x04)
68DEFINE_TWI_REG(SLAVE_CTL, 0x08)
69DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
70DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
71DEFINE_TWI_REG(MASTER_CTL, 0x14)
72DEFINE_TWI_REG(MASTER_STAT, 0x18)
73DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
74DEFINE_TWI_REG(INT_STAT, 0x20)
75DEFINE_TWI_REG(INT_MASK, 0x24)
76DEFINE_TWI_REG(FIFO_CTL, 0x28)
77DEFINE_TWI_REG(FIFO_STAT, 0x2C)
78DEFINE_TWI_REG(XMT_DATA8, 0x80)
79DEFINE_TWI_REG(XMT_DATA16, 0x84)
80DEFINE_TWI_REG(RCV_DATA8, 0x88)
81DEFINE_TWI_REG(RCV_DATA16, 0x8C)
d24ecfcc 82
74d362e0
BW		 83static const u16 pin_req[2][3] = {
84 {P_TWI0_SCL, P_TWI0_SDA, 0},
85 {P_TWI1_SCL, P_TWI1_SDA, 0},
86};
87
d24ecfcc
BW		 88static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
89{
aa3d0209
BW		 90 unsigned short twi_int_status = read_INT_STAT(iface);
91 unsigned short mast_stat = read_MASTER_STAT(iface);
d24ecfcc
BW		 92
93 if (twi_int_status & XMTSERV) {
94 /* Transmit next data */
95 if (iface->writeNum > 0) {
aa3d0209 96 write_XMT_DATA8(iface, *(iface->transPtr++));
d24ecfcc
BW		 97 iface->writeNum--;
98 }
99 /* start receive immediately after complete sending in
100 * combine mode.
101 */
4dd39bb1 102 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
aa3d0209
BW		 103 write_MASTER_CTL(iface,
104 read_MASTER_CTL(iface) | MDIR | RSTART);
4dd39bb1 105 else if (iface->manual_stop)
aa3d0209
BW		 106 write_MASTER_CTL(iface,
107 read_MASTER_CTL(iface) | STOP);
4dd39bb1 108 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
94327d00
FS		 109 iface->cur_msg + 1 < iface->msg_num) {
110 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
111 write_MASTER_CTL(iface,
112 read_MASTER_CTL(iface) | RSTART | MDIR);
113 else
114 write_MASTER_CTL(iface,
115 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
116 }
d24ecfcc
BW		 117 SSYNC();
118 /* Clear status */
aa3d0209 119 write_INT_STAT(iface, XMTSERV);
d24ecfcc
BW		 120 SSYNC();
121 }
122 if (twi_int_status & RCVSERV) {
123 if (iface->readNum > 0) {
124 /* Receive next data */
aa3d0209 125 *(iface->transPtr) = read_RCV_DATA8(iface);
d24ecfcc
BW		 126 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
127 /* Change combine mode into sub mode after
128 * read first data.
129 */
130 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
131 /* Get read number from first byte in block
132 * combine mode.
133 */
134 if (iface->readNum == 1 && iface->manual_stop)
135 iface->readNum = *iface->transPtr + 1;
136 }
137 iface->transPtr++;
138 iface->readNum--;
139 } else if (iface->manual_stop) {
aa3d0209
BW		 140 write_MASTER_CTL(iface,
141 read_MASTER_CTL(iface) | STOP);
d24ecfcc 142 SSYNC();
4dd39bb1 143 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
94327d00
FS		 144 iface->cur_msg + 1 < iface->msg_num) {
145 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
146 write_MASTER_CTL(iface,
147 read_MASTER_CTL(iface) | RSTART | MDIR);
148 else
149 write_MASTER_CTL(iface,
150 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
4dd39bb1 151 SSYNC();
d24ecfcc
BW		 152 }
153 /* Clear interrupt source */
aa3d0209 154 write_INT_STAT(iface, RCVSERV);
d24ecfcc
BW		 155 SSYNC();
156 }
157 if (twi_int_status & MERR) {
aa3d0209
BW		 158 write_INT_STAT(iface, MERR);
159 write_INT_MASK(iface, 0);
160 write_MASTER_STAT(iface, 0x3e);
161 write_MASTER_CTL(iface, 0);
d24ecfcc 162 SSYNC();
4dd39bb1 163 iface->result = -EIO;
d24ecfcc
BW		 164 /* if both err and complete int stats are set, return proper
165 * results.
166 */
167 if (twi_int_status & MCOMP) {
aa3d0209
BW		 168 write_INT_STAT(iface, MCOMP);
169 write_INT_MASK(iface, 0);
170 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 171 SSYNC();
172 /* If it is a quick transfer, only address bug no data,
173 * not an err, return 1.
174 */
175 if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
176 iface->result = 1;
177 /* If address not acknowledged return -1,
178 * else return 0.
179 */
180 else if (!(mast_stat & ANAK))
181 iface->result = 0;
182 }
183 complete(&iface->complete);
184 return;
185 }
186 if (twi_int_status & MCOMP) {
aa3d0209 187 write_INT_STAT(iface, MCOMP);
d24ecfcc
BW		 188 SSYNC();
189 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
190 if (iface->readNum == 0) {
191 /* set the read number to 1 and ask for manual
192 * stop in block combine mode
193 */
194 iface->readNum = 1;
195 iface->manual_stop = 1;
aa3d0209
BW		 196 write_MASTER_CTL(iface,
197 read_MASTER_CTL(iface) | (0xff << 6));
d24ecfcc
BW		 198 } else {
199 /* set the readd number in other
200 * combine mode.
201 */
aa3d0209
BW		 202 write_MASTER_CTL(iface,
203 (read_MASTER_CTL(iface) &
d24ecfcc 204 (~(0xff << 6))) |
aa3d0209 205 (iface->readNum << 6));
d24ecfcc
BW		 206 }
207 /* remove restart bit and enable master receive */
aa3d0209
BW		 208 write_MASTER_CTL(iface,
209 read_MASTER_CTL(iface) & ~RSTART);
d24ecfcc 210 SSYNC();
4dd39bb1
SZ		 211 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
212 iface->cur_msg+1 < iface->msg_num) {
213 iface->cur_msg++;
214 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
215 iface->writeNum = iface->readNum =
216 iface->pmsg[iface->cur_msg].len;
217 /* Set Transmit device address */
aa3d0209 218 write_MASTER_ADDR(iface,
4dd39bb1
SZ		 219 iface->pmsg[iface->cur_msg].addr);
220 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
221 iface->read_write = I2C_SMBUS_READ;
222 else {
223 iface->read_write = I2C_SMBUS_WRITE;
224 /* Transmit first data */
225 if (iface->writeNum > 0) {
aa3d0209 226 write_XMT_DATA8(iface,
4dd39bb1
SZ		 227 *(iface->transPtr++));
228 iface->writeNum--;
229 SSYNC();
230 }
231 }
232
233 if (iface->pmsg[iface->cur_msg].len <= 255)
57a8f32e
SZ		 234 write_MASTER_CTL(iface,
235 (read_MASTER_CTL(iface) &
236 (~(0xff << 6))) |
237 (iface->pmsg[iface->cur_msg].len << 6));
4dd39bb1 238 else {
57a8f32e
SZ		 239 write_MASTER_CTL(iface,
240 (read_MASTER_CTL(iface) |
241 (0xff << 6)));
4dd39bb1
SZ		 242 iface->manual_stop = 1;
243 }
244 /* remove restart bit and enable master receive */
aa3d0209
BW		 245 write_MASTER_CTL(iface,
246 read_MASTER_CTL(iface) & ~RSTART);
4dd39bb1 247 SSYNC();
d24ecfcc
BW		 248 } else {
249 iface->result = 1;
aa3d0209
BW		 250 write_INT_MASK(iface, 0);
251 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 252 SSYNC();
253 complete(&iface->complete);
254 }
255 }
256}
257
258/* Interrupt handler */
259static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
260{
261 struct bfin_twi_iface *iface = dev_id;
262 unsigned long flags;
263
264 spin_lock_irqsave(&iface->lock, flags);
265 del_timer(&iface->timeout_timer);
266 bfin_twi_handle_interrupt(iface);
267 spin_unlock_irqrestore(&iface->lock, flags);
268 return IRQ_HANDLED;
269}
270
271static void bfin_twi_timeout(unsigned long data)
272{
273 struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
274 unsigned long flags;
275
276 spin_lock_irqsave(&iface->lock, flags);
277 bfin_twi_handle_interrupt(iface);
278 if (iface->result == 0) {
279 iface->timeout_count--;
280 if (iface->timeout_count > 0) {
281 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
282 add_timer(&iface->timeout_timer);
283 } else {
284 iface->result = -1;
285 complete(&iface->complete);
286 }
287 }
288 spin_unlock_irqrestore(&iface->lock, flags);
289}
290
291/*
292 * Generic i2c master transfer entrypoint
293 */
294static int bfin_twi_master_xfer(struct i2c_adapter *adap,
295 struct i2c_msg *msgs, int num)
296{
297 struct bfin_twi_iface *iface = adap->algo_data;
298 struct i2c_msg *pmsg;
d24ecfcc
BW		 299 int rc = 0;
300
aa3d0209 301 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 302 return -ENXIO;
303
aa3d0209 304 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 305 yield();
d24ecfcc 306
4dd39bb1
SZ		 307 iface->pmsg = msgs;
308 iface->msg_num = num;
309 iface->cur_msg = 0;
d24ecfcc 310
4dd39bb1
SZ		 311 pmsg = &msgs[0];
312 if (pmsg->flags & I2C_M_TEN) {
313 dev_err(&adap->dev, "10 bits addr not supported!\n");
314 return -EINVAL;
315 }
d24ecfcc 316
4dd39bb1
SZ		 317 iface->cur_mode = TWI_I2C_MODE_REPEAT;
318 iface->manual_stop = 0;
319 iface->transPtr = pmsg->buf;
320 iface->writeNum = iface->readNum = pmsg->len;
321 iface->result = 0;
322 iface->timeout_count = 10;
afc13b76 323 init_completion(&(iface->complete));
4dd39bb1 324 /* Set Transmit device address */
aa3d0209 325 write_MASTER_ADDR(iface, pmsg->addr);
4dd39bb1
SZ		 326
327 /* FIFO Initiation. Data in FIFO should be
328 * discarded before start a new operation.
329 */
aa3d0209 330 write_FIFO_CTL(iface, 0x3);
4dd39bb1 331 SSYNC();
aa3d0209 332 write_FIFO_CTL(iface, 0);
4dd39bb1
SZ		 333 SSYNC();
334
335 if (pmsg->flags & I2C_M_RD)
336 iface->read_write = I2C_SMBUS_READ;
337 else {
338 iface->read_write = I2C_SMBUS_WRITE;
339 /* Transmit first data */
340 if (iface->writeNum > 0) {
aa3d0209 341 write_XMT_DATA8(iface, *(iface->transPtr++));
4dd39bb1
SZ		 342 iface->writeNum--;
343 SSYNC();
d24ecfcc 344 }
4dd39bb1 345 }
d24ecfcc 346
4dd39bb1 347 /* clear int stat */
aa3d0209 348 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc 349
4dd39bb1 350 /* Interrupt mask . Enable XMT, RCV interrupt */
aa3d0209 351 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
4dd39bb1 352 SSYNC();
d24ecfcc 353
4dd39bb1 354 if (pmsg->len <= 255)
aa3d0209 355 write_MASTER_CTL(iface, pmsg->len << 6);
4dd39bb1 356 else {
aa3d0209 357 write_MASTER_CTL(iface, 0xff << 6);
4dd39bb1
SZ		 358 iface->manual_stop = 1;
359 }
d24ecfcc 360
4dd39bb1
SZ		 361 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
362 add_timer(&iface->timeout_timer);
d24ecfcc 363
4dd39bb1 364 /* Master enable */
aa3d0209 365 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
4dd39bb1
SZ		 366 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
367 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
368 SSYNC();
369
370 wait_for_completion(&iface->complete);
371
372 rc = iface->result;
d24ecfcc 373
4dd39bb1
SZ		 374 if (rc == 1)
375 return num;
376 else
377 return rc;
d24ecfcc
BW		 378}
379
380/*
381 * SMBus type transfer entrypoint
382 */
383
384int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
385 unsigned short flags, char read_write,
386 u8 command, int size, union i2c_smbus_data *data)
387{
388 struct bfin_twi_iface *iface = adap->algo_data;
389 int rc = 0;
390
aa3d0209 391 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 392 return -ENXIO;
393
aa3d0209 394 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 395 yield();
d24ecfcc
BW		 396
397 iface->writeNum = 0;
398 iface->readNum = 0;
399
400 /* Prepare datas & select mode */
401 switch (size) {
402 case I2C_SMBUS_QUICK:
403 iface->transPtr = NULL;
404 iface->cur_mode = TWI_I2C_MODE_STANDARD;
405 break;
406 case I2C_SMBUS_BYTE:
407 if (data == NULL)
408 iface->transPtr = NULL;
409 else {
410 if (read_write == I2C_SMBUS_READ)
411 iface->readNum = 1;
412 else
413 iface->writeNum = 1;
414 iface->transPtr = &data->byte;
415 }
416 iface->cur_mode = TWI_I2C_MODE_STANDARD;
417 break;
418 case I2C_SMBUS_BYTE_DATA:
419 if (read_write == I2C_SMBUS_READ) {
420 iface->readNum = 1;
421 iface->cur_mode = TWI_I2C_MODE_COMBINED;
422 } else {
423 iface->writeNum = 1;
424 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
425 }
426 iface->transPtr = &data->byte;
427 break;
428 case I2C_SMBUS_WORD_DATA:
429 if (read_write == I2C_SMBUS_READ) {
430 iface->readNum = 2;
431 iface->cur_mode = TWI_I2C_MODE_COMBINED;
432 } else {
433 iface->writeNum = 2;
434 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
435 }
436 iface->transPtr = (u8 *)&data->word;
437 break;
438 case I2C_SMBUS_PROC_CALL:
439 iface->writeNum = 2;
440 iface->readNum = 2;
441 iface->cur_mode = TWI_I2C_MODE_COMBINED;
442 iface->transPtr = (u8 *)&data->word;
443 break;
444 case I2C_SMBUS_BLOCK_DATA:
445 if (read_write == I2C_SMBUS_READ) {
446 iface->readNum = 0;
447 iface->cur_mode = TWI_I2C_MODE_COMBINED;
448 } else {
449 iface->writeNum = data->block[0] + 1;
450 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
451 }
452 iface->transPtr = data->block;
453 break;
e0cd2dd5
MH		 454 case I2C_SMBUS_I2C_BLOCK_DATA:
455 if (read_write == I2C_SMBUS_READ) {
456 iface->readNum = data->block[0];
457 iface->cur_mode = TWI_I2C_MODE_COMBINED;
458 } else {
459 iface->writeNum = data->block[0];
460 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
461 }
462 iface->transPtr = (u8 *)&data->block[1];
463 break;
d24ecfcc
BW		 464 default:
465 return -1;
466 }
467
468 iface->result = 0;
469 iface->manual_stop = 0;
470 iface->read_write = read_write;
471 iface->command = command;
472 iface->timeout_count = 10;
afc13b76 473 init_completion(&(iface->complete));
d24ecfcc
BW		 474
475 /* FIFO Initiation. Data in FIFO should be discarded before
476 * start a new operation.
477 */
aa3d0209 478 write_FIFO_CTL(iface, 0x3);
d24ecfcc 479 SSYNC();
aa3d0209 480 write_FIFO_CTL(iface, 0);
d24ecfcc
BW		 481
482 /* clear int stat */
aa3d0209 483 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc
BW		 484
485 /* Set Transmit device address */
aa3d0209 486 write_MASTER_ADDR(iface, addr);
d24ecfcc
BW		 487 SSYNC();
488
489 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
490 add_timer(&iface->timeout_timer);
491
492 switch (iface->cur_mode) {
493 case TWI_I2C_MODE_STANDARDSUB:
aa3d0209
BW		 494 write_XMT_DATA8(iface, iface->command);
495 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 496 ((iface->read_write == I2C_SMBUS_READ) ?
497 RCVSERV : XMTSERV));
498 SSYNC();
499
500 if (iface->writeNum + 1 <= 255)
aa3d0209 501 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 502 else {
aa3d0209 503 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 504 iface->manual_stop = 1;
505 }
506 /* Master enable */
aa3d0209 507 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 508 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
509 break;
510 case TWI_I2C_MODE_COMBINED:
aa3d0209
BW		 511 write_XMT_DATA8(iface, iface->command);
512 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
d24ecfcc
BW		 513 SSYNC();
514
515 if (iface->writeNum > 0)
aa3d0209 516 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 517 else
aa3d0209 518 write_MASTER_CTL(iface, 0x1 << 6);
d24ecfcc 519 /* Master enable */
aa3d0209 520 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 521 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
522 break;
523 default:
aa3d0209 524 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 525 if (size != I2C_SMBUS_QUICK) {
526 /* Don't access xmit data register when this is a
527 * read operation.
528 */
529 if (iface->read_write != I2C_SMBUS_READ) {
530 if (iface->writeNum > 0) {
aa3d0209
BW		 531 write_XMT_DATA8(iface,
532 *(iface->transPtr++));
d24ecfcc 533 if (iface->writeNum <= 255)
aa3d0209
BW		 534 write_MASTER_CTL(iface,
535 iface->writeNum << 6);
d24ecfcc 536 else {
aa3d0209
BW		 537 write_MASTER_CTL(iface,
538 0xff << 6);
d24ecfcc
BW		 539 iface->manual_stop = 1;
540 }
541 iface->writeNum--;
542 } else {
aa3d0209
BW		 543 write_XMT_DATA8(iface, iface->command);
544 write_MASTER_CTL(iface, 1 << 6);
d24ecfcc
BW		 545 }
546 } else {
547 if (iface->readNum > 0 && iface->readNum <= 255)
aa3d0209
BW		 548 write_MASTER_CTL(iface,
549 iface->readNum << 6);
d24ecfcc 550 else if (iface->readNum > 255) {
aa3d0209 551 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 552 iface->manual_stop = 1;
553 } else {
554 del_timer(&iface->timeout_timer);
555 break;
556 }
557 }
558 }
aa3d0209 559 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 560 ((iface->read_write == I2C_SMBUS_READ) ?
561 RCVSERV : XMTSERV));
562 SSYNC();
563
564 /* Master enable */
aa3d0209 565 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 566 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
567 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
568 break;
569 }
570 SSYNC();
571
572 wait_for_completion(&iface->complete);
573
574 rc = (iface->result >= 0) ? 0 : -1;
575
d24ecfcc
BW		 576 return rc;
577}
578
579/*
580 * Return what the adapter supports
581 */
582static u32 bfin_twi_functionality(struct i2c_adapter *adap)
583{
584 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
585 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
586 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
e0cd2dd5 587 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
d24ecfcc
BW		 588}
589
d24ecfcc
BW		 590static struct i2c_algorithm bfin_twi_algorithm = {
591 .master_xfer = bfin_twi_master_xfer,
592 .smbus_xfer = bfin_twi_smbus_xfer,
593 .functionality = bfin_twi_functionality,
594};
595
958585f5 596static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
d24ecfcc 597{
958585f5
MH		 598 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
599
600 iface->saved_clkdiv = read_CLKDIV(iface);
601 iface->saved_control = read_CONTROL(iface);
602
603 free_irq(iface->irq, iface);
d24ecfcc
BW		 604
605 /* Disable TWI */
958585f5 606 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
d24ecfcc
BW		 607
608 return 0;
609}
610
958585f5 611static int i2c_bfin_twi_resume(struct platform_device *pdev)
d24ecfcc 612{
958585f5 613 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
d24ecfcc 614
958585f5
MH		 615 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
616 IRQF_DISABLED, pdev->name, iface);
617 if (rc) {
618 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
619 return -ENODEV;
620 }
621
622 /* Resume TWI interface clock as specified */
623 write_CLKDIV(iface, iface->saved_clkdiv);
624
625 /* Resume TWI */
626 write_CONTROL(iface, iface->saved_control);
d24ecfcc
BW		 627
628 return 0;
629}
630
aa3d0209 631static int i2c_bfin_twi_probe(struct platform_device *pdev)
d24ecfcc 632{
aa3d0209 633 struct bfin_twi_iface *iface;
d24ecfcc 634 struct i2c_adapter *p_adap;
aa3d0209 635 struct resource *res;
d24ecfcc 636 int rc;
9528d1c7 637 unsigned int clkhilow;
d24ecfcc 638
aa3d0209
BW		 639 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
640 if (!iface) {
641 dev_err(&pdev->dev, "Cannot allocate memory\n");
642 rc = -ENOMEM;
643 goto out_error_nomem;
644 }
645
d24ecfcc 646 spin_lock_init(&(iface->lock));
aa3d0209
BW		 647
648 /* Find and map our resources */
649 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
650 if (res == NULL) {
651 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
652 rc = -ENOENT;
653 goto out_error_get_res;
654 }
655
c6ffddea 656 iface->regs_base = ioremap(res->start, resource_size(res));
aa3d0209
BW		 657 if (iface->regs_base == NULL) {
658 dev_err(&pdev->dev, "Cannot map IO\n");
659 rc = -ENXIO;
660 goto out_error_ioremap;
661 }
662
663 iface->irq = platform_get_irq(pdev, 0);
664 if (iface->irq < 0) {
665 dev_err(&pdev->dev, "No IRQ specified\n");
666 rc = -ENOENT;
667 goto out_error_no_irq;
668 }
d24ecfcc
BW		 669
670 init_timer(&(iface->timeout_timer));
671 iface->timeout_timer.function = bfin_twi_timeout;
672 iface->timeout_timer.data = (unsigned long)iface;
673
674 p_adap = &iface->adap;
aa3d0209
BW		 675 p_adap->nr = pdev->id;
676 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
d24ecfcc
BW		 677 p_adap->algo = &bfin_twi_algorithm;
678 p_adap->algo_data = iface;
e1995f65 679 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
aa3d0209 680 p_adap->dev.parent = &pdev->dev;
d24ecfcc 681
74d362e0
BW		 682 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
683 if (rc) {
684 dev_err(&pdev->dev, "Can't setup pin mux!\n");
685 goto out_error_pin_mux;
686 }
687
d24ecfcc 688 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
aa3d0209 689 IRQF_DISABLED, pdev->name, iface);
d24ecfcc 690 if (rc) {
aa3d0209
BW		 691 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
692 rc = -ENODEV;
693 goto out_error_req_irq;
d24ecfcc
BW		 694 }
695
696 /* Set TWI internal clock as 10MHz */
ac07fb4d 697 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
d24ecfcc 698
9528d1c7
MH		 699 /*
700 * We will not end up with a CLKDIV=0 because no one will specify
ac07fb4d 701 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
9528d1c7 702 */
ac07fb4d 703 clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
9528d1c7 704
d24ecfcc 705 /* Set Twi interface clock as specified */
9528d1c7 706 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
d24ecfcc
BW		 707
708 /* Enable TWI */
aa3d0209 709 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
d24ecfcc
BW		 710 SSYNC();
711
991dee59 712 rc = i2c_add_numbered_adapter(p_adap);
aa3d0209
BW		 713 if (rc < 0) {
714 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
715 goto out_error_add_adapter;
716 }
717
718 platform_set_drvdata(pdev, iface);
d24ecfcc 719
fa6ad222
BW		 720 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
721 "regs_base@%p\n", iface->regs_base);
aa3d0209
BW		 722
723 return 0;
724
725out_error_add_adapter:
726 free_irq(iface->irq, iface);
727out_error_req_irq:
728out_error_no_irq:
74d362e0
BW		 729 peripheral_free_list(pin_req[pdev->id]);
730out_error_pin_mux:
aa3d0209
BW		 731 iounmap(iface->regs_base);
732out_error_ioremap:
733out_error_get_res:
734 kfree(iface);
735out_error_nomem:
d24ecfcc
BW		 736 return rc;
737}
738
739static int i2c_bfin_twi_remove(struct platform_device *pdev)
740{
741 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
742
743 platform_set_drvdata(pdev, NULL);
744
745 i2c_del_adapter(&(iface->adap));
746 free_irq(iface->irq, iface);
74d362e0 747 peripheral_free_list(pin_req[pdev->id]);
aa3d0209
BW		 748 iounmap(iface->regs_base);
749 kfree(iface);
d24ecfcc
BW		 750
751 return 0;
752}
753
754static struct platform_driver i2c_bfin_twi_driver = {
755 .probe = i2c_bfin_twi_probe,
756 .remove = i2c_bfin_twi_remove,
757 .suspend = i2c_bfin_twi_suspend,
758 .resume = i2c_bfin_twi_resume,
759 .driver = {
760 .name = "i2c-bfin-twi",
761 .owner = THIS_MODULE,
762 },
763};
764
765static int __init i2c_bfin_twi_init(void)
766{
d24ecfcc
BW		 767 return platform_driver_register(&i2c_bfin_twi_driver);
768}
769
770static void __exit i2c_bfin_twi_exit(void)
771{
772 platform_driver_unregister(&i2c_bfin_twi_driver);
773}
774
d24ecfcc
BW		 775module_init(i2c_bfin_twi_init);
776module_exit(i2c_bfin_twi_exit);
fa6ad222
BW		 777
778MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
779MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
780MODULE_LICENSE("GPL");
add8eda7 781MODULE_ALIAS("platform:i2c-bfin-twi");
Linux 6.x block layer and io_uring tree(s)