[linux-block.git] / drivers / i2c / busses / i2c-bcm2835.c

/*
 * BCM2835 master mode driver
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#define BCM2835_I2C_C		0x0
#define BCM2835_I2C_S		0x4
#define BCM2835_I2C_DLEN	0x8
#define BCM2835_I2C_A		0xc
#define BCM2835_I2C_FIFO	0x10
#define BCM2835_I2C_DIV		0x14
#define BCM2835_I2C_DEL		0x18
#define BCM2835_I2C_CLKT	0x1c

#define BCM2835_I2C_C_READ	BIT(0)
#define BCM2835_I2C_C_CLEAR	BIT(4) /* bits 4 and 5 both clear */
#define BCM2835_I2C_C_ST	BIT(7)
#define BCM2835_I2C_C_INTD	BIT(8)
#define BCM2835_I2C_C_INTT	BIT(9)
#define BCM2835_I2C_C_INTR	BIT(10)
#define BCM2835_I2C_C_I2CEN	BIT(15)

#define BCM2835_I2C_S_TA	BIT(0)
#define BCM2835_I2C_S_DONE	BIT(1)
#define BCM2835_I2C_S_TXW	BIT(2)
#define BCM2835_I2C_S_RXR	BIT(3)
#define BCM2835_I2C_S_TXD	BIT(4)
#define BCM2835_I2C_S_RXD	BIT(5)
#define BCM2835_I2C_S_TXE	BIT(6)
#define BCM2835_I2C_S_RXF	BIT(7)
#define BCM2835_I2C_S_ERR	BIT(8)
#define BCM2835_I2C_S_CLKT	BIT(9)
#define BCM2835_I2C_S_LEN	BIT(10) /* Fake bit for SW error reporting */

#define BCM2835_I2C_FEDL_SHIFT	16
#define BCM2835_I2C_REDL_SHIFT	0

#define BCM2835_I2C_CDIV_MIN	0x0002
#define BCM2835_I2C_CDIV_MAX	0xFFFE

struct bcm2835_i2c_dev {
	struct device *dev;
	void __iomem *regs;
	struct clk *clk;
	int irq;
	u32 bus_clk_rate;
	struct i2c_adapter adapter;
	struct completion completion;
	struct i2c_msg *curr_msg;
	int num_msgs;
	u32 msg_err;
	u8 *msg_buf;
	size_t msg_buf_remaining;
};

static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
				      u32 reg, u32 val)
{
	writel(val, i2c_dev->regs + reg);
}

static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
{
	return readl(i2c_dev->regs + reg);
}

static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
{
	u32 divider, redl, fedl;

	divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
			       i2c_dev->bus_clk_rate);
	/*
	 * Per the datasheet, the register is always interpreted as an even
	 * number, by rounding down. In other words, the LSB is ignored. So,
	 * if the LSB is set, increment the divider to avoid any issue.
	 */
	if (divider & 1)
		divider++;
	if ((divider < BCM2835_I2C_CDIV_MIN) ||
	    (divider > BCM2835_I2C_CDIV_MAX)) {
		dev_err_ratelimited(i2c_dev->dev, "Invalid clock-frequency\n");
		return -EINVAL;
	}

	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);

	/*
	 * Number of core clocks to wait after falling edge before
	 * outputting the next data bit.  Note that both FEDL and REDL
	 * can't be greater than CDIV/2.
	 */
	fedl = max(divider / 16, 1u);

	/*
	 * Number of core clocks to wait after rising edge before
	 * sampling the next incoming data bit.
	 */
	redl = max(divider / 4, 1u);

	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL,
			   (fedl << BCM2835_I2C_FEDL_SHIFT) |
			   (redl << BCM2835_I2C_REDL_SHIFT));
	return 0;
}

static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
{
	u32 val;

	while (i2c_dev->msg_buf_remaining) {
		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
		if (!(val & BCM2835_I2C_S_TXD))
			break;
		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
				   *i2c_dev->msg_buf);
		i2c_dev->msg_buf++;
		i2c_dev->msg_buf_remaining--;
	}
}

static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
{
	u32 val;

	while (i2c_dev->msg_buf_remaining) {
		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
		if (!(val & BCM2835_I2C_S_RXD))
			break;
		*i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
						      BCM2835_I2C_FIFO);
		i2c_dev->msg_buf++;
		i2c_dev->msg_buf_remaining--;
	}
}

/*
 * Repeated Start Condition (Sr)
 * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
 * talks about reading from a slave with 10 bit address. This is achieved by
 * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
 * issue a read.
 * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
 * firmware actually does it using polling and says that it's a workaround for
 * a problem in the state machine.
 * It turns out that it is possible to use the TXW interrupt to know when the
 * transfer is active, provided the FIFO has not been prefilled.
 */

static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
{
	u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN;
	struct i2c_msg *msg = i2c_dev->curr_msg;
	bool last_msg = (i2c_dev->num_msgs == 1);

	if (!i2c_dev->num_msgs)
		return;

	i2c_dev->num_msgs--;
	i2c_dev->msg_buf = msg->buf;
	i2c_dev->msg_buf_remaining = msg->len;

	if (msg->flags & I2C_M_RD)
		c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR;
	else
		c |= BCM2835_I2C_C_INTT;

	if (last_msg)
		c |= BCM2835_I2C_C_INTD;

	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
}

/*
 * Note about I2C_C_CLEAR on error:
 * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
 * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
 * the state machine to send a NACK and a STOP. Since we're setting CLEAR
 * without I2CEN, that NACK will be hanging around queued up for next time
 * we start the engine.
 */

static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
{
	struct bcm2835_i2c_dev *i2c_dev = data;
	u32 val, err;

	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);

	err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
	if (err) {
		i2c_dev->msg_err = err;
		goto complete;
	}

	if (val & BCM2835_I2C_S_DONE) {
		if (!i2c_dev->curr_msg) {
			dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
		} else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
			bcm2835_drain_rxfifo(i2c_dev);
			val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
		}

		if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining)
			i2c_dev->msg_err = BCM2835_I2C_S_LEN;
		else
			i2c_dev->msg_err = 0;
		goto complete;
	}

	if (val & BCM2835_I2C_S_TXW) {
		if (!i2c_dev->msg_buf_remaining) {
			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
			goto complete;
		}

		bcm2835_fill_txfifo(i2c_dev);

		if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
			i2c_dev->curr_msg++;
			bcm2835_i2c_start_transfer(i2c_dev);
		}

		return IRQ_HANDLED;
	}

	if (val & BCM2835_I2C_S_RXR) {
		if (!i2c_dev->msg_buf_remaining) {
			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
			goto complete;
		}

		bcm2835_drain_rxfifo(i2c_dev);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;

complete:
	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
			   BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
	complete(&i2c_dev->completion);

	return IRQ_HANDLED;
}

static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
			    int num)
{
	struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
	unsigned long time_left;
	int i, ret;

	for (i = 0; i < (num - 1); i++)
		if (msgs[i].flags & I2C_M_RD) {
			dev_warn_once(i2c_dev->dev,
				      "only one read message supported, has to be last\n");
			return -EOPNOTSUPP;
		}

	ret = bcm2835_i2c_set_divider(i2c_dev);
	if (ret)
		return ret;

	i2c_dev->curr_msg = msgs;
	i2c_dev->num_msgs = num;
	reinit_completion(&i2c_dev->completion);

	bcm2835_i2c_start_transfer(i2c_dev);

	time_left = wait_for_completion_timeout(&i2c_dev->completion,
						adap->timeout);
	if (!time_left) {
		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
				   BCM2835_I2C_C_CLEAR);
		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
		return -ETIMEDOUT;
	}

	if (!i2c_dev->msg_err)
		return num;

	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);

	if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
		return -EREMOTEIO;

	return -EIO;
}

static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm bcm2835_i2c_algo = {
	.master_xfer	= bcm2835_i2c_xfer,
	.functionality	= bcm2835_i2c_func,
};

/*
 * This HW was reported to have problems with clock stretching:
 * http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
 * https://www.raspberrypi.org/forums/viewtopic.php?p=146272
 */
static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
	.flags = I2C_AQ_NO_CLK_STRETCH,
};

static int bcm2835_i2c_probe(struct platform_device *pdev)
{
	struct bcm2835_i2c_dev *i2c_dev;
	struct resource *mem, *irq;
	int ret;
	struct i2c_adapter *adap;

	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
	if (!i2c_dev)
		return -ENOMEM;
	platform_set_drvdata(pdev, i2c_dev);
	i2c_dev->dev = &pdev->dev;
	init_completion(&i2c_dev->completion);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(i2c_dev->regs))
		return PTR_ERR(i2c_dev->regs);

	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(i2c_dev->clk)) {
		if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER)
			dev_err(&pdev->dev, "Could not get clock\n");
		return PTR_ERR(i2c_dev->clk);
	}

	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
				   &i2c_dev->bus_clk_rate);
	if (ret < 0) {
		dev_warn(&pdev->dev,
			 "Could not read clock-frequency property\n");
		i2c_dev->bus_clk_rate = 100000;
	}

	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!irq) {
		dev_err(&pdev->dev, "No IRQ resource\n");
		return -ENODEV;
	}
	i2c_dev->irq = irq->start;

	ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
			  dev_name(&pdev->dev), i2c_dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not request IRQ\n");
		return -ENODEV;
	}

	adap = &i2c_dev->adapter;
	i2c_set_adapdata(adap, i2c_dev);
	adap->owner = THIS_MODULE;
	adap->class = I2C_CLASS_DEPRECATED;
	strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name));
	adap->algo = &bcm2835_i2c_algo;
	adap->dev.parent = &pdev->dev;
	adap->dev.of_node = pdev->dev.of_node;
	adap->quirks = &bcm2835_i2c_quirks;

	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);

	ret = i2c_add_adapter(adap);
	if (ret)
		free_irq(i2c_dev->irq, i2c_dev);

	return ret;
}

static int bcm2835_i2c_remove(struct platform_device *pdev)
{
	struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);

	free_irq(i2c_dev->irq, i2c_dev);
	i2c_del_adapter(&i2c_dev->adapter);

	return 0;
}

static const struct of_device_id bcm2835_i2c_of_match[] = {
	{ .compatible = "brcm,bcm2835-i2c" },
	{},
};
MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);

static struct platform_driver bcm2835_i2c_driver = {
	.probe		= bcm2835_i2c_probe,
	.remove		= bcm2835_i2c_remove,
	.driver		= {
		.name	= "i2c-bcm2835",
		.of_match_table = bcm2835_i2c_of_match,
	},
};
module_platform_driver(bcm2835_i2c_driver);

MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:i2c-bcm2835");
Commit	Line	Data
f3b54b9a SW	1	/*
	2	* BCM2835 master mode driver
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/completion.h>
	16	#include <linux/err.h>
	17	#include <linux/i2c.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/io.h>
	20	#include <linux/module.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/slab.h>
	23
	24	#define BCM2835_I2C_C 0x0
	25	#define BCM2835_I2C_S 0x4
	26	#define BCM2835_I2C_DLEN 0x8
	27	#define BCM2835_I2C_A 0xc
	28	#define BCM2835_I2C_FIFO 0x10
	29	#define BCM2835_I2C_DIV 0x14
	30	#define BCM2835_I2C_DEL 0x18
	31	#define BCM2835_I2C_CLKT 0x1c
	32
	33	#define BCM2835_I2C_C_READ BIT(0)
	34	#define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */
	35	#define BCM2835_I2C_C_ST BIT(7)
	36	#define BCM2835_I2C_C_INTD BIT(8)
	37	#define BCM2835_I2C_C_INTT BIT(9)
	38	#define BCM2835_I2C_C_INTR BIT(10)
	39	#define BCM2835_I2C_C_I2CEN BIT(15)
	40
	41	#define BCM2835_I2C_S_TA BIT(0)
	42	#define BCM2835_I2C_S_DONE BIT(1)
	43	#define BCM2835_I2C_S_TXW BIT(2)
	44	#define BCM2835_I2C_S_RXR BIT(3)
	45	#define BCM2835_I2C_S_TXD BIT(4)
	46	#define BCM2835_I2C_S_RXD BIT(5)
	47	#define BCM2835_I2C_S_TXE BIT(6)
	48	#define BCM2835_I2C_S_RXF BIT(7)
	49	#define BCM2835_I2C_S_ERR BIT(8)
	50	#define BCM2835_I2C_S_CLKT BIT(9)
	51	#define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
	52
fe32a815 EA	53	#define BCM2835_I2C_FEDL_SHIFT 16
	54	#define BCM2835_I2C_REDL_SHIFT 0
	55
a294aba1 SW	56	#define BCM2835_I2C_CDIV_MIN 0x0002
	57	#define BCM2835_I2C_CDIV_MAX 0xFFFE
	58
f3b54b9a SW	59	struct bcm2835_i2c_dev {
	60	struct device *dev;
	61	void __iomem *regs;
	62	struct clk *clk;
	63	int irq;
9446f62e	64	u32 bus_clk_rate;
f3b54b9a SW	65	struct i2c_adapter adapter;
f3b54b9a SW	66	struct completion completion;
e2474541	67	struct i2c_msg *curr_msg;
ee05fea2	68	int num_msgs;
f3b54b9a SW	69	u32 msg_err;
	70	u8 *msg_buf;
	71	size_t msg_buf_remaining;
	72	};
	73
	74	static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
	75	u32 reg, u32 val)
	76	{
	77	writel(val, i2c_dev->regs + reg);
	78	}
	79
	80	static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
	81	{
	82	return readl(i2c_dev->regs + reg);
	83	}
	84
9446f62e NT	85	static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
9446f62e NT	86	{
fe32a815	87	u32 divider, redl, fedl;
9446f62e NT	88
	89	divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
	90	i2c_dev->bus_clk_rate);
	91	/*
	92	* Per the datasheet, the register is always interpreted as an even
	93	* number, by rounding down. In other words, the LSB is ignored. So,
	94	* if the LSB is set, increment the divider to avoid any issue.
	95	*/
	96	if (divider & 1)
	97	divider++;
	98	if ((divider < BCM2835_I2C_CDIV_MIN) \|\|
	99	(divider > BCM2835_I2C_CDIV_MAX)) {
	100	dev_err_ratelimited(i2c_dev->dev, "Invalid clock-frequency\n");
	101	return -EINVAL;
	102	}
	103
	104	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
	105
fe32a815 EA	106	/*
	107	* Number of core clocks to wait after falling edge before
	108	* outputting the next data bit. Note that both FEDL and REDL
	109	* can't be greater than CDIV/2.
	110	*/
	111	fedl = max(divider / 16, 1u);
	112
	113	/*
	114	* Number of core clocks to wait after rising edge before
	115	* sampling the next incoming data bit.
	116	*/
	117	redl = max(divider / 4, 1u);
	118
	119	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL,
	120	(fedl << BCM2835_I2C_FEDL_SHIFT) \|
	121	(redl << BCM2835_I2C_REDL_SHIFT));
9446f62e NT	122	return 0;
	123	}
	124
f3b54b9a SW	125	static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
	126	{
	127	u32 val;
	128
	129	while (i2c_dev->msg_buf_remaining) {
	130	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
	131	if (!(val & BCM2835_I2C_S_TXD))
	132	break;
	133	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
	134	*i2c_dev->msg_buf);
	135	i2c_dev->msg_buf++;
	136	i2c_dev->msg_buf_remaining--;
	137	}
	138	}
	139
	140	static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
	141	{
	142	u32 val;
	143
	144	while (i2c_dev->msg_buf_remaining) {
	145	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
	146	if (!(val & BCM2835_I2C_S_RXD))
	147	break;
	148	*i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
	149	BCM2835_I2C_FIFO);
	150	i2c_dev->msg_buf++;
	151	i2c_dev->msg_buf_remaining--;
	152	}
	153	}
	154
ee05fea2 NT	155	/*
	156	* Repeated Start Condition (Sr)
	157	* The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
	158	* talks about reading from a slave with 10 bit address. This is achieved by
	159	* issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
	160	* issue a read.
	161	* A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
	162	* firmware actually does it using polling and says that it's a workaround for
	163	* a problem in the state machine.
	164	* It turns out that it is possible to use the TXW interrupt to know when the
	165	* transfer is active, provided the FIFO has not been prefilled.
	166	*/
	167
	168	static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
	169	{
	170	u32 c = BCM2835_I2C_C_ST \| BCM2835_I2C_C_I2CEN;
	171	struct i2c_msg *msg = i2c_dev->curr_msg;
	172	bool last_msg = (i2c_dev->num_msgs == 1);
	173
	174	if (!i2c_dev->num_msgs)
	175	return;
	176
	177	i2c_dev->num_msgs--;
	178	i2c_dev->msg_buf = msg->buf;
	179	i2c_dev->msg_buf_remaining = msg->len;
	180
	181	if (msg->flags & I2C_M_RD)
	182	c \|= BCM2835_I2C_C_READ \| BCM2835_I2C_C_INTR;
	183	else
	184	c \|= BCM2835_I2C_C_INTT;
	185
	186	if (last_msg)
	187	c \|= BCM2835_I2C_C_INTD;
	188
	189	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
	190	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
	191	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
	192	}
	193
d4030d75 NT	194	/*
	195	* Note about I2C_C_CLEAR on error:
	196	* The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
	197	* non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
	198	* the state machine to send a NACK and a STOP. Since we're setting CLEAR
	199	* without I2CEN, that NACK will be hanging around queued up for next time
	200	* we start the engine.
	201	*/
	202
f3b54b9a SW	203	static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
	204	{
	205	struct bcm2835_i2c_dev *i2c_dev = data;
	206	u32 val, err;
	207
	208	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
f3b54b9a SW	209
	210	err = val & (BCM2835_I2C_S_CLKT \| BCM2835_I2C_S_ERR);
	211	if (err) {
	212	i2c_dev->msg_err = err;
d4030d75	213	goto complete;
f3b54b9a SW	214	}
f3b54b9a SW	215
f3b54b9a	216	if (val & BCM2835_I2C_S_DONE) {
ababb089 SW	217	if (!i2c_dev->curr_msg) {
	218	dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
	219	} else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
e2474541 NT	220	bcm2835_drain_rxfifo(i2c_dev);
	221	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
	222	}
	223
	224	if ((val & BCM2835_I2C_S_RXD) \|\| i2c_dev->msg_buf_remaining)
f3b54b9a SW	225	i2c_dev->msg_err = BCM2835_I2C_S_LEN;
	226	else
	227	i2c_dev->msg_err = 0;
d4030d75	228	goto complete;
f3b54b9a SW	229	}
f3b54b9a SW	230
e2474541	231	if (val & BCM2835_I2C_S_TXW) {
d4030d75 NT	232	if (!i2c_dev->msg_buf_remaining) {
	233	i2c_dev->msg_err = val \| BCM2835_I2C_S_LEN;
	234	goto complete;
	235	}
	236
f3b54b9a	237	bcm2835_fill_txfifo(i2c_dev);
ee05fea2 NT	238
	239	if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
	240	i2c_dev->curr_msg++;
	241	bcm2835_i2c_start_transfer(i2c_dev);
	242	}
	243
f3b54b9a SW	244	return IRQ_HANDLED;
	245	}
	246
e2474541	247	if (val & BCM2835_I2C_S_RXR) {
d4030d75 NT	248	if (!i2c_dev->msg_buf_remaining) {
	249	i2c_dev->msg_err = val \| BCM2835_I2C_S_LEN;
	250	goto complete;
	251	}
	252
e2474541 NT	253	bcm2835_drain_rxfifo(i2c_dev);
	254	return IRQ_HANDLED;
	255	}
	256
f3b54b9a	257	return IRQ_NONE;
d4030d75 NT	258
	259	complete:
	260	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
	261	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT \|
	262	BCM2835_I2C_S_ERR \| BCM2835_I2C_S_DONE);
	263	complete(&i2c_dev->completion);
	264
	265	return IRQ_HANDLED;
f3b54b9a SW	266	}
f3b54b9a SW	267
ee05fea2 NT	268	static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
ee05fea2 NT	269	int num)
f3b54b9a	270	{
ee05fea2	271	struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
c4dc1216	272	unsigned long time_left;
9446f62e	273	int i, ret;
f3b54b9a	274
ee05fea2 NT	275	for (i = 0; i < (num - 1); i++)
	276	if (msgs[i].flags & I2C_M_RD) {
	277	dev_warn_once(i2c_dev->dev,
	278	"only one read message supported, has to be last\n");
	279	return -EOPNOTSUPP;
	280	}
f3b54b9a	281
9446f62e NT	282	ret = bcm2835_i2c_set_divider(i2c_dev);
	283	if (ret)
	284	return ret;
	285
ee05fea2 NT	286	i2c_dev->curr_msg = msgs;
	287	i2c_dev->num_msgs = num;
	288	reinit_completion(&i2c_dev->completion);
f3b54b9a	289
ee05fea2	290	bcm2835_i2c_start_transfer(i2c_dev);
f3b54b9a SW	291
f3b54b9a SW	292	time_left = wait_for_completion_timeout(&i2c_dev->completion,
e13e19e1	293	adap->timeout);
f3b54b9a	294	if (!time_left) {
d4030d75 NT	295	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
d4030d75 NT	296	BCM2835_I2C_C_CLEAR);
f3b54b9a SW	297	dev_err(i2c_dev->dev, "i2c transfer timed out\n");
	298	return -ETIMEDOUT;
	299	}
	300
ee05fea2 NT	301	if (!i2c_dev->msg_err)
ee05fea2 NT	302	return num;
f3b54b9a	303
23c9540b	304	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
f3b54b9a SW	305
	306	if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
	307	return -EREMOTEIO;
f3b54b9a	308
ee05fea2	309	return -EIO;
f3b54b9a SW	310	}
	311
	312	static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
	313	{
	314	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	315	}
	316
	317	static const struct i2c_algorithm bcm2835_i2c_algo = {
	318	.master_xfer = bcm2835_i2c_xfer,
	319	.functionality = bcm2835_i2c_func,
	320	};
	321
4dbfb5f4 NC	322	/*
	323	* This HW was reported to have problems with clock stretching:
	324	* http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
	325	* https://www.raspberrypi.org/forums/viewtopic.php?p=146272
	326	*/
	327	static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
	328	.flags = I2C_AQ_NO_CLK_STRETCH,
	329	};
	330
f3b54b9a SW	331	static int bcm2835_i2c_probe(struct platform_device *pdev)
	332	{
	333	struct bcm2835_i2c_dev *i2c_dev;
ae50b1df	334	struct resource mem, irq;
f3b54b9a SW	335	int ret;
	336	struct i2c_adapter *adap;
	337
	338	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
46797a2a	339	if (!i2c_dev)
f3b54b9a	340	return -ENOMEM;
f3b54b9a SW	341	platform_set_drvdata(pdev, i2c_dev);
	342	i2c_dev->dev = &pdev->dev;
	343	init_completion(&i2c_dev->completion);
	344
	345	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ae50b1df JH	346	i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
	347	if (IS_ERR(i2c_dev->regs))
	348	return PTR_ERR(i2c_dev->regs);
f3b54b9a SW	349
	350	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
	351	if (IS_ERR(i2c_dev->clk)) {
85946abc EA	352	if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER)
85946abc EA	353	dev_err(&pdev->dev, "Could not get clock\n");
f3b54b9a SW	354	return PTR_ERR(i2c_dev->clk);
	355	}
	356
	357	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
9446f62e	358	&i2c_dev->bus_clk_rate);
f3b54b9a SW	359	if (ret < 0) {
	360	dev_warn(&pdev->dev,
	361	"Could not read clock-frequency property\n");
9446f62e	362	i2c_dev->bus_clk_rate = 100000;
f3b54b9a SW	363	}
f3b54b9a SW	364
f3b54b9a SW	365	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	366	if (!irq) {
	367	dev_err(&pdev->dev, "No IRQ resource\n");
	368	return -ENODEV;
	369	}
	370	i2c_dev->irq = irq->start;
	371
	372	ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
	373	dev_name(&pdev->dev), i2c_dev);
	374	if (ret) {
	375	dev_err(&pdev->dev, "Could not request IRQ\n");
	376	return -ENODEV;
	377	}
	378
	379	adap = &i2c_dev->adapter;
	380	i2c_set_adapdata(adap, i2c_dev);
	381	adap->owner = THIS_MODULE;
37e4f91a	382	adap->class = I2C_CLASS_DEPRECATED;
f3b54b9a SW	383	strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name));
	384	adap->algo = &bcm2835_i2c_algo;
	385	adap->dev.parent = &pdev->dev;
07a27a00	386	adap->dev.of_node = pdev->dev.of_node;
4dbfb5f4	387	adap->quirks = &bcm2835_i2c_quirks;
f3b54b9a SW	388
	389	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
	390
	391	ret = i2c_add_adapter(adap);
	392	if (ret)
	393	free_irq(i2c_dev->irq, i2c_dev);
	394
	395	return ret;
	396	}
	397
	398	static int bcm2835_i2c_remove(struct platform_device *pdev)
	399	{
	400	struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
	401
	402	free_irq(i2c_dev->irq, i2c_dev);
	403	i2c_del_adapter(&i2c_dev->adapter);
	404
	405	return 0;
	406	}
	407
	408	static const struct of_device_id bcm2835_i2c_of_match[] = {
	409	{ .compatible = "brcm,bcm2835-i2c" },
	410	{},
	411	};
	412	MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
	413
	414	static struct platform_driver bcm2835_i2c_driver = {
	415	.probe = bcm2835_i2c_probe,
	416	.remove = bcm2835_i2c_remove,
	417	.driver = {
	418	.name = "i2c-bcm2835",
f3b54b9a SW	419	.of_match_table = bcm2835_i2c_of_match,
	420	},
	421	};
	422	module_platform_driver(bcm2835_i2c_driver);
	423
	424	MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
	425	MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
	426	MODULE_LICENSE("GPL v2");
	427	MODULE_ALIAS("platform:i2c-bcm2835");