Commit | Line | Data |
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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface | |
4 | * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> | |
5 | * | |
6 | * 2.6 port by Matt Porter <mporter@kernel.crashing.org> | |
7 | * | |
8 | * The documentation describes this as an SMBus controller, but it doesn't | |
9 | * understand any of the SMBus protocol in hardware. It's really an I2C | |
10 | * controller that could emulate most of the SMBus in software. | |
11 | * | |
12 | * This is just a skeleton adapter to use with the Au1550 PSC | |
13 | * algorithm. It was developed for the Pb1550, but will work with | |
14 | * any Au1550 board that has a similar PSC configuration. | |
1da177e4 LT |
15 | */ |
16 | ||
1da177e4 LT |
17 | #include <linux/delay.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
8b798c4d | 20 | #include <linux/platform_device.h> |
1da177e4 LT |
21 | #include <linux/errno.h> |
22 | #include <linux/i2c.h> | |
8b798c4d | 23 | #include <linux/slab.h> |
1da177e4 | 24 | |
50d5676e | 25 | #include <asm/mach-au1x00/au1000.h> |
1da177e4 LT |
26 | #include <asm/mach-au1x00/au1xxx_psc.h> |
27 | ||
c5de6467 ML |
28 | #define PSC_SEL 0x00 |
29 | #define PSC_CTRL 0x04 | |
30 | #define PSC_SMBCFG 0x08 | |
31 | #define PSC_SMBMSK 0x0C | |
32 | #define PSC_SMBPCR 0x10 | |
33 | #define PSC_SMBSTAT 0x14 | |
34 | #define PSC_SMBEVNT 0x18 | |
35 | #define PSC_SMBTXRX 0x1C | |
36 | #define PSC_SMBTMR 0x20 | |
37 | ||
8b798c4d | 38 | struct i2c_au1550_data { |
c5de6467 | 39 | void __iomem *psc_base; |
8b798c4d | 40 | int xfer_timeout; |
8b798c4d | 41 | struct i2c_adapter adap; |
8b798c4d | 42 | }; |
1da177e4 | 43 | |
c5de6467 | 44 | static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v) |
1da177e4 | 45 | { |
c5de6467 ML |
46 | __raw_writel(v, a->psc_base + r); |
47 | wmb(); | |
48 | } | |
1da177e4 | 49 | |
c5de6467 ML |
50 | static inline unsigned long RD(struct i2c_au1550_data *a, int r) |
51 | { | |
52 | return __raw_readl(a->psc_base + r); | |
53 | } | |
1da177e4 | 54 | |
c5de6467 ML |
55 | static int wait_xfer_done(struct i2c_au1550_data *adap) |
56 | { | |
57 | int i; | |
58 | ||
59 | /* Wait for Tx Buffer Empty */ | |
1da177e4 | 60 | for (i = 0; i < adap->xfer_timeout; i++) { |
c5de6467 | 61 | if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE) |
1da177e4 | 62 | return 0; |
a202707e | 63 | |
1da177e4 LT |
64 | udelay(1); |
65 | } | |
66 | ||
67 | return -ETIMEDOUT; | |
68 | } | |
69 | ||
c5de6467 | 70 | static int wait_ack(struct i2c_au1550_data *adap) |
1da177e4 | 71 | { |
c5de6467 | 72 | unsigned long stat; |
1da177e4 LT |
73 | |
74 | if (wait_xfer_done(adap)) | |
75 | return -ETIMEDOUT; | |
76 | ||
c5de6467 | 77 | stat = RD(adap, PSC_SMBEVNT); |
1da177e4 LT |
78 | if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) |
79 | return -ETIMEDOUT; | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
a4c98e4a | 84 | static int wait_controller_done(struct i2c_au1550_data *adap) |
1da177e4 | 85 | { |
c5de6467 | 86 | int i; |
1da177e4 | 87 | |
84785f12 | 88 | for (i = 0; i < 2 * adap->xfer_timeout; i++) { |
c5de6467 | 89 | if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0) |
1da177e4 LT |
90 | return 0; |
91 | udelay(1); | |
92 | } | |
93 | ||
94 | return -ETIMEDOUT; | |
95 | } | |
96 | ||
97 | static int | |
91f27958 | 98 | do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q) |
1da177e4 | 99 | { |
c5de6467 | 100 | unsigned long stat; |
1da177e4 | 101 | |
c5de6467 ML |
102 | /* Reset the FIFOs, clear events. */ |
103 | stat = RD(adap, PSC_SMBSTAT); | |
104 | WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR); | |
8859942e DP |
105 | |
106 | if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) { | |
c5de6467 ML |
107 | WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); |
108 | while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0) | |
109 | cpu_relax(); | |
8859942e DP |
110 | udelay(50); |
111 | } | |
1da177e4 | 112 | |
c5de6467 | 113 | /* Write out the i2c chip address and specify operation */ |
1da177e4 LT |
114 | addr <<= 1; |
115 | if (rd) | |
116 | addr |= 1; | |
117 | ||
91f27958 ML |
118 | /* zero-byte xfers stop immediately */ |
119 | if (q) | |
120 | addr |= PSC_SMBTXRX_STP; | |
121 | ||
a4c98e4a | 122 | /* Put byte into fifo, start up controller */ |
c5de6467 ML |
123 | WR(adap, PSC_SMBTXRX, addr); |
124 | WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); | |
1da177e4 LT |
125 | if (wait_ack(adap)) |
126 | return -EIO; | |
a4c98e4a | 127 | return (q) ? wait_controller_done(adap) : 0; |
1da177e4 LT |
128 | } |
129 | ||
c5de6467 | 130 | static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out) |
1da177e4 | 131 | { |
c5de6467 | 132 | int j; |
1da177e4 LT |
133 | |
134 | if (wait_xfer_done(adap)) | |
135 | return -EIO; | |
136 | ||
1da177e4 LT |
137 | j = adap->xfer_timeout * 100; |
138 | do { | |
139 | j--; | |
140 | if (j <= 0) | |
141 | return -EIO; | |
142 | ||
c5de6467 | 143 | if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0) |
1da177e4 LT |
144 | j = 0; |
145 | else | |
146 | udelay(1); | |
147 | } while (j > 0); | |
c5de6467 ML |
148 | |
149 | *out = RD(adap, PSC_SMBTXRX); | |
1da177e4 LT |
150 | |
151 | return 0; | |
152 | } | |
153 | ||
c5de6467 | 154 | static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf, |
1da177e4 LT |
155 | unsigned int len) |
156 | { | |
c5de6467 | 157 | int i; |
1da177e4 LT |
158 | |
159 | if (len == 0) | |
160 | return 0; | |
161 | ||
162 | /* A read is performed by stuffing the transmit fifo with | |
163 | * zero bytes for timing, waiting for bytes to appear in the | |
164 | * receive fifo, then reading the bytes. | |
165 | */ | |
1da177e4 | 166 | i = 0; |
c5de6467 ML |
167 | while (i < (len - 1)) { |
168 | WR(adap, PSC_SMBTXRX, 0); | |
169 | if (wait_for_rx_byte(adap, &buf[i])) | |
1da177e4 LT |
170 | return -EIO; |
171 | ||
1da177e4 LT |
172 | i++; |
173 | } | |
174 | ||
c5de6467 ML |
175 | /* The last byte has to indicate transfer done. */ |
176 | WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP); | |
a4c98e4a | 177 | if (wait_controller_done(adap)) |
1da177e4 LT |
178 | return -EIO; |
179 | ||
c5de6467 | 180 | buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff); |
1da177e4 LT |
181 | return 0; |
182 | } | |
183 | ||
c5de6467 | 184 | static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf, |
1da177e4 LT |
185 | unsigned int len) |
186 | { | |
c5de6467 ML |
187 | int i; |
188 | unsigned long data; | |
1da177e4 LT |
189 | |
190 | if (len == 0) | |
191 | return 0; | |
192 | ||
1da177e4 LT |
193 | i = 0; |
194 | while (i < (len-1)) { | |
195 | data = buf[i]; | |
c5de6467 | 196 | WR(adap, PSC_SMBTXRX, data); |
1da177e4 LT |
197 | if (wait_ack(adap)) |
198 | return -EIO; | |
199 | i++; | |
200 | } | |
201 | ||
c5de6467 | 202 | /* The last byte has to indicate transfer done. */ |
1da177e4 LT |
203 | data = buf[i]; |
204 | data |= PSC_SMBTXRX_STP; | |
c5de6467 | 205 | WR(adap, PSC_SMBTXRX, data); |
a4c98e4a | 206 | if (wait_controller_done(adap)) |
1da177e4 LT |
207 | return -EIO; |
208 | return 0; | |
209 | } | |
210 | ||
211 | static int | |
212 | au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) | |
213 | { | |
214 | struct i2c_au1550_data *adap = i2c_adap->algo_data; | |
215 | struct i2c_msg *p; | |
216 | int i, err = 0; | |
217 | ||
c5de6467 | 218 | WR(adap, PSC_CTRL, PSC_CTRL_ENABLE); |
f09f71b2 | 219 | |
1da177e4 LT |
220 | for (i = 0; !err && i < num; i++) { |
221 | p = &msgs[i]; | |
91f27958 ML |
222 | err = do_address(adap, p->addr, p->flags & I2C_M_RD, |
223 | (p->len == 0)); | |
1da177e4 LT |
224 | if (err || !p->len) |
225 | continue; | |
226 | if (p->flags & I2C_M_RD) | |
227 | err = i2c_read(adap, p->buf, p->len); | |
228 | else | |
229 | err = i2c_write(adap, p->buf, p->len); | |
230 | } | |
231 | ||
232 | /* Return the number of messages processed, or the error code. | |
233 | */ | |
234 | if (err == 0) | |
235 | err = num; | |
f09f71b2 | 236 | |
c5de6467 | 237 | WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND); |
f09f71b2 | 238 | |
1da177e4 LT |
239 | return err; |
240 | } | |
241 | ||
c5de6467 | 242 | static u32 au1550_func(struct i2c_adapter *adap) |
1da177e4 | 243 | { |
6ed07134 | 244 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
1da177e4 LT |
245 | } |
246 | ||
8f9082c5 | 247 | static const struct i2c_algorithm au1550_algo = { |
a4c98e4a WS |
248 | .xfer = au1550_xfer, |
249 | .functionality = au1550_func, | |
1da177e4 LT |
250 | }; |
251 | ||
f09f71b2 ML |
252 | static void i2c_au1550_setup(struct i2c_au1550_data *priv) |
253 | { | |
c5de6467 | 254 | unsigned long cfg; |
f09f71b2 | 255 | |
c5de6467 ML |
256 | WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); |
257 | WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE); | |
258 | WR(priv, PSC_SMBCFG, 0); | |
259 | WR(priv, PSC_CTRL, PSC_CTRL_ENABLE); | |
260 | while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0) | |
261 | cpu_relax(); | |
262 | ||
263 | cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE; | |
264 | WR(priv, PSC_SMBCFG, cfg); | |
f09f71b2 ML |
265 | |
266 | /* Divide by 8 to get a 6.25 MHz clock. The later protocol | |
267 | * timings are based on this clock. | |
268 | */ | |
c5de6467 ML |
269 | cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); |
270 | WR(priv, PSC_SMBCFG, cfg); | |
271 | WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK); | |
f09f71b2 ML |
272 | |
273 | /* Set the protocol timer values. See Table 71 in the | |
274 | * Au1550 Data Book for standard timing values. | |
275 | */ | |
8a5e3d47 ML |
276 | WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(20) | \ |
277 | PSC_SMBTMR_SET_PU(20) | PSC_SMBTMR_SET_SH(20) | \ | |
278 | PSC_SMBTMR_SET_SU(20) | PSC_SMBTMR_SET_CL(20) | \ | |
279 | PSC_SMBTMR_SET_CH(20)); | |
f09f71b2 | 280 | |
c5de6467 ML |
281 | cfg |= PSC_SMBCFG_DE_ENABLE; |
282 | WR(priv, PSC_SMBCFG, cfg); | |
283 | while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0) | |
284 | cpu_relax(); | |
f09f71b2 | 285 | |
c5de6467 | 286 | WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND); |
f09f71b2 ML |
287 | } |
288 | ||
289 | static void i2c_au1550_disable(struct i2c_au1550_data *priv) | |
290 | { | |
c5de6467 ML |
291 | WR(priv, PSC_SMBCFG, 0); |
292 | WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); | |
f09f71b2 ML |
293 | } |
294 | ||
1da177e4 LT |
295 | /* |
296 | * registering functions to load algorithms at runtime | |
297 | * Prior to calling us, the 50MHz clock frequency and routing | |
298 | * must have been set up for the PSC indicated by the adapter. | |
299 | */ | |
0b255e92 | 300 | static int |
8b798c4d | 301 | i2c_au1550_probe(struct platform_device *pdev) |
1da177e4 | 302 | { |
8b798c4d | 303 | struct i2c_au1550_data *priv; |
8b798c4d ML |
304 | int ret; |
305 | ||
174f2366 AL |
306 | priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_au1550_data), |
307 | GFP_KERNEL); | |
308 | if (!priv) | |
309 | return -ENOMEM; | |
1da177e4 | 310 | |
3cf77ad2 | 311 | priv->psc_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); |
174f2366 AL |
312 | if (IS_ERR(priv->psc_base)) |
313 | return PTR_ERR(priv->psc_base); | |
8b798c4d | 314 | |
8b798c4d | 315 | priv->xfer_timeout = 200; |
8b798c4d | 316 | |
8b798c4d ML |
317 | priv->adap.nr = pdev->id; |
318 | priv->adap.algo = &au1550_algo; | |
319 | priv->adap.algo_data = priv; | |
320 | priv->adap.dev.parent = &pdev->dev; | |
ea1558ce | 321 | strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); |
1da177e4 | 322 | |
c5de6467 | 323 | /* Now, set up the PSC for SMBus PIO mode. */ |
f09f71b2 | 324 | i2c_au1550_setup(priv); |
1da177e4 | 325 | |
8b798c4d | 326 | ret = i2c_add_numbered_adapter(&priv->adap); |
174f2366 AL |
327 | if (ret) { |
328 | i2c_au1550_disable(priv); | |
329 | return ret; | |
8b798c4d ML |
330 | } |
331 | ||
174f2366 AL |
332 | platform_set_drvdata(pdev, priv); |
333 | return 0; | |
8b798c4d | 334 | } |
1da177e4 | 335 | |
e190a0c3 | 336 | static void i2c_au1550_remove(struct platform_device *pdev) |
1da177e4 | 337 | { |
8b798c4d | 338 | struct i2c_au1550_data *priv = platform_get_drvdata(pdev); |
8b798c4d | 339 | |
8b798c4d | 340 | i2c_del_adapter(&priv->adap); |
f09f71b2 | 341 | i2c_au1550_disable(priv); |
1da177e4 LT |
342 | } |
343 | ||
46f344e2 | 344 | static int i2c_au1550_suspend(struct device *dev) |
1da177e4 | 345 | { |
46f344e2 | 346 | struct i2c_au1550_data *priv = dev_get_drvdata(dev); |
8b798c4d | 347 | |
f09f71b2 ML |
348 | i2c_au1550_disable(priv); |
349 | ||
1da177e4 LT |
350 | return 0; |
351 | } | |
352 | ||
46f344e2 | 353 | static int i2c_au1550_resume(struct device *dev) |
1da177e4 | 354 | { |
46f344e2 | 355 | struct i2c_au1550_data *priv = dev_get_drvdata(dev); |
8b798c4d | 356 | |
f09f71b2 ML |
357 | i2c_au1550_setup(priv); |
358 | ||
1da177e4 LT |
359 | return 0; |
360 | } | |
46f344e2 | 361 | |
2f0a81a2 PC |
362 | static DEFINE_SIMPLE_DEV_PM_OPS(i2c_au1550_pmops, |
363 | i2c_au1550_suspend, i2c_au1550_resume); | |
1da177e4 | 364 | |
8b798c4d ML |
365 | static struct platform_driver au1xpsc_smbus_driver = { |
366 | .driver = { | |
367 | .name = "au1xpsc_smbus", | |
2f0a81a2 | 368 | .pm = pm_sleep_ptr(&i2c_au1550_pmops), |
8b798c4d ML |
369 | }, |
370 | .probe = i2c_au1550_probe, | |
e190a0c3 | 371 | .remove_new = i2c_au1550_remove, |
1da177e4 LT |
372 | }; |
373 | ||
a3664b51 | 374 | module_platform_driver(au1xpsc_smbus_driver); |
1da177e4 LT |
375 | |
376 | MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC."); | |
377 | MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550"); | |
378 | MODULE_LICENSE("GPL"); | |
add8eda7 | 379 | MODULE_ALIAS("platform:au1xpsc_smbus"); |