Commit | Line | Data |
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fac368a0 NV |
1 | /* |
2 | * i2c Support for Atmel's AT91 Two-Wire Interface (TWI) | |
3 | * | |
4 | * Copyright (C) 2011 Weinmann Medical GmbH | |
5 | * Author: Nikolaus Voss <n.voss@weinmann.de> | |
6 | * | |
7 | * Evolved from original work by: | |
8 | * Copyright (C) 2004 Rick Bronson | |
9 | * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com> | |
10 | * | |
11 | * Borrowed heavily from original work by: | |
12 | * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | */ | |
19 | ||
20 | #include <linux/clk.h> | |
21 | #include <linux/completion.h> | |
60937b2c LD |
22 | #include <linux/dma-mapping.h> |
23 | #include <linux/dmaengine.h> | |
fac368a0 NV |
24 | #include <linux/err.h> |
25 | #include <linux/i2c.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
70d46a24 LD |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
31 | #include <linux/of_i2c.h> | |
fac368a0 NV |
32 | #include <linux/platform_device.h> |
33 | #include <linux/slab.h> | |
60937b2c | 34 | #include <linux/platform_data/dma-atmel.h> |
fac368a0 NV |
35 | |
36 | #define TWI_CLK_HZ 100000 /* max 400 Kbits/s */ | |
37 | #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */ | |
60937b2c | 38 | #define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */ |
fac368a0 NV |
39 | |
40 | /* AT91 TWI register definitions */ | |
41 | #define AT91_TWI_CR 0x0000 /* Control Register */ | |
42 | #define AT91_TWI_START 0x0001 /* Send a Start Condition */ | |
43 | #define AT91_TWI_STOP 0x0002 /* Send a Stop Condition */ | |
44 | #define AT91_TWI_MSEN 0x0004 /* Master Transfer Enable */ | |
45 | #define AT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */ | |
7c3fe64d | 46 | #define AT91_TWI_QUICK 0x0040 /* SMBus quick command */ |
fac368a0 NV |
47 | #define AT91_TWI_SWRST 0x0080 /* Software Reset */ |
48 | ||
49 | #define AT91_TWI_MMR 0x0004 /* Master Mode Register */ | |
50 | #define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */ | |
51 | #define AT91_TWI_MREAD 0x1000 /* Master Read Direction */ | |
52 | ||
53 | #define AT91_TWI_IADR 0x000c /* Internal Address Register */ | |
54 | ||
55 | #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */ | |
56 | ||
57 | #define AT91_TWI_SR 0x0020 /* Status Register */ | |
58 | #define AT91_TWI_TXCOMP 0x0001 /* Transmission Complete */ | |
59 | #define AT91_TWI_RXRDY 0x0002 /* Receive Holding Register Ready */ | |
60 | #define AT91_TWI_TXRDY 0x0004 /* Transmit Holding Register Ready */ | |
61 | ||
62 | #define AT91_TWI_OVRE 0x0040 /* Overrun Error */ | |
63 | #define AT91_TWI_UNRE 0x0080 /* Underrun Error */ | |
64 | #define AT91_TWI_NACK 0x0100 /* Not Acknowledged */ | |
65 | ||
66 | #define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */ | |
67 | #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */ | |
68 | #define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */ | |
69 | #define AT91_TWI_RHR 0x0030 /* Receive Holding Register */ | |
70 | #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */ | |
71 | ||
72 | struct at91_twi_pdata { | |
5f433819 LD |
73 | unsigned clk_max_div; |
74 | unsigned clk_offset; | |
75 | bool has_unre_flag; | |
60937b2c LD |
76 | bool has_dma_support; |
77 | struct at_dma_slave dma_slave; | |
78 | }; | |
79 | ||
80 | struct at91_twi_dma { | |
81 | struct dma_chan *chan_rx; | |
82 | struct dma_chan *chan_tx; | |
83 | struct scatterlist sg; | |
84 | struct dma_async_tx_descriptor *data_desc; | |
85 | enum dma_data_direction direction; | |
86 | bool buf_mapped; | |
87 | bool xfer_in_progress; | |
fac368a0 NV |
88 | }; |
89 | ||
90 | struct at91_twi_dev { | |
5f433819 LD |
91 | struct device *dev; |
92 | void __iomem *base; | |
93 | struct completion cmd_complete; | |
94 | struct clk *clk; | |
95 | u8 *buf; | |
96 | size_t buf_len; | |
97 | struct i2c_msg *msg; | |
98 | int irq; | |
60937b2c | 99 | unsigned imr; |
5f433819 LD |
100 | unsigned transfer_status; |
101 | struct i2c_adapter adapter; | |
102 | unsigned twi_cwgr_reg; | |
103 | struct at91_twi_pdata *pdata; | |
60937b2c LD |
104 | bool use_dma; |
105 | struct at91_twi_dma dma; | |
fac368a0 NV |
106 | }; |
107 | ||
108 | static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg) | |
109 | { | |
110 | return readl_relaxed(dev->base + reg); | |
111 | } | |
112 | ||
113 | static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val) | |
114 | { | |
115 | writel_relaxed(val, dev->base + reg); | |
116 | } | |
117 | ||
118 | static void at91_disable_twi_interrupts(struct at91_twi_dev *dev) | |
119 | { | |
120 | at91_twi_write(dev, AT91_TWI_IDR, | |
121 | AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY); | |
122 | } | |
123 | ||
60937b2c LD |
124 | static void at91_twi_irq_save(struct at91_twi_dev *dev) |
125 | { | |
126 | dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & 0x7; | |
127 | at91_disable_twi_interrupts(dev); | |
128 | } | |
129 | ||
130 | static void at91_twi_irq_restore(struct at91_twi_dev *dev) | |
131 | { | |
132 | at91_twi_write(dev, AT91_TWI_IER, dev->imr); | |
133 | } | |
134 | ||
fac368a0 NV |
135 | static void at91_init_twi_bus(struct at91_twi_dev *dev) |
136 | { | |
137 | at91_disable_twi_interrupts(dev); | |
138 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST); | |
139 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN); | |
140 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS); | |
141 | at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg); | |
142 | } | |
143 | ||
144 | /* | |
145 | * Calculate symmetric clock as stated in datasheet: | |
146 | * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) | |
147 | */ | |
0b255e92 | 148 | static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk) |
fac368a0 NV |
149 | { |
150 | int ckdiv, cdiv, div; | |
151 | struct at91_twi_pdata *pdata = dev->pdata; | |
152 | int offset = pdata->clk_offset; | |
153 | int max_ckdiv = pdata->clk_max_div; | |
154 | ||
155 | div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk), | |
156 | 2 * twi_clk) - offset); | |
157 | ckdiv = fls(div >> 8); | |
158 | cdiv = div >> ckdiv; | |
159 | ||
160 | if (ckdiv > max_ckdiv) { | |
161 | dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n", | |
162 | ckdiv, max_ckdiv); | |
163 | ckdiv = max_ckdiv; | |
164 | cdiv = 255; | |
165 | } | |
166 | ||
167 | dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv; | |
168 | dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv); | |
169 | } | |
170 | ||
60937b2c LD |
171 | static void at91_twi_dma_cleanup(struct at91_twi_dev *dev) |
172 | { | |
173 | struct at91_twi_dma *dma = &dev->dma; | |
174 | ||
175 | at91_twi_irq_save(dev); | |
176 | ||
177 | if (dma->xfer_in_progress) { | |
178 | if (dma->direction == DMA_FROM_DEVICE) | |
179 | dmaengine_terminate_all(dma->chan_rx); | |
180 | else | |
181 | dmaengine_terminate_all(dma->chan_tx); | |
182 | dma->xfer_in_progress = false; | |
183 | } | |
184 | if (dma->buf_mapped) { | |
185 | dma_unmap_single(dev->dev, sg_dma_address(&dma->sg), | |
186 | dev->buf_len, dma->direction); | |
187 | dma->buf_mapped = false; | |
188 | } | |
189 | ||
190 | at91_twi_irq_restore(dev); | |
191 | } | |
192 | ||
fac368a0 NV |
193 | static void at91_twi_write_next_byte(struct at91_twi_dev *dev) |
194 | { | |
195 | if (dev->buf_len <= 0) | |
196 | return; | |
197 | ||
198 | at91_twi_write(dev, AT91_TWI_THR, *dev->buf); | |
199 | ||
200 | /* send stop when last byte has been written */ | |
201 | if (--dev->buf_len == 0) | |
202 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
203 | ||
204 | dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len); | |
205 | ||
206 | ++dev->buf; | |
207 | } | |
208 | ||
60937b2c LD |
209 | static void at91_twi_write_data_dma_callback(void *data) |
210 | { | |
211 | struct at91_twi_dev *dev = (struct at91_twi_dev *)data; | |
212 | ||
213 | dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg), | |
214 | dev->buf_len, DMA_MEM_TO_DEV); | |
215 | ||
216 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
217 | } | |
218 | ||
219 | static void at91_twi_write_data_dma(struct at91_twi_dev *dev) | |
220 | { | |
221 | dma_addr_t dma_addr; | |
222 | struct dma_async_tx_descriptor *txdesc; | |
223 | struct at91_twi_dma *dma = &dev->dma; | |
224 | struct dma_chan *chan_tx = dma->chan_tx; | |
225 | ||
226 | if (dev->buf_len <= 0) | |
227 | return; | |
228 | ||
229 | dma->direction = DMA_TO_DEVICE; | |
230 | ||
231 | at91_twi_irq_save(dev); | |
232 | dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len, | |
233 | DMA_TO_DEVICE); | |
234 | if (dma_mapping_error(dev->dev, dma_addr)) { | |
235 | dev_err(dev->dev, "dma map failed\n"); | |
236 | return; | |
237 | } | |
238 | dma->buf_mapped = true; | |
239 | at91_twi_irq_restore(dev); | |
240 | sg_dma_len(&dma->sg) = dev->buf_len; | |
241 | sg_dma_address(&dma->sg) = dma_addr; | |
242 | ||
243 | txdesc = dmaengine_prep_slave_sg(chan_tx, &dma->sg, 1, DMA_MEM_TO_DEV, | |
244 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
245 | if (!txdesc) { | |
246 | dev_err(dev->dev, "dma prep slave sg failed\n"); | |
247 | goto error; | |
248 | } | |
249 | ||
250 | txdesc->callback = at91_twi_write_data_dma_callback; | |
251 | txdesc->callback_param = dev; | |
252 | ||
253 | dma->xfer_in_progress = true; | |
254 | dmaengine_submit(txdesc); | |
255 | dma_async_issue_pending(chan_tx); | |
256 | ||
257 | return; | |
258 | ||
259 | error: | |
260 | at91_twi_dma_cleanup(dev); | |
261 | } | |
262 | ||
fac368a0 NV |
263 | static void at91_twi_read_next_byte(struct at91_twi_dev *dev) |
264 | { | |
265 | if (dev->buf_len <= 0) | |
266 | return; | |
267 | ||
268 | *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff; | |
269 | --dev->buf_len; | |
270 | ||
271 | /* handle I2C_SMBUS_BLOCK_DATA */ | |
272 | if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) { | |
273 | dev->msg->flags &= ~I2C_M_RECV_LEN; | |
274 | dev->buf_len += *dev->buf; | |
275 | dev->msg->len = dev->buf_len + 1; | |
276 | dev_dbg(dev->dev, "received block length %d\n", dev->buf_len); | |
277 | } | |
278 | ||
279 | /* send stop if second but last byte has been read */ | |
280 | if (dev->buf_len == 1) | |
281 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | |
282 | ||
283 | dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len); | |
284 | ||
285 | ++dev->buf; | |
286 | } | |
287 | ||
60937b2c LD |
288 | static void at91_twi_read_data_dma_callback(void *data) |
289 | { | |
290 | struct at91_twi_dev *dev = (struct at91_twi_dev *)data; | |
291 | ||
292 | dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg), | |
293 | dev->buf_len, DMA_DEV_TO_MEM); | |
294 | ||
295 | /* The last two bytes have to be read without using dma */ | |
296 | dev->buf += dev->buf_len - 2; | |
297 | dev->buf_len = 2; | |
298 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY); | |
299 | } | |
300 | ||
301 | static void at91_twi_read_data_dma(struct at91_twi_dev *dev) | |
302 | { | |
303 | dma_addr_t dma_addr; | |
304 | struct dma_async_tx_descriptor *rxdesc; | |
305 | struct at91_twi_dma *dma = &dev->dma; | |
306 | struct dma_chan *chan_rx = dma->chan_rx; | |
307 | ||
308 | dma->direction = DMA_FROM_DEVICE; | |
309 | ||
310 | /* Keep in mind that we won't use dma to read the last two bytes */ | |
311 | at91_twi_irq_save(dev); | |
312 | dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2, | |
313 | DMA_FROM_DEVICE); | |
314 | if (dma_mapping_error(dev->dev, dma_addr)) { | |
315 | dev_err(dev->dev, "dma map failed\n"); | |
316 | return; | |
317 | } | |
318 | dma->buf_mapped = true; | |
319 | at91_twi_irq_restore(dev); | |
320 | dma->sg.dma_address = dma_addr; | |
321 | sg_dma_len(&dma->sg) = dev->buf_len - 2; | |
322 | ||
323 | rxdesc = dmaengine_prep_slave_sg(chan_rx, &dma->sg, 1, DMA_DEV_TO_MEM, | |
324 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
325 | if (!rxdesc) { | |
326 | dev_err(dev->dev, "dma prep slave sg failed\n"); | |
327 | goto error; | |
328 | } | |
329 | ||
330 | rxdesc->callback = at91_twi_read_data_dma_callback; | |
331 | rxdesc->callback_param = dev; | |
332 | ||
333 | dma->xfer_in_progress = true; | |
334 | dmaengine_submit(rxdesc); | |
335 | dma_async_issue_pending(dma->chan_rx); | |
336 | ||
337 | return; | |
338 | ||
339 | error: | |
340 | at91_twi_dma_cleanup(dev); | |
341 | } | |
342 | ||
fac368a0 NV |
343 | static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id) |
344 | { | |
345 | struct at91_twi_dev *dev = dev_id; | |
346 | const unsigned status = at91_twi_read(dev, AT91_TWI_SR); | |
347 | const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR); | |
348 | ||
349 | if (!irqstatus) | |
350 | return IRQ_NONE; | |
351 | else if (irqstatus & AT91_TWI_RXRDY) | |
352 | at91_twi_read_next_byte(dev); | |
353 | else if (irqstatus & AT91_TWI_TXRDY) | |
354 | at91_twi_write_next_byte(dev); | |
355 | ||
356 | /* catch error flags */ | |
357 | dev->transfer_status |= status; | |
358 | ||
359 | if (irqstatus & AT91_TWI_TXCOMP) { | |
360 | at91_disable_twi_interrupts(dev); | |
361 | complete(&dev->cmd_complete); | |
362 | } | |
363 | ||
364 | return IRQ_HANDLED; | |
365 | } | |
366 | ||
367 | static int at91_do_twi_transfer(struct at91_twi_dev *dev) | |
368 | { | |
369 | int ret; | |
370 | bool has_unre_flag = dev->pdata->has_unre_flag; | |
371 | ||
372 | dev_dbg(dev->dev, "transfer: %s %d bytes.\n", | |
373 | (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len); | |
374 | ||
375 | INIT_COMPLETION(dev->cmd_complete); | |
376 | dev->transfer_status = 0; | |
7c3fe64d LD |
377 | |
378 | if (!dev->buf_len) { | |
379 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK); | |
380 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); | |
381 | } else if (dev->msg->flags & I2C_M_RD) { | |
fac368a0 NV |
382 | unsigned start_flags = AT91_TWI_START; |
383 | ||
384 | if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) { | |
385 | dev_err(dev->dev, "RXRDY still set!"); | |
386 | at91_twi_read(dev, AT91_TWI_RHR); | |
387 | } | |
388 | ||
389 | /* if only one byte is to be read, immediately stop transfer */ | |
390 | if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN)) | |
391 | start_flags |= AT91_TWI_STOP; | |
392 | at91_twi_write(dev, AT91_TWI_CR, start_flags); | |
60937b2c LD |
393 | /* |
394 | * When using dma, the last byte has to be read manually in | |
395 | * order to not send the stop command too late and then | |
396 | * to receive extra data. In practice, there are some issues | |
397 | * if you use the dma to read n-1 bytes because of latency. | |
398 | * Reading n-2 bytes with dma and the two last ones manually | |
399 | * seems to be the best solution. | |
400 | */ | |
401 | if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) { | |
402 | at91_twi_read_data_dma(dev); | |
403 | /* | |
404 | * It is important to enable TXCOMP irq here because | |
405 | * doing it only when transferring the last two bytes | |
406 | * will mask NACK errors since TXCOMP is set when a | |
407 | * NACK occurs. | |
408 | */ | |
409 | at91_twi_write(dev, AT91_TWI_IER, | |
410 | AT91_TWI_TXCOMP); | |
411 | } else | |
412 | at91_twi_write(dev, AT91_TWI_IER, | |
fac368a0 NV |
413 | AT91_TWI_TXCOMP | AT91_TWI_RXRDY); |
414 | } else { | |
60937b2c LD |
415 | if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) { |
416 | at91_twi_write_data_dma(dev); | |
417 | at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); | |
418 | } else { | |
419 | at91_twi_write_next_byte(dev); | |
420 | at91_twi_write(dev, AT91_TWI_IER, | |
421 | AT91_TWI_TXCOMP | AT91_TWI_TXRDY); | |
422 | } | |
fac368a0 NV |
423 | } |
424 | ||
425 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, | |
426 | dev->adapter.timeout); | |
427 | if (ret == 0) { | |
428 | dev_err(dev->dev, "controller timed out\n"); | |
429 | at91_init_twi_bus(dev); | |
60937b2c LD |
430 | ret = -ETIMEDOUT; |
431 | goto error; | |
fac368a0 NV |
432 | } |
433 | if (dev->transfer_status & AT91_TWI_NACK) { | |
434 | dev_dbg(dev->dev, "received nack\n"); | |
60937b2c LD |
435 | ret = -EREMOTEIO; |
436 | goto error; | |
fac368a0 NV |
437 | } |
438 | if (dev->transfer_status & AT91_TWI_OVRE) { | |
439 | dev_err(dev->dev, "overrun while reading\n"); | |
60937b2c LD |
440 | ret = -EIO; |
441 | goto error; | |
fac368a0 NV |
442 | } |
443 | if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) { | |
444 | dev_err(dev->dev, "underrun while writing\n"); | |
60937b2c LD |
445 | ret = -EIO; |
446 | goto error; | |
fac368a0 NV |
447 | } |
448 | dev_dbg(dev->dev, "transfer complete\n"); | |
449 | ||
450 | return 0; | |
60937b2c LD |
451 | |
452 | error: | |
453 | at91_twi_dma_cleanup(dev); | |
454 | return ret; | |
fac368a0 NV |
455 | } |
456 | ||
457 | static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num) | |
458 | { | |
459 | struct at91_twi_dev *dev = i2c_get_adapdata(adap); | |
460 | int ret; | |
461 | unsigned int_addr_flag = 0; | |
462 | struct i2c_msg *m_start = msg; | |
463 | ||
464 | dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num); | |
465 | ||
466 | /* | |
467 | * The hardware can handle at most two messages concatenated by a | |
468 | * repeated start via it's internal address feature. | |
469 | */ | |
470 | if (num > 2) { | |
471 | dev_err(dev->dev, | |
472 | "cannot handle more than two concatenated messages.\n"); | |
473 | return 0; | |
474 | } else if (num == 2) { | |
475 | int internal_address = 0; | |
476 | int i; | |
477 | ||
478 | if (msg->flags & I2C_M_RD) { | |
479 | dev_err(dev->dev, "first transfer must be write.\n"); | |
480 | return -EINVAL; | |
481 | } | |
482 | if (msg->len > 3) { | |
483 | dev_err(dev->dev, "first message size must be <= 3.\n"); | |
484 | return -EINVAL; | |
485 | } | |
486 | ||
487 | /* 1st msg is put into the internal address, start with 2nd */ | |
488 | m_start = &msg[1]; | |
489 | for (i = 0; i < msg->len; ++i) { | |
490 | const unsigned addr = msg->buf[msg->len - 1 - i]; | |
491 | ||
492 | internal_address |= addr << (8 * i); | |
493 | int_addr_flag += AT91_TWI_IADRSZ_1; | |
494 | } | |
495 | at91_twi_write(dev, AT91_TWI_IADR, internal_address); | |
496 | } | |
497 | ||
498 | at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag | |
499 | | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0)); | |
500 | ||
501 | dev->buf_len = m_start->len; | |
502 | dev->buf = m_start->buf; | |
503 | dev->msg = m_start; | |
504 | ||
505 | ret = at91_do_twi_transfer(dev); | |
506 | ||
507 | return (ret < 0) ? ret : num; | |
508 | } | |
509 | ||
510 | static u32 at91_twi_func(struct i2c_adapter *adapter) | |
511 | { | |
512 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
513 | | I2C_FUNC_SMBUS_READ_BLOCK_DATA; | |
514 | } | |
515 | ||
516 | static struct i2c_algorithm at91_twi_algorithm = { | |
517 | .master_xfer = at91_twi_xfer, | |
518 | .functionality = at91_twi_func, | |
519 | }; | |
520 | ||
521 | static struct at91_twi_pdata at91rm9200_config = { | |
522 | .clk_max_div = 5, | |
523 | .clk_offset = 3, | |
524 | .has_unre_flag = true, | |
60937b2c | 525 | .has_dma_support = false, |
fac368a0 NV |
526 | }; |
527 | ||
528 | static struct at91_twi_pdata at91sam9261_config = { | |
529 | .clk_max_div = 5, | |
530 | .clk_offset = 4, | |
531 | .has_unre_flag = false, | |
60937b2c | 532 | .has_dma_support = false, |
fac368a0 NV |
533 | }; |
534 | ||
535 | static struct at91_twi_pdata at91sam9260_config = { | |
536 | .clk_max_div = 7, | |
537 | .clk_offset = 4, | |
538 | .has_unre_flag = false, | |
60937b2c | 539 | .has_dma_support = false, |
fac368a0 NV |
540 | }; |
541 | ||
542 | static struct at91_twi_pdata at91sam9g20_config = { | |
543 | .clk_max_div = 7, | |
544 | .clk_offset = 4, | |
545 | .has_unre_flag = false, | |
60937b2c | 546 | .has_dma_support = false, |
fac368a0 NV |
547 | }; |
548 | ||
549 | static struct at91_twi_pdata at91sam9g10_config = { | |
550 | .clk_max_div = 7, | |
551 | .clk_offset = 4, | |
552 | .has_unre_flag = false, | |
60937b2c | 553 | .has_dma_support = false, |
fac368a0 NV |
554 | }; |
555 | ||
556 | static const struct platform_device_id at91_twi_devtypes[] = { | |
557 | { | |
558 | .name = "i2c-at91rm9200", | |
559 | .driver_data = (unsigned long) &at91rm9200_config, | |
560 | }, { | |
561 | .name = "i2c-at91sam9261", | |
562 | .driver_data = (unsigned long) &at91sam9261_config, | |
563 | }, { | |
564 | .name = "i2c-at91sam9260", | |
565 | .driver_data = (unsigned long) &at91sam9260_config, | |
566 | }, { | |
567 | .name = "i2c-at91sam9g20", | |
568 | .driver_data = (unsigned long) &at91sam9g20_config, | |
569 | }, { | |
570 | .name = "i2c-at91sam9g10", | |
571 | .driver_data = (unsigned long) &at91sam9g10_config, | |
572 | }, { | |
573 | /* sentinel */ | |
574 | } | |
575 | }; | |
576 | ||
70d46a24 | 577 | #if defined(CONFIG_OF) |
4182b434 JE |
578 | static struct at91_twi_pdata at91sam9x5_config = { |
579 | .clk_max_div = 7, | |
580 | .clk_offset = 4, | |
581 | .has_unre_flag = false, | |
582 | .has_dma_support = true, | |
583 | }; | |
584 | ||
70d46a24 LD |
585 | static const struct of_device_id atmel_twi_dt_ids[] = { |
586 | { | |
631056c3 JE |
587 | .compatible = "atmel,at91rm9200-i2c", |
588 | .data = &at91rm9200_config, | |
589 | } , { | |
70d46a24 LD |
590 | .compatible = "atmel,at91sam9260-i2c", |
591 | .data = &at91sam9260_config, | |
592 | } , { | |
593 | .compatible = "atmel,at91sam9g20-i2c", | |
594 | .data = &at91sam9g20_config, | |
595 | } , { | |
596 | .compatible = "atmel,at91sam9g10-i2c", | |
597 | .data = &at91sam9g10_config, | |
598 | }, { | |
599 | .compatible = "atmel,at91sam9x5-i2c", | |
600 | .data = &at91sam9x5_config, | |
601 | }, { | |
602 | /* sentinel */ | |
603 | } | |
604 | }; | |
605 | MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids); | |
70d46a24 LD |
606 | #endif |
607 | ||
d877a721 | 608 | static bool filter(struct dma_chan *chan, void *pdata) |
60937b2c | 609 | { |
d877a721 LD |
610 | struct at91_twi_pdata *sl_pdata = pdata; |
611 | struct at_dma_slave *sl; | |
60937b2c | 612 | |
d877a721 LD |
613 | if (!sl_pdata) |
614 | return false; | |
615 | ||
616 | sl = &sl_pdata->dma_slave; | |
617 | if (sl && (sl->dma_dev == chan->device->dev)) { | |
60937b2c LD |
618 | chan->private = sl; |
619 | return true; | |
620 | } else { | |
621 | return false; | |
622 | } | |
623 | } | |
624 | ||
0b255e92 | 625 | static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr) |
60937b2c LD |
626 | { |
627 | int ret = 0; | |
d877a721 | 628 | struct at91_twi_pdata *pdata = dev->pdata; |
60937b2c LD |
629 | struct dma_slave_config slave_config; |
630 | struct at91_twi_dma *dma = &dev->dma; | |
d877a721 | 631 | dma_cap_mask_t mask; |
60937b2c LD |
632 | |
633 | memset(&slave_config, 0, sizeof(slave_config)); | |
634 | slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR; | |
635 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
636 | slave_config.src_maxburst = 1; | |
637 | slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR; | |
638 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
639 | slave_config.dst_maxburst = 1; | |
640 | slave_config.device_fc = false; | |
641 | ||
d877a721 LD |
642 | dma_cap_zero(mask); |
643 | dma_cap_set(DMA_SLAVE, mask); | |
60937b2c | 644 | |
d877a721 LD |
645 | dma->chan_tx = dma_request_slave_channel_compat(mask, filter, pdata, |
646 | dev->dev, "tx"); | |
647 | if (!dma->chan_tx) { | |
648 | dev_err(dev->dev, "can't get a DMA channel for tx\n"); | |
649 | ret = -EBUSY; | |
650 | goto error; | |
651 | } | |
652 | ||
653 | dma->chan_rx = dma_request_slave_channel_compat(mask, filter, pdata, | |
654 | dev->dev, "rx"); | |
655 | if (!dma->chan_rx) { | |
656 | dev_err(dev->dev, "can't get a DMA channel for rx\n"); | |
657 | ret = -EBUSY; | |
60937b2c LD |
658 | goto error; |
659 | } | |
660 | ||
661 | slave_config.direction = DMA_MEM_TO_DEV; | |
662 | if (dmaengine_slave_config(dma->chan_tx, &slave_config)) { | |
663 | dev_err(dev->dev, "failed to configure tx channel\n"); | |
664 | ret = -EINVAL; | |
665 | goto error; | |
666 | } | |
667 | ||
668 | slave_config.direction = DMA_DEV_TO_MEM; | |
669 | if (dmaengine_slave_config(dma->chan_rx, &slave_config)) { | |
670 | dev_err(dev->dev, "failed to configure rx channel\n"); | |
671 | ret = -EINVAL; | |
672 | goto error; | |
673 | } | |
674 | ||
675 | sg_init_table(&dma->sg, 1); | |
676 | dma->buf_mapped = false; | |
677 | dma->xfer_in_progress = false; | |
678 | ||
679 | dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n", | |
680 | dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); | |
681 | ||
682 | return ret; | |
683 | ||
684 | error: | |
685 | dev_info(dev->dev, "can't use DMA\n"); | |
686 | if (dma->chan_rx) | |
687 | dma_release_channel(dma->chan_rx); | |
688 | if (dma->chan_tx) | |
689 | dma_release_channel(dma->chan_tx); | |
690 | return ret; | |
691 | } | |
692 | ||
0b255e92 | 693 | static struct at91_twi_pdata *at91_twi_get_driver_data( |
70d46a24 LD |
694 | struct platform_device *pdev) |
695 | { | |
696 | if (pdev->dev.of_node) { | |
697 | const struct of_device_id *match; | |
698 | match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node); | |
699 | if (!match) | |
700 | return NULL; | |
cd32e6cc | 701 | return (struct at91_twi_pdata *)match->data; |
70d46a24 LD |
702 | } |
703 | return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data; | |
704 | } | |
705 | ||
0b255e92 | 706 | static int at91_twi_probe(struct platform_device *pdev) |
fac368a0 NV |
707 | { |
708 | struct at91_twi_dev *dev; | |
709 | struct resource *mem; | |
710 | int rc; | |
60937b2c | 711 | u32 phy_addr; |
fac368a0 NV |
712 | |
713 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); | |
714 | if (!dev) | |
715 | return -ENOMEM; | |
716 | init_completion(&dev->cmd_complete); | |
717 | dev->dev = &pdev->dev; | |
718 | ||
719 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
720 | if (!mem) | |
721 | return -ENODEV; | |
60937b2c | 722 | phy_addr = mem->start; |
fac368a0 NV |
723 | |
724 | dev->pdata = at91_twi_get_driver_data(pdev); | |
725 | if (!dev->pdata) | |
726 | return -ENODEV; | |
727 | ||
84dbf809 TR |
728 | dev->base = devm_ioremap_resource(&pdev->dev, mem); |
729 | if (IS_ERR(dev->base)) | |
730 | return PTR_ERR(dev->base); | |
fac368a0 NV |
731 | |
732 | dev->irq = platform_get_irq(pdev, 0); | |
733 | if (dev->irq < 0) | |
734 | return dev->irq; | |
735 | ||
736 | rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0, | |
737 | dev_name(dev->dev), dev); | |
738 | if (rc) { | |
739 | dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc); | |
740 | return rc; | |
741 | } | |
742 | ||
743 | platform_set_drvdata(pdev, dev); | |
744 | ||
745 | dev->clk = devm_clk_get(dev->dev, NULL); | |
746 | if (IS_ERR(dev->clk)) { | |
747 | dev_err(dev->dev, "no clock defined\n"); | |
748 | return -ENODEV; | |
749 | } | |
750 | clk_prepare_enable(dev->clk); | |
751 | ||
60937b2c LD |
752 | if (dev->pdata->has_dma_support) { |
753 | if (at91_twi_configure_dma(dev, phy_addr) == 0) | |
754 | dev->use_dma = true; | |
755 | } | |
756 | ||
fac368a0 NV |
757 | at91_calc_twi_clock(dev, TWI_CLK_HZ); |
758 | at91_init_twi_bus(dev); | |
759 | ||
760 | snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91"); | |
761 | i2c_set_adapdata(&dev->adapter, dev); | |
762 | dev->adapter.owner = THIS_MODULE; | |
763 | dev->adapter.class = I2C_CLASS_HWMON; | |
764 | dev->adapter.algo = &at91_twi_algorithm; | |
765 | dev->adapter.dev.parent = dev->dev; | |
766 | dev->adapter.nr = pdev->id; | |
767 | dev->adapter.timeout = AT91_I2C_TIMEOUT; | |
70d46a24 | 768 | dev->adapter.dev.of_node = pdev->dev.of_node; |
fac368a0 NV |
769 | |
770 | rc = i2c_add_numbered_adapter(&dev->adapter); | |
771 | if (rc) { | |
772 | dev_err(dev->dev, "Adapter %s registration failed\n", | |
773 | dev->adapter.name); | |
774 | clk_disable_unprepare(dev->clk); | |
775 | return rc; | |
776 | } | |
777 | ||
70d46a24 LD |
778 | of_i2c_register_devices(&dev->adapter); |
779 | ||
fac368a0 NV |
780 | dev_info(dev->dev, "AT91 i2c bus driver.\n"); |
781 | return 0; | |
782 | } | |
783 | ||
0b255e92 | 784 | static int at91_twi_remove(struct platform_device *pdev) |
fac368a0 NV |
785 | { |
786 | struct at91_twi_dev *dev = platform_get_drvdata(pdev); | |
fac368a0 | 787 | |
bf51a8c5 | 788 | i2c_del_adapter(&dev->adapter); |
fac368a0 NV |
789 | clk_disable_unprepare(dev->clk); |
790 | ||
bf51a8c5 | 791 | return 0; |
fac368a0 NV |
792 | } |
793 | ||
794 | #ifdef CONFIG_PM | |
795 | ||
796 | static int at91_twi_runtime_suspend(struct device *dev) | |
797 | { | |
798 | struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); | |
799 | ||
800 | clk_disable(twi_dev->clk); | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
805 | static int at91_twi_runtime_resume(struct device *dev) | |
806 | { | |
807 | struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); | |
808 | ||
809 | return clk_enable(twi_dev->clk); | |
810 | } | |
811 | ||
812 | static const struct dev_pm_ops at91_twi_pm = { | |
813 | .runtime_suspend = at91_twi_runtime_suspend, | |
814 | .runtime_resume = at91_twi_runtime_resume, | |
815 | }; | |
816 | ||
817 | #define at91_twi_pm_ops (&at91_twi_pm) | |
818 | #else | |
819 | #define at91_twi_pm_ops NULL | |
820 | #endif | |
821 | ||
822 | static struct platform_driver at91_twi_driver = { | |
823 | .probe = at91_twi_probe, | |
0b255e92 | 824 | .remove = at91_twi_remove, |
fac368a0 NV |
825 | .id_table = at91_twi_devtypes, |
826 | .driver = { | |
827 | .name = "at91_i2c", | |
828 | .owner = THIS_MODULE, | |
600abead | 829 | .of_match_table = of_match_ptr(atmel_twi_dt_ids), |
fac368a0 NV |
830 | .pm = at91_twi_pm_ops, |
831 | }, | |
832 | }; | |
833 | ||
834 | static int __init at91_twi_init(void) | |
835 | { | |
836 | return platform_driver_register(&at91_twi_driver); | |
837 | } | |
838 | ||
839 | static void __exit at91_twi_exit(void) | |
840 | { | |
841 | platform_driver_unregister(&at91_twi_driver); | |
842 | } | |
843 | ||
844 | subsys_initcall(at91_twi_init); | |
845 | module_exit(at91_twi_exit); | |
846 | ||
847 | MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>"); | |
848 | MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91"); | |
849 | MODULE_LICENSE("GPL"); | |
850 | MODULE_ALIAS("platform:at91_i2c"); |