coresight: tmc-etr: Disallow perf mode
[linux-2.6-block.git] / drivers / hwtracing / coresight / coresight.c
CommitLineData
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MP
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
a06ae860
PP
4 */
5
6#include <linux/kernel.h>
a06ae860
PP
7#include <linux/init.h>
8#include <linux/types.h>
9#include <linux/device.h>
10#include <linux/io.h>
11#include <linux/err.h>
12#include <linux/export.h>
13#include <linux/slab.h>
14#include <linux/mutex.h>
15#include <linux/clk.h>
16#include <linux/coresight.h>
17#include <linux/of_platform.h>
18#include <linux/delay.h>
5da5325f 19#include <linux/pm_runtime.h>
a06ae860
PP
20
21#include "coresight-priv.h"
22
23static DEFINE_MUTEX(coresight_mutex);
24
b3e94405
MP
25/**
26 * struct coresight_node - elements of a path, from source to sink
27 * @csdev: Address of an element.
28 * @link: hook to the list.
29 */
30struct coresight_node {
31 struct coresight_device *csdev;
32 struct list_head link;
33};
34
35/*
36 * When operating Coresight drivers from the sysFS interface, only a single
37 * path can exist from a tracer (associated to a CPU) to a sink.
38 */
a685d683
MP
39static DEFINE_PER_CPU(struct list_head *, tracer_path);
40
41/*
42 * As of this writing only a single STM can be found in CS topologies. Since
43 * there is no way to know if we'll ever see more and what kind of
44 * configuration they will enact, for the time being only define a single path
45 * for STM.
46 */
47static struct list_head *stm_path;
b3e94405 48
0c3fc4d5
MP
49/*
50 * When losing synchronisation a new barrier packet needs to be inserted at the
51 * beginning of the data collected in a buffer. That way the decoder knows that
52 * it needs to look for another sync sequence.
53 */
54const u32 barrier_pkt[5] = {0x7fffffff, 0x7fffffff,
55 0x7fffffff, 0x7fffffff, 0x0};
56
a06ae860
PP
57static int coresight_id_match(struct device *dev, void *data)
58{
59 int trace_id, i_trace_id;
60 struct coresight_device *csdev, *i_csdev;
61
62 csdev = data;
63 i_csdev = to_coresight_device(dev);
64
65 /*
66 * No need to care about oneself and components that are not
67 * sources or not enabled
68 */
69 if (i_csdev == csdev || !i_csdev->enable ||
70 i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE)
71 return 0;
72
73 /* Get the source ID for both compoment */
74 trace_id = source_ops(csdev)->trace_id(csdev);
75 i_trace_id = source_ops(i_csdev)->trace_id(i_csdev);
76
77 /* All you need is one */
78 if (trace_id == i_trace_id)
79 return 1;
80
81 return 0;
82}
83
84static int coresight_source_is_unique(struct coresight_device *csdev)
85{
86 int trace_id = source_ops(csdev)->trace_id(csdev);
87
88 /* this shouldn't happen */
89 if (trace_id < 0)
90 return 0;
91
92 return !bus_for_each_dev(&coresight_bustype, NULL,
93 csdev, coresight_id_match);
94}
95
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MP
96static int coresight_find_link_inport(struct coresight_device *csdev,
97 struct coresight_device *parent)
a06ae860
PP
98{
99 int i;
a06ae860
PP
100 struct coresight_connection *conn;
101
a06ae860
PP
102 for (i = 0; i < parent->nr_outport; i++) {
103 conn = &parent->conns[i];
104 if (conn->child_dev == csdev)
105 return conn->child_port;
106 }
107
108 dev_err(&csdev->dev, "couldn't find inport, parent: %s, child: %s\n",
109 dev_name(&parent->dev), dev_name(&csdev->dev));
110
111 return 0;
112}
113
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MP
114static int coresight_find_link_outport(struct coresight_device *csdev,
115 struct coresight_device *child)
a06ae860
PP
116{
117 int i;
a06ae860
PP
118 struct coresight_connection *conn;
119
a06ae860
PP
120 for (i = 0; i < csdev->nr_outport; i++) {
121 conn = &csdev->conns[i];
122 if (conn->child_dev == child)
123 return conn->outport;
124 }
125
126 dev_err(&csdev->dev, "couldn't find outport, parent: %s, child: %s\n",
127 dev_name(&csdev->dev), dev_name(&child->dev));
128
129 return 0;
130}
131
e827d455 132static int coresight_enable_sink(struct coresight_device *csdev, u32 mode)
a06ae860
PP
133{
134 int ret;
135
136 if (!csdev->enable) {
137 if (sink_ops(csdev)->enable) {
e827d455 138 ret = sink_ops(csdev)->enable(csdev, mode);
a06ae860
PP
139 if (ret)
140 return ret;
141 }
142 csdev->enable = true;
143 }
144
145 atomic_inc(csdev->refcnt);
146
147 return 0;
148}
149
150static void coresight_disable_sink(struct coresight_device *csdev)
151{
152 if (atomic_dec_return(csdev->refcnt) == 0) {
153 if (sink_ops(csdev)->disable) {
154 sink_ops(csdev)->disable(csdev);
155 csdev->enable = false;
156 }
157 }
158}
159
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MP
160static int coresight_enable_link(struct coresight_device *csdev,
161 struct coresight_device *parent,
162 struct coresight_device *child)
a06ae860
PP
163{
164 int ret;
165 int link_subtype;
166 int refport, inport, outport;
167
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MP
168 if (!parent || !child)
169 return -EINVAL;
170
171 inport = coresight_find_link_inport(csdev, parent);
172 outport = coresight_find_link_outport(csdev, child);
a06ae860
PP
173 link_subtype = csdev->subtype.link_subtype;
174
175 if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG)
176 refport = inport;
177 else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT)
178 refport = outport;
179 else
180 refport = 0;
181
182 if (atomic_inc_return(&csdev->refcnt[refport]) == 1) {
183 if (link_ops(csdev)->enable) {
184 ret = link_ops(csdev)->enable(csdev, inport, outport);
185 if (ret)
186 return ret;
187 }
188 }
189
190 csdev->enable = true;
191
192 return 0;
193}
194
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MP
195static void coresight_disable_link(struct coresight_device *csdev,
196 struct coresight_device *parent,
197 struct coresight_device *child)
a06ae860
PP
198{
199 int i, nr_conns;
200 int link_subtype;
201 int refport, inport, outport;
202
b3e94405
MP
203 if (!parent || !child)
204 return;
205
206 inport = coresight_find_link_inport(csdev, parent);
207 outport = coresight_find_link_outport(csdev, child);
a06ae860
PP
208 link_subtype = csdev->subtype.link_subtype;
209
210 if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG) {
211 refport = inport;
212 nr_conns = csdev->nr_inport;
213 } else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT) {
214 refport = outport;
215 nr_conns = csdev->nr_outport;
216 } else {
217 refport = 0;
218 nr_conns = 1;
219 }
220
221 if (atomic_dec_return(&csdev->refcnt[refport]) == 0) {
222 if (link_ops(csdev)->disable)
223 link_ops(csdev)->disable(csdev, inport, outport);
224 }
225
226 for (i = 0; i < nr_conns; i++)
227 if (atomic_read(&csdev->refcnt[i]) != 0)
228 return;
229
230 csdev->enable = false;
231}
232
22fd532e 233static int coresight_enable_source(struct coresight_device *csdev, u32 mode)
a06ae860
PP
234{
235 int ret;
236
237 if (!coresight_source_is_unique(csdev)) {
238 dev_warn(&csdev->dev, "traceID %d not unique\n",
239 source_ops(csdev)->trace_id(csdev));
240 return -EINVAL;
241 }
242
243 if (!csdev->enable) {
244 if (source_ops(csdev)->enable) {
882d5e11 245 ret = source_ops(csdev)->enable(csdev, NULL, mode);
a06ae860
PP
246 if (ret)
247 return ret;
248 }
249 csdev->enable = true;
250 }
251
252 atomic_inc(csdev->refcnt);
253
254 return 0;
255}
256
f73f20e1
SP
257/**
258 * coresight_disable_source - Drop the reference count by 1 and disable
259 * the device if there are no users left.
260 *
261 * @csdev - The coresight device to disable
262 *
263 * Returns true if the device has been disabled.
264 */
265static bool coresight_disable_source(struct coresight_device *csdev)
a06ae860
PP
266{
267 if (atomic_dec_return(csdev->refcnt) == 0) {
f73f20e1 268 if (source_ops(csdev)->disable)
68905d73 269 source_ops(csdev)->disable(csdev, NULL);
f73f20e1 270 csdev->enable = false;
a06ae860 271 }
f73f20e1 272 return !csdev->enable;
a06ae860
PP
273}
274
b3e94405 275void coresight_disable_path(struct list_head *path)
a06ae860 276{
dc2c4ef1 277 u32 type;
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MP
278 struct coresight_node *nd;
279 struct coresight_device *csdev, *parent, *child;
280
281 list_for_each_entry(nd, path, link) {
282 csdev = nd->csdev;
dc2c4ef1
MP
283 type = csdev->type;
284
285 /*
286 * ETF devices are tricky... They can be a link or a sink,
287 * depending on how they are configured. If an ETF has been
288 * "activated" it will be configured as a sink, otherwise
289 * go ahead with the link configuration.
290 */
291 if (type == CORESIGHT_DEV_TYPE_LINKSINK)
292 type = (csdev == coresight_get_sink(path)) ?
293 CORESIGHT_DEV_TYPE_SINK :
294 CORESIGHT_DEV_TYPE_LINK;
295
296 switch (type) {
b3e94405 297 case CORESIGHT_DEV_TYPE_SINK:
b3e94405
MP
298 coresight_disable_sink(csdev);
299 break;
300 case CORESIGHT_DEV_TYPE_SOURCE:
301 /* sources are disabled from either sysFS or Perf */
302 break;
303 case CORESIGHT_DEV_TYPE_LINK:
304 parent = list_prev_entry(nd, link)->csdev;
305 child = list_next_entry(nd, link)->csdev;
306 coresight_disable_link(csdev, parent, child);
307 break;
308 default:
309 break;
a06ae860 310 }
a06ae860 311 }
b3e94405 312}
a06ae860 313
e827d455 314int coresight_enable_path(struct list_head *path, u32 mode)
b3e94405
MP
315{
316
317 int ret = 0;
dc2c4ef1 318 u32 type;
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MP
319 struct coresight_node *nd;
320 struct coresight_device *csdev, *parent, *child;
321
322 list_for_each_entry_reverse(nd, path, link) {
323 csdev = nd->csdev;
dc2c4ef1
MP
324 type = csdev->type;
325
326 /*
327 * ETF devices are tricky... They can be a link or a sink,
328 * depending on how they are configured. If an ETF has been
329 * "activated" it will be configured as a sink, otherwise
330 * go ahead with the link configuration.
331 */
332 if (type == CORESIGHT_DEV_TYPE_LINKSINK)
333 type = (csdev == coresight_get_sink(path)) ?
334 CORESIGHT_DEV_TYPE_SINK :
335 CORESIGHT_DEV_TYPE_LINK;
336
337 switch (type) {
b3e94405 338 case CORESIGHT_DEV_TYPE_SINK:
e827d455 339 ret = coresight_enable_sink(csdev, mode);
b3e94405
MP
340 if (ret)
341 goto err;
342 break;
343 case CORESIGHT_DEV_TYPE_SOURCE:
344 /* sources are enabled from either sysFS or Perf */
345 break;
346 case CORESIGHT_DEV_TYPE_LINK:
347 parent = list_prev_entry(nd, link)->csdev;
348 child = list_next_entry(nd, link)->csdev;
349 ret = coresight_enable_link(csdev, parent, child);
350 if (ret)
351 goto err;
352 break;
353 default:
354 goto err;
a06ae860
PP
355 }
356 }
357
b3e94405 358out:
a06ae860 359 return ret;
b3e94405
MP
360err:
361 coresight_disable_path(path);
362 goto out;
a06ae860
PP
363}
364
b6404e21
MP
365struct coresight_device *coresight_get_sink(struct list_head *path)
366{
367 struct coresight_device *csdev;
368
369 if (!path)
370 return NULL;
371
372 csdev = list_last_entry(path, struct coresight_node, link)->csdev;
373 if (csdev->type != CORESIGHT_DEV_TYPE_SINK &&
374 csdev->type != CORESIGHT_DEV_TYPE_LINKSINK)
375 return NULL;
376
377 return csdev;
378}
379
d52c9750
MP
380static int coresight_enabled_sink(struct device *dev, void *data)
381{
382 bool *reset = data;
383 struct coresight_device *csdev = to_coresight_device(dev);
384
385 if ((csdev->type == CORESIGHT_DEV_TYPE_SINK ||
386 csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) &&
387 csdev->activated) {
388 /*
389 * Now that we have a handle on the sink for this session,
390 * disable the sysFS "enable_sink" flag so that possible
391 * concurrent perf session that wish to use another sink don't
392 * trip on it. Doing so has no ramification for the current
393 * session.
394 */
395 if (*reset)
396 csdev->activated = false;
397
398 return 1;
399 }
400
401 return 0;
402}
403
404/**
405 * coresight_get_enabled_sink - returns the first enabled sink found on the bus
406 * @deactivate: Whether the 'enable_sink' flag should be reset
407 *
408 * When operated from perf the deactivate parameter should be set to 'true'.
409 * That way the "enabled_sink" flag of the sink that was selected can be reset,
410 * allowing for other concurrent perf sessions to choose a different sink.
411 *
412 * When operated from sysFS users have full control and as such the deactivate
413 * parameter should be set to 'false', hence mandating users to explicitly
414 * clear the flag.
415 */
416struct coresight_device *coresight_get_enabled_sink(bool deactivate)
417{
418 struct device *dev = NULL;
419
420 dev = bus_find_device(&coresight_bustype, NULL, &deactivate,
421 coresight_enabled_sink);
422
423 return dev ? to_coresight_device(dev) : NULL;
424}
425
b3e94405
MP
426/**
427 * _coresight_build_path - recursively build a path from a @csdev to a sink.
428 * @csdev: The device to start from.
429 * @path: The list to add devices to.
430 *
431 * The tree of Coresight device is traversed until an activated sink is
432 * found. From there the sink is added to the list along with all the
433 * devices that led to that point - the end result is a list from source
434 * to sink. In that list the source is the first device and the sink the
435 * last one.
436 */
437static int _coresight_build_path(struct coresight_device *csdev,
d52c9750 438 struct coresight_device *sink,
b3e94405 439 struct list_head *path)
a06ae860 440{
b3e94405
MP
441 int i;
442 bool found = false;
443 struct coresight_node *node;
b3e94405
MP
444
445 /* An activated sink has been found. Enqueue the element */
d52c9750 446 if (csdev == sink)
b3e94405
MP
447 goto out;
448
449 /* Not a sink - recursively explore each port found on this element */
450 for (i = 0; i < csdev->nr_outport; i++) {
ec48a1d9
SP
451 struct coresight_device *child_dev = csdev->conns[i].child_dev;
452
d52c9750
MP
453 if (child_dev &&
454 _coresight_build_path(child_dev, sink, path) == 0) {
b3e94405
MP
455 found = true;
456 break;
a06ae860
PP
457 }
458 }
459
b3e94405
MP
460 if (!found)
461 return -ENODEV;
462
463out:
464 /*
465 * A path from this element to a sink has been found. The elements
466 * leading to the sink are already enqueued, all that is left to do
5da5325f
MP
467 * is tell the PM runtime core we need this element and add a node
468 * for it.
b3e94405
MP
469 */
470 node = kzalloc(sizeof(struct coresight_node), GFP_KERNEL);
471 if (!node)
472 return -ENOMEM;
473
474 node->csdev = csdev;
475 list_add(&node->link, path);
5da5325f 476 pm_runtime_get_sync(csdev->dev.parent);
b3e94405 477
a06ae860
PP
478 return 0;
479}
480
d52c9750
MP
481struct list_head *coresight_build_path(struct coresight_device *source,
482 struct coresight_device *sink)
a06ae860 483{
b3e94405 484 struct list_head *path;
5014e904 485 int rc;
a06ae860 486
d52c9750
MP
487 if (!sink)
488 return ERR_PTR(-EINVAL);
489
b3e94405
MP
490 path = kzalloc(sizeof(struct list_head), GFP_KERNEL);
491 if (!path)
8e67cdbc 492 return ERR_PTR(-ENOMEM);
a06ae860 493
b3e94405
MP
494 INIT_LIST_HEAD(path);
495
d52c9750 496 rc = _coresight_build_path(source, sink, path);
5014e904 497 if (rc) {
b3e94405 498 kfree(path);
5014e904 499 return ERR_PTR(rc);
a06ae860
PP
500 }
501
b3e94405
MP
502 return path;
503}
a06ae860 504
b3e94405
MP
505/**
506 * coresight_release_path - release a previously built path.
507 * @path: the path to release.
508 *
509 * Go through all the elements of a path and 1) removed it from the list and
510 * 2) free the memory allocated for each node.
511 */
512void coresight_release_path(struct list_head *path)
513{
5da5325f 514 struct coresight_device *csdev;
b3e94405 515 struct coresight_node *nd, *next;
a06ae860 516
b3e94405 517 list_for_each_entry_safe(nd, next, path, link) {
5da5325f
MP
518 csdev = nd->csdev;
519
520 pm_runtime_put_sync(csdev->dev.parent);
b3e94405
MP
521 list_del(&nd->link);
522 kfree(nd);
523 }
524
525 kfree(path);
526 path = NULL;
a06ae860
PP
527}
528
a685d683
MP
529/** coresight_validate_source - make sure a source has the right credentials
530 * @csdev: the device structure for a source.
531 * @function: the function this was called from.
532 *
533 * Assumes the coresight_mutex is held.
534 */
535static int coresight_validate_source(struct coresight_device *csdev,
536 const char *function)
537{
538 u32 type, subtype;
539
540 type = csdev->type;
541 subtype = csdev->subtype.source_subtype;
542
543 if (type != CORESIGHT_DEV_TYPE_SOURCE) {
544 dev_err(&csdev->dev, "wrong device type in %s\n", function);
545 return -EINVAL;
546 }
547
548 if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC &&
549 subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) {
550 dev_err(&csdev->dev, "wrong device subtype in %s\n", function);
551 return -EINVAL;
552 }
553
554 return 0;
555}
556
a06ae860
PP
557int coresight_enable(struct coresight_device *csdev)
558{
a685d683 559 int cpu, ret = 0;
d52c9750 560 struct coresight_device *sink;
b3e94405 561 struct list_head *path;
022aa1a8
SP
562 enum coresight_dev_subtype_source subtype;
563
564 subtype = csdev->subtype.source_subtype;
a06ae860
PP
565
566 mutex_lock(&coresight_mutex);
a685d683
MP
567
568 ret = coresight_validate_source(csdev, __func__);
569 if (ret)
a06ae860 570 goto out;
a685d683 571
022aa1a8
SP
572 if (csdev->enable) {
573 /*
574 * There could be multiple applications driving the software
575 * source. So keep the refcount for each such user when the
576 * source is already enabled.
577 */
578 if (subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE)
579 atomic_inc(csdev->refcnt);
a06ae860 580 goto out;
022aa1a8 581 }
a06ae860 582
d52c9750
MP
583 /*
584 * Search for a valid sink for this session but don't reset the
585 * "enable_sink" flag in sysFS. Users get to do that explicitly.
586 */
587 sink = coresight_get_enabled_sink(false);
588 if (!sink) {
589 ret = -EINVAL;
590 goto out;
591 }
592
593 path = coresight_build_path(csdev, sink);
5014e904 594 if (IS_ERR(path)) {
b3e94405 595 pr_err("building path(s) failed\n");
5014e904 596 ret = PTR_ERR(path);
a06ae860
PP
597 goto out;
598 }
599
e827d455 600 ret = coresight_enable_path(path, CS_MODE_SYSFS);
b3e94405
MP
601 if (ret)
602 goto err_path;
603
22fd532e 604 ret = coresight_enable_source(csdev, CS_MODE_SYSFS);
b3e94405
MP
605 if (ret)
606 goto err_source;
607
022aa1a8 608 switch (subtype) {
a685d683
MP
609 case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
610 /*
611 * When working from sysFS it is important to keep track
612 * of the paths that were created so that they can be
613 * undone in 'coresight_disable()'. Since there can only
614 * be a single session per tracer (when working from sysFS)
615 * a per-cpu variable will do just fine.
616 */
617 cpu = source_ops(csdev)->cpu_id(csdev);
618 per_cpu(tracer_path, cpu) = path;
619 break;
620 case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
621 stm_path = path;
622 break;
623 default:
624 /* We can't be here */
625 break;
626 }
b3e94405 627
a06ae860
PP
628out:
629 mutex_unlock(&coresight_mutex);
630 return ret;
b3e94405
MP
631
632err_source:
633 coresight_disable_path(path);
634
635err_path:
636 coresight_release_path(path);
637 goto out;
a06ae860
PP
638}
639EXPORT_SYMBOL_GPL(coresight_enable);
640
641void coresight_disable(struct coresight_device *csdev)
642{
a685d683
MP
643 int cpu, ret;
644 struct list_head *path = NULL;
a06ae860
PP
645
646 mutex_lock(&coresight_mutex);
a685d683
MP
647
648 ret = coresight_validate_source(csdev, __func__);
649 if (ret)
a06ae860 650 goto out;
a685d683 651
f73f20e1 652 if (!csdev->enable || !coresight_disable_source(csdev))
a06ae860
PP
653 goto out;
654
a685d683
MP
655 switch (csdev->subtype.source_subtype) {
656 case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
657 cpu = source_ops(csdev)->cpu_id(csdev);
658 path = per_cpu(tracer_path, cpu);
659 per_cpu(tracer_path, cpu) = NULL;
660 break;
661 case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
662 path = stm_path;
663 stm_path = NULL;
664 break;
665 default:
666 /* We can't be here */
667 break;
668 }
669
b3e94405
MP
670 coresight_disable_path(path);
671 coresight_release_path(path);
a06ae860
PP
672
673out:
674 mutex_unlock(&coresight_mutex);
675}
676EXPORT_SYMBOL_GPL(coresight_disable);
677
678static ssize_t enable_sink_show(struct device *dev,
679 struct device_attribute *attr, char *buf)
680{
681 struct coresight_device *csdev = to_coresight_device(dev);
682
e8dc27d0 683 return scnprintf(buf, PAGE_SIZE, "%u\n", csdev->activated);
a06ae860
PP
684}
685
686static ssize_t enable_sink_store(struct device *dev,
687 struct device_attribute *attr,
688 const char *buf, size_t size)
689{
690 int ret;
691 unsigned long val;
692 struct coresight_device *csdev = to_coresight_device(dev);
693
694 ret = kstrtoul(buf, 10, &val);
695 if (ret)
696 return ret;
697
698 if (val)
699 csdev->activated = true;
700 else
701 csdev->activated = false;
702
703 return size;
704
705}
706static DEVICE_ATTR_RW(enable_sink);
707
708static ssize_t enable_source_show(struct device *dev,
709 struct device_attribute *attr, char *buf)
710{
711 struct coresight_device *csdev = to_coresight_device(dev);
712
e8dc27d0 713 return scnprintf(buf, PAGE_SIZE, "%u\n", csdev->enable);
a06ae860
PP
714}
715
716static ssize_t enable_source_store(struct device *dev,
717 struct device_attribute *attr,
718 const char *buf, size_t size)
719{
720 int ret = 0;
721 unsigned long val;
722 struct coresight_device *csdev = to_coresight_device(dev);
723
724 ret = kstrtoul(buf, 10, &val);
725 if (ret)
726 return ret;
727
728 if (val) {
729 ret = coresight_enable(csdev);
730 if (ret)
731 return ret;
732 } else {
733 coresight_disable(csdev);
734 }
735
736 return size;
737}
738static DEVICE_ATTR_RW(enable_source);
739
740static struct attribute *coresight_sink_attrs[] = {
741 &dev_attr_enable_sink.attr,
742 NULL,
743};
744ATTRIBUTE_GROUPS(coresight_sink);
745
746static struct attribute *coresight_source_attrs[] = {
747 &dev_attr_enable_source.attr,
748 NULL,
749};
750ATTRIBUTE_GROUPS(coresight_source);
751
752static struct device_type coresight_dev_type[] = {
753 {
754 .name = "none",
755 },
756 {
757 .name = "sink",
758 .groups = coresight_sink_groups,
759 },
760 {
761 .name = "link",
762 },
763 {
764 .name = "linksink",
765 .groups = coresight_sink_groups,
766 },
767 {
768 .name = "source",
769 .groups = coresight_source_groups,
770 },
771};
772
773static void coresight_device_release(struct device *dev)
774{
775 struct coresight_device *csdev = to_coresight_device(dev);
776
fae54158
MP
777 kfree(csdev->conns);
778 kfree(csdev->refcnt);
a06ae860
PP
779 kfree(csdev);
780}
781
782static int coresight_orphan_match(struct device *dev, void *data)
783{
784 int i;
785 bool still_orphan = false;
786 struct coresight_device *csdev, *i_csdev;
787 struct coresight_connection *conn;
788
789 csdev = data;
790 i_csdev = to_coresight_device(dev);
791
792 /* No need to check oneself */
793 if (csdev == i_csdev)
794 return 0;
795
796 /* Move on to another component if no connection is orphan */
797 if (!i_csdev->orphan)
798 return 0;
799 /*
800 * Circle throuch all the connection of that component. If we find
801 * an orphan connection whose name matches @csdev, link it.
802 */
d786a47d 803 for (i = 0; i < i_csdev->nr_outport; i++) {
a06ae860
PP
804 conn = &i_csdev->conns[i];
805
806 /* We have found at least one orphan connection */
807 if (conn->child_dev == NULL) {
808 /* Does it match this newly added device? */
b8392153
SH
809 if (conn->child_name &&
810 !strcmp(dev_name(&csdev->dev), conn->child_name)) {
a06ae860 811 conn->child_dev = csdev;
22394bc5
KX
812 } else {
813 /* This component still has an orphan */
814 still_orphan = true;
815 }
a06ae860
PP
816 }
817 }
818
819 i_csdev->orphan = still_orphan;
820
821 /*
822 * Returning '0' ensures that all known component on the
823 * bus will be checked.
824 */
825 return 0;
826}
827
828static void coresight_fixup_orphan_conns(struct coresight_device *csdev)
829{
830 /*
831 * No need to check for a return value as orphan connection(s)
832 * are hooked-up with each newly added component.
833 */
834 bus_for_each_dev(&coresight_bustype, NULL,
ff874227 835 csdev, coresight_orphan_match);
a06ae860
PP
836}
837
838
a06ae860
PP
839static void coresight_fixup_device_conns(struct coresight_device *csdev)
840{
841 int i;
a06ae860
PP
842
843 for (i = 0; i < csdev->nr_outport; i++) {
26cf91f4
LW
844 struct coresight_connection *conn = &csdev->conns[i];
845 struct device *dev = NULL;
a06ae860 846
26cf91f4
LW
847 if (conn->child_name)
848 dev = bus_find_device_by_name(&coresight_bustype, NULL,
849 conn->child_name);
a06ae860
PP
850 if (dev) {
851 conn->child_dev = to_coresight_device(dev);
f2dfab35
MP
852 /* and put reference from 'bus_find_device()' */
853 put_device(dev);
a06ae860
PP
854 } else {
855 csdev->orphan = true;
856 conn->child_dev = NULL;
857 }
858 }
859}
860
ad725aee
MP
861static int coresight_remove_match(struct device *dev, void *data)
862{
863 int i;
864 struct coresight_device *csdev, *iterator;
865 struct coresight_connection *conn;
866
867 csdev = data;
868 iterator = to_coresight_device(dev);
869
870 /* No need to check oneself */
871 if (csdev == iterator)
872 return 0;
873
874 /*
875 * Circle throuch all the connection of that component. If we find
876 * a connection whose name matches @csdev, remove it.
877 */
878 for (i = 0; i < iterator->nr_outport; i++) {
879 conn = &iterator->conns[i];
880
881 if (conn->child_dev == NULL)
882 continue;
883
884 if (!strcmp(dev_name(&csdev->dev), conn->child_name)) {
885 iterator->orphan = true;
886 conn->child_dev = NULL;
887 /* No need to continue */
888 break;
889 }
890 }
891
892 /*
893 * Returning '0' ensures that all known component on the
894 * bus will be checked.
895 */
896 return 0;
897}
898
899static void coresight_remove_conns(struct coresight_device *csdev)
900{
901 bus_for_each_dev(&coresight_bustype, NULL,
902 csdev, coresight_remove_match);
903}
904
a06ae860
PP
905/**
906 * coresight_timeout - loop until a bit has changed to a specific state.
907 * @addr: base address of the area of interest.
908 * @offset: address of a register, starting from @addr.
909 * @position: the position of the bit of interest.
910 * @value: the value the bit should have.
911 *
912 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
913 * TIMEOUT_US has elapsed, which ever happens first.
914 */
915
916int coresight_timeout(void __iomem *addr, u32 offset, int position, int value)
917{
918 int i;
919 u32 val;
920
921 for (i = TIMEOUT_US; i > 0; i--) {
922 val = __raw_readl(addr + offset);
923 /* waiting on the bit to go from 0 to 1 */
924 if (value) {
925 if (val & BIT(position))
926 return 0;
927 /* waiting on the bit to go from 1 to 0 */
928 } else {
929 if (!(val & BIT(position)))
930 return 0;
931 }
932
933 /*
934 * Delay is arbitrary - the specification doesn't say how long
935 * we are expected to wait. Extra check required to make sure
936 * we don't wait needlessly on the last iteration.
937 */
938 if (i - 1)
939 udelay(1);
940 }
941
942 return -EAGAIN;
943}
944
945struct bus_type coresight_bustype = {
946 .name = "coresight",
947};
948
949static int __init coresight_init(void)
950{
951 return bus_register(&coresight_bustype);
952}
953postcore_initcall(coresight_init);
954
955struct coresight_device *coresight_register(struct coresight_desc *desc)
956{
957 int i;
958 int ret;
959 int link_subtype;
960 int nr_refcnts = 1;
961 atomic_t *refcnts = NULL;
962 struct coresight_device *csdev;
068c0a54 963 struct coresight_connection *conns = NULL;
a06ae860
PP
964
965 csdev = kzalloc(sizeof(*csdev), GFP_KERNEL);
966 if (!csdev) {
967 ret = -ENOMEM;
968 goto err_kzalloc_csdev;
969 }
970
971 if (desc->type == CORESIGHT_DEV_TYPE_LINK ||
972 desc->type == CORESIGHT_DEV_TYPE_LINKSINK) {
973 link_subtype = desc->subtype.link_subtype;
974
975 if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG)
976 nr_refcnts = desc->pdata->nr_inport;
977 else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT)
978 nr_refcnts = desc->pdata->nr_outport;
979 }
980
981 refcnts = kcalloc(nr_refcnts, sizeof(*refcnts), GFP_KERNEL);
982 if (!refcnts) {
983 ret = -ENOMEM;
984 goto err_kzalloc_refcnts;
985 }
986
987 csdev->refcnt = refcnts;
988
989 csdev->nr_inport = desc->pdata->nr_inport;
990 csdev->nr_outport = desc->pdata->nr_outport;
a06ae860 991
068c0a54
SP
992 /* Initialise connections if there is at least one outport */
993 if (csdev->nr_outport) {
994 conns = kcalloc(csdev->nr_outport, sizeof(*conns), GFP_KERNEL);
995 if (!conns) {
996 ret = -ENOMEM;
997 goto err_kzalloc_conns;
998 }
999
1000 for (i = 0; i < csdev->nr_outport; i++) {
1001 conns[i].outport = desc->pdata->outports[i];
1002 conns[i].child_name = desc->pdata->child_names[i];
1003 conns[i].child_port = desc->pdata->child_ports[i];
1004 }
a06ae860
PP
1005 }
1006
1007 csdev->conns = conns;
1008
1009 csdev->type = desc->type;
1010 csdev->subtype = desc->subtype;
1011 csdev->ops = desc->ops;
1012 csdev->orphan = false;
1013
1014 csdev->dev.type = &coresight_dev_type[desc->type];
1015 csdev->dev.groups = desc->groups;
1016 csdev->dev.parent = desc->dev;
1017 csdev->dev.release = coresight_device_release;
1018 csdev->dev.bus = &coresight_bustype;
1019 dev_set_name(&csdev->dev, "%s", desc->pdata->name);
1020
1021 ret = device_register(&csdev->dev);
a7082daa
AY
1022 if (ret) {
1023 put_device(&csdev->dev);
1024 goto err_kzalloc_csdev;
1025 }
a06ae860
PP
1026
1027 mutex_lock(&coresight_mutex);
1028
1029 coresight_fixup_device_conns(csdev);
1030 coresight_fixup_orphan_conns(csdev);
1031
1032 mutex_unlock(&coresight_mutex);
1033
1034 return csdev;
1035
a06ae860
PP
1036err_kzalloc_conns:
1037 kfree(refcnts);
1038err_kzalloc_refcnts:
1039 kfree(csdev);
1040err_kzalloc_csdev:
1041 return ERR_PTR(ret);
1042}
1043EXPORT_SYMBOL_GPL(coresight_register);
1044
1045void coresight_unregister(struct coresight_device *csdev)
1046{
ad725aee
MP
1047 /* Remove references of that device in the topology */
1048 coresight_remove_conns(csdev);
a06ae860 1049 device_unregister(&csdev->dev);
a06ae860
PP
1050}
1051EXPORT_SYMBOL_GPL(coresight_unregister);