Commit | Line | Data |
---|---|---|
bc4bf7fe | 1 | /* Copyright (c) 2012, The Linux Foundation. All rights reserved. |
941943cf PG |
2 | * |
3 | * Description: CoreSight Trace Memory Controller driver | |
bc4bf7fe PP |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 and | |
7 | * only version 2 as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
bc4bf7fe PP |
16 | #include <linux/init.h> |
17 | #include <linux/types.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/fs.h> | |
22 | #include <linux/miscdevice.h> | |
23 | #include <linux/uaccess.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/spinlock.h> | |
32398ef6 | 27 | #include <linux/pm_runtime.h> |
bc4bf7fe PP |
28 | #include <linux/of.h> |
29 | #include <linux/coresight.h> | |
30 | #include <linux/amba/bus.h> | |
31 | ||
32 | #include "coresight-priv.h" | |
4c324b5f | 33 | #include "coresight-tmc.h" |
bc4bf7fe | 34 | |
6c6ed1e2 | 35 | void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) |
bc4bf7fe PP |
36 | { |
37 | /* Ensure formatter, unformatter and hardware fifo are empty */ | |
38 | if (coresight_timeout(drvdata->base, | |
580ff804 | 39 | TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { |
bc4bf7fe PP |
40 | dev_err(drvdata->dev, |
41 | "timeout observed when probing at offset %#x\n", | |
42 | TMC_STS); | |
43 | } | |
44 | } | |
45 | ||
6c6ed1e2 | 46 | void tmc_flush_and_stop(struct tmc_drvdata *drvdata) |
bc4bf7fe PP |
47 | { |
48 | u32 ffcr; | |
49 | ||
50 | ffcr = readl_relaxed(drvdata->base + TMC_FFCR); | |
51 | ffcr |= TMC_FFCR_STOP_ON_FLUSH; | |
52 | writel_relaxed(ffcr, drvdata->base + TMC_FFCR); | |
a8ab4268 | 53 | ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); |
bc4bf7fe PP |
54 | writel_relaxed(ffcr, drvdata->base + TMC_FFCR); |
55 | /* Ensure flush completes */ | |
56 | if (coresight_timeout(drvdata->base, | |
57 | TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { | |
58 | dev_err(drvdata->dev, | |
59 | "timeout observed when probing at offset %#x\n", | |
60 | TMC_FFCR); | |
61 | } | |
62 | ||
580ff804 | 63 | tmc_wait_for_tmcready(drvdata); |
bc4bf7fe PP |
64 | } |
65 | ||
6c6ed1e2 | 66 | void tmc_enable_hw(struct tmc_drvdata *drvdata) |
bc4bf7fe PP |
67 | { |
68 | writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); | |
69 | } | |
70 | ||
6c6ed1e2 | 71 | void tmc_disable_hw(struct tmc_drvdata *drvdata) |
bc4bf7fe PP |
72 | { |
73 | writel_relaxed(0x0, drvdata->base + TMC_CTL); | |
74 | } | |
75 | ||
bc4bf7fe PP |
76 | static int tmc_read_prepare(struct tmc_drvdata *drvdata) |
77 | { | |
b1789b79 | 78 | int ret = 0; |
bc4bf7fe | 79 | |
b1789b79 MP |
80 | switch (drvdata->config_type) { |
81 | case TMC_CONFIG_TYPE_ETB: | |
b1789b79 | 82 | case TMC_CONFIG_TYPE_ETF: |
4525412a | 83 | ret = tmc_read_prepare_etb(drvdata); |
b1789b79 MP |
84 | break; |
85 | case TMC_CONFIG_TYPE_ETR: | |
4525412a | 86 | ret = tmc_read_prepare_etr(drvdata); |
b1789b79 MP |
87 | break; |
88 | default: | |
89 | ret = -EINVAL; | |
bc4bf7fe | 90 | } |
b1789b79 | 91 | |
4525412a MP |
92 | if (!ret) |
93 | dev_info(drvdata->dev, "TMC read start\n"); | |
94 | ||
bc4bf7fe PP |
95 | return ret; |
96 | } | |
97 | ||
f74debbe | 98 | static int tmc_read_unprepare(struct tmc_drvdata *drvdata) |
bc4bf7fe | 99 | { |
4525412a | 100 | int ret = 0; |
bc4bf7fe | 101 | |
b1789b79 MP |
102 | switch (drvdata->config_type) { |
103 | case TMC_CONFIG_TYPE_ETB: | |
b1789b79 | 104 | case TMC_CONFIG_TYPE_ETF: |
4525412a | 105 | ret = tmc_read_unprepare_etb(drvdata); |
b1789b79 MP |
106 | break; |
107 | case TMC_CONFIG_TYPE_ETR: | |
4525412a | 108 | ret = tmc_read_unprepare_etr(drvdata); |
b1789b79 MP |
109 | break; |
110 | default: | |
4525412a | 111 | ret = -EINVAL; |
bc4bf7fe | 112 | } |
b1789b79 | 113 | |
4525412a MP |
114 | if (!ret) |
115 | dev_info(drvdata->dev, "TMC read end\n"); | |
f74debbe MP |
116 | |
117 | return ret; | |
bc4bf7fe PP |
118 | } |
119 | ||
120 | static int tmc_open(struct inode *inode, struct file *file) | |
121 | { | |
f74debbe | 122 | int ret; |
bc4bf7fe PP |
123 | struct tmc_drvdata *drvdata = container_of(file->private_data, |
124 | struct tmc_drvdata, miscdev); | |
bc4bf7fe PP |
125 | |
126 | ret = tmc_read_prepare(drvdata); | |
127 | if (ret) | |
128 | return ret; | |
f74debbe | 129 | |
bc4bf7fe PP |
130 | nonseekable_open(inode, file); |
131 | ||
132 | dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__); | |
133 | return 0; | |
134 | } | |
135 | ||
136 | static ssize_t tmc_read(struct file *file, char __user *data, size_t len, | |
137 | loff_t *ppos) | |
138 | { | |
139 | struct tmc_drvdata *drvdata = container_of(file->private_data, | |
140 | struct tmc_drvdata, miscdev); | |
141 | char *bufp = drvdata->buf + *ppos; | |
142 | ||
8505feae SP |
143 | if (*ppos + len > drvdata->len) |
144 | len = drvdata->len - *ppos; | |
bc4bf7fe PP |
145 | |
146 | if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { | |
147 | if (bufp == (char *)(drvdata->vaddr + drvdata->size)) | |
148 | bufp = drvdata->vaddr; | |
149 | else if (bufp > (char *)(drvdata->vaddr + drvdata->size)) | |
150 | bufp -= drvdata->size; | |
151 | if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size)) | |
152 | len = (char *)(drvdata->vaddr + drvdata->size) - bufp; | |
153 | } | |
154 | ||
155 | if (copy_to_user(data, bufp, len)) { | |
156 | dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__); | |
157 | return -EFAULT; | |
158 | } | |
159 | ||
160 | *ppos += len; | |
161 | ||
72f641fe | 162 | dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n", |
8505feae | 163 | __func__, len, (int)(drvdata->len - *ppos)); |
bc4bf7fe PP |
164 | return len; |
165 | } | |
166 | ||
167 | static int tmc_release(struct inode *inode, struct file *file) | |
168 | { | |
f74debbe | 169 | int ret; |
bc4bf7fe PP |
170 | struct tmc_drvdata *drvdata = container_of(file->private_data, |
171 | struct tmc_drvdata, miscdev); | |
172 | ||
f74debbe MP |
173 | ret = tmc_read_unprepare(drvdata); |
174 | if (ret) | |
175 | return ret; | |
bc4bf7fe | 176 | |
bc4bf7fe PP |
177 | dev_dbg(drvdata->dev, "%s: released\n", __func__); |
178 | return 0; | |
179 | } | |
180 | ||
181 | static const struct file_operations tmc_fops = { | |
182 | .owner = THIS_MODULE, | |
183 | .open = tmc_open, | |
184 | .read = tmc_read, | |
185 | .release = tmc_release, | |
186 | .llseek = no_llseek, | |
187 | }; | |
188 | ||
4f1ff3de MP |
189 | static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid) |
190 | { | |
191 | enum tmc_mem_intf_width memwidth; | |
192 | ||
193 | /* | |
194 | * Excerpt from the TRM: | |
195 | * | |
196 | * DEVID::MEMWIDTH[10:8] | |
197 | * 0x2 Memory interface databus is 32 bits wide. | |
198 | * 0x3 Memory interface databus is 64 bits wide. | |
199 | * 0x4 Memory interface databus is 128 bits wide. | |
200 | * 0x5 Memory interface databus is 256 bits wide. | |
201 | */ | |
202 | switch (BMVAL(devid, 8, 10)) { | |
203 | case 0x2: | |
204 | memwidth = TMC_MEM_INTF_WIDTH_32BITS; | |
205 | break; | |
206 | case 0x3: | |
207 | memwidth = TMC_MEM_INTF_WIDTH_64BITS; | |
208 | break; | |
209 | case 0x4: | |
210 | memwidth = TMC_MEM_INTF_WIDTH_128BITS; | |
211 | break; | |
212 | case 0x5: | |
213 | memwidth = TMC_MEM_INTF_WIDTH_256BITS; | |
214 | break; | |
215 | default: | |
216 | memwidth = 0; | |
217 | } | |
218 | ||
219 | return memwidth; | |
220 | } | |
221 | ||
7d83d177 MP |
222 | #define coresight_tmc_simple_func(name, offset) \ |
223 | coresight_simple_func(struct tmc_drvdata, name, offset) | |
224 | ||
225 | coresight_tmc_simple_func(rsz, TMC_RSZ); | |
226 | coresight_tmc_simple_func(sts, TMC_STS); | |
227 | coresight_tmc_simple_func(rrp, TMC_RRP); | |
228 | coresight_tmc_simple_func(rwp, TMC_RWP); | |
229 | coresight_tmc_simple_func(trg, TMC_TRG); | |
230 | coresight_tmc_simple_func(ctl, TMC_CTL); | |
231 | coresight_tmc_simple_func(ffsr, TMC_FFSR); | |
232 | coresight_tmc_simple_func(ffcr, TMC_FFCR); | |
233 | coresight_tmc_simple_func(mode, TMC_MODE); | |
234 | coresight_tmc_simple_func(pscr, TMC_PSCR); | |
235 | coresight_tmc_simple_func(devid, CORESIGHT_DEVID); | |
236 | ||
237 | static struct attribute *coresight_tmc_mgmt_attrs[] = { | |
238 | &dev_attr_rsz.attr, | |
239 | &dev_attr_sts.attr, | |
240 | &dev_attr_rrp.attr, | |
241 | &dev_attr_rwp.attr, | |
242 | &dev_attr_trg.attr, | |
243 | &dev_attr_ctl.attr, | |
244 | &dev_attr_ffsr.attr, | |
245 | &dev_attr_ffcr.attr, | |
246 | &dev_attr_mode.attr, | |
247 | &dev_attr_pscr.attr, | |
248 | &dev_attr_devid.attr, | |
249 | NULL, | |
250 | }; | |
a2d6e184 | 251 | |
7d83d177 MP |
252 | ssize_t trigger_cntr_show(struct device *dev, |
253 | struct device_attribute *attr, char *buf) | |
bc4bf7fe PP |
254 | { |
255 | struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); | |
256 | unsigned long val = drvdata->trigger_cntr; | |
257 | ||
258 | return sprintf(buf, "%#lx\n", val); | |
259 | } | |
260 | ||
261 | static ssize_t trigger_cntr_store(struct device *dev, | |
262 | struct device_attribute *attr, | |
263 | const char *buf, size_t size) | |
264 | { | |
265 | int ret; | |
266 | unsigned long val; | |
267 | struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); | |
268 | ||
269 | ret = kstrtoul(buf, 16, &val); | |
270 | if (ret) | |
271 | return ret; | |
272 | ||
273 | drvdata->trigger_cntr = val; | |
274 | return size; | |
275 | } | |
276 | static DEVICE_ATTR_RW(trigger_cntr); | |
277 | ||
7d83d177 | 278 | static struct attribute *coresight_tmc_attrs[] = { |
bc4bf7fe PP |
279 | &dev_attr_trigger_cntr.attr, |
280 | NULL, | |
281 | }; | |
bc4bf7fe | 282 | |
7d83d177 MP |
283 | static const struct attribute_group coresight_tmc_group = { |
284 | .attrs = coresight_tmc_attrs, | |
bc4bf7fe | 285 | }; |
bc4bf7fe | 286 | |
7d83d177 MP |
287 | static const struct attribute_group coresight_tmc_mgmt_group = { |
288 | .attrs = coresight_tmc_mgmt_attrs, | |
289 | .name = "mgmt", | |
290 | }; | |
291 | ||
292 | const struct attribute_group *coresight_tmc_groups[] = { | |
293 | &coresight_tmc_group, | |
294 | &coresight_tmc_mgmt_group, | |
bc4bf7fe PP |
295 | NULL, |
296 | }; | |
bc4bf7fe PP |
297 | |
298 | static int tmc_probe(struct amba_device *adev, const struct amba_id *id) | |
299 | { | |
300 | int ret = 0; | |
301 | u32 devid; | |
302 | void __iomem *base; | |
303 | struct device *dev = &adev->dev; | |
304 | struct coresight_platform_data *pdata = NULL; | |
305 | struct tmc_drvdata *drvdata; | |
306 | struct resource *res = &adev->res; | |
307 | struct coresight_desc *desc; | |
308 | struct device_node *np = adev->dev.of_node; | |
309 | ||
310 | if (np) { | |
311 | pdata = of_get_coresight_platform_data(dev, np); | |
3afd0634 SP |
312 | if (IS_ERR(pdata)) { |
313 | ret = PTR_ERR(pdata); | |
314 | goto out; | |
315 | } | |
bc4bf7fe PP |
316 | adev->dev.platform_data = pdata; |
317 | } | |
318 | ||
3afd0634 | 319 | ret = -ENOMEM; |
bc4bf7fe PP |
320 | drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); |
321 | if (!drvdata) | |
3afd0634 SP |
322 | goto out; |
323 | ||
324 | desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); | |
325 | if (!desc) | |
326 | goto out; | |
bc4bf7fe PP |
327 | |
328 | drvdata->dev = &adev->dev; | |
329 | dev_set_drvdata(dev, drvdata); | |
330 | ||
331 | /* Validity for the resource is already checked by the AMBA core */ | |
332 | base = devm_ioremap_resource(dev, res); | |
3afd0634 SP |
333 | if (IS_ERR(base)) { |
334 | ret = PTR_ERR(base); | |
335 | goto out; | |
336 | } | |
bc4bf7fe PP |
337 | |
338 | drvdata->base = base; | |
339 | ||
340 | spin_lock_init(&drvdata->spinlock); | |
341 | ||
bc4bf7fe PP |
342 | devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); |
343 | drvdata->config_type = BMVAL(devid, 6, 7); | |
4f1ff3de | 344 | drvdata->memwidth = tmc_get_memwidth(devid); |
bc4bf7fe PP |
345 | |
346 | if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { | |
347 | if (np) | |
348 | ret = of_property_read_u32(np, | |
349 | "arm,buffer-size", | |
350 | &drvdata->size); | |
351 | if (ret) | |
352 | drvdata->size = SZ_1M; | |
353 | } else { | |
354 | drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; | |
355 | } | |
356 | ||
32398ef6 | 357 | pm_runtime_put(&adev->dev); |
bc4bf7fe | 358 | |
bc4bf7fe PP |
359 | desc->pdata = pdata; |
360 | desc->dev = dev; | |
361 | desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; | |
7d83d177 | 362 | desc->groups = coresight_tmc_groups; |
bc4bf7fe PP |
363 | |
364 | if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) { | |
365 | desc->type = CORESIGHT_DEV_TYPE_SINK; | |
366 | desc->ops = &tmc_etb_cs_ops; | |
bc4bf7fe PP |
367 | } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { |
368 | desc->type = CORESIGHT_DEV_TYPE_SINK; | |
369 | desc->ops = &tmc_etr_cs_ops; | |
bc4bf7fe PP |
370 | } else { |
371 | desc->type = CORESIGHT_DEV_TYPE_LINKSINK; | |
372 | desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; | |
373 | desc->ops = &tmc_etf_cs_ops; | |
bc4bf7fe PP |
374 | } |
375 | ||
376 | drvdata->csdev = coresight_register(desc); | |
377 | if (IS_ERR(drvdata->csdev)) { | |
378 | ret = PTR_ERR(drvdata->csdev); | |
3afd0634 | 379 | goto out; |
bc4bf7fe PP |
380 | } |
381 | ||
382 | drvdata->miscdev.name = pdata->name; | |
383 | drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; | |
384 | drvdata->miscdev.fops = &tmc_fops; | |
385 | ret = misc_register(&drvdata->miscdev); | |
386 | if (ret) | |
3afd0634 SP |
387 | coresight_unregister(drvdata->csdev); |
388 | out: | |
bc4bf7fe PP |
389 | return ret; |
390 | } | |
391 | ||
bc4bf7fe PP |
392 | static struct amba_id tmc_ids[] = { |
393 | { | |
394 | .id = 0x0003b961, | |
395 | .mask = 0x0003ffff, | |
396 | }, | |
397 | { 0, 0}, | |
398 | }; | |
399 | ||
400 | static struct amba_driver tmc_driver = { | |
401 | .drv = { | |
402 | .name = "coresight-tmc", | |
403 | .owner = THIS_MODULE, | |
b15f0fb6 | 404 | .suppress_bind_attrs = true, |
bc4bf7fe PP |
405 | }, |
406 | .probe = tmc_probe, | |
bc4bf7fe PP |
407 | .id_table = tmc_ids, |
408 | }; | |
941943cf | 409 | builtin_amba_driver(tmc_driver); |