[linux-2.6-block.git] / drivers / hwspinlock / u8500_hsem.c

// SPDX-License-Identifier: GPL-2.0
/*
 * u8500 HWSEM driver
 *
 * Copyright (C) 2010-2011 ST-Ericsson
 *
 * Implements u8500 semaphore handling for protocol 1, no interrupts.
 *
 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
 * Heavily borrowed from the work of :
 *   Simon Que <sque@ti.com>
 *   Hari Kanigeri <h-kanigeri2@ti.com>
 *   Ohad Ben-Cohen <ohad@wizery.com>
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/hwspinlock.h>
#include <linux/platform_device.h>

#include "hwspinlock_internal.h"

/*
 * Implementation of STE's HSem protocol 1 without interrutps.
 * The only masterID we allow is '0x01' to force people to use
 * HSems for synchronisation between processors rather than processes
 * on the ARM core.
 */

#define U8500_MAX_SEMAPHORE		32	/* a total of 32 semaphore */
#define RESET_SEMAPHORE			(0)	/* free */

/*
 * CPU ID for master running u8500 kernel.
 * Hswpinlocks should only be used to synchonise operations
 * between the Cortex A9 core and the other CPUs.  Hence
 * forcing the masterID to a preset value.
 */
#define HSEM_MASTER_ID			0x01

#define HSEM_REGISTER_OFFSET		0x08

#define HSEM_CTRL_REG			0x00
#define HSEM_ICRALL			0x90
#define HSEM_PROTOCOL_1			0x01

static int u8500_hsem_trylock(struct hwspinlock *lock)
{
	void __iomem *lock_addr = lock->priv;

	writel(HSEM_MASTER_ID, lock_addr);

	/* get only first 4 bit and compare to masterID.
	 * if equal, we have the semaphore, otherwise
	 * someone else has it.
	 */
	return (HSEM_MASTER_ID == (0x0F & readl(lock_addr)));
}

static void u8500_hsem_unlock(struct hwspinlock *lock)
{
	void __iomem *lock_addr = lock->priv;

	/* release the lock by writing 0 to it */
	writel(RESET_SEMAPHORE, lock_addr);
}

/*
 * u8500: what value is recommended here ?
 */
static void u8500_hsem_relax(struct hwspinlock *lock)
{
	ndelay(50);
}

static const struct hwspinlock_ops u8500_hwspinlock_ops = {
	.trylock	= u8500_hsem_trylock,
	.unlock		= u8500_hsem_unlock,
	.relax		= u8500_hsem_relax,
};

static int u8500_hsem_probe(struct platform_device *pdev)
{
	struct hwspinlock_pdata *pdata = pdev->dev.platform_data;
	struct hwspinlock_device *bank;
	struct hwspinlock *hwlock;
	void __iomem *io_base;
	int i, num_locks = U8500_MAX_SEMAPHORE;
	ulong val;

	if (!pdata)
		return -ENODEV;

	io_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(io_base))
		return PTR_ERR(io_base);

	/* make sure protocol 1 is selected */
	val = readl(io_base + HSEM_CTRL_REG);
	writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG);

	/* clear all interrupts */
	writel(0xFFFF, io_base + HSEM_ICRALL);

	bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
			    GFP_KERNEL);
	if (!bank)
		return -ENOMEM;

	platform_set_drvdata(pdev, bank);

	for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)
		hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i;

	return devm_hwspin_lock_register(&pdev->dev, bank,
					 &u8500_hwspinlock_ops,
					 pdata->base_id, num_locks);
}

static void u8500_hsem_remove(struct platform_device *pdev)
{
	struct hwspinlock_device *bank = platform_get_drvdata(pdev);
	void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET;

	/* clear all interrupts */
	writel(0xFFFF, io_base + HSEM_ICRALL);
}

static struct platform_driver u8500_hsem_driver = {
	.probe		= u8500_hsem_probe,
	.remove_new	= u8500_hsem_remove,
	.driver		= {
		.name	= "u8500_hsem",
	},
};

static int __init u8500_hsem_init(void)
{
	return platform_driver_register(&u8500_hsem_driver);
}
/* board init code might need to reserve hwspinlocks for predefined purposes */
postcore_initcall(u8500_hsem_init);

static void __exit u8500_hsem_exit(void)
{
	platform_driver_unregister(&u8500_hsem_driver);
}
module_exit(u8500_hsem_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Hardware Spinlock driver for u8500");
MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
Commit	Line	Data
e759176c	1	// SPDX-License-Identifier: GPL-2.0
f84a8ecf MP	2	/*
	3	* u8500 HWSEM driver
	4	*
	5	* Copyright (C) 2010-2011 ST-Ericsson
	6	*
	7	* Implements u8500 semaphore handling for protocol 1, no interrupts.
	8	*
	9	* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
	10	* Heavily borrowed from the work of :
	11	* Simon Que <sque@ti.com>
	12	* Hari Kanigeri <h-kanigeri2@ti.com>
	13	* Ohad Ben-Cohen <ohad@wizery.com>
f84a8ecf MP	14	*/
f84a8ecf MP	15
8f7346bd	16	#include <linux/module.h>
f84a8ecf MP	17	#include <linux/delay.h>
f84a8ecf MP	18	#include <linux/io.h>
f84a8ecf MP	19	#include <linux/slab.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/hwspinlock.h>
	22	#include <linux/platform_device.h>
	23
	24	#include "hwspinlock_internal.h"
	25
	26	/*
	27	* Implementation of STE's HSem protocol 1 without interrutps.
	28	* The only masterID we allow is '0x01' to force people to use
	29	* HSems for synchronisation between processors rather than processes
	30	* on the ARM core.
	31	*/
	32
	33	#define U8500_MAX_SEMAPHORE 32 /* a total of 32 semaphore */
	34	#define RESET_SEMAPHORE (0) /* free */
	35
	36	/*
	37	* CPU ID for master running u8500 kernel.
	38	* Hswpinlocks should only be used to synchonise operations
	39	* between the Cortex A9 core and the other CPUs. Hence
	40	* forcing the masterID to a preset value.
	41	*/
	42	#define HSEM_MASTER_ID 0x01
	43
	44	#define HSEM_REGISTER_OFFSET 0x08
	45
	46	#define HSEM_CTRL_REG 0x00
	47	#define HSEM_ICRALL 0x90
	48	#define HSEM_PROTOCOL_1 0x01
	49
	50	static int u8500_hsem_trylock(struct hwspinlock *lock)
	51	{
	52	void __iomem *lock_addr = lock->priv;
	53
	54	writel(HSEM_MASTER_ID, lock_addr);
	55
	56	/* get only first 4 bit and compare to masterID.
	57	* if equal, we have the semaphore, otherwise
	58	* someone else has it.
	59	*/
	60	return (HSEM_MASTER_ID == (0x0F & readl(lock_addr)));
	61	}
	62
	63	static void u8500_hsem_unlock(struct hwspinlock *lock)
	64	{
	65	void __iomem *lock_addr = lock->priv;
	66
	67	/* release the lock by writing 0 to it */
	68	writel(RESET_SEMAPHORE, lock_addr);
	69	}
	70
	71	/*
	72	* u8500: what value is recommended here ?
	73	*/
	74	static void u8500_hsem_relax(struct hwspinlock *lock)
	75	{
	76	ndelay(50);
	77	}
	78
	79	static const struct hwspinlock_ops u8500_hwspinlock_ops = {
	80	.trylock = u8500_hsem_trylock,
	81	.unlock = u8500_hsem_unlock,
	82	.relax = u8500_hsem_relax,
83	};
84
57129106	85	static int u8500_hsem_probe(struct platform_device *pdev)
f84a8ecf MP	86	{
	87	struct hwspinlock_pdata *pdata = pdev->dev.platform_data;
	88	struct hwspinlock_device *bank;
	89	struct hwspinlock *hwlock;
f84a8ecf	90	void __iomem *io_base;
9d399f0c	91	int i, num_locks = U8500_MAX_SEMAPHORE;
f84a8ecf MP	92	ulong val;
	93
	94	if (!pdata)
	95	return -ENODEV;
	96
5ee45e0c BW	97	io_base = devm_platform_ioremap_resource(pdev, 0);
	98	if (IS_ERR(io_base))
	99	return PTR_ERR(io_base);
f84a8ecf MP	100
	101	/* make sure protocol 1 is selected */
	102	val = readl(io_base + HSEM_CTRL_REG);
	103	writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG);
	104
	105	/* clear all interrupts */
	106	writel(0xFFFF, io_base + HSEM_ICRALL);
	107
637bcd19 BW	108	bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
637bcd19 BW	109	GFP_KERNEL);
5ee45e0c BW	110	if (!bank)
5ee45e0c BW	111	return -ENOMEM;
f84a8ecf MP	112
	113	platform_set_drvdata(pdev, bank);
	114
	115	for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)
	116	hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i;
	117
9d399f0c BW	118	return devm_hwspin_lock_register(&pdev->dev, bank,
	119	&u8500_hwspinlock_ops,
	120	pdata->base_id, num_locks);
f84a8ecf MP	121	}
f84a8ecf MP	122
9519793b	123	static void u8500_hsem_remove(struct platform_device *pdev)
f84a8ecf MP	124	{
	125	struct hwspinlock_device *bank = platform_get_drvdata(pdev);
	126	void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET;
f84a8ecf MP	127
	128	/* clear all interrupts */
	129	writel(0xFFFF, io_base + HSEM_ICRALL);
f84a8ecf MP	130	}
	131
	132	static struct platform_driver u8500_hsem_driver = {
	133	.probe = u8500_hsem_probe,
9519793b	134	.remove_new = u8500_hsem_remove,
f84a8ecf MP	135	.driver = {
f84a8ecf MP	136	.name = "u8500_hsem",
f84a8ecf MP	137	},
	138	};
	139
	140	static int __init u8500_hsem_init(void)
	141	{
	142	return platform_driver_register(&u8500_hsem_driver);
	143	}
	144	/* board init code might need to reserve hwspinlocks for predefined purposes */
	145	postcore_initcall(u8500_hsem_init);
	146
	147	static void __exit u8500_hsem_exit(void)
	148	{
	149	platform_driver_unregister(&u8500_hsem_driver);
	150	}
	151	module_exit(u8500_hsem_exit);
	152
	153	MODULE_LICENSE("GPL v2");
	154	MODULE_DESCRIPTION("Hardware Spinlock driver for u8500");
	155	MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");