[linux-2.6-block.git] / drivers / hwspinlock / stm32_hwspinlock.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) STMicroelectronics SA 2018
 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/hwspinlock.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

#include "hwspinlock_internal.h"

#define STM32_MUTEX_COREID	BIT(8)
#define STM32_MUTEX_LOCK_BIT	BIT(31)
#define STM32_MUTEX_NUM_LOCKS	32

struct stm32_hwspinlock {
	struct clk *clk;
	struct hwspinlock_device bank;
};

static int stm32_hwspinlock_trylock(struct hwspinlock *lock)
{
	void __iomem *lock_addr = lock->priv;
	u32 status;

	writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr);
	status = readl(lock_addr);

	return status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID);
}

static void stm32_hwspinlock_unlock(struct hwspinlock *lock)
{
	void __iomem *lock_addr = lock->priv;

	writel(STM32_MUTEX_COREID, lock_addr);
}

static void stm32_hwspinlock_relax(struct hwspinlock *lock)
{
	ndelay(50);
}

static const struct hwspinlock_ops stm32_hwspinlock_ops = {
	.trylock	= stm32_hwspinlock_trylock,
	.unlock		= stm32_hwspinlock_unlock,
	.relax		= stm32_hwspinlock_relax,
};

static void stm32_hwspinlock_disable_clk(void *data)
{
	struct platform_device *pdev = data;
	struct stm32_hwspinlock *hw = platform_get_drvdata(pdev);
	struct device *dev = &pdev->dev;

	pm_runtime_get_sync(dev);
	pm_runtime_disable(dev);
	pm_runtime_set_suspended(dev);
	pm_runtime_put_noidle(dev);

	clk_disable_unprepare(hw->clk);
}

static int stm32_hwspinlock_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct stm32_hwspinlock *hw;
	void __iomem *io_base;
	int i, ret;

	io_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(io_base))
		return PTR_ERR(io_base);

	hw = devm_kzalloc(dev, struct_size(hw, bank.lock, STM32_MUTEX_NUM_LOCKS), GFP_KERNEL);
	if (!hw)
		return -ENOMEM;

	hw->clk = devm_clk_get(dev, "hsem");
	if (IS_ERR(hw->clk))
		return PTR_ERR(hw->clk);

	ret = clk_prepare_enable(hw->clk);
	if (ret) {
		dev_err(dev, "Failed to prepare_enable clock\n");
		return ret;
	}

	platform_set_drvdata(pdev, hw);

	pm_runtime_get_noresume(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);
	pm_runtime_put(dev);

	ret = devm_add_action_or_reset(dev, stm32_hwspinlock_disable_clk, pdev);
	if (ret) {
		dev_err(dev, "Failed to register action\n");
		return ret;
	}

	for (i = 0; i < STM32_MUTEX_NUM_LOCKS; i++)
		hw->bank.lock[i].priv = io_base + i * sizeof(u32);

	ret = devm_hwspin_lock_register(dev, &hw->bank, &stm32_hwspinlock_ops,
					0, STM32_MUTEX_NUM_LOCKS);

	if (ret)
		dev_err(dev, "Failed to register hwspinlock\n");

	return ret;
}

static int __maybe_unused stm32_hwspinlock_runtime_suspend(struct device *dev)
{
	struct stm32_hwspinlock *hw = dev_get_drvdata(dev);

	clk_disable_unprepare(hw->clk);

	return 0;
}

static int __maybe_unused stm32_hwspinlock_runtime_resume(struct device *dev)
{
	struct stm32_hwspinlock *hw = dev_get_drvdata(dev);

	clk_prepare_enable(hw->clk);

	return 0;
}

static const struct dev_pm_ops stm32_hwspinlock_pm_ops = {
	SET_RUNTIME_PM_OPS(stm32_hwspinlock_runtime_suspend,
			   stm32_hwspinlock_runtime_resume,
			   NULL)
};

static const struct of_device_id stm32_hwpinlock_ids[] = {
	{ .compatible = "st,stm32-hwspinlock", },
	{},
};
MODULE_DEVICE_TABLE(of, stm32_hwpinlock_ids);

static struct platform_driver stm32_hwspinlock_driver = {
	.probe		= stm32_hwspinlock_probe,
	.driver		= {
		.name	= "stm32_hwspinlock",
		.of_match_table = stm32_hwpinlock_ids,
		.pm	= &stm32_hwspinlock_pm_ops,
	},
};

static int __init stm32_hwspinlock_init(void)
{
	return platform_driver_register(&stm32_hwspinlock_driver);
}
/* board init code might need to reserve hwspinlocks for predefined purposes */
postcore_initcall(stm32_hwspinlock_init);

static void __exit stm32_hwspinlock_exit(void)
{
	platform_driver_unregister(&stm32_hwspinlock_driver);
}
module_exit(stm32_hwspinlock_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Hardware spinlock driver for STM32 SoCs");
MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
Commit	Line	Data
f24fcff1 BG	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) STMicroelectronics SA 2018
	4	* Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
	5	*/
	6
	7	#include <linux/clk.h>
5cd69f13	8	#include <linux/delay.h>
f24fcff1 BG	9	#include <linux/hwspinlock.h>
	10	#include <linux/io.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/pm_runtime.h>
	16
	17	#include "hwspinlock_internal.h"
	18
	19	#define STM32_MUTEX_COREID BIT(8)
	20	#define STM32_MUTEX_LOCK_BIT BIT(31)
	21	#define STM32_MUTEX_NUM_LOCKS 32
	22
	23	struct stm32_hwspinlock {
	24	struct clk *clk;
	25	struct hwspinlock_device bank;
	26	};
	27
	28	static int stm32_hwspinlock_trylock(struct hwspinlock *lock)
	29	{
	30	void __iomem *lock_addr = lock->priv;
	31	u32 status;
	32
	33	writel(STM32_MUTEX_LOCK_BIT \| STM32_MUTEX_COREID, lock_addr);
	34	status = readl(lock_addr);
	35
	36	return status == (STM32_MUTEX_LOCK_BIT \| STM32_MUTEX_COREID);
	37	}
	38
	39	static void stm32_hwspinlock_unlock(struct hwspinlock *lock)
	40	{
	41	void __iomem *lock_addr = lock->priv;
	42
	43	writel(STM32_MUTEX_COREID, lock_addr);
	44	}
	45
5cd69f13 FD	46	static void stm32_hwspinlock_relax(struct hwspinlock *lock)
	47	{
	48	ndelay(50);
	49	}
	50
f24fcff1 BG	51	static const struct hwspinlock_ops stm32_hwspinlock_ops = {
	52	.trylock = stm32_hwspinlock_trylock,
	53	.unlock = stm32_hwspinlock_unlock,
5cd69f13	54	.relax = stm32_hwspinlock_relax,
f24fcff1 BG	55	};
f24fcff1 BG	56
60630924 FD	57	static void stm32_hwspinlock_disable_clk(void *data)
	58	{
	59	struct platform_device *pdev = data;
	60	struct stm32_hwspinlock *hw = platform_get_drvdata(pdev);
	61	struct device *dev = &pdev->dev;
	62
	63	pm_runtime_get_sync(dev);
	64	pm_runtime_disable(dev);
	65	pm_runtime_set_suspended(dev);
	66	pm_runtime_put_noidle(dev);
	67
	68	clk_disable_unprepare(hw->clk);
	69	}
	70
f24fcff1 BG	71	static int stm32_hwspinlock_probe(struct platform_device *pdev)
f24fcff1 BG	72	{
60630924	73	struct device *dev = &pdev->dev;
f24fcff1 BG	74	struct stm32_hwspinlock *hw;
f24fcff1 BG	75	void __iomem *io_base;
f24fcff1 BG	76	int i, ret;
f24fcff1 BG	77
d4824486	78	io_base = devm_platform_ioremap_resource(pdev, 0);
4d5a91fd WY	79	if (IS_ERR(io_base))
4d5a91fd WY	80	return PTR_ERR(io_base);
f24fcff1	81
3e5f1ff7	82	hw = devm_kzalloc(dev, struct_size(hw, bank.lock, STM32_MUTEX_NUM_LOCKS), GFP_KERNEL);
f24fcff1 BG	83	if (!hw)
	84	return -ENOMEM;
	85
60630924	86	hw->clk = devm_clk_get(dev, "hsem");
f24fcff1 BG	87	if (IS_ERR(hw->clk))
	88	return PTR_ERR(hw->clk);
	89
60630924 FD	90	ret = clk_prepare_enable(hw->clk);
	91	if (ret) {
	92	dev_err(dev, "Failed to prepare_enable clock\n");
	93	return ret;
	94	}
f24fcff1 BG	95
f24fcff1 BG	96	platform_set_drvdata(pdev, hw);
f24fcff1	97
60630924 FD	98	pm_runtime_get_noresume(dev);
	99	pm_runtime_set_active(dev);
	100	pm_runtime_enable(dev);
	101	pm_runtime_put(dev);
f24fcff1	102
60630924 FD	103	ret = devm_add_action_or_reset(dev, stm32_hwspinlock_disable_clk, pdev);
	104	if (ret) {
	105	dev_err(dev, "Failed to register action\n");
	106	return ret;
	107	}
f24fcff1	108
60630924 FD	109	for (i = 0; i < STM32_MUTEX_NUM_LOCKS; i++)
60630924 FD	110	hw->bank.lock[i].priv = io_base + i * sizeof(u32);
f24fcff1	111
60630924 FD	112	ret = devm_hwspin_lock_register(dev, &hw->bank, &stm32_hwspinlock_ops,
60630924 FD	113	0, STM32_MUTEX_NUM_LOCKS);
f24fcff1	114
f24fcff1	115	if (ret)
60630924	116	dev_err(dev, "Failed to register hwspinlock\n");
f24fcff1	117
60630924	118	return ret;
f24fcff1 BG	119	}
	120
	121	static int __maybe_unused stm32_hwspinlock_runtime_suspend(struct device *dev)
	122	{
	123	struct stm32_hwspinlock *hw = dev_get_drvdata(dev);
	124
	125	clk_disable_unprepare(hw->clk);
	126
	127	return 0;
	128	}
	129
	130	static int __maybe_unused stm32_hwspinlock_runtime_resume(struct device *dev)
	131	{
	132	struct stm32_hwspinlock *hw = dev_get_drvdata(dev);
	133
	134	clk_prepare_enable(hw->clk);
	135
	136	return 0;
	137	}
	138
	139	static const struct dev_pm_ops stm32_hwspinlock_pm_ops = {
	140	SET_RUNTIME_PM_OPS(stm32_hwspinlock_runtime_suspend,
	141	stm32_hwspinlock_runtime_resume,
	142	NULL)
	143	};
	144
	145	static const struct of_device_id stm32_hwpinlock_ids[] = {
	146	{ .compatible = "st,stm32-hwspinlock", },
	147	{},
	148	};
	149	MODULE_DEVICE_TABLE(of, stm32_hwpinlock_ids);
	150
	151	static struct platform_driver stm32_hwspinlock_driver = {
	152	.probe = stm32_hwspinlock_probe,
f24fcff1 BG	153	.driver = {
	154	.name = "stm32_hwspinlock",
	155	.of_match_table = stm32_hwpinlock_ids,
	156	.pm = &stm32_hwspinlock_pm_ops,
	157	},
	158	};
	159
	160	static int __init stm32_hwspinlock_init(void)
	161	{
	162	return platform_driver_register(&stm32_hwspinlock_driver);
	163	}
	164	/* board init code might need to reserve hwspinlocks for predefined purposes */
	165	postcore_initcall(stm32_hwspinlock_init);
	166
	167	static void __exit stm32_hwspinlock_exit(void)
	168	{
	169	platform_driver_unregister(&stm32_hwspinlock_driver);
	170	}
	171	module_exit(stm32_hwspinlock_exit);
	172
	173	MODULE_LICENSE("GPL v2");
	174	MODULE_DESCRIPTION("Hardware spinlock driver for STM32 SoCs");
	175	MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");