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f24fcff1 BG |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) STMicroelectronics SA 2018 | |
4 | * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics. | |
5 | */ | |
6 | ||
7 | #include <linux/clk.h> | |
5cd69f13 | 8 | #include <linux/delay.h> |
f24fcff1 BG |
9 | #include <linux/hwspinlock.h> |
10 | #include <linux/io.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/pm_runtime.h> | |
16 | ||
17 | #include "hwspinlock_internal.h" | |
18 | ||
19 | #define STM32_MUTEX_COREID BIT(8) | |
20 | #define STM32_MUTEX_LOCK_BIT BIT(31) | |
21 | #define STM32_MUTEX_NUM_LOCKS 32 | |
22 | ||
23 | struct stm32_hwspinlock { | |
24 | struct clk *clk; | |
25 | struct hwspinlock_device bank; | |
26 | }; | |
27 | ||
28 | static int stm32_hwspinlock_trylock(struct hwspinlock *lock) | |
29 | { | |
30 | void __iomem *lock_addr = lock->priv; | |
31 | u32 status; | |
32 | ||
33 | writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr); | |
34 | status = readl(lock_addr); | |
35 | ||
36 | return status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID); | |
37 | } | |
38 | ||
39 | static void stm32_hwspinlock_unlock(struct hwspinlock *lock) | |
40 | { | |
41 | void __iomem *lock_addr = lock->priv; | |
42 | ||
43 | writel(STM32_MUTEX_COREID, lock_addr); | |
44 | } | |
45 | ||
5cd69f13 FD |
46 | static void stm32_hwspinlock_relax(struct hwspinlock *lock) |
47 | { | |
48 | ndelay(50); | |
49 | } | |
50 | ||
f24fcff1 BG |
51 | static const struct hwspinlock_ops stm32_hwspinlock_ops = { |
52 | .trylock = stm32_hwspinlock_trylock, | |
53 | .unlock = stm32_hwspinlock_unlock, | |
5cd69f13 | 54 | .relax = stm32_hwspinlock_relax, |
f24fcff1 BG |
55 | }; |
56 | ||
57 | static int stm32_hwspinlock_probe(struct platform_device *pdev) | |
58 | { | |
59 | struct stm32_hwspinlock *hw; | |
60 | void __iomem *io_base; | |
f24fcff1 BG |
61 | size_t array_size; |
62 | int i, ret; | |
63 | ||
d4824486 | 64 | io_base = devm_platform_ioremap_resource(pdev, 0); |
4d5a91fd WY |
65 | if (IS_ERR(io_base)) |
66 | return PTR_ERR(io_base); | |
f24fcff1 BG |
67 | |
68 | array_size = STM32_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); | |
69 | hw = devm_kzalloc(&pdev->dev, sizeof(*hw) + array_size, GFP_KERNEL); | |
70 | if (!hw) | |
71 | return -ENOMEM; | |
72 | ||
73 | hw->clk = devm_clk_get(&pdev->dev, "hsem"); | |
74 | if (IS_ERR(hw->clk)) | |
75 | return PTR_ERR(hw->clk); | |
76 | ||
77 | for (i = 0; i < STM32_MUTEX_NUM_LOCKS; i++) | |
78 | hw->bank.lock[i].priv = io_base + i * sizeof(u32); | |
79 | ||
80 | platform_set_drvdata(pdev, hw); | |
81 | pm_runtime_enable(&pdev->dev); | |
82 | ||
83 | ret = hwspin_lock_register(&hw->bank, &pdev->dev, &stm32_hwspinlock_ops, | |
84 | 0, STM32_MUTEX_NUM_LOCKS); | |
85 | ||
86 | if (ret) | |
87 | pm_runtime_disable(&pdev->dev); | |
88 | ||
89 | return ret; | |
90 | } | |
91 | ||
92 | static int stm32_hwspinlock_remove(struct platform_device *pdev) | |
93 | { | |
94 | struct stm32_hwspinlock *hw = platform_get_drvdata(pdev); | |
95 | int ret; | |
96 | ||
97 | ret = hwspin_lock_unregister(&hw->bank); | |
98 | if (ret) | |
99 | dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); | |
100 | ||
101 | pm_runtime_disable(&pdev->dev); | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | static int __maybe_unused stm32_hwspinlock_runtime_suspend(struct device *dev) | |
107 | { | |
108 | struct stm32_hwspinlock *hw = dev_get_drvdata(dev); | |
109 | ||
110 | clk_disable_unprepare(hw->clk); | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | static int __maybe_unused stm32_hwspinlock_runtime_resume(struct device *dev) | |
116 | { | |
117 | struct stm32_hwspinlock *hw = dev_get_drvdata(dev); | |
118 | ||
119 | clk_prepare_enable(hw->clk); | |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
124 | static const struct dev_pm_ops stm32_hwspinlock_pm_ops = { | |
125 | SET_RUNTIME_PM_OPS(stm32_hwspinlock_runtime_suspend, | |
126 | stm32_hwspinlock_runtime_resume, | |
127 | NULL) | |
128 | }; | |
129 | ||
130 | static const struct of_device_id stm32_hwpinlock_ids[] = { | |
131 | { .compatible = "st,stm32-hwspinlock", }, | |
132 | {}, | |
133 | }; | |
134 | MODULE_DEVICE_TABLE(of, stm32_hwpinlock_ids); | |
135 | ||
136 | static struct platform_driver stm32_hwspinlock_driver = { | |
137 | .probe = stm32_hwspinlock_probe, | |
138 | .remove = stm32_hwspinlock_remove, | |
139 | .driver = { | |
140 | .name = "stm32_hwspinlock", | |
141 | .of_match_table = stm32_hwpinlock_ids, | |
142 | .pm = &stm32_hwspinlock_pm_ops, | |
143 | }, | |
144 | }; | |
145 | ||
146 | static int __init stm32_hwspinlock_init(void) | |
147 | { | |
148 | return platform_driver_register(&stm32_hwspinlock_driver); | |
149 | } | |
150 | /* board init code might need to reserve hwspinlocks for predefined purposes */ | |
151 | postcore_initcall(stm32_hwspinlock_init); | |
152 | ||
153 | static void __exit stm32_hwspinlock_exit(void) | |
154 | { | |
155 | platform_driver_unregister(&stm32_hwspinlock_driver); | |
156 | } | |
157 | module_exit(stm32_hwspinlock_exit); | |
158 | ||
159 | MODULE_LICENSE("GPL v2"); | |
160 | MODULE_DESCRIPTION("Hardware spinlock driver for STM32 SoCs"); | |
161 | MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); |