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hwmon: remove use of __devinitdata
[linux-2.6-block.git] / drivers / hwmon / w83781d.c
CommitLineData
1da177e4 1/*
aff6e00e
GR		 2 * w83781d.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring
4 * Copyright (c) 1998 - 2001 Frodo Looijaard <frodol@dds.nl>,
5 * Philip Edelbrock <phil@netroedge.com>,
6 * and Mark Studebaker <mdsxyz123@yahoo.com>
7 * Copyright (c) 2007 - 2008 Jean Delvare <khali@linux-fr.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
1da177e4
LT		 23
24/*
aff6e00e
GR		 25 * Supports following chips:
26 *
4101ece3 27 * Chip #vin #fanin #pwm #temp wchipid vendid i2c ISA
aff6e00e
GR		 28 * as99127f 7 3 0 3 0x31 0x12c3 yes no
29 * as99127f rev.2 (type_name = as99127f) 0x31 0x5ca3 yes no
30 * w83781d 7 3 0 3 0x10-1 0x5ca3 yes yes
31 * w83782d 9 3 2-4 3 0x30 0x5ca3 yes yes
32 * w83783s 5-6 3 2 1-2 0x40 0x5ca3 yes no
33 *
34 */
1da177e4 35
1ca28218
JP		 36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/init.h>
40#include <linux/slab.h>
41#include <linux/jiffies.h>
42#include <linux/i2c.h>
943b0830 43#include <linux/hwmon.h>
303760b4 44#include <linux/hwmon-vid.h>
34875337 45#include <linux/hwmon-sysfs.h>
311ce2ef 46#include <linux/sysfs.h>
943b0830 47#include <linux/err.h>
9a61bf63 48#include <linux/mutex.h>
443850ce
WG		 49
50#ifdef CONFIG_ISA
51#include <linux/platform_device.h>
52#include <linux/ioport.h>
6055fae8 53#include <linux/io.h>
443850ce 54#endif
1da177e4 55
443850ce 56#include "lm75.h"
7666c13c 57
1da177e4 58/* Addresses to scan */
25e9c86d
MH		 59static const unsigned short normal_i2c[] = { 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d,
60 0x2e, 0x2f, I2C_CLIENT_END };
3aed198c 61
e5e9f44c
JD		 62enum chips { w83781d, w83782d, w83783s, as99127f };
63
64/* Insmod parameters */
3aed198c
JD		 65static unsigned short force_subclients[4];
66module_param_array(force_subclients, short, NULL, 0);
67MODULE_PARM_DESC(force_subclients, "List of subclient addresses: "
1da177e4
LT		 68 "{bus, clientaddr, subclientaddr1, subclientaddr2}");
69
90ab5ee9 70static bool reset;
fabddcd4
JD		 71module_param(reset, bool, 0);
72MODULE_PARM_DESC(reset, "Set to one to reset chip on load");
73
90ab5ee9 74static bool init = 1;
1da177e4
LT		 75module_param(init, bool, 0);
76MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization");
77
78/* Constants specified below */
79
80/* Length of ISA address segment */
81#define W83781D_EXTENT 8
82
83/* Where are the ISA address/data registers relative to the base address */
84#define W83781D_ADDR_REG_OFFSET 5
85#define W83781D_DATA_REG_OFFSET 6
86
34875337
JD		 87/* The device registers */
88/* in nr from 0 to 8 */
1da177e4
LT		 89#define W83781D_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
90 (0x554 + (((nr) - 7) * 2)))
91#define W83781D_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
92 (0x555 + (((nr) - 7) * 2)))
93#define W83781D_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
94 (0x550 + (nr) - 7))
95
34875337
JD		 96/* fan nr from 0 to 2 */
97#define W83781D_REG_FAN_MIN(nr) (0x3b + (nr))
98#define W83781D_REG_FAN(nr) (0x28 + (nr))
1da177e4
LT		 99
100#define W83781D_REG_BANK 0x4E
101#define W83781D_REG_TEMP2_CONFIG 0x152
102#define W83781D_REG_TEMP3_CONFIG 0x252
34875337 103/* temp nr from 1 to 3 */
1da177e4
LT		 104#define W83781D_REG_TEMP(nr) ((nr == 3) ? (0x0250) : \
105 ((nr == 2) ? (0x0150) : \
106 (0x27)))
107#define W83781D_REG_TEMP_HYST(nr) ((nr == 3) ? (0x253) : \
108 ((nr == 2) ? (0x153) : \
109 (0x3A)))
110#define W83781D_REG_TEMP_OVER(nr) ((nr == 3) ? (0x255) : \
111 ((nr == 2) ? (0x155) : \
112 (0x39)))
113
114#define W83781D_REG_CONFIG 0x40
c7f5d7ed
JD		 115
116/* Interrupt status (W83781D, AS99127F) */
1da177e4
LT		 117#define W83781D_REG_ALARM1 0x41
118#define W83781D_REG_ALARM2 0x42
1da177e4 119
05663368 120/* Real-time status (W83782D, W83783S) */
c7f5d7ed
JD		 121#define W83782D_REG_ALARM1 0x459
122#define W83782D_REG_ALARM2 0x45A
123#define W83782D_REG_ALARM3 0x45B
124
1da177e4
LT		 125#define W83781D_REG_BEEP_CONFIG 0x4D
126#define W83781D_REG_BEEP_INTS1 0x56
127#define W83781D_REG_BEEP_INTS2 0x57
128#define W83781D_REG_BEEP_INTS3 0x453 /* not on W83781D */
129
130#define W83781D_REG_VID_FANDIV 0x47
131
132#define W83781D_REG_CHIPID 0x49
133#define W83781D_REG_WCHIPID 0x58
134#define W83781D_REG_CHIPMAN 0x4F
135#define W83781D_REG_PIN 0x4B
136
137/* 782D/783S only */
138#define W83781D_REG_VBAT 0x5D
139
140/* PWM 782D (1-4) and 783S (1-2) only */
34875337 141static const u8 W83781D_REG_PWM[] = { 0x5B, 0x5A, 0x5E, 0x5F };
1da177e4
LT		 142#define W83781D_REG_PWMCLK12 0x5C
143#define W83781D_REG_PWMCLK34 0x45C
1da177e4
LT		 144
145#define W83781D_REG_I2C_ADDR 0x48
146#define W83781D_REG_I2C_SUBADDR 0x4A
147
aff6e00e
GR		 148/*
149 * The following are undocumented in the data sheets however we
150 * received the information in an email from Winbond tech support
151 */
1da177e4
LT		 152/* Sensor selection - not on 781d */
153#define W83781D_REG_SCFG1 0x5D
154static const u8 BIT_SCFG1[] = { 0x02, 0x04, 0x08 };
155
156#define W83781D_REG_SCFG2 0x59
157static const u8 BIT_SCFG2[] = { 0x10, 0x20, 0x40 };
158
159#define W83781D_DEFAULT_BETA 3435
160
474d00a8
JD		 161/* Conversions */
162#define IN_TO_REG(val) SENSORS_LIMIT(((val) + 8) / 16, 0, 255)
163#define IN_FROM_REG(val) ((val) * 16)
1da177e4
LT		 164
165static inline u8
166FAN_TO_REG(long rpm, int div)
167{
168 if (rpm == 0)
169 return 255;
170 rpm = SENSORS_LIMIT(rpm, 1, 1000000);
171 return SENSORS_LIMIT((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
172}
173
474d00a8
JD		 174static inline long
175FAN_FROM_REG(u8 val, int div)
176{
177 if (val == 0)
178 return -1;
179 if (val == 255)
180 return 0;
181 return 1350000 / (val * div);
182}
1da177e4 183
474d00a8
JD		 184#define TEMP_TO_REG(val) SENSORS_LIMIT((val) / 1000, -127, 128)
185#define TEMP_FROM_REG(val) ((val) * 1000)
1da177e4 186
c531eb3f 187#define BEEP_MASK_FROM_REG(val, type) ((type) == as99127f ? \
2fbbbf14 188 (~(val)) & 0x7fff : (val) & 0xff7fff)
c531eb3f 189#define BEEP_MASK_TO_REG(val, type) ((type) == as99127f ? \
2fbbbf14 190 (~(val)) & 0x7fff : (val) & 0xff7fff)
1da177e4 191
1da177e4
LT		 192#define DIV_FROM_REG(val) (1 << (val))
193
194static inline u8
195DIV_TO_REG(long val, enum chips type)
196{
197 int i;
198 val = SENSORS_LIMIT(val, 1,
199 ((type == w83781d
200 || type == as99127f) ? 8 : 128)) >> 1;
abc01922 201 for (i = 0; i < 7; i++) {
1da177e4
LT		 202 if (val == 0)
203 break;
204 val >>= 1;
205 }
474d00a8 206 return i;
1da177e4
LT		 207}
208
1da177e4 209struct w83781d_data {
0217eae3 210 struct i2c_client *client;
1beeffe4 211 struct device *hwmon_dev;
9a61bf63 212 struct mutex lock;
1da177e4
LT		 213 enum chips type;
214
360782dd
JD		 215 /* For ISA device only */
216 const char *name;
217 int isa_addr;
218
9a61bf63 219 struct mutex update_lock;
1da177e4
LT		 220 char valid; /* !=0 if following fields are valid */
221 unsigned long last_updated; /* In jiffies */
222
223 struct i2c_client *lm75[2]; /* for secondary I2C addresses */
224 /* array of 2 pointers to subclients */
225
226 u8 in[9]; /* Register value - 8 & 9 for 782D only */
227 u8 in_max[9]; /* Register value - 8 & 9 for 782D only */
228 u8 in_min[9]; /* Register value - 8 & 9 for 782D only */
229 u8 fan[3]; /* Register value */
230 u8 fan_min[3]; /* Register value */
474d00a8
JD		 231 s8 temp; /* Register value */
232 s8 temp_max; /* Register value */
233 s8 temp_max_hyst; /* Register value */
1da177e4
LT		 234 u16 temp_add[2]; /* Register value */
235 u16 temp_max_add[2]; /* Register value */
236 u16 temp_max_hyst_add[2]; /* Register value */
237 u8 fan_div[3]; /* Register encoding, shifted right */
238 u8 vid; /* Register encoding, combined */
239 u32 alarms; /* Register encoding, combined */
240 u32 beep_mask; /* Register encoding, combined */
1da177e4 241 u8 pwm[4]; /* Register value */
34875337 242 u8 pwm2_enable; /* Boolean */
aff6e00e
GR		 243 u16 sens[3]; /*
244 * 782D/783S only.
245 * 1 = pentium diode; 2 = 3904 diode;
246 * 4 = thermistor
247 */
1da177e4
LT		 248 u8 vrm;
249};
250
443850ce
WG		 251static struct w83781d_data *w83781d_data_if_isa(void);
252static int w83781d_alias_detect(struct i2c_client *client, u8 chipid);
253
31b8dc4d
JD		 254static int w83781d_read_value(struct w83781d_data *data, u16 reg);
255static int w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value);
1da177e4 256static struct w83781d_data *w83781d_update_device(struct device *dev);
7666c13c 257static void w83781d_init_device(struct device *dev);
1da177e4 258
1da177e4
LT		 259/* following are the sysfs callback functions */
260#define show_in_reg(reg) \
c531eb3f 261static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \
34875337 262 char *buf) \
1da177e4 263{ \
34875337 264 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
1da177e4 265 struct w83781d_data *data = w83781d_update_device(dev); \
34875337
JD		 266 return sprintf(buf, "%ld\n", \
267 (long)IN_FROM_REG(data->reg[attr->index])); \
1da177e4
LT		 268}
269show_in_reg(in);
270show_in_reg(in_min);
271show_in_reg(in_max);
272
273#define store_in_reg(REG, reg) \
c531eb3f 274static ssize_t store_in_##reg(struct device *dev, struct device_attribute \
34875337 275 *da, const char *buf, size_t count) \
1da177e4 276{ \
34875337 277 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
7666c13c 278 struct w83781d_data *data = dev_get_drvdata(dev); \
34875337 279 int nr = attr->index; \
c531eb3f
GR		 280 unsigned long val; \
281 int err = kstrtoul(buf, 10, &val); \
282 if (err) \
283 return err; \
9a61bf63 284 mutex_lock(&data->update_lock); \
1da177e4 285 data->in_##reg[nr] = IN_TO_REG(val); \
c531eb3f
GR		 286 w83781d_write_value(data, W83781D_REG_IN_##REG(nr), \
287 data->in_##reg[nr]); \
288 \
9a61bf63 289 mutex_unlock(&data->update_lock); \
1da177e4
LT		 290 return count; \
291}
292store_in_reg(MIN, min);
293store_in_reg(MAX, max);
294
1da177e4 295#define sysfs_in_offsets(offset) \
34875337
JD		 296static SENSOR_DEVICE_ATTR(in##offset##_input, S_IRUGO, \
297 show_in, NULL, offset); \
298static SENSOR_DEVICE_ATTR(in##offset##_min, S_IRUGO | S_IWUSR, \
299 show_in_min, store_in_min, offset); \
300static SENSOR_DEVICE_ATTR(in##offset##_max, S_IRUGO | S_IWUSR, \
301 show_in_max, store_in_max, offset)
1da177e4
LT		 302
303sysfs_in_offsets(0);
304sysfs_in_offsets(1);
305sysfs_in_offsets(2);
306sysfs_in_offsets(3);
307sysfs_in_offsets(4);
308sysfs_in_offsets(5);
309sysfs_in_offsets(6);
310sysfs_in_offsets(7);
311sysfs_in_offsets(8);
312
1da177e4 313#define show_fan_reg(reg) \
c531eb3f 314static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \
34875337 315 char *buf) \
1da177e4 316{ \
34875337 317 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
1da177e4 318 struct w83781d_data *data = w83781d_update_device(dev); \
c531eb3f 319 return sprintf(buf, "%ld\n", \
34875337
JD		 320 FAN_FROM_REG(data->reg[attr->index], \
321 DIV_FROM_REG(data->fan_div[attr->index]))); \
1da177e4
LT		 322}
323show_fan_reg(fan);
324show_fan_reg(fan_min);
325
326static ssize_t
34875337
JD		 327store_fan_min(struct device *dev, struct device_attribute *da,
328 const char *buf, size_t count)
1da177e4 329{
34875337 330 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 331 struct w83781d_data *data = dev_get_drvdata(dev);
34875337 332 int nr = attr->index;
c531eb3f
GR		 333 unsigned long val;
334 int err;
1da177e4 335
c531eb3f
GR		 336 err = kstrtoul(buf, 10, &val);
337 if (err)
338 return err;
1da177e4 339
9a61bf63 340 mutex_lock(&data->update_lock);
34875337
JD		 341 data->fan_min[nr] =
342 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
31b8dc4d 343 w83781d_write_value(data, W83781D_REG_FAN_MIN(nr),
34875337 344 data->fan_min[nr]);
1da177e4 345
9a61bf63 346 mutex_unlock(&data->update_lock);
1da177e4
LT		 347 return count;
348}
349
34875337
JD		 350static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0);
351static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO | S_IWUSR,
352 show_fan_min, store_fan_min, 0);
353static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1);
354static SENSOR_DEVICE_ATTR(fan2_min, S_IRUGO | S_IWUSR,
355 show_fan_min, store_fan_min, 1);
356static SENSOR_DEVICE_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2);
357static SENSOR_DEVICE_ATTR(fan3_min, S_IRUGO | S_IWUSR,
358 show_fan_min, store_fan_min, 2);
1da177e4 359
1da177e4 360#define show_temp_reg(reg) \
c531eb3f 361static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \
34875337 362 char *buf) \
1da177e4 363{ \
34875337 364 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
1da177e4 365 struct w83781d_data *data = w83781d_update_device(dev); \
34875337 366 int nr = attr->index; \
1da177e4 367 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
c531eb3f 368 return sprintf(buf, "%d\n", \
1da177e4
LT		 369 LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \
370 } else { /* TEMP1 */ \
c531eb3f 371 return sprintf(buf, "%ld\n", (long)TEMP_FROM_REG(data->reg)); \
1da177e4
LT		 372 } \
373}
374show_temp_reg(temp);
375show_temp_reg(temp_max);
376show_temp_reg(temp_max_hyst);
377
378#define store_temp_reg(REG, reg) \
c531eb3f 379static ssize_t store_temp_##reg(struct device *dev, \
34875337 380 struct device_attribute *da, const char *buf, size_t count) \
1da177e4 381{ \
34875337 382 struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
7666c13c 383 struct w83781d_data *data = dev_get_drvdata(dev); \
34875337 384 int nr = attr->index; \
5bfedac0 385 long val; \
c531eb3f
GR		 386 int err = kstrtol(buf, 10, &val); \
387 if (err) \
388 return err; \
9a61bf63 389 mutex_lock(&data->update_lock); \
1da177e4
LT		 390 \
391 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
392 data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \
31b8dc4d 393 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
1da177e4
LT		 394 data->temp_##reg##_add[nr-2]); \
395 } else { /* TEMP1 */ \
396 data->temp_##reg = TEMP_TO_REG(val); \
31b8dc4d 397 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
1da177e4
LT		 398 data->temp_##reg); \
399 } \
400 \
9a61bf63 401 mutex_unlock(&data->update_lock); \
1da177e4
LT		 402 return count; \
403}
404store_temp_reg(OVER, max);
405store_temp_reg(HYST, max_hyst);
406
1da177e4 407#define sysfs_temp_offsets(offset) \
34875337
JD		 408static SENSOR_DEVICE_ATTR(temp##offset##_input, S_IRUGO, \
409 show_temp, NULL, offset); \
410static SENSOR_DEVICE_ATTR(temp##offset##_max, S_IRUGO | S_IWUSR, \
411 show_temp_max, store_temp_max, offset); \
412static SENSOR_DEVICE_ATTR(temp##offset##_max_hyst, S_IRUGO | S_IWUSR, \
413 show_temp_max_hyst, store_temp_max_hyst, offset);
1da177e4
LT		 414
415sysfs_temp_offsets(1);
416sysfs_temp_offsets(2);
417sysfs_temp_offsets(3);
418
1da177e4 419static ssize_t
e404e274 420show_vid_reg(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT		 421{
422 struct w83781d_data *data = w83781d_update_device(dev);
423 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
424}
425
311ce2ef
JC		 426static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
427
1da177e4 428static ssize_t
e404e274 429show_vrm_reg(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4 430{
90d6619a 431 struct w83781d_data *data = dev_get_drvdata(dev);
1da177e4
LT		 432 return sprintf(buf, "%ld\n", (long) data->vrm);
433}
434
435static ssize_t
c531eb3f
GR		 436store_vrm_reg(struct device *dev, struct device_attribute *attr,
437 const char *buf, size_t count)
1da177e4 438{
7666c13c 439 struct w83781d_data *data = dev_get_drvdata(dev);
c531eb3f
GR		 440 unsigned long val;
441 int err;
1da177e4 442
c531eb3f
GR		 443 err = kstrtoul(buf, 10, &val);
444 if (err)
445 return err;
446 data->vrm = SENSORS_LIMIT(val, 0, 255);
1da177e4
LT		 447
448 return count;
449}
450
311ce2ef
JC		 451static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
452
1da177e4 453static ssize_t
e404e274 454show_alarms_reg(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT		 455{
456 struct w83781d_data *data = w83781d_update_device(dev);
68188ba7 457 return sprintf(buf, "%u\n", data->alarms);
1da177e4
LT		 458}
459
311ce2ef
JC		 460static DEVICE_ATTR(alarms, S_IRUGO, show_alarms_reg, NULL);
461
7d4a1374
JD		 462static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
463 char *buf)
464{
465 struct w83781d_data *data = w83781d_update_device(dev);
466 int bitnr = to_sensor_dev_attr(attr)->index;
467 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
468}
469
470/* The W83781D has a single alarm bit for temp2 and temp3 */
471static ssize_t show_temp3_alarm(struct device *dev,
472 struct device_attribute *attr, char *buf)
473{
474 struct w83781d_data *data = w83781d_update_device(dev);
475 int bitnr = (data->type == w83781d) ? 5 : 13;
476 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
477}
478
479static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0);
480static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1);
481static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2);
482static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3);
483static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8);
484static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 9);
485static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 10);
486static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16);
487static SENSOR_DEVICE_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17);
488static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6);
489static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7);
490static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11);
491static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4);
492static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5);
493static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_temp3_alarm, NULL, 0);
494
c531eb3f
GR		 495static ssize_t show_beep_mask(struct device *dev,
496 struct device_attribute *attr, char *buf)
1da177e4
LT		 497{
498 struct w83781d_data *data = w83781d_update_device(dev);
499 return sprintf(buf, "%ld\n",
500 (long)BEEP_MASK_FROM_REG(data->beep_mask, data->type));
501}
1da177e4 502
1da177e4 503static ssize_t
34875337
JD		 504store_beep_mask(struct device *dev, struct device_attribute *attr,
505 const char *buf, size_t count)
1da177e4 506{
7666c13c 507 struct w83781d_data *data = dev_get_drvdata(dev);
c531eb3f
GR		 508 unsigned long val;
509 int err;
1da177e4 510
c531eb3f
GR		 511 err = kstrtoul(buf, 10, &val);
512 if (err)
513 return err;
1da177e4 514
9a61bf63 515 mutex_lock(&data->update_lock);
2fbbbf14
JD		 516 data->beep_mask &= 0x8000; /* preserve beep enable */
517 data->beep_mask |= BEEP_MASK_TO_REG(val, data->type);
34875337
JD		 518 w83781d_write_value(data, W83781D_REG_BEEP_INTS1,
519 data->beep_mask & 0xff);
520 w83781d_write_value(data, W83781D_REG_BEEP_INTS2,
2fbbbf14 521 (data->beep_mask >> 8) & 0xff);
34875337
JD		 522 if (data->type != w83781d && data->type != as99127f) {
523 w83781d_write_value(data, W83781D_REG_BEEP_INTS3,
524 ((data->beep_mask) >> 16) & 0xff);
525 }
526 mutex_unlock(&data->update_lock);
1da177e4 527
34875337
JD		 528 return count;
529}
1da177e4 530
34875337
JD		 531static DEVICE_ATTR(beep_mask, S_IRUGO | S_IWUSR,
532 show_beep_mask, store_beep_mask);
1da177e4 533
7d4a1374
JD		 534static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
535 char *buf)
536{
537 struct w83781d_data *data = w83781d_update_device(dev);
538 int bitnr = to_sensor_dev_attr(attr)->index;
539 return sprintf(buf, "%u\n", (data->beep_mask >> bitnr) & 1);
540}
541
542static ssize_t
543store_beep(struct device *dev, struct device_attribute *attr,
544 const char *buf, size_t count)
545{
546 struct w83781d_data *data = dev_get_drvdata(dev);
547 int bitnr = to_sensor_dev_attr(attr)->index;
7d4a1374 548 u8 reg;
c531eb3f
GR		 549 unsigned long bit;
550 int err;
551
552 err = kstrtoul(buf, 10, &bit);
553 if (err)
554 return err;
7d4a1374 555
7d4a1374
JD		 556 if (bit & ~1)
557 return -EINVAL;
558
559 mutex_lock(&data->update_lock);
560 if (bit)
561 data->beep_mask |= (1 << bitnr);
562 else
563 data->beep_mask &= ~(1 << bitnr);
564
565 if (bitnr < 8) {
566 reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS1);
567 if (bit)
568 reg |= (1 << bitnr);
569 else
570 reg &= ~(1 << bitnr);
571 w83781d_write_value(data, W83781D_REG_BEEP_INTS1, reg);
572 } else if (bitnr < 16) {
573 reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS2);
574 if (bit)
575 reg |= (1 << (bitnr - 8));
576 else
577 reg &= ~(1 << (bitnr - 8));
578 w83781d_write_value(data, W83781D_REG_BEEP_INTS2, reg);
579 } else {
580 reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS3);
581 if (bit)
582 reg |= (1 << (bitnr - 16));
583 else
584 reg &= ~(1 << (bitnr - 16));
585 w83781d_write_value(data, W83781D_REG_BEEP_INTS3, reg);
586 }
587 mutex_unlock(&data->update_lock);
588
589 return count;
590}
591
592/* The W83781D has a single beep bit for temp2 and temp3 */
593static ssize_t show_temp3_beep(struct device *dev,
594 struct device_attribute *attr, char *buf)
595{
596 struct w83781d_data *data = w83781d_update_device(dev);
597 int bitnr = (data->type == w83781d) ? 5 : 13;
598 return sprintf(buf, "%u\n", (data->beep_mask >> bitnr) & 1);
599}
600
601static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
602 show_beep, store_beep, 0);
603static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO | S_IWUSR,
604 show_beep, store_beep, 1);
605static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO | S_IWUSR,
606 show_beep, store_beep, 2);
607static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO | S_IWUSR,
608 show_beep, store_beep, 3);
609static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO | S_IWUSR,
610 show_beep, store_beep, 8);
611static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO | S_IWUSR,
612 show_beep, store_beep, 9);
613static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO | S_IWUSR,
614 show_beep, store_beep, 10);
615static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO | S_IWUSR,
616 show_beep, store_beep, 16);
617static SENSOR_DEVICE_ATTR(in8_beep, S_IRUGO | S_IWUSR,
618 show_beep, store_beep, 17);
619static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO | S_IWUSR,
620 show_beep, store_beep, 6);
621static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO | S_IWUSR,
622 show_beep, store_beep, 7);
623static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO | S_IWUSR,
624 show_beep, store_beep, 11);
625static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
626 show_beep, store_beep, 4);
627static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO | S_IWUSR,
628 show_beep, store_beep, 5);
629static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO,
630 show_temp3_beep, store_beep, 13);
2fbbbf14
JD		 631static SENSOR_DEVICE_ATTR(beep_enable, S_IRUGO | S_IWUSR,
632 show_beep, store_beep, 15);
7d4a1374 633
1da177e4 634static ssize_t
34875337 635show_fan_div(struct device *dev, struct device_attribute *da, char *buf)
1da177e4 636{
34875337 637 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
1da177e4
LT		 638 struct w83781d_data *data = w83781d_update_device(dev);
639 return sprintf(buf, "%ld\n",
34875337 640 (long) DIV_FROM_REG(data->fan_div[attr->index]));
1da177e4
LT		 641}
642
aff6e00e
GR		 643/*
644 * Note: we save and restore the fan minimum here, because its value is
645 * determined in part by the fan divisor. This follows the principle of
646 * least surprise; the user doesn't expect the fan minimum to change just
647 * because the divisor changed.
648 */
1da177e4 649static ssize_t
34875337
JD		 650store_fan_div(struct device *dev, struct device_attribute *da,
651 const char *buf, size_t count)
1da177e4 652{
34875337 653 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 654 struct w83781d_data *data = dev_get_drvdata(dev);
1da177e4 655 unsigned long min;
34875337 656 int nr = attr->index;
1da177e4 657 u8 reg;
c531eb3f
GR		 658 unsigned long val;
659 int err;
660
661 err = kstrtoul(buf, 10, &val);
662 if (err)
663 return err;
1da177e4 664
9a61bf63 665 mutex_lock(&data->update_lock);
293c0997 666
1da177e4
LT		 667 /* Save fan_min */
668 min = FAN_FROM_REG(data->fan_min[nr],
669 DIV_FROM_REG(data->fan_div[nr]));
670
671 data->fan_div[nr] = DIV_TO_REG(val, data->type);
672
c531eb3f
GR		 673 reg = (w83781d_read_value(data, nr == 2 ?
674 W83781D_REG_PIN : W83781D_REG_VID_FANDIV)
675 & (nr == 0 ? 0xcf : 0x3f))
676 | ((data->fan_div[nr] & 0x03) << (nr == 0 ? 4 : 6));
677 w83781d_write_value(data, nr == 2 ?
678 W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg);
1da177e4
LT		 679
680 /* w83781d and as99127f don't have extended divisor bits */
681 if (data->type != w83781d && data->type != as99127f) {
31b8dc4d 682 reg = (w83781d_read_value(data, W83781D_REG_VBAT)
1da177e4
LT		 683 & ~(1 << (5 + nr)))
684 | ((data->fan_div[nr] & 0x04) << (3 + nr));
31b8dc4d 685 w83781d_write_value(data, W83781D_REG_VBAT, reg);
1da177e4
LT		 686 }
687
688 /* Restore fan_min */
689 data->fan_min[nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
34875337 690 w83781d_write_value(data, W83781D_REG_FAN_MIN(nr), data->fan_min[nr]);
1da177e4 691
9a61bf63 692 mutex_unlock(&data->update_lock);
1da177e4
LT		 693 return count;
694}
695
34875337
JD		 696static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR,
697 show_fan_div, store_fan_div, 0);
698static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR,
699 show_fan_div, store_fan_div, 1);
700static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR,
701 show_fan_div, store_fan_div, 2);
1da177e4 702
1da177e4 703static ssize_t
34875337 704show_pwm(struct device *dev, struct device_attribute *da, char *buf)
1da177e4 705{
34875337 706 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
1da177e4 707 struct w83781d_data *data = w83781d_update_device(dev);
34875337 708 return sprintf(buf, "%d\n", (int)data->pwm[attr->index]);
1da177e4
LT		 709}
710
711static ssize_t
34875337 712show_pwm2_enable(struct device *dev, struct device_attribute *da, char *buf)
1da177e4
LT		 713{
714 struct w83781d_data *data = w83781d_update_device(dev);
34875337 715 return sprintf(buf, "%d\n", (int)data->pwm2_enable);
1da177e4
LT		 716}
717
718static ssize_t
34875337
JD		 719store_pwm(struct device *dev, struct device_attribute *da, const char *buf,
720 size_t count)
1da177e4 721{
34875337 722 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 723 struct w83781d_data *data = dev_get_drvdata(dev);
34875337 724 int nr = attr->index;
c531eb3f
GR		 725 unsigned long val;
726 int err;
1da177e4 727
c531eb3f
GR		 728 err = kstrtoul(buf, 10, &val);
729 if (err)
730 return err;
1da177e4 731
9a61bf63 732 mutex_lock(&data->update_lock);
34875337
JD		 733 data->pwm[nr] = SENSORS_LIMIT(val, 0, 255);
734 w83781d_write_value(data, W83781D_REG_PWM[nr], data->pwm[nr]);
9a61bf63 735 mutex_unlock(&data->update_lock);
1da177e4
LT		 736 return count;
737}
738
739static ssize_t
34875337
JD		 740store_pwm2_enable(struct device *dev, struct device_attribute *da,
741 const char *buf, size_t count)
1da177e4 742{
7666c13c 743 struct w83781d_data *data = dev_get_drvdata(dev);
c531eb3f
GR		 744 unsigned long val;
745 u32 reg;
746 int err;
1da177e4 747
c531eb3f
GR		 748 err = kstrtoul(buf, 10, &val);
749 if (err)
750 return err;
1da177e4 751
9a61bf63 752 mutex_lock(&data->update_lock);
1da177e4
LT		 753
754 switch (val) {
755 case 0:
756 case 1:
31b8dc4d
JD		 757 reg = w83781d_read_value(data, W83781D_REG_PWMCLK12);
758 w83781d_write_value(data, W83781D_REG_PWMCLK12,
1da177e4
LT		 759 (reg & 0xf7) | (val << 3));
760
31b8dc4d
JD		 761 reg = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG);
762 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG,
1da177e4
LT		 763 (reg & 0xef) | (!val << 4));
764
34875337 765 data->pwm2_enable = val;
1da177e4
LT		 766 break;
767
768 default:
9a61bf63 769 mutex_unlock(&data->update_lock);
1da177e4
LT		 770 return -EINVAL;
771 }
772
9a61bf63 773 mutex_unlock(&data->update_lock);
1da177e4
LT		 774 return count;
775}
776
34875337
JD		 777static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 0);
778static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 1);
779static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 2);
780static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, store_pwm, 3);
781/* only PWM2 can be enabled/disabled */
782static DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
783 show_pwm2_enable, store_pwm2_enable);
1da177e4 784
1da177e4 785static ssize_t
34875337 786show_sensor(struct device *dev, struct device_attribute *da, char *buf)
1da177e4 787{
34875337 788 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
1da177e4 789 struct w83781d_data *data = w83781d_update_device(dev);
34875337 790 return sprintf(buf, "%d\n", (int)data->sens[attr->index]);
1da177e4
LT		 791}
792
793static ssize_t
34875337
JD		 794store_sensor(struct device *dev, struct device_attribute *da,
795 const char *buf, size_t count)
1da177e4 796{
34875337 797 struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
7666c13c 798 struct w83781d_data *data = dev_get_drvdata(dev);
34875337 799 int nr = attr->index;
c531eb3f
GR		 800 unsigned long val;
801 u32 tmp;
802 int err;
1da177e4 803
c531eb3f
GR		 804 err = kstrtoul(buf, 10, &val);
805 if (err)
806 return err;
1da177e4 807
9a61bf63 808 mutex_lock(&data->update_lock);
1da177e4
LT		 809
810 switch (val) {
811 case 1: /* PII/Celeron diode */
31b8dc4d
JD		 812 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
813 w83781d_write_value(data, W83781D_REG_SCFG1,
34875337 814 tmp | BIT_SCFG1[nr]);
31b8dc4d
JD		 815 tmp = w83781d_read_value(data, W83781D_REG_SCFG2);
816 w83781d_write_value(data, W83781D_REG_SCFG2,
34875337
JD		 817 tmp | BIT_SCFG2[nr]);
818 data->sens[nr] = val;
1da177e4
LT		 819 break;
820 case 2: /* 3904 */
31b8dc4d
JD		 821 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
822 w83781d_write_value(data, W83781D_REG_SCFG1,
34875337 823 tmp | BIT_SCFG1[nr]);
31b8dc4d
JD		 824 tmp = w83781d_read_value(data, W83781D_REG_SCFG2);
825 w83781d_write_value(data, W83781D_REG_SCFG2,
34875337
JD		 826 tmp & ~BIT_SCFG2[nr]);
827 data->sens[nr] = val;
1da177e4 828 break;
b26f9330
JD		 829 case W83781D_DEFAULT_BETA:
830 dev_warn(dev, "Sensor type %d is deprecated, please use 4 "
831 "instead\n", W83781D_DEFAULT_BETA);
832 /* fall through */
833 case 4: /* thermistor */
31b8dc4d
JD		 834 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
835 w83781d_write_value(data, W83781D_REG_SCFG1,
34875337
JD		 836 tmp & ~BIT_SCFG1[nr]);
837 data->sens[nr] = val;
1da177e4
LT		 838 break;
839 default:
b26f9330
JD		 840 dev_err(dev, "Invalid sensor type %ld; must be 1, 2, or 4\n",
841 (long) val);
1da177e4
LT		 842 break;
843 }
844
9a61bf63 845 mutex_unlock(&data->update_lock);
1da177e4
LT		 846 return count;
847}
848
34875337
JD		 849static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR,
850 show_sensor, store_sensor, 0);
851static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR,
393cdad6 852 show_sensor, store_sensor, 1);
34875337 853static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR,
393cdad6 854 show_sensor, store_sensor, 2);
1da177e4 855
aff6e00e
GR		 856/*
857 * Assumes that adapter is of I2C, not ISA variety.
1da177e4
LT		 858 * OTHERWISE DON'T CALL THIS
859 */
860static int
0217eae3 861w83781d_detect_subclients(struct i2c_client *new_client)
1da177e4
LT		 862{
863 int i, val1 = 0, id;
864 int err;
0217eae3
WG		 865 int address = new_client->addr;
866 unsigned short sc_addr[2];
867 struct i2c_adapter *adapter = new_client->adapter;
1da177e4 868 struct w83781d_data *data = i2c_get_clientdata(new_client);
0217eae3 869 enum chips kind = data->type;
bbc8a569 870 int num_sc = 1;
1da177e4
LT		 871
872 id = i2c_adapter_id(adapter);
873
874 if (force_subclients[0] == id && force_subclients[1] == address) {
875 for (i = 2; i <= 3; i++) {
876 if (force_subclients[i] < 0x48 ||
877 force_subclients[i] > 0x4f) {
878 dev_err(&new_client->dev, "Invalid subclient "
879 "address %d; must be 0x48-0x4f\n",
880 force_subclients[i]);
881 err = -EINVAL;
882 goto ERROR_SC_1;
883 }
884 }
31b8dc4d 885 w83781d_write_value(data, W83781D_REG_I2C_SUBADDR,
1da177e4
LT		 886 (force_subclients[2] & 0x07) |
887 ((force_subclients[3] & 0x07) << 4));
0217eae3 888 sc_addr[0] = force_subclients[2];
1da177e4 889 } else {
31b8dc4d 890 val1 = w83781d_read_value(data, W83781D_REG_I2C_SUBADDR);
0217eae3 891 sc_addr[0] = 0x48 + (val1 & 0x07);
1da177e4
LT		 892 }
893
894 if (kind != w83783s) {
bbc8a569 895 num_sc = 2;
1da177e4
LT		 896 if (force_subclients[0] == id &&
897 force_subclients[1] == address) {
0217eae3 898 sc_addr[1] = force_subclients[3];
1da177e4 899 } else {
0217eae3 900 sc_addr[1] = 0x48 + ((val1 >> 4) & 0x07);
1da177e4 901 }
0217eae3 902 if (sc_addr[0] == sc_addr[1]) {
1da177e4
LT		 903 dev_err(&new_client->dev,
904 "Duplicate addresses 0x%x for subclients.\n",
0217eae3 905 sc_addr[0]);
1da177e4
LT		 906 err = -EBUSY;
907 goto ERROR_SC_2;
908 }
909 }
910
bbc8a569 911 for (i = 0; i < num_sc; i++) {
0217eae3
WG		 912 data->lm75[i] = i2c_new_dummy(adapter, sc_addr[i]);
913 if (!data->lm75[i]) {
1da177e4
LT		 914 dev_err(&new_client->dev, "Subclient %d "
915 "registration at address 0x%x "
0217eae3
WG		 916 "failed.\n", i, sc_addr[i]);
917 err = -ENOMEM;
1da177e4
LT		 918 if (i == 1)
919 goto ERROR_SC_3;
920 goto ERROR_SC_2;
921 }
1da177e4
LT		 922 }
923
924 return 0;
925
926/* Undo inits in case of errors */
927ERROR_SC_3:
0217eae3 928 i2c_unregister_device(data->lm75[0]);
1da177e4 929ERROR_SC_2:
1da177e4 930ERROR_SC_1:
1da177e4
LT		 931 return err;
932}
933
34875337
JD		 934#define IN_UNIT_ATTRS(X) \
935 &sensor_dev_attr_in##X##_input.dev_attr.attr, \
936 &sensor_dev_attr_in##X##_min.dev_attr.attr, \
293c0997 937 &sensor_dev_attr_in##X##_max.dev_attr.attr, \
7d4a1374
JD		 938 &sensor_dev_attr_in##X##_alarm.dev_attr.attr, \
939 &sensor_dev_attr_in##X##_beep.dev_attr.attr
311ce2ef 940
34875337
JD		 941#define FAN_UNIT_ATTRS(X) \
942 &sensor_dev_attr_fan##X##_input.dev_attr.attr, \
943 &sensor_dev_attr_fan##X##_min.dev_attr.attr, \
7d4a1374
JD		 944 &sensor_dev_attr_fan##X##_div.dev_attr.attr, \
945 &sensor_dev_attr_fan##X##_alarm.dev_attr.attr, \
946 &sensor_dev_attr_fan##X##_beep.dev_attr.attr
311ce2ef 947
34875337
JD		 948#define TEMP_UNIT_ATTRS(X) \
949 &sensor_dev_attr_temp##X##_input.dev_attr.attr, \
950 &sensor_dev_attr_temp##X##_max.dev_attr.attr, \
7d4a1374
JD		 951 &sensor_dev_attr_temp##X##_max_hyst.dev_attr.attr, \
952 &sensor_dev_attr_temp##X##_alarm.dev_attr.attr, \
953 &sensor_dev_attr_temp##X##_beep.dev_attr.attr
311ce2ef 954
c531eb3f 955static struct attribute *w83781d_attributes[] = {
311ce2ef
JC		 956 IN_UNIT_ATTRS(0),
957 IN_UNIT_ATTRS(2),
958 IN_UNIT_ATTRS(3),
959 IN_UNIT_ATTRS(4),
960 IN_UNIT_ATTRS(5),
961 IN_UNIT_ATTRS(6),
962 FAN_UNIT_ATTRS(1),
963 FAN_UNIT_ATTRS(2),
964 FAN_UNIT_ATTRS(3),
965 TEMP_UNIT_ATTRS(1),
966 TEMP_UNIT_ATTRS(2),
967 &dev_attr_cpu0_vid.attr,
968 &dev_attr_vrm.attr,
969 &dev_attr_alarms.attr,
970 &dev_attr_beep_mask.attr,
2fbbbf14 971 &sensor_dev_attr_beep_enable.dev_attr.attr,
311ce2ef
JC		 972 NULL
973};
974static const struct attribute_group w83781d_group = {
975 .attrs = w83781d_attributes,
976};
977
79501333 978static struct attribute *w83781d_attributes_in1[] = {
311ce2ef 979 IN_UNIT_ATTRS(1),
79501333
GR		 980 NULL
981};
982static const struct attribute_group w83781d_group_in1 = {
983 .attrs = w83781d_attributes_in1,
984};
985
986static struct attribute *w83781d_attributes_in78[] = {
311ce2ef
JC		 987 IN_UNIT_ATTRS(7),
988 IN_UNIT_ATTRS(8),
79501333
GR		 989 NULL
990};
991static const struct attribute_group w83781d_group_in78 = {
992 .attrs = w83781d_attributes_in78,
993};
994
995static struct attribute *w83781d_attributes_temp3[] = {
311ce2ef 996 TEMP_UNIT_ATTRS(3),
79501333
GR		 997 NULL
998};
999static const struct attribute_group w83781d_group_temp3 = {
1000 .attrs = w83781d_attributes_temp3,
1001};
1002
1003static struct attribute *w83781d_attributes_pwm12[] = {
34875337
JD		 1004 &sensor_dev_attr_pwm1.dev_attr.attr,
1005 &sensor_dev_attr_pwm2.dev_attr.attr,
79501333
GR		 1006 &dev_attr_pwm2_enable.attr,
1007 NULL
1008};
1009static const struct attribute_group w83781d_group_pwm12 = {
1010 .attrs = w83781d_attributes_pwm12,
1011};
1012
1013static struct attribute *w83781d_attributes_pwm34[] = {
34875337
JD		 1014 &sensor_dev_attr_pwm3.dev_attr.attr,
1015 &sensor_dev_attr_pwm4.dev_attr.attr,
79501333
GR		 1016 NULL
1017};
1018static const struct attribute_group w83781d_group_pwm34 = {
1019 .attrs = w83781d_attributes_pwm34,
1020};
1021
1022static struct attribute *w83781d_attributes_other[] = {
34875337
JD		 1023 &sensor_dev_attr_temp1_type.dev_attr.attr,
1024 &sensor_dev_attr_temp2_type.dev_attr.attr,
1025 &sensor_dev_attr_temp3_type.dev_attr.attr,
311ce2ef
JC		 1026 NULL
1027};
79501333
GR		 1028static const struct attribute_group w83781d_group_other = {
1029 .attrs = w83781d_attributes_other,
311ce2ef
JC		 1030};
1031
7666c13c 1032/* No clean up is done on error, it's up to the caller */
1da177e4 1033static int
7666c13c 1034w83781d_create_files(struct device *dev, int kind, int is_isa)
1da177e4 1035{
1da177e4 1036 int err;
1da177e4 1037
c531eb3f
GR		 1038 err = sysfs_create_group(&dev->kobj, &w83781d_group);
1039 if (err)
7666c13c
JD		 1040 return err;
1041
1042 if (kind != w83783s) {
79501333
GR		 1043 err = sysfs_create_group(&dev->kobj, &w83781d_group_in1);
1044 if (err)
7666c13c
JD		 1045 return err;
1046 }
1047 if (kind != as99127f && kind != w83781d && kind != w83783s) {
79501333
GR		 1048 err = sysfs_create_group(&dev->kobj, &w83781d_group_in78);
1049 if (err)
7666c13c
JD		 1050 return err;
1051 }
1052 if (kind != w83783s) {
79501333
GR		 1053 err = sysfs_create_group(&dev->kobj, &w83781d_group_temp3);
1054 if (err)
7666c13c 1055 return err;
7d4a1374 1056
7768aa76 1057 if (kind != w83781d) {
7d4a1374
JD		 1058 err = sysfs_chmod_file(&dev->kobj,
1059 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1060 S_IRUGO | S_IWUSR);
1061 if (err)
1062 return err;
7768aa76 1063 }
1da177e4
LT		 1064 }
1065
7666c13c 1066 if (kind != w83781d && kind != as99127f) {
79501333
GR		 1067 err = sysfs_create_group(&dev->kobj, &w83781d_group_pwm12);
1068 if (err)
7666c13c 1069 return err;
1da177e4 1070 }
7666c13c 1071 if (kind == w83782d && !is_isa) {
79501333
GR		 1072 err = sysfs_create_group(&dev->kobj, &w83781d_group_pwm34);
1073 if (err)
7666c13c
JD		 1074 return err;
1075 }
1076
1077 if (kind != as99127f && kind != w83781d) {
79501333
GR		 1078 err = device_create_file(dev,
1079 &sensor_dev_attr_temp1_type.dev_attr);
1080 if (err)
1081 return err;
1082 err = device_create_file(dev,
1083 &sensor_dev_attr_temp2_type.dev_attr);
1084 if (err)
7666c13c
JD		 1085 return err;
1086 if (kind != w83783s) {
c531eb3f 1087 err = device_create_file(dev,
79501333 1088 &sensor_dev_attr_temp3_type.dev_attr);
c531eb3f 1089 if (err)
7666c13c 1090 return err;
1da177e4 1091 }
7666c13c 1092 }
1da177e4 1093
7666c13c
JD		 1094 return 0;
1095}
1da177e4 1096
0217eae3 1097/* Return 0 if detection is successful, -ENODEV otherwise */
7666c13c 1098static int
310ec792 1099w83781d_detect(struct i2c_client *client, struct i2c_board_info *info)
7666c13c 1100{
bab2bf44 1101 int val1, val2;
0217eae3
WG		 1102 struct w83781d_data *isa = w83781d_data_if_isa();
1103 struct i2c_adapter *adapter = client->adapter;
1104 int address = client->addr;
bab2bf44 1105 const char *client_name;
7666c13c
JD		 1106 enum vendor { winbond, asus } vendid;
1107
0217eae3
WG		 1108 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1109 return -ENODEV;
1da177e4 1110
aff6e00e
GR		 1111 /*
1112 * We block updates of the ISA device to minimize the risk of
1113 * concurrent access to the same W83781D chip through different
1114 * interfaces.
1115 */
0217eae3
WG		 1116 if (isa)
1117 mutex_lock(&isa->update_lock);
1da177e4 1118
bab2bf44
JD		 1119 if (i2c_smbus_read_byte_data(client, W83781D_REG_CONFIG) & 0x80) {
1120 dev_dbg(&adapter->dev,
1121 "Detection of w83781d chip failed at step 3\n");
1122 goto err_nodev;
1123 }
1124
1125 val1 = i2c_smbus_read_byte_data(client, W83781D_REG_BANK);
1126 val2 = i2c_smbus_read_byte_data(client, W83781D_REG_CHIPMAN);
1127 /* Check for Winbond or Asus ID if in bank 0 */
1128 if (!(val1 & 0x07) &&
1129 ((!(val1 & 0x80) && val2 != 0xa3 && val2 != 0xc3) ||
c531eb3f 1130 ((val1 & 0x80) && val2 != 0x5c && val2 != 0x12))) {
bab2bf44
JD		 1131 dev_dbg(&adapter->dev,
1132 "Detection of w83781d chip failed at step 4\n");
1133 goto err_nodev;
1134 }
aff6e00e
GR		 1135 /*
1136 * If Winbond SMBus, check address at 0x48.
1137 * Asus doesn't support, except for as99127f rev.2
1138 */
bab2bf44 1139 if ((!(val1 & 0x80) && val2 == 0xa3) ||
c531eb3f 1140 ((val1 & 0x80) && val2 == 0x5c)) {
bab2bf44
JD		 1141 if (i2c_smbus_read_byte_data(client, W83781D_REG_I2C_ADDR)
1142 != address) {
1143 dev_dbg(&adapter->dev,
1144 "Detection of w83781d chip failed at step 5\n");
0217eae3 1145 goto err_nodev;
1da177e4 1146 }
1da177e4
LT		 1147 }
1148
bab2bf44 1149 /* Put it now into bank 0 and Vendor ID High Byte */
0217eae3
WG		 1150 i2c_smbus_write_byte_data(client, W83781D_REG_BANK,
1151 (i2c_smbus_read_byte_data(client, W83781D_REG_BANK)
1152 & 0x78) | 0x80);
1da177e4 1153
bab2bf44
JD		 1154 /* Get the vendor ID */
1155 val2 = i2c_smbus_read_byte_data(client, W83781D_REG_CHIPMAN);
1156 if (val2 == 0x5c)
1157 vendid = winbond;
1158 else if (val2 == 0x12)
1159 vendid = asus;
1160 else {
1161 dev_dbg(&adapter->dev,
1162 "w83781d chip vendor is neither Winbond nor Asus\n");
1163 goto err_nodev;
1da177e4
LT		 1164 }
1165
bab2bf44
JD		 1166 /* Determine the chip type. */
1167 val1 = i2c_smbus_read_byte_data(client, W83781D_REG_WCHIPID);
1168 if ((val1 == 0x10 || val1 == 0x11) && vendid == winbond)
1da177e4 1169 client_name = "w83781d";
bab2bf44 1170 else if (val1 == 0x30 && vendid == winbond)
1da177e4 1171 client_name = "w83782d";
bab2bf44 1172 else if (val1 == 0x40 && vendid == winbond && address == 0x2d)
1da177e4 1173 client_name = "w83783s";
bab2bf44 1174 else if (val1 == 0x31)
1da177e4 1175 client_name = "as99127f";
bab2bf44
JD		 1176 else
1177 goto err_nodev;
1178
1179 if (val1 <= 0x30 && w83781d_alias_detect(client, val1)) {
1180 dev_dbg(&adapter->dev, "Device at 0x%02x appears to "
1181 "be the same as ISA device\n", address);
1182 goto err_nodev;
1da177e4
LT		 1183 }
1184
bab2bf44
JD		 1185 if (isa)
1186 mutex_unlock(&isa->update_lock);
1187
0217eae3
WG		 1188 strlcpy(info->type, client_name, I2C_NAME_SIZE);
1189
1190 return 0;
1191
1192 err_nodev:
1193 if (isa)
1194 mutex_unlock(&isa->update_lock);
1195 return -ENODEV;
1196}
1197
79501333
GR		 1198static void w83781d_remove_files(struct device *dev)
1199{
1200 sysfs_remove_group(&dev->kobj, &w83781d_group);
1201 sysfs_remove_group(&dev->kobj, &w83781d_group_in1);
1202 sysfs_remove_group(&dev->kobj, &w83781d_group_in78);
1203 sysfs_remove_group(&dev->kobj, &w83781d_group_temp3);
1204 sysfs_remove_group(&dev->kobj, &w83781d_group_pwm12);
1205 sysfs_remove_group(&dev->kobj, &w83781d_group_pwm34);
1206 sysfs_remove_group(&dev->kobj, &w83781d_group_other);
1207}
1208
0217eae3
WG		 1209static int
1210w83781d_probe(struct i2c_client *client, const struct i2c_device_id *id)
1211{
1212 struct device *dev = &client->dev;
1213 struct w83781d_data *data;
1214 int err;
1215
144d2b99
GR		 1216 data = devm_kzalloc(dev, sizeof(struct w83781d_data), GFP_KERNEL);
1217 if (!data)
1218 return -ENOMEM;
0217eae3
WG		 1219
1220 i2c_set_clientdata(client, data);
1221 mutex_init(&data->lock);
1222 mutex_init(&data->update_lock);
1da177e4 1223
0217eae3
WG		 1224 data->type = id->driver_data;
1225 data->client = client;
1da177e4
LT		 1226
1227 /* attach secondary i2c lm75-like clients */
0217eae3
WG		 1228 err = w83781d_detect_subclients(client);
1229 if (err)
144d2b99 1230 return err;
1da177e4
LT		 1231
1232 /* Initialize the chip */
7666c13c 1233 w83781d_init_device(dev);
1da177e4
LT		 1234
1235 /* Register sysfs hooks */
0217eae3 1236 err = w83781d_create_files(dev, data->type, 0);
7666c13c 1237 if (err)
144d2b99 1238 goto exit_remove_files;
943b0830 1239
1beeffe4
TJ		 1240 data->hwmon_dev = hwmon_device_register(dev);
1241 if (IS_ERR(data->hwmon_dev)) {
1242 err = PTR_ERR(data->hwmon_dev);
144d2b99 1243 goto exit_remove_files;
1da177e4
LT		 1244 }
1245
1246 return 0;
1247
144d2b99 1248 exit_remove_files:
79501333 1249 w83781d_remove_files(dev);
0217eae3
WG		 1250 if (data->lm75[0])
1251 i2c_unregister_device(data->lm75[0]);
1252 if (data->lm75[1])
1253 i2c_unregister_device(data->lm75[1]);
1da177e4
LT		 1254 return err;
1255}
1256
1257static int
0217eae3 1258w83781d_remove(struct i2c_client *client)
1da177e4 1259{
943b0830 1260 struct w83781d_data *data = i2c_get_clientdata(client);
0217eae3 1261 struct device *dev = &client->dev;
1da177e4 1262
0217eae3 1263 hwmon_device_unregister(data->hwmon_dev);
79501333 1264 w83781d_remove_files(dev);
1da177e4 1265
0217eae3
WG		 1266 if (data->lm75[0])
1267 i2c_unregister_device(data->lm75[0]);
1268 if (data->lm75[1])
1269 i2c_unregister_device(data->lm75[1]);
943b0830 1270
1da177e4
LT		 1271 return 0;
1272}
1273
1da177e4 1274static int
443850ce 1275w83781d_read_value_i2c(struct w83781d_data *data, u16 reg)
1da177e4 1276{
0217eae3 1277 struct i2c_client *client = data->client;
443850ce 1278 int res, bank;
1da177e4
LT		 1279 struct i2c_client *cl;
1280
443850ce
WG		 1281 bank = (reg >> 8) & 0x0f;
1282 if (bank > 2)
1283 /* switch banks */
1284 i2c_smbus_write_byte_data(client, W83781D_REG_BANK,
1285 bank);
1286 if (bank == 0 || bank > 2) {
1287 res = i2c_smbus_read_byte_data(client, reg & 0xff);
1da177e4 1288 } else {
443850ce
WG		 1289 /* switch to subclient */
1290 cl = data->lm75[bank - 1];
1291 /* convert from ISA to LM75 I2C addresses */
1292 switch (reg & 0xff) {
1293 case 0x50: /* TEMP */
90f4102c 1294 res = i2c_smbus_read_word_swapped(cl, 0);
443850ce
WG		 1295 break;
1296 case 0x52: /* CONFIG */
1297 res = i2c_smbus_read_byte_data(cl, 1);
1298 break;
1299 case 0x53: /* HYST */
90f4102c 1300 res = i2c_smbus_read_word_swapped(cl, 2);
443850ce
WG		 1301 break;
1302 case 0x55: /* OVER */
1303 default:
90f4102c 1304 res = i2c_smbus_read_word_swapped(cl, 3);
443850ce 1305 break;
1da177e4 1306 }
1da177e4 1307 }
443850ce
WG		 1308 if (bank > 2)
1309 i2c_smbus_write_byte_data(client, W83781D_REG_BANK, 0);
1310
1da177e4
LT		 1311 return res;
1312}
1313
1314static int
443850ce 1315w83781d_write_value_i2c(struct w83781d_data *data, u16 reg, u16 value)
1da177e4 1316{
0217eae3 1317 struct i2c_client *client = data->client;
443850ce 1318 int bank;
1da177e4
LT		 1319 struct i2c_client *cl;
1320
443850ce
WG		 1321 bank = (reg >> 8) & 0x0f;
1322 if (bank > 2)
1323 /* switch banks */
1324 i2c_smbus_write_byte_data(client, W83781D_REG_BANK,
1325 bank);
1326 if (bank == 0 || bank > 2) {
1327 i2c_smbus_write_byte_data(client, reg & 0xff,
1328 value & 0xff);
1da177e4 1329 } else {
443850ce
WG		 1330 /* switch to subclient */
1331 cl = data->lm75[bank - 1];
1332 /* convert from ISA to LM75 I2C addresses */
1333 switch (reg & 0xff) {
1334 case 0x52: /* CONFIG */
1335 i2c_smbus_write_byte_data(cl, 1, value & 0xff);
1336 break;
1337 case 0x53: /* HYST */
90f4102c 1338 i2c_smbus_write_word_swapped(cl, 2, value);
443850ce
WG		 1339 break;
1340 case 0x55: /* OVER */
90f4102c 1341 i2c_smbus_write_word_swapped(cl, 3, value);
443850ce 1342 break;
1da177e4 1343 }
1da177e4 1344 }
443850ce
WG		 1345 if (bank > 2)
1346 i2c_smbus_write_byte_data(client, W83781D_REG_BANK, 0);
1347
1da177e4
LT		 1348 return 0;
1349}
1350
1da177e4 1351static void
7666c13c 1352w83781d_init_device(struct device *dev)
1da177e4 1353{
7666c13c 1354 struct w83781d_data *data = dev_get_drvdata(dev);
1da177e4
LT		 1355 int i, p;
1356 int type = data->type;
1357 u8 tmp;
1358
aff6e00e
GR		 1359 if (reset && type != as99127f) { /*
1360 * this resets registers we don't have
1361 * documentation for on the as99127f
1362 */
1363 /*
1364 * Resetting the chip has been the default for a long time,
1365 * but it causes the BIOS initializations (fan clock dividers,
1366 * thermal sensor types...) to be lost, so it is now optional.
1367 * It might even go away if nobody reports it as being useful,
1368 * as I see very little reason why this would be needed at
1369 * all.
1370 */
7666c13c 1371 dev_info(dev, "If reset=1 solved a problem you were "
fabddcd4
JD		 1372 "having, please report!\n");
1373
1da177e4 1374 /* save these registers */
31b8dc4d
JD		 1375 i = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG);
1376 p = w83781d_read_value(data, W83781D_REG_PWMCLK12);
aff6e00e
GR		 1377 /*
1378 * Reset all except Watchdog values and last conversion values
1379 * This sets fan-divs to 2, among others
1380 */
31b8dc4d 1381 w83781d_write_value(data, W83781D_REG_CONFIG, 0x80);
aff6e00e
GR		 1382 /*
1383 * Restore the registers and disable power-on abnormal beep.
1384 * This saves FAN 1/2/3 input/output values set by BIOS.
1385 */
31b8dc4d
JD		 1386 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
1387 w83781d_write_value(data, W83781D_REG_PWMCLK12, p);
c531eb3f
GR		 1388 /*
1389 * Disable master beep-enable (reset turns it on).
1390 * Individual beep_mask should be reset to off but for some
1391 * reason disabling this bit helps some people not get beeped
1392 */
31b8dc4d 1393 w83781d_write_value(data, W83781D_REG_BEEP_INTS2, 0);
1da177e4
LT		 1394 }
1395
aff6e00e
GR		 1396 /*
1397 * Disable power-on abnormal beep, as advised by the datasheet.
1398 * Already done if reset=1.
1399 */
fabddcd4 1400 if (init && !reset && type != as99127f) {
31b8dc4d
JD		 1401 i = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG);
1402 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
fabddcd4
JD		 1403 }
1404
303760b4 1405 data->vrm = vid_which_vrm();
1da177e4
LT		 1406
1407 if ((type != w83781d) && (type != as99127f)) {
31b8dc4d 1408 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
1da177e4
LT		 1409 for (i = 1; i <= 3; i++) {
1410 if (!(tmp & BIT_SCFG1[i - 1])) {
b26f9330 1411 data->sens[i - 1] = 4;
1da177e4
LT		 1412 } else {
1413 if (w83781d_read_value
31b8dc4d 1414 (data,
1da177e4
LT		 1415 W83781D_REG_SCFG2) & BIT_SCFG2[i - 1])
1416 data->sens[i - 1] = 1;
1417 else
1418 data->sens[i - 1] = 2;
1419 }
7c7a5304 1420 if (type == w83783s && i == 2)
1da177e4
LT		 1421 break;
1422 }
1423 }
1424
1425 if (init && type != as99127f) {
1426 /* Enable temp2 */
31b8dc4d 1427 tmp = w83781d_read_value(data, W83781D_REG_TEMP2_CONFIG);
1da177e4 1428 if (tmp & 0x01) {
7666c13c 1429 dev_warn(dev, "Enabling temp2, readings "
1da177e4 1430 "might not make sense\n");
31b8dc4d 1431 w83781d_write_value(data, W83781D_REG_TEMP2_CONFIG,
1da177e4
LT		 1432 tmp & 0xfe);
1433 }
1434
1435 /* Enable temp3 */
7c7a5304 1436 if (type != w83783s) {
31b8dc4d 1437 tmp = w83781d_read_value(data,
1da177e4
LT		 1438 W83781D_REG_TEMP3_CONFIG);
1439 if (tmp & 0x01) {
7666c13c 1440 dev_warn(dev, "Enabling temp3, "
1da177e4 1441 "readings might not make sense\n");
31b8dc4d 1442 w83781d_write_value(data,
1da177e4
LT		 1443 W83781D_REG_TEMP3_CONFIG, tmp & 0xfe);
1444 }
1445 }
1da177e4
LT		 1446 }
1447
1448 /* Start monitoring */
31b8dc4d
JD		 1449 w83781d_write_value(data, W83781D_REG_CONFIG,
1450 (w83781d_read_value(data,
1da177e4
LT		 1451 W83781D_REG_CONFIG) & 0xf7)
1452 | 0x01);
7666c13c
JD		 1453
1454 /* A few vars need to be filled upon startup */
34875337
JD		 1455 for (i = 0; i < 3; i++) {
1456 data->fan_min[i] = w83781d_read_value(data,
7666c13c
JD		 1457 W83781D_REG_FAN_MIN(i));
1458 }
7666c13c
JD		 1459
1460 mutex_init(&data->update_lock);
1da177e4
LT		 1461}
1462
1463static struct w83781d_data *w83781d_update_device(struct device *dev)
1464{
7666c13c 1465 struct w83781d_data *data = dev_get_drvdata(dev);
0217eae3 1466 struct i2c_client *client = data->client;
1da177e4
LT		 1467 int i;
1468
9a61bf63 1469 mutex_lock(&data->update_lock);
1da177e4
LT		 1470
1471 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1472 || !data->valid) {
1473 dev_dbg(dev, "Starting device update\n");
1474
1475 for (i = 0; i <= 8; i++) {
7c7a5304 1476 if (data->type == w83783s && i == 1)
1da177e4
LT		 1477 continue; /* 783S has no in1 */
1478 data->in[i] =
31b8dc4d 1479 w83781d_read_value(data, W83781D_REG_IN(i));
1da177e4 1480 data->in_min[i] =
31b8dc4d 1481 w83781d_read_value(data, W83781D_REG_IN_MIN(i));
1da177e4 1482 data->in_max[i] =
31b8dc4d 1483 w83781d_read_value(data, W83781D_REG_IN_MAX(i));
05663368 1484 if ((data->type != w83782d) && (i == 6))
1da177e4
LT		 1485 break;
1486 }
34875337
JD		 1487 for (i = 0; i < 3; i++) {
1488 data->fan[i] =
31b8dc4d 1489 w83781d_read_value(data, W83781D_REG_FAN(i));
34875337 1490 data->fan_min[i] =
31b8dc4d 1491 w83781d_read_value(data, W83781D_REG_FAN_MIN(i));
1da177e4
LT		 1492 }
1493 if (data->type != w83781d && data->type != as99127f) {
34875337
JD		 1494 for (i = 0; i < 4; i++) {
1495 data->pwm[i] =
31b8dc4d 1496 w83781d_read_value(data,
34875337 1497 W83781D_REG_PWM[i]);
848ddf11
JD		 1498 /* Only W83782D on SMBus has PWM3 and PWM4 */
1499 if ((data->type != w83782d || !client)
34875337 1500 && i == 1)
1da177e4
LT		 1501 break;
1502 }
1503 /* Only PWM2 can be disabled */
34875337 1504 data->pwm2_enable = (w83781d_read_value(data,
c531eb3f 1505 W83781D_REG_PWMCLK12) & 0x08) >> 3;
1da177e4
LT		 1506 }
1507
31b8dc4d 1508 data->temp = w83781d_read_value(data, W83781D_REG_TEMP(1));
1da177e4 1509 data->temp_max =
31b8dc4d 1510 w83781d_read_value(data, W83781D_REG_TEMP_OVER(1));
1da177e4 1511 data->temp_max_hyst =
31b8dc4d 1512 w83781d_read_value(data, W83781D_REG_TEMP_HYST(1));
1da177e4 1513 data->temp_add[0] =
31b8dc4d 1514 w83781d_read_value(data, W83781D_REG_TEMP(2));
1da177e4 1515 data->temp_max_add[0] =
31b8dc4d 1516 w83781d_read_value(data, W83781D_REG_TEMP_OVER(2));
1da177e4 1517 data->temp_max_hyst_add[0] =
31b8dc4d 1518 w83781d_read_value(data, W83781D_REG_TEMP_HYST(2));
7c7a5304 1519 if (data->type != w83783s) {
1da177e4 1520 data->temp_add[1] =
31b8dc4d 1521 w83781d_read_value(data, W83781D_REG_TEMP(3));
1da177e4 1522 data->temp_max_add[1] =
31b8dc4d 1523 w83781d_read_value(data,
1da177e4
LT		 1524 W83781D_REG_TEMP_OVER(3));
1525 data->temp_max_hyst_add[1] =
31b8dc4d 1526 w83781d_read_value(data,
1da177e4
LT		 1527 W83781D_REG_TEMP_HYST(3));
1528 }
31b8dc4d 1529 i = w83781d_read_value(data, W83781D_REG_VID_FANDIV);
7c7a5304 1530 data->vid = i & 0x0f;
31b8dc4d 1531 data->vid |= (w83781d_read_value(data,
7c7a5304 1532 W83781D_REG_CHIPID) & 0x01) << 4;
1da177e4
LT		 1533 data->fan_div[0] = (i >> 4) & 0x03;
1534 data->fan_div[1] = (i >> 6) & 0x03;
31b8dc4d 1535 data->fan_div[2] = (w83781d_read_value(data,
7c7a5304 1536 W83781D_REG_PIN) >> 6) & 0x03;
1da177e4 1537 if ((data->type != w83781d) && (data->type != as99127f)) {
31b8dc4d 1538 i = w83781d_read_value(data, W83781D_REG_VBAT);
1da177e4
LT		 1539 data->fan_div[0] |= (i >> 3) & 0x04;
1540 data->fan_div[1] |= (i >> 4) & 0x04;
7c7a5304 1541 data->fan_div[2] |= (i >> 5) & 0x04;
1da177e4 1542 }
05663368 1543 if (data->type == w83782d) {
31b8dc4d 1544 data->alarms = w83781d_read_value(data,
c7f5d7ed 1545 W83782D_REG_ALARM1)
31b8dc4d 1546 | (w83781d_read_value(data,
c7f5d7ed 1547 W83782D_REG_ALARM2) << 8)
31b8dc4d 1548 | (w83781d_read_value(data,
c7f5d7ed
JD		 1549 W83782D_REG_ALARM3) << 16);
1550 } else if (data->type == w83783s) {
31b8dc4d 1551 data->alarms = w83781d_read_value(data,
c7f5d7ed 1552 W83782D_REG_ALARM1)
31b8dc4d 1553 | (w83781d_read_value(data,
c7f5d7ed
JD		 1554 W83782D_REG_ALARM2) << 8);
1555 } else {
aff6e00e
GR		 1556 /*
1557 * No real-time status registers, fall back to
1558 * interrupt status registers
1559 */
31b8dc4d 1560 data->alarms = w83781d_read_value(data,
c7f5d7ed 1561 W83781D_REG_ALARM1)
31b8dc4d 1562 | (w83781d_read_value(data,
c7f5d7ed 1563 W83781D_REG_ALARM2) << 8);
1da177e4 1564 }
31b8dc4d 1565 i = w83781d_read_value(data, W83781D_REG_BEEP_INTS2);
2fbbbf14 1566 data->beep_mask = (i << 8) +
31b8dc4d 1567 w83781d_read_value(data, W83781D_REG_BEEP_INTS1);
1da177e4
LT		 1568 if ((data->type != w83781d) && (data->type != as99127f)) {
1569 data->beep_mask |=
31b8dc4d 1570 w83781d_read_value(data,
1da177e4
LT		 1571 W83781D_REG_BEEP_INTS3) << 16;
1572 }
1573 data->last_updated = jiffies;
1574 data->valid = 1;
1575 }
1576
9a61bf63 1577 mutex_unlock(&data->update_lock);
1da177e4
LT		 1578
1579 return data;
1580}
1581
0217eae3
WG		 1582static const struct i2c_device_id w83781d_ids[] = {
1583 { "w83781d", w83781d, },
1584 { "w83782d", w83782d, },
1585 { "w83783s", w83783s, },
1586 { "as99127f", as99127f },
1587 { /* LIST END */ }
1588};
1589MODULE_DEVICE_TABLE(i2c, w83781d_ids);
1590
1591static struct i2c_driver w83781d_driver = {
1592 .class = I2C_CLASS_HWMON,
1593 .driver = {
1594 .name = "w83781d",
1595 },
1596 .probe = w83781d_probe,
1597 .remove = w83781d_remove,
1598 .id_table = w83781d_ids,
1599 .detect = w83781d_detect,
c3813d6a 1600 .address_list = normal_i2c,
0217eae3
WG		 1601};
1602
1603/*
1604 * ISA related code
1605 */
443850ce
WG		 1606#ifdef CONFIG_ISA
1607
1608/* ISA device, if found */
1609static struct platform_device *pdev;
1610
1611static unsigned short isa_address = 0x290;
1612
aff6e00e
GR		 1613/*
1614 * I2C devices get this name attribute automatically, but for ISA devices
1615 * we must create it by ourselves.
1616 */
443850ce
WG		 1617static ssize_t
1618show_name(struct device *dev, struct device_attribute *devattr, char *buf)
1619{
1620 struct w83781d_data *data = dev_get_drvdata(dev);
360782dd 1621 return sprintf(buf, "%s\n", data->name);
443850ce
WG		 1622}
1623static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1624
1625static struct w83781d_data *w83781d_data_if_isa(void)
1626{
1627 return pdev ? platform_get_drvdata(pdev) : NULL;
1628}
1629
1630/* Returns 1 if the I2C chip appears to be an alias of the ISA chip */
1631static int w83781d_alias_detect(struct i2c_client *client, u8 chipid)
1632{
0217eae3 1633 struct w83781d_data *isa;
443850ce
WG		 1634 int i;
1635
1636 if (!pdev) /* No ISA chip */
1637 return 0;
1638
443850ce
WG		 1639 isa = platform_get_drvdata(pdev);
1640
1641 if (w83781d_read_value(isa, W83781D_REG_I2C_ADDR) != client->addr)
1642 return 0; /* Address doesn't match */
1643 if (w83781d_read_value(isa, W83781D_REG_WCHIPID) != chipid)
1644 return 0; /* Chip type doesn't match */
1645
aff6e00e
GR		 1646 /*
1647 * We compare all the limit registers, the config register and the
1648 * interrupt mask registers
1649 */
443850ce 1650 for (i = 0x2b; i <= 0x3d; i++) {
0217eae3
WG		 1651 if (w83781d_read_value(isa, i) !=
1652 i2c_smbus_read_byte_data(client, i))
443850ce
WG		 1653 return 0;
1654 }
1655 if (w83781d_read_value(isa, W83781D_REG_CONFIG) !=
0217eae3 1656 i2c_smbus_read_byte_data(client, W83781D_REG_CONFIG))
443850ce
WG		 1657 return 0;
1658 for (i = 0x43; i <= 0x46; i++) {
0217eae3
WG		 1659 if (w83781d_read_value(isa, i) !=
1660 i2c_smbus_read_byte_data(client, i))
443850ce
WG		 1661 return 0;
1662 }
1663
1664 return 1;
1665}
1666
1667static int
1668w83781d_read_value_isa(struct w83781d_data *data, u16 reg)
1669{
443850ce
WG		 1670 int word_sized, res;
1671
1672 word_sized = (((reg & 0xff00) == 0x100)
1673 || ((reg & 0xff00) == 0x200))
1674 && (((reg & 0x00ff) == 0x50)
1675 || ((reg & 0x00ff) == 0x53)
1676 || ((reg & 0x00ff) == 0x55));
1677 if (reg & 0xff00) {
1678 outb_p(W83781D_REG_BANK,
360782dd 1679 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1680 outb_p(reg >> 8,
360782dd 1681 data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce 1682 }
360782dd
JD		 1683 outb_p(reg & 0xff, data->isa_addr + W83781D_ADDR_REG_OFFSET);
1684 res = inb_p(data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1685 if (word_sized) {
1686 outb_p((reg & 0xff) + 1,
360782dd 1687 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1688 res =
360782dd 1689 (res << 8) + inb_p(data->isa_addr +
443850ce
WG		 1690 W83781D_DATA_REG_OFFSET);
1691 }
1692 if (reg & 0xff00) {
1693 outb_p(W83781D_REG_BANK,
360782dd
JD		 1694 data->isa_addr + W83781D_ADDR_REG_OFFSET);
1695 outb_p(0, data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1696 }
1697 return res;
1698}
1699
1700static void
1701w83781d_write_value_isa(struct w83781d_data *data, u16 reg, u16 value)
1702{
443850ce
WG		 1703 int word_sized;
1704
1705 word_sized = (((reg & 0xff00) == 0x100)
1706 || ((reg & 0xff00) == 0x200))
1707 && (((reg & 0x00ff) == 0x53)
1708 || ((reg & 0x00ff) == 0x55));
1709 if (reg & 0xff00) {
1710 outb_p(W83781D_REG_BANK,
360782dd 1711 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1712 outb_p(reg >> 8,
360782dd 1713 data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce 1714 }
360782dd 1715 outb_p(reg & 0xff, data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce
WG		 1716 if (word_sized) {
1717 outb_p(value >> 8,
360782dd 1718 data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce 1719 outb_p((reg & 0xff) + 1,
360782dd 1720 data->isa_addr + W83781D_ADDR_REG_OFFSET);
443850ce 1721 }
360782dd 1722 outb_p(value & 0xff, data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1723 if (reg & 0xff00) {
1724 outb_p(W83781D_REG_BANK,
360782dd
JD		 1725 data->isa_addr + W83781D_ADDR_REG_OFFSET);
1726 outb_p(0, data->isa_addr + W83781D_DATA_REG_OFFSET);
443850ce
WG		 1727 }
1728}
1729
aff6e00e
GR		 1730/*
1731 * The SMBus locks itself, usually, but nothing may access the Winbond between
1732 * bank switches. ISA access must always be locked explicitly!
1733 * We ignore the W83781D BUSY flag at this moment - it could lead to deadlocks,
1734 * would slow down the W83781D access and should not be necessary.
1735 * There are some ugly typecasts here, but the good news is - they should
1736 * nowhere else be necessary!
1737 */
443850ce
WG		 1738static int
1739w83781d_read_value(struct w83781d_data *data, u16 reg)
1740{
0217eae3 1741 struct i2c_client *client = data->client;
443850ce
WG		 1742 int res;
1743
1744 mutex_lock(&data->lock);
0217eae3 1745 if (client)
443850ce
WG		 1746 res = w83781d_read_value_i2c(data, reg);
1747 else
1748 res = w83781d_read_value_isa(data, reg);
1749 mutex_unlock(&data->lock);
1750 return res;
1751}
1752
1753static int
1754w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value)
1755{
0217eae3 1756 struct i2c_client *client = data->client;
443850ce
WG		 1757
1758 mutex_lock(&data->lock);
0217eae3 1759 if (client)
443850ce
WG		 1760 w83781d_write_value_i2c(data, reg, value);
1761 else
1762 w83781d_write_value_isa(data, reg, value);
1763 mutex_unlock(&data->lock);
1764 return 0;
1765}
1766
6c931ae1 1767static int
443850ce
WG		 1768w83781d_isa_probe(struct platform_device *pdev)
1769{
1770 int err, reg;
1771 struct w83781d_data *data;
1772 struct resource *res;
443850ce
WG		 1773
1774 /* Reserve the ISA region */
1775 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
144d2b99
GR		 1776 if (!devm_request_region(&pdev->dev,
1777 res->start + W83781D_ADDR_REG_OFFSET, 2,
1778 "w83781d"))
1779 return -EBUSY;
1780
1781 data = devm_kzalloc(&pdev->dev, sizeof(struct w83781d_data),
1782 GFP_KERNEL);
1783 if (!data)
1784 return -ENOMEM;
443850ce 1785
443850ce 1786 mutex_init(&data->lock);
360782dd 1787 data->isa_addr = res->start;
443850ce
WG		 1788 platform_set_drvdata(pdev, data);
1789
1790 reg = w83781d_read_value(data, W83781D_REG_WCHIPID);
1791 switch (reg) {
1792 case 0x30:
1793 data->type = w83782d;
360782dd 1794 data->name = "w83782d";
443850ce
WG		 1795 break;
1796 default:
1797 data->type = w83781d;
360782dd 1798 data->name = "w83781d";
443850ce 1799 }
443850ce
WG		 1800
1801 /* Initialize the W83781D chip */
1802 w83781d_init_device(&pdev->dev);
1803
1804 /* Register sysfs hooks */
1805 err = w83781d_create_files(&pdev->dev, data->type, 1);
1806 if (err)
1807 goto exit_remove_files;
1808
1809 err = device_create_file(&pdev->dev, &dev_attr_name);
1810 if (err)
1811 goto exit_remove_files;
1812
1813 data->hwmon_dev = hwmon_device_register(&pdev->dev);
1814 if (IS_ERR(data->hwmon_dev)) {
1815 err = PTR_ERR(data->hwmon_dev);
1816 goto exit_remove_files;
1817 }
1818
1819 return 0;
1820
1821 exit_remove_files:
79501333 1822 w83781d_remove_files(&pdev->dev);
443850ce 1823 device_remove_file(&pdev->dev, &dev_attr_name);
443850ce
WG		 1824 return err;
1825}
1826
1827static int __devexit
1828w83781d_isa_remove(struct platform_device *pdev)
1829{
1830 struct w83781d_data *data = platform_get_drvdata(pdev);
1831
1832 hwmon_device_unregister(data->hwmon_dev);
79501333 1833 w83781d_remove_files(&pdev->dev);
443850ce 1834 device_remove_file(&pdev->dev, &dev_attr_name);
443850ce
WG		 1835
1836 return 0;
1837}
1838
1839static struct platform_driver w83781d_isa_driver = {
1840 .driver = {
1841 .owner = THIS_MODULE,
1842 .name = "w83781d",
1843 },
1844 .probe = w83781d_isa_probe,
9e5e9b7a 1845 .remove = w83781d_isa_remove,
443850ce
WG		 1846};
1847
7666c13c
JD		 1848/* return 1 if a supported chip is found, 0 otherwise */
1849static int __init
1850w83781d_isa_found(unsigned short address)
1851{
1852 int val, save, found = 0;
b0bcdd3c
JD		 1853 int port;
1854
aff6e00e
GR		 1855 /*
1856 * Some boards declare base+0 to base+7 as a PNP device, some base+4
b0bcdd3c 1857 * to base+7 and some base+5 to base+6. So we better request each port
aff6e00e
GR		 1858 * individually for the probing phase.
1859 */
b0bcdd3c
JD		 1860 for (port = address; port < address + W83781D_EXTENT; port++) {
1861 if (!request_region(port, 1, "w83781d")) {
1ca28218 1862 pr_debug("Failed to request port 0x%x\n", port);
b0bcdd3c
JD		 1863 goto release;
1864 }
2961cb22 1865 }
7666c13c
JD		 1866
1867#define REALLY_SLOW_IO
aff6e00e
GR		 1868 /*
1869 * We need the timeouts for at least some W83781D-like
1870 * chips. But only if we read 'undefined' registers.
1871 */
7666c13c
JD		 1872 val = inb_p(address + 1);
1873 if (inb_p(address + 2) != val
1874 || inb_p(address + 3) != val
1875 || inb_p(address + 7) != val) {
1ca28218 1876 pr_debug("Detection failed at step %d\n", 1);
7666c13c
JD		 1877 goto release;
1878 }
1879#undef REALLY_SLOW_IO
1880
aff6e00e
GR		 1881 /*
1882 * We should be able to change the 7 LSB of the address port. The
1883 * MSB (busy flag) should be clear initially, set after the write.
1884 */
7666c13c
JD		 1885 save = inb_p(address + W83781D_ADDR_REG_OFFSET);
1886 if (save & 0x80) {
1ca28218 1887 pr_debug("Detection failed at step %d\n", 2);
7666c13c
JD		 1888 goto release;
1889 }
1890 val = ~save & 0x7f;
1891 outb_p(val, address + W83781D_ADDR_REG_OFFSET);
1892 if (inb_p(address + W83781D_ADDR_REG_OFFSET) != (val | 0x80)) {
1893 outb_p(save, address + W83781D_ADDR_REG_OFFSET);
1ca28218 1894 pr_debug("Detection failed at step %d\n", 3);
7666c13c
JD		 1895 goto release;
1896 }
1897
1898 /* We found a device, now see if it could be a W83781D */
1899 outb_p(W83781D_REG_CONFIG, address + W83781D_ADDR_REG_OFFSET);
1900 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1901 if (val & 0x80) {
1ca28218 1902 pr_debug("Detection failed at step %d\n", 4);
7666c13c
JD		 1903 goto release;
1904 }
1905 outb_p(W83781D_REG_BANK, address + W83781D_ADDR_REG_OFFSET);
1906 save = inb_p(address + W83781D_DATA_REG_OFFSET);
1907 outb_p(W83781D_REG_CHIPMAN, address + W83781D_ADDR_REG_OFFSET);
1908 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1909 if ((!(save & 0x80) && (val != 0xa3))
1910 || ((save & 0x80) && (val != 0x5c))) {
1ca28218 1911 pr_debug("Detection failed at step %d\n", 5);
7666c13c
JD		 1912 goto release;
1913 }
1914 outb_p(W83781D_REG_I2C_ADDR, address + W83781D_ADDR_REG_OFFSET);
1915 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1916 if (val < 0x03 || val > 0x77) { /* Not a valid I2C address */
1ca28218 1917 pr_debug("Detection failed at step %d\n", 6);
7666c13c
JD		 1918 goto release;
1919 }
1920
1921 /* The busy flag should be clear again */
1922 if (inb_p(address + W83781D_ADDR_REG_OFFSET) & 0x80) {
1ca28218 1923 pr_debug("Detection failed at step %d\n", 7);
7666c13c
JD		 1924 goto release;
1925 }
1926
1927 /* Determine the chip type */
1928 outb_p(W83781D_REG_BANK, address + W83781D_ADDR_REG_OFFSET);
1929 save = inb_p(address + W83781D_DATA_REG_OFFSET);
1930 outb_p(save & 0xf8, address + W83781D_DATA_REG_OFFSET);
1931 outb_p(W83781D_REG_WCHIPID, address + W83781D_ADDR_REG_OFFSET);
1932 val = inb_p(address + W83781D_DATA_REG_OFFSET);
1933 if ((val & 0xfe) == 0x10 /* W83781D */
05663368 1934 || val == 0x30) /* W83782D */
7666c13c
JD		 1935 found = 1;
1936
1937 if (found)
1ca28218 1938 pr_info("Found a %s chip at %#x\n",
7666c13c
JD		 1939 val == 0x30 ? "W83782D" : "W83781D", (int)address);
1940
1941 release:
b0bcdd3c
JD		 1942 for (port--; port >= address; port--)
1943 release_region(port, 1);
7666c13c
JD		 1944 return found;
1945}
1946
1947static int __init
1948w83781d_isa_device_add(unsigned short address)
1949{
1950 struct resource res = {
1951 .start = address,
15bde2f1 1952 .end = address + W83781D_EXTENT - 1,
7666c13c
JD		 1953 .name = "w83781d",
1954 .flags = IORESOURCE_IO,
1955 };
1956 int err;
1957
1958 pdev = platform_device_alloc("w83781d", address);
1959 if (!pdev) {
1960 err = -ENOMEM;
1ca28218 1961 pr_err("Device allocation failed\n");
7666c13c
JD		 1962 goto exit;
1963 }
1964
1965 err = platform_device_add_resources(pdev, &res, 1);
1966 if (err) {
1ca28218 1967 pr_err("Device resource addition failed (%d)\n", err);
7666c13c
JD		 1968 goto exit_device_put;
1969 }
1970
1971 err = platform_device_add(pdev);
1972 if (err) {
1ca28218 1973 pr_err("Device addition failed (%d)\n", err);
7666c13c
JD		 1974 goto exit_device_put;
1975 }
1976
1977 return 0;
1978
1979 exit_device_put:
1980 platform_device_put(pdev);
1981 exit:
1982 pdev = NULL;
1983 return err;
1984}
1985
1da177e4 1986static int __init
443850ce 1987w83781d_isa_register(void)
1da177e4 1988{
fde09509
JD		 1989 int res;
1990
7666c13c
JD		 1991 if (w83781d_isa_found(isa_address)) {
1992 res = platform_driver_register(&w83781d_isa_driver);
1993 if (res)
c6566206 1994 goto exit;
fde09509 1995
7666c13c
JD		 1996 /* Sets global pdev as a side effect */
1997 res = w83781d_isa_device_add(isa_address);
1998 if (res)
1999 goto exit_unreg_isa_driver;
2000 }
fde09509
JD		 2001
2002 return 0;
7666c13c 2003
443850ce 2004exit_unreg_isa_driver:
7666c13c 2005 platform_driver_unregister(&w83781d_isa_driver);
443850ce 2006exit:
7666c13c 2007 return res;
1da177e4
LT		 2008}
2009
dd56b638 2010static void
443850ce 2011w83781d_isa_unregister(void)
1da177e4 2012{
7666c13c
JD		 2013 if (pdev) {
2014 platform_device_unregister(pdev);
2015 platform_driver_unregister(&w83781d_isa_driver);
2016 }
443850ce
WG		 2017}
2018#else /* !CONFIG_ISA */
2019
2020static struct w83781d_data *w83781d_data_if_isa(void)
2021{
2022 return NULL;
2023}
2024
2025static int
2026w83781d_alias_detect(struct i2c_client *client, u8 chipid)
2027{
2028 return 0;
2029}
2030
2031static int
2032w83781d_read_value(struct w83781d_data *data, u16 reg)
2033{
2034 int res;
2035
2036 mutex_lock(&data->lock);
2037 res = w83781d_read_value_i2c(data, reg);
2038 mutex_unlock(&data->lock);
2039
2040 return res;
2041}
2042
2043static int
2044w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value)
2045{
2046 mutex_lock(&data->lock);
2047 w83781d_write_value_i2c(data, reg, value);
2048 mutex_unlock(&data->lock);
2049
2050 return 0;
2051}
2052
2053static int __init
2054w83781d_isa_register(void)
2055{
2056 return 0;
2057}
2058
dd56b638 2059static void
443850ce
WG		 2060w83781d_isa_unregister(void)
2061{
2062}
2063#endif /* CONFIG_ISA */
2064
2065static int __init
2066sensors_w83781d_init(void)
2067{
2068 int res;
2069
aff6e00e
GR		 2070 /*
2071 * We register the ISA device first, so that we can skip the
2072 * registration of an I2C interface to the same device.
2073 */
443850ce
WG		 2074 res = w83781d_isa_register();
2075 if (res)
2076 goto exit;
2077
2078 res = i2c_add_driver(&w83781d_driver);
2079 if (res)
2080 goto exit_unreg_isa;
2081
2082 return 0;
2083
2084 exit_unreg_isa:
2085 w83781d_isa_unregister();
2086 exit:
2087 return res;
2088}
2089
2090static void __exit
2091sensors_w83781d_exit(void)
2092{
2093 w83781d_isa_unregister();
1da177e4
LT		 2094 i2c_del_driver(&w83781d_driver);
2095}
2096
2097MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
2098 "Philip Edelbrock <phil@netroedge.com>, "
2099 "and Mark Studebaker <mdsxyz123@yahoo.com>");
2100MODULE_DESCRIPTION("W83781D driver");
2101MODULE_LICENSE("GPL");
2102
2103module_init(sensors_w83781d_init);
2104module_exit(sensors_w83781d_exit);
Linux 6.x block layer and io_uring tree(s)