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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 61
[linux-block.git] / drivers / hwmon / w83627ehf.c
CommitLineData
74ba9207 1// SPDX-License-Identifier: GPL-2.0-or-later
08e7e278 2/*
8969e84d
GR		 3 * w83627ehf - Driver for the hardware monitoring functionality of
4 * the Winbond W83627EHF Super-I/O chip
7c81c60f 5 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
8969e84d
GR		 6 * Copyright (C) 2006 Yuan Mu (Winbond),
7 * Rudolf Marek <r.marek@assembler.cz>
8 * David Hubbard <david.c.hubbard@gmail.com>
9 * Daniel J Blueman <daniel.blueman@gmail.com>
10 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
11 *
12 * Shamelessly ripped from the w83627hf driver
13 * Copyright (C) 2003 Mark Studebaker
14 *
15 * Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
16 * in testing and debugging this driver.
17 *
18 * This driver also supports the W83627EHG, which is the lead-free
19 * version of the W83627EHF.
20 *
8969e84d
GR		 21 * Supports the following chips:
22 *
23 * Chip #vin #fan #pwm #temp chip IDs man ID
24 * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
25 * 0x8860 0xa1
26 * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
27 * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
28 * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
29 * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
30 * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
31 * nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
32 * nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
33 */
08e7e278 34
abdc6fd1
JP		 35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
08e7e278
JD		 37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/slab.h>
1ea6dd38
DH		 40#include <linux/jiffies.h>
41#include <linux/platform_device.h>
943b0830 42#include <linux/hwmon.h>
412fec82 43#include <linux/hwmon-sysfs.h>
fc18d6c0 44#include <linux/hwmon-vid.h>
943b0830 45#include <linux/err.h>
9a61bf63 46#include <linux/mutex.h>
b9acb64a 47#include <linux/acpi.h>
6055fae8 48#include <linux/io.h>
08e7e278
JD		 49#include "lm75.h"
50
eff7687d
JD		 51enum kinds {
52 w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
53 w83667hg, w83667hg_b, nct6775, nct6776,
54};
08e7e278 55
1ea6dd38 56/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 57static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 58 "w83627ehf",
59 "w83627dhg",
c1e48dce 60 "w83627dhg",
eff7687d 61 "w83627uhg",
237c8d2f 62 "w83667hg",
c39aedaf 63 "w83667hg",
ec3e5a16
GR		 64 "nct6775",
65 "nct6776",
1ea6dd38
DH		 66};
67
67b671bc
JD		 68static unsigned short force_id;
69module_param(force_id, ushort, 0);
70MODULE_PARM_DESC(force_id, "Override the detected device ID");
71
d42e869a
ID		 72static unsigned short fan_debounce;
73module_param(fan_debounce, ushort, 0);
74MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
75
1ea6dd38 76#define DRVNAME "w83627ehf"
08e7e278 77
657c93b1 78/*
1ea6dd38 79 * Super-I/O constants and functions
657c93b1 80 */
08e7e278
JD		 81
82#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 83#define W83667HG_LD_VID 0x0d
08e7e278
JD		 84
85#define SIO_REG_LDSEL 0x07 /* Logical device select */
86#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 87#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 88#define SIO_REG_ENABLE 0x30 /* Logical device enable */
89#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 90#define SIO_REG_VID_CTRL 0xF0 /* VID control */
91#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 92
657c93b1
DH		 93#define SIO_W83627EHF_ID 0x8850
94#define SIO_W83627EHG_ID 0x8860
95#define SIO_W83627DHG_ID 0xa020
c1e48dce 96#define SIO_W83627DHG_P_ID 0xb070
eff7687d 97#define SIO_W83627UHG_ID 0xa230
e7e1ca6e 98#define SIO_W83667HG_ID 0xa510
c39aedaf 99#define SIO_W83667HG_B_ID 0xb350
ec3e5a16
GR		 100#define SIO_NCT6775_ID 0xb470
101#define SIO_NCT6776_ID 0xc330
657c93b1 102#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 103
104static inline void
1ea6dd38 105superio_outb(int ioreg, int reg, int val)
08e7e278 106{
1ea6dd38
DH		 107 outb(reg, ioreg);
108 outb(val, ioreg + 1);
08e7e278
JD		 109}
110
111static inline int
1ea6dd38 112superio_inb(int ioreg, int reg)
08e7e278 113{
1ea6dd38
DH		 114 outb(reg, ioreg);
115 return inb(ioreg + 1);
08e7e278
JD		 116}
117
118static inline void
1ea6dd38 119superio_select(int ioreg, int ld)
08e7e278 120{
1ea6dd38
DH		 121 outb(SIO_REG_LDSEL, ioreg);
122 outb(ld, ioreg + 1);
08e7e278
JD		 123}
124
0d023530 125static inline int
1ea6dd38 126superio_enter(int ioreg)
08e7e278 127{
0d023530
KS		 128 if (!request_muxed_region(ioreg, 2, DRVNAME))
129 return -EBUSY;
130
1ea6dd38
DH		 131 outb(0x87, ioreg);
132 outb(0x87, ioreg);
0d023530
KS		 133
134 return 0;
08e7e278
JD		 135}
136
137static inline void
1ea6dd38 138superio_exit(int ioreg)
08e7e278 139{
022b75a3 140 outb(0xaa, ioreg);
1ea6dd38
DH		 141 outb(0x02, ioreg);
142 outb(0x02, ioreg + 1);
0d023530 143 release_region(ioreg, 2);
08e7e278
JD		 144}
145
146/*
147 * ISA constants
148 */
149
e7e1ca6e 150#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 151#define IOREGION_OFFSET 5
152#define IOREGION_LENGTH 2
1ea6dd38
DH		 153#define ADDR_REG_OFFSET 0
154#define DATA_REG_OFFSET 1
08e7e278
JD		 155
156#define W83627EHF_REG_BANK 0x4E
157#define W83627EHF_REG_CONFIG 0x40
657c93b1 158
8969e84d
GR		 159/*
160 * Not currently used:
657c93b1
DH		 161 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
162 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
163 * REG_MAN_ID is at port 0x4f
8969e84d
GR		 164 * REG_CHIP_ID is at port 0x58
165 */
08e7e278
JD		 166
167static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
168static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
169
cf0676fe
RM		 170/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
171#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
172 (0x554 + (((nr) - 7) * 2)))
173#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
174 (0x555 + (((nr) - 7) * 2)))
175#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
176 (0x550 + (nr) - 7))
177
d36cf32c
GR		 178static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
179static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
180static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
181static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 182
183/* Fan clock dividers are spread over the following five registers */
184#define W83627EHF_REG_FANDIV1 0x47
185#define W83627EHF_REG_FANDIV2 0x4B
186#define W83627EHF_REG_VBAT 0x5D
187#define W83627EHF_REG_DIODE 0x59
188#define W83627EHF_REG_SMI_OVT 0x4C
189
ec3e5a16
GR		 190/* NCT6775F has its own fan divider registers */
191#define NCT6775_REG_FANDIV1 0x506
192#define NCT6775_REG_FANDIV2 0x507
d42e869a 193#define NCT6775_REG_FAN_DEBOUNCE 0xf0
ec3e5a16 194
a4589dbb
JD		 195#define W83627EHF_REG_ALARM1 0x459
196#define W83627EHF_REG_ALARM2 0x45A
197#define W83627EHF_REG_ALARM3 0x45B
198
363a12a4
DA		 199#define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
200#define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
201
08c79950 202/* SmartFan registers */
41e9a062
DB		 203#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
204#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
205
08c79950
RM		 206/* DC or PWM output fan configuration */
207static const u8 W83627EHF_REG_PWM_ENABLE[] = {
208 0x04, /* SYS FAN0 output mode and PWM mode */
209 0x04, /* CPU FAN0 output mode and PWM mode */
210 0x12, /* AUX FAN mode */
41e9a062 211 0x62, /* CPU FAN1 mode */
08c79950
RM		 212};
213
214static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
215static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
216
217/* FAN Duty Cycle, be used to control */
279af1a9
GR		 218static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
219static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 220static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
221
08c79950 222/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 223static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
224static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
225static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 226
279af1a9 227static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 228 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 229static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 230 = { 0xff, 0x68, 0xff, 0x6a };
231
279af1a9
GR		 232static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
233static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
234 = { 0x68, 0x6a, 0x6c };
08c79950 235
840e191d
GR		 236static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
237
ec3e5a16
GR		 238static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
239static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
240static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
241static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
242static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
243static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
244static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
245static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
26bc440e 246static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
ec3e5a16
GR		 247static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
248
249static const u16 NCT6775_REG_TEMP[]
250 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
251static const u16 NCT6775_REG_TEMP_CONFIG[]
252 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
253static const u16 NCT6775_REG_TEMP_HYST[]
254 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
255static const u16 NCT6775_REG_TEMP_OVER[]
256 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
257static const u16 NCT6775_REG_TEMP_SOURCE[]
258 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
259
d36cf32c
GR		 260static const char *const w83667hg_b_temp_label[] = {
261 "SYSTIN",
262 "CPUTIN",
263 "AUXTIN",
264 "AMDTSI",
265 "PECI Agent 1",
266 "PECI Agent 2",
267 "PECI Agent 3",
268 "PECI Agent 4"
269};
270
ec3e5a16
GR		 271static const char *const nct6775_temp_label[] = {
272 "",
273 "SYSTIN",
274 "CPUTIN",
275 "AUXTIN",
276 "AMD SB-TSI",
277 "PECI Agent 0",
278 "PECI Agent 1",
279 "PECI Agent 2",
280 "PECI Agent 3",
281 "PECI Agent 4",
282 "PECI Agent 5",
283 "PECI Agent 6",
284 "PECI Agent 7",
285 "PCH_CHIP_CPU_MAX_TEMP",
286 "PCH_CHIP_TEMP",
287 "PCH_CPU_TEMP",
288 "PCH_MCH_TEMP",
289 "PCH_DIM0_TEMP",
290 "PCH_DIM1_TEMP",
291 "PCH_DIM2_TEMP",
292 "PCH_DIM3_TEMP"
293};
294
295static const char *const nct6776_temp_label[] = {
296 "",
297 "SYSTIN",
298 "CPUTIN",
299 "AUXTIN",
300 "SMBUSMASTER 0",
301 "SMBUSMASTER 1",
302 "SMBUSMASTER 2",
303 "SMBUSMASTER 3",
304 "SMBUSMASTER 4",
305 "SMBUSMASTER 5",
306 "SMBUSMASTER 6",
307 "SMBUSMASTER 7",
308 "PECI Agent 0",
309 "PECI Agent 1",
310 "PCH_CHIP_CPU_MAX_TEMP",
311 "PCH_CHIP_TEMP",
312 "PCH_CPU_TEMP",
313 "PCH_MCH_TEMP",
314 "PCH_DIM0_TEMP",
315 "PCH_DIM1_TEMP",
316 "PCH_DIM2_TEMP",
317 "PCH_DIM3_TEMP",
318 "BYTE_TEMP"
319};
320
321#define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
d36cf32c 322
17296feb 323static int is_word_sized(u16 reg)
bce26c58 324{
ec3e5a16 325 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 326 || (reg & 0xff00) == 0x200)
327 && ((reg & 0x00ff) == 0x50
328 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 329 || (reg & 0x00ff) == 0x55))
330 || (reg & 0xfff0) == 0x630
331 || reg == 0x640 || reg == 0x642
332 || ((reg & 0xfff0) == 0x650
333 && (reg & 0x000f) >= 0x06)
334 || reg == 0x73 || reg == 0x75 || reg == 0x77
335 );
bce26c58
GR		 336}
337
08e7e278
JD		 338/*
339 * Conversions
340 */
341
08c79950
RM		 342/* 1 is PWM mode, output in ms */
343static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
344{
345 return mode ? 100 * reg : 400 * reg;
346}
347
348static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
349{
2a844c14
GR		 350 return clamp_val((mode ? (msec + 50) / 100 : (msec + 200) / 400),
351 1, 255);
08c79950
RM		 352}
353
26bc440e 354static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
08e7e278 355{
26bc440e 356 if (reg == 0 || reg == 255)
08e7e278 357 return 0;
26bc440e
GR		 358 return 1350000U / (reg << divreg);
359}
360
361static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
362{
363 if ((reg & 0xff1f) == 0xff1f)
364 return 0;
365
366 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
367
368 if (reg == 0)
369 return 0;
370
371 return 1350000U / reg;
372}
373
374static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
375{
376 if (reg == 0 || reg == 0xffff)
377 return 0;
378
379 /*
380 * Even though the registers are 16 bit wide, the fan divisor
381 * still applies.
382 */
383 return 1350000U / (reg << divreg);
08e7e278
JD		 384}
385
386static inline unsigned int
387div_from_reg(u8 reg)
388{
389 return 1 << reg;
390}
391
8969e84d
GR		 392/*
393 * Some of the voltage inputs have internal scaling, the tables below
394 * contain 8 (the ADC LSB in mV) * scaling factor * 100
395 */
eff7687d
JD		 396static const u16 scale_in_common[10] = {
397 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
398};
399static const u16 scale_in_w83627uhg[9] = {
400 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
401};
cf0676fe 402
eff7687d 403static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
cf0676fe 404{
eff7687d 405 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
cf0676fe
RM		 406}
407
eff7687d 408static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
cf0676fe 409{
2a844c14 410 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
cf0676fe
RM		 411}
412
08e7e278
JD		 413/*
414 * Data structures and manipulation thereof
415 */
416
417struct w83627ehf_data {
1ea6dd38
DH		 418 int addr; /* IO base of hw monitor block */
419 const char *name;
420
1beeffe4 421 struct device *hwmon_dev;
9a61bf63 422 struct mutex lock;
08e7e278 423
ec3e5a16
GR		 424 u16 reg_temp[NUM_REG_TEMP];
425 u16 reg_temp_over[NUM_REG_TEMP];
426 u16 reg_temp_hyst[NUM_REG_TEMP];
427 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 428 u8 temp_src[NUM_REG_TEMP];
429 const char * const *temp_label;
430
279af1a9
GR		 431 const u16 *REG_PWM;
432 const u16 *REG_TARGET;
433 const u16 *REG_FAN;
434 const u16 *REG_FAN_MIN;
435 const u16 *REG_FAN_START_OUTPUT;
436 const u16 *REG_FAN_STOP_OUTPUT;
437 const u16 *REG_FAN_STOP_TIME;
438 const u16 *REG_FAN_MAX_OUTPUT;
439 const u16 *REG_FAN_STEP_OUTPUT;
eff7687d 440 const u16 *scale_in;
da2e0255 441
26bc440e
GR		 442 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
443 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
444
9a61bf63 445 struct mutex update_lock;
08e7e278
JD		 446 char valid; /* !=0 if following fields are valid */
447 unsigned long last_updated; /* In jiffies */
448
449 /* Register values */
83cc8985 450 u8 bank; /* current register bank */
1ea6dd38 451 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 452 u8 in[10]; /* Register value */
453 u8 in_max[10]; /* Register value */
454 u8 in_min[10]; /* Register value */
3382a918 455 unsigned int rpm[5];
ec3e5a16 456 u16 fan_min[5];
08e7e278
JD		 457 u8 fan_div[5];
458 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 459 u8 has_fan_min; /* some fans don't have min register */
26bc440e 460 bool has_fan_div;
da667365 461 u8 temp_type[3];
840e191d 462 s8 temp_offset[3];
ec3e5a16
GR		 463 s16 temp[9];
464 s16 temp_max[9];
465 s16 temp_max_hyst[9];
a4589dbb 466 u32 alarms;
363a12a4 467 u8 caseopen;
08c79950
RM		 468
469 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
470 u8 pwm_enable[4]; /* 1->manual
8969e84d
GR		 471 * 2->thermal cruise mode (also called SmartFan I)
472 * 3->fan speed cruise mode
473 * 4->variable thermal cruise (also called
474 * SmartFan III)
475 * 5->enhanced variable thermal cruise (also called
476 * SmartFan IV)
477 */
b84bb518 478 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 479 u8 pwm_num; /* number of pwm */
08c79950
RM		 480 u8 pwm[4];
481 u8 target_temp[4];
482 u8 tolerance[4];
483
41e9a062
DB		 484 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
485 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
486 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
487 u8 fan_max_output[4]; /* maximum fan speed */
488 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 489
490 u8 vid;
491 u8 vrm;
a157d06d 492
ec3e5a16 493 u16 have_temp;
840e191d 494 u16 have_temp_offset;
eff7687d
JD		 495 u8 in6_skip:1;
496 u8 temp3_val_only:1;
7e630bb5
JD		 497
498#ifdef CONFIG_PM
499 /* Remember extra register values over suspend/resume */
500 u8 vbat;
501 u8 fandiv1;
502 u8 fandiv2;
503#endif
08e7e278
JD		 504};
505
1ea6dd38
DH		 506struct w83627ehf_sio_data {
507 int sioreg;
508 enum kinds kind;
509};
510
83cc8985
GR		 511/*
512 * On older chips, only registers 0x50-0x5f are banked.
513 * On more recent chips, all registers are banked.
514 * Assume that is the case and set the bank number for each access.
515 * Cache the bank number so it only needs to be set if it changes.
516 */
1ea6dd38 517static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 518{
83cc8985
GR		 519 u8 bank = reg >> 8;
520 if (data->bank != bank) {
1ea6dd38 521 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 522 outb_p(bank, data->addr + DATA_REG_OFFSET);
523 data->bank = bank;
08e7e278
JD		 524 }
525}
526
1ea6dd38 527static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 528{
08e7e278
JD		 529 int res, word_sized = is_word_sized(reg);
530
9a61bf63 531 mutex_lock(&data->lock);
08e7e278 532
1ea6dd38
DH		 533 w83627ehf_set_bank(data, reg);
534 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
535 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 536 if (word_sized) {
537 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 538 data->addr + ADDR_REG_OFFSET);
539 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 540 }
08e7e278 541
9a61bf63 542 mutex_unlock(&data->lock);
08e7e278
JD		 543 return res;
544}
545
e7e1ca6e
GR		 546static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
547 u16 value)
08e7e278 548{
08e7e278
JD		 549 int word_sized = is_word_sized(reg);
550
9a61bf63 551 mutex_lock(&data->lock);
08e7e278 552
1ea6dd38
DH		 553 w83627ehf_set_bank(data, reg);
554 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 555 if (word_sized) {
1ea6dd38 556 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 557 outb_p((reg & 0xff) + 1,
1ea6dd38 558 data->addr + ADDR_REG_OFFSET);
08e7e278 559 }
1ea6dd38 560 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 561
9a61bf63 562 mutex_unlock(&data->lock);
08e7e278
JD		 563 return 0;
564}
565
c5794cfa
JD		 566/* We left-align 8-bit temperature values to make the code simpler */
567static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
568{
569 u16 res;
570
571 res = w83627ehf_read_value(data, reg);
572 if (!is_word_sized(reg))
573 res <<= 8;
574
575 return res;
576}
577
578static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
579 u16 value)
580{
581 if (!is_word_sized(reg))
582 value >>= 8;
583 return w83627ehf_write_value(data, reg, value);
584}
585
ec3e5a16
GR		 586/* This function assumes that the caller holds data->update_lock */
587static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
588{
589 u8 reg;
590
591 switch (nr) {
592 case 0:
593 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
594 | (data->fan_div[0] & 0x7);
595 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
596 break;
597 case 1:
598 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
599 | ((data->fan_div[1] << 4) & 0x70);
600 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
58c3667d 601 break;
ec3e5a16
GR		 602 case 2:
603 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
604 | (data->fan_div[2] & 0x7);
605 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
606 break;
607 case 3:
608 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
609 | ((data->fan_div[3] << 4) & 0x70);
610 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
611 break;
612 }
613}
614
08e7e278 615/* This function assumes that the caller holds data->update_lock */
1ea6dd38 616static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 617{
08e7e278
JD		 618 u8 reg;
619
620 switch (nr) {
621 case 0:
1ea6dd38 622 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 623 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 624 /* fan5 input control bit is write only, compute the value */
625 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 626 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
627 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 628 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 629 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 630 break;
631 case 1:
1ea6dd38 632 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 633 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 634 /* fan5 input control bit is write only, compute the value */
635 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 636 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
637 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 638 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 639 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 640 break;
641 case 2:
1ea6dd38 642 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 643 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 644 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
645 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 646 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 647 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 648 break;
649 case 3:
1ea6dd38 650 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 651 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 652 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
653 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 654 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 655 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 656 break;
657 case 4:
1ea6dd38 658 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 659 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 660 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 661 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 662 break;
663 }
664}
665
ec3e5a16
GR		 666static void w83627ehf_write_fan_div_common(struct device *dev,
667 struct w83627ehf_data *data, int nr)
668{
a8b3a3a5 669 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
ec3e5a16
GR		 670
671 if (sio_data->kind == nct6776)
672 ; /* no dividers, do nothing */
673 else if (sio_data->kind == nct6775)
674 nct6775_write_fan_div(data, nr);
675 else
676 w83627ehf_write_fan_div(data, nr);
677}
678
679static void nct6775_update_fan_div(struct w83627ehf_data *data)
680{
681 u8 i;
682
683 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
684 data->fan_div[0] = i & 0x7;
685 data->fan_div[1] = (i & 0x70) >> 4;
686 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
687 data->fan_div[2] = i & 0x7;
688 if (data->has_fan & (1<<3))
689 data->fan_div[3] = (i & 0x70) >> 4;
690}
691
ea7be66c
MH		 692static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
693{
694 int i;
695
696 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
697 data->fan_div[0] = (i >> 4) & 0x03;
698 data->fan_div[1] = (i >> 6) & 0x03;
699 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
700 data->fan_div[2] = (i >> 6) & 0x03;
701 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
702 data->fan_div[0] |= (i >> 3) & 0x04;
703 data->fan_div[1] |= (i >> 4) & 0x04;
704 data->fan_div[2] |= (i >> 5) & 0x04;
705 if (data->has_fan & ((1 << 3) | (1 << 4))) {
706 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
707 data->fan_div[3] = i & 0x03;
708 data->fan_div[4] = ((i >> 2) & 0x03)
709 | ((i >> 5) & 0x04);
710 }
711 if (data->has_fan & (1 << 3)) {
712 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
713 data->fan_div[3] |= (i >> 5) & 0x04;
714 }
715}
716
ec3e5a16
GR		 717static void w83627ehf_update_fan_div_common(struct device *dev,
718 struct w83627ehf_data *data)
719{
a8b3a3a5 720 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
ec3e5a16
GR		 721
722 if (sio_data->kind == nct6776)
723 ; /* no dividers, do nothing */
724 else if (sio_data->kind == nct6775)
725 nct6775_update_fan_div(data);
726 else
727 w83627ehf_update_fan_div(data);
728}
729
730static void nct6775_update_pwm(struct w83627ehf_data *data)
731{
732 int i;
733 int pwmcfg, fanmodecfg;
734
735 for (i = 0; i < data->pwm_num; i++) {
736 pwmcfg = w83627ehf_read_value(data,
737 W83627EHF_REG_PWM_ENABLE[i]);
738 fanmodecfg = w83627ehf_read_value(data,
739 NCT6775_REG_FAN_MODE[i]);
740 data->pwm_mode[i] =
741 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
742 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
743 data->tolerance[i] = fanmodecfg & 0x0f;
744 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
745 }
746}
747
748static void w83627ehf_update_pwm(struct w83627ehf_data *data)
749{
750 int i;
751 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
752
753 for (i = 0; i < data->pwm_num; i++) {
754 if (!(data->has_fan & (1 << i)))
755 continue;
756
757 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
758 if (i != 1) {
759 pwmcfg = w83627ehf_read_value(data,
760 W83627EHF_REG_PWM_ENABLE[i]);
761 tolerance = w83627ehf_read_value(data,
762 W83627EHF_REG_TOLERANCE[i]);
763 }
764 data->pwm_mode[i] =
765 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
766 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
767 & 3) + 1;
768 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
769
770 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
771 }
772}
773
774static void w83627ehf_update_pwm_common(struct device *dev,
775 struct w83627ehf_data *data)
776{
a8b3a3a5 777 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
ec3e5a16
GR		 778
779 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
780 nct6775_update_pwm(data);
781 else
782 w83627ehf_update_pwm(data);
783}
784
08e7e278
JD		 785static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
786{
1ea6dd38 787 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 788 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
ec3e5a16 789
08e7e278
JD		 790 int i;
791
9a61bf63 792 mutex_lock(&data->update_lock);
08e7e278 793
6b3e4645 794 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 795 || !data->valid) {
796 /* Fan clock dividers */
ec3e5a16 797 w83627ehf_update_fan_div_common(dev, data);
08e7e278 798
cf0676fe 799 /* Measured voltages and limits */
1ea6dd38 800 for (i = 0; i < data->in_num; i++) {
389ef65d
JD		 801 if ((i == 6) && data->in6_skip)
802 continue;
803
1ea6dd38 804 data->in[i] = w83627ehf_read_value(data,
cf0676fe 805 W83627EHF_REG_IN(i));
1ea6dd38 806 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 807 W83627EHF_REG_IN_MIN(i));
1ea6dd38 808 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 809 W83627EHF_REG_IN_MAX(i));
810 }
811
08e7e278
JD		 812 /* Measured fan speeds and limits */
813 for (i = 0; i < 5; i++) {
3382a918
GR		 814 u16 reg;
815
08e7e278
JD		 816 if (!(data->has_fan & (1 << i)))
817 continue;
818
3382a918
GR		 819 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
820 data->rpm[i] = data->fan_from_reg(reg,
821 data->fan_div[i]);
ec3e5a16
GR		 822
823 if (data->has_fan_min & (1 << i))
824 data->fan_min[i] = w83627ehf_read_value(data,
279af1a9 825 data->REG_FAN_MIN[i]);
08e7e278 826
8969e84d
GR		 827 /*
828 * If we failed to measure the fan speed and clock
829 * divider can be increased, let's try that for next
830 * time
831 */
26bc440e 832 if (data->has_fan_div
3382a918
GR		 833 && (reg >= 0xff || (sio_data->kind == nct6775
834 && reg == 0x00))
ec3e5a16 835 && data->fan_div[i] < 0x07) {
b55f3757
GR		 836 dev_dbg(dev,
837 "Increasing fan%d clock divider from %u to %u\n",
33725ad3 838 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 839 div_from_reg(data->fan_div[i] + 1));
840 data->fan_div[i]++;
ec3e5a16 841 w83627ehf_write_fan_div_common(dev, data, i);
08e7e278 842 /* Preserve min limit if possible */
ec3e5a16
GR		 843 if ((data->has_fan_min & (1 << i))
844 && data->fan_min[i] >= 2
08e7e278 845 && data->fan_min[i] != 255)
1ea6dd38 846 w83627ehf_write_value(data,
279af1a9 847 data->REG_FAN_MIN[i],
08e7e278
JD		 848 (data->fan_min[i] /= 2));
849 }
850 }
851
ec3e5a16
GR		 852 w83627ehf_update_pwm_common(dev, data);
853
da2e0255
GR		 854 for (i = 0; i < data->pwm_num; i++) {
855 if (!(data->has_fan & (1 << i)))
856 continue;
857
ec3e5a16
GR		 858 data->fan_start_output[i] =
859 w83627ehf_read_value(data,
860 data->REG_FAN_START_OUTPUT[i]);
861 data->fan_stop_output[i] =
862 w83627ehf_read_value(data,
863 data->REG_FAN_STOP_OUTPUT[i]);
864 data->fan_stop_time[i] =
865 w83627ehf_read_value(data,
866 data->REG_FAN_STOP_TIME[i]);
867
868 if (data->REG_FAN_MAX_OUTPUT &&
869 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 870 data->fan_max_output[i] =
871 w83627ehf_read_value(data,
ec3e5a16 872 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 873
ec3e5a16
GR		 874 if (data->REG_FAN_STEP_OUTPUT &&
875 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 876 data->fan_step_output[i] =
877 w83627ehf_read_value(data,
ec3e5a16 878 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 879
08c79950 880 data->target_temp[i] =
1ea6dd38 881 w83627ehf_read_value(data,
279af1a9 882 data->REG_TARGET[i]) &
08c79950 883 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 884 }
885
08e7e278 886 /* Measured temperatures and limits */
d36cf32c
GR		 887 for (i = 0; i < NUM_REG_TEMP; i++) {
888 if (!(data->have_temp & (1 << i)))
889 continue;
c5794cfa 890 data->temp[i] = w83627ehf_read_temp(data,
ec3e5a16
GR		 891 data->reg_temp[i]);
892 if (data->reg_temp_over[i])
893 data->temp_max[i]
c5794cfa 894 = w83627ehf_read_temp(data,
ec3e5a16
GR		 895 data->reg_temp_over[i]);
896 if (data->reg_temp_hyst[i])
897 data->temp_max_hyst[i]
c5794cfa 898 = w83627ehf_read_temp(data,
ec3e5a16 899 data->reg_temp_hyst[i]);
45633fb3
JD		 900 if (i > 2)
901 continue;
840e191d
GR		 902 if (data->have_temp_offset & (1 << i))
903 data->temp_offset[i]
904 = w83627ehf_read_value(data,
905 W83627EHF_REG_TEMP_OFFSET[i]);
08e7e278
JD		 906 }
907
1ea6dd38 908 data->alarms = w83627ehf_read_value(data,
a4589dbb 909 W83627EHF_REG_ALARM1) |
1ea6dd38 910 (w83627ehf_read_value(data,
a4589dbb 911 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 912 (w83627ehf_read_value(data,
a4589dbb
JD		 913 W83627EHF_REG_ALARM3) << 16);
914
363a12a4
DA		 915 data->caseopen = w83627ehf_read_value(data,
916 W83627EHF_REG_CASEOPEN_DET);
917
08e7e278
JD		 918 data->last_updated = jiffies;
919 data->valid = 1;
920 }
921
9a61bf63 922 mutex_unlock(&data->update_lock);
08e7e278
JD		 923 return data;
924}
925
926/*
927 * Sysfs callback functions
928 */
cf0676fe
RM		 929#define show_in_reg(reg) \
930static ssize_t \
931show_##reg(struct device *dev, struct device_attribute *attr, \
932 char *buf) \
933{ \
934 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 935 struct sensor_device_attribute *sensor_attr = \
936 to_sensor_dev_attr(attr); \
cf0676fe 937 int nr = sensor_attr->index; \
eff7687d
JD		 938 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr, \
939 data->scale_in)); \
cf0676fe
RM		 940}
941show_in_reg(in)
942show_in_reg(in_min)
943show_in_reg(in_max)
944
945#define store_in_reg(REG, reg) \
946static ssize_t \
e7e1ca6e
GR		 947store_in_##reg(struct device *dev, struct device_attribute *attr, \
948 const char *buf, size_t count) \
cf0676fe 949{ \
1ea6dd38 950 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 951 struct sensor_device_attribute *sensor_attr = \
952 to_sensor_dev_attr(attr); \
cf0676fe 953 int nr = sensor_attr->index; \
bce26c58
GR		 954 unsigned long val; \
955 int err; \
179c4fdb 956 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 957 if (err < 0) \
958 return err; \
cf0676fe 959 mutex_lock(&data->update_lock); \
eff7687d 960 data->in_##reg[nr] = in_to_reg(val, nr, data->scale_in); \
1ea6dd38 961 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 962 data->in_##reg[nr]); \
963 mutex_unlock(&data->update_lock); \
964 return count; \
965}
966
967store_in_reg(MIN, min)
968store_in_reg(MAX, max)
969
e7e1ca6e
GR		 970static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
971 char *buf)
a4589dbb
JD		 972{
973 struct w83627ehf_data *data = w83627ehf_update_device(dev);
974 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
975 int nr = sensor_attr->index;
976 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
977}
978
cf0676fe
RM		 979static struct sensor_device_attribute sda_in_input[] = {
980 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
981 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
982 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
983 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
984 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
985 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
986 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
987 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
988 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
989 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
990};
991
a4589dbb
JD		 992static struct sensor_device_attribute sda_in_alarm[] = {
993 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
994 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
995 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
996 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
997 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
998 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
999 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
1000 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
1001 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
1002 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
1003};
1004
cf0676fe 1005static struct sensor_device_attribute sda_in_min[] = {
e7e1ca6e
GR		 1006 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
1007 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
1008 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
1009 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
1010 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
1011 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
1012 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
1013 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
1014 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
1015 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
cf0676fe
RM		 1016};
1017
1018static struct sensor_device_attribute sda_in_max[] = {
e7e1ca6e
GR		 1019 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
1020 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
1021 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
1022 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
1023 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
1024 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
1025 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
1026 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
1027 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
1028 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
cf0676fe
RM		 1029};
1030
ec3e5a16
GR		 1031static ssize_t
1032show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1033{
1034 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1035 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1036 int nr = sensor_attr->index;
3382a918 1037 return sprintf(buf, "%d\n", data->rpm[nr]);
ec3e5a16
GR		 1038}
1039
1040static ssize_t
1041show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1042{
1043 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1044 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1045 int nr = sensor_attr->index;
1046 return sprintf(buf, "%d\n",
26bc440e
GR		 1047 data->fan_from_reg_min(data->fan_min[nr],
1048 data->fan_div[nr]));
08e7e278 1049}
08e7e278
JD		 1050
1051static ssize_t
412fec82
YM		 1052show_fan_div(struct device *dev, struct device_attribute *attr,
1053 char *buf)
08e7e278
JD		 1054{
1055 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 1056 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1057 int nr = sensor_attr->index;
1058 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 1059}
1060
1061static ssize_t
412fec82
YM		 1062store_fan_min(struct device *dev, struct device_attribute *attr,
1063 const char *buf, size_t count)
08e7e278 1064{
1ea6dd38 1065 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 1066 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1067 int nr = sensor_attr->index;
bce26c58
GR		 1068 unsigned long val;
1069 int err;
08e7e278
JD		 1070 unsigned int reg;
1071 u8 new_div;
1072
179c4fdb 1073 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1074 if (err < 0)
1075 return err;
1076
9a61bf63 1077 mutex_lock(&data->update_lock);
26bc440e
GR		 1078 if (!data->has_fan_div) {
1079 /*
1080 * Only NCT6776F for now, so we know that this is a 13 bit
1081 * register
1082 */
ec3e5a16
GR		 1083 if (!val) {
1084 val = 0xff1f;
1085 } else {
1086 if (val > 1350000U)
1087 val = 135000U;
1088 val = 1350000U / val;
1089 val = (val & 0x1f) | ((val << 3) & 0xff00);
1090 }
1091 data->fan_min[nr] = val;
1092 goto done; /* Leave fan divider alone */
1093 }
08e7e278
JD		 1094 if (!val) {
1095 /* No min limit, alarm disabled */
1096 data->fan_min[nr] = 255;
1097 new_div = data->fan_div[nr]; /* No change */
1098 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1099 } else if ((reg = 1350000U / val) >= 128 * 255) {
8969e84d
GR		 1100 /*
1101 * Speed below this value cannot possibly be represented,
1102 * even with the highest divider (128)
1103 */
08e7e278
JD		 1104 data->fan_min[nr] = 254;
1105 new_div = 7; /* 128 == (1 << 7) */
b55f3757
GR		 1106 dev_warn(dev,
1107 "fan%u low limit %lu below minimum %u, set to minimum\n",
1108 nr + 1, val, data->fan_from_reg_min(254, 7));
08e7e278 1109 } else if (!reg) {
8969e84d
GR		 1110 /*
1111 * Speed above this value cannot possibly be represented,
1112 * even with the lowest divider (1)
1113 */
08e7e278
JD		 1114 data->fan_min[nr] = 1;
1115 new_div = 0; /* 1 == (1 << 0) */
b55f3757
GR		 1116 dev_warn(dev,
1117 "fan%u low limit %lu above maximum %u, set to maximum\n",
1118 nr + 1, val, data->fan_from_reg_min(1, 0));
08e7e278 1119 } else {
8969e84d
GR		 1120 /*
1121 * Automatically pick the best divider, i.e. the one such
1122 * that the min limit will correspond to a register value
1123 * in the 96..192 range
1124 */
08e7e278
JD		 1125 new_div = 0;
1126 while (reg > 192 && new_div < 7) {
1127 reg >>= 1;
1128 new_div++;
1129 }
1130 data->fan_min[nr] = reg;
1131 }
1132
8969e84d
GR		 1133 /*
1134 * Write both the fan clock divider (if it changed) and the new
1135 * fan min (unconditionally)
1136 */
08e7e278 1137 if (new_div != data->fan_div[nr]) {
08e7e278
JD		 1138 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1139 nr + 1, div_from_reg(data->fan_div[nr]),
1140 div_from_reg(new_div));
1141 data->fan_div[nr] = new_div;
ec3e5a16 1142 w83627ehf_write_fan_div_common(dev, data, nr);
6b3e4645
JD		 1143 /* Give the chip time to sample a new speed value */
1144 data->last_updated = jiffies;
08e7e278 1145 }
ec3e5a16 1146done:
279af1a9 1147 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
08e7e278 1148 data->fan_min[nr]);
9a61bf63 1149 mutex_unlock(&data->update_lock);
08e7e278
JD		 1150
1151 return count;
1152}
1153
412fec82
YM		 1154static struct sensor_device_attribute sda_fan_input[] = {
1155 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1156 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1157 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1158 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1159 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1160};
08e7e278 1161
a4589dbb
JD		 1162static struct sensor_device_attribute sda_fan_alarm[] = {
1163 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1164 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1165 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1166 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1167 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1168};
1169
412fec82
YM		 1170static struct sensor_device_attribute sda_fan_min[] = {
1171 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1172 store_fan_min, 0),
1173 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1174 store_fan_min, 1),
1175 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1176 store_fan_min, 2),
1177 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1178 store_fan_min, 3),
1179 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1180 store_fan_min, 4),
1181};
08e7e278 1182
412fec82
YM		 1183static struct sensor_device_attribute sda_fan_div[] = {
1184 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1185 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1186 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1187 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1188 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1189};
1190
d36cf32c
GR		 1191static ssize_t
1192show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1193{
1194 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1195 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1196 int nr = sensor_attr->index;
1197 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1198}
1199
ec3e5a16 1200#define show_temp_reg(addr, reg) \
08e7e278 1201static ssize_t \
412fec82
YM		 1202show_##reg(struct device *dev, struct device_attribute *attr, \
1203 char *buf) \
08e7e278
JD		 1204{ \
1205 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1206 struct sensor_device_attribute *sensor_attr = \
1207 to_sensor_dev_attr(attr); \
412fec82 1208 int nr = sensor_attr->index; \
c5794cfa 1209 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->reg[nr])); \
08e7e278 1210}
ec3e5a16
GR		 1211show_temp_reg(reg_temp, temp);
1212show_temp_reg(reg_temp_over, temp_max);
1213show_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1214
ec3e5a16 1215#define store_temp_reg(addr, reg) \
08e7e278 1216static ssize_t \
412fec82
YM		 1217store_##reg(struct device *dev, struct device_attribute *attr, \
1218 const char *buf, size_t count) \
08e7e278 1219{ \
1ea6dd38 1220 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1221 struct sensor_device_attribute *sensor_attr = \
1222 to_sensor_dev_attr(attr); \
412fec82 1223 int nr = sensor_attr->index; \
bce26c58
GR		 1224 int err; \
1225 long val; \
179c4fdb 1226 err = kstrtol(buf, 10, &val); \
bce26c58
GR		 1227 if (err < 0) \
1228 return err; \
9a61bf63 1229 mutex_lock(&data->update_lock); \
c5794cfa
JD		 1230 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1231 w83627ehf_write_temp(data, data->addr[nr], data->reg[nr]); \
9a61bf63 1232 mutex_unlock(&data->update_lock); \
08e7e278
JD		 1233 return count; \
1234}
ec3e5a16
GR		 1235store_temp_reg(reg_temp_over, temp_max);
1236store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1237
840e191d
GR		 1238static ssize_t
1239show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
1240{
1241 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1242 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1243
1244 return sprintf(buf, "%d\n",
1245 data->temp_offset[sensor_attr->index] * 1000);
1246}
1247
1248static ssize_t
1249store_temp_offset(struct device *dev, struct device_attribute *attr,
1250 const char *buf, size_t count)
1251{
1252 struct w83627ehf_data *data = dev_get_drvdata(dev);
1253 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1254 int nr = sensor_attr->index;
1255 long val;
1256 int err;
1257
1258 err = kstrtol(buf, 10, &val);
1259 if (err < 0)
1260 return err;
1261
2a844c14 1262 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
840e191d
GR		 1263
1264 mutex_lock(&data->update_lock);
1265 data->temp_offset[nr] = val;
1266 w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[nr], val);
1267 mutex_unlock(&data->update_lock);
1268 return count;
1269}
1270
da667365
JD		 1271static ssize_t
1272show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1273{
1274 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1275 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1276 int nr = sensor_attr->index;
1277 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1278}
1279
a157d06d 1280static struct sensor_device_attribute sda_temp_input[] = {
bce26c58
GR		 1281 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1282 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1283 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
d36cf32c 1284 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
ec3e5a16
GR		 1285 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1286 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1287 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1288 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1289 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
d36cf32c
GR		 1290};
1291
1292static struct sensor_device_attribute sda_temp_label[] = {
1293 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1294 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1295 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1296 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
ec3e5a16
GR		 1297 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1298 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1299 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1300 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1301 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
a157d06d
GJ		 1302};
1303
1304static struct sensor_device_attribute sda_temp_max[] = {
bce26c58 1305 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1306 store_temp_max, 0),
bce26c58 1307 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1308 store_temp_max, 1),
bce26c58
GR		 1309 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1310 store_temp_max, 2),
ec3e5a16
GR		 1311 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1312 store_temp_max, 3),
1313 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1314 store_temp_max, 4),
1315 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1316 store_temp_max, 5),
1317 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1318 store_temp_max, 6),
1319 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1320 store_temp_max, 7),
1321 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1322 store_temp_max, 8),
a157d06d
GJ		 1323};
1324
1325static struct sensor_device_attribute sda_temp_max_hyst[] = {
bce26c58 1326 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1327 store_temp_max_hyst, 0),
bce26c58 1328 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1329 store_temp_max_hyst, 1),
bce26c58
GR		 1330 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1331 store_temp_max_hyst, 2),
ec3e5a16
GR		 1332 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1333 store_temp_max_hyst, 3),
1334 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1335 store_temp_max_hyst, 4),
1336 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1337 store_temp_max_hyst, 5),
1338 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1339 store_temp_max_hyst, 6),
1340 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1341 store_temp_max_hyst, 7),
1342 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1343 store_temp_max_hyst, 8),
a157d06d
GJ		 1344};
1345
1346static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 1347 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1348 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1349 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 1350};
1351
1352static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 1353 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1354 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1355 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 1356};
08e7e278 1357
840e191d
GR		 1358static struct sensor_device_attribute sda_temp_offset[] = {
1359 SENSOR_ATTR(temp1_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1360 store_temp_offset, 0),
1361 SENSOR_ATTR(temp2_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1362 store_temp_offset, 1),
1363 SENSOR_ATTR(temp3_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1364 store_temp_offset, 2),
1365};
1366
08c79950 1367#define show_pwm_reg(reg) \
e7e1ca6e
GR		 1368static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1369 char *buf) \
08c79950
RM		 1370{ \
1371 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1372 struct sensor_device_attribute *sensor_attr = \
1373 to_sensor_dev_attr(attr); \
08c79950
RM		 1374 int nr = sensor_attr->index; \
1375 return sprintf(buf, "%d\n", data->reg[nr]); \
1376}
1377
1378show_pwm_reg(pwm_mode)
1379show_pwm_reg(pwm_enable)
1380show_pwm_reg(pwm)
1381
1382static ssize_t
1383store_pwm_mode(struct device *dev, struct device_attribute *attr,
1384 const char *buf, size_t count)
1385{
1ea6dd38 1386 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 1387 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
a8b3a3a5 1388 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08c79950 1389 int nr = sensor_attr->index;
bce26c58
GR		 1390 unsigned long val;
1391 int err;
08c79950
RM		 1392 u16 reg;
1393
179c4fdb 1394 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1395 if (err < 0)
1396 return err;
1397
08c79950
RM		 1398 if (val > 1)
1399 return -EINVAL;
ad77c3e1
GR		 1400
1401 /* On NCT67766F, DC mode is only supported for pwm1 */
1402 if (sio_data->kind == nct6776 && nr && val != 1)
1403 return -EINVAL;
1404
08c79950 1405 mutex_lock(&data->update_lock);
1ea6dd38 1406 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1407 data->pwm_mode[nr] = val;
1408 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1409 if (!val)
1410 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 1411 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1412 mutex_unlock(&data->update_lock);
1413 return count;
1414}
1415
1416static ssize_t
1417store_pwm(struct device *dev, struct device_attribute *attr,
1418 const char *buf, size_t count)
1419{
1ea6dd38 1420 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1421 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1422 int nr = sensor_attr->index;
bce26c58
GR		 1423 unsigned long val;
1424 int err;
1425
179c4fdb 1426 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1427 if (err < 0)
1428 return err;
1429
2a844c14 1430 val = clamp_val(val, 0, 255);
08c79950
RM		 1431
1432 mutex_lock(&data->update_lock);
1433 data->pwm[nr] = val;
279af1a9 1434 w83627ehf_write_value(data, data->REG_PWM[nr], val);
08c79950
RM		 1435 mutex_unlock(&data->update_lock);
1436 return count;
1437}
1438
1439static ssize_t
1440store_pwm_enable(struct device *dev, struct device_attribute *attr,
1441 const char *buf, size_t count)
1442{
1ea6dd38 1443 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 1444 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08c79950
RM		 1445 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1446 int nr = sensor_attr->index;
bce26c58
GR		 1447 unsigned long val;
1448 int err;
08c79950
RM		 1449 u16 reg;
1450
179c4fdb 1451 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1452 if (err < 0)
1453 return err;
1454
b84bb518 1455 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
08c79950 1456 return -EINVAL;
ec3e5a16
GR		 1457 /* SmartFan III mode is not supported on NCT6776F */
1458 if (sio_data->kind == nct6776 && val == 4)
1459 return -EINVAL;
1460
08c79950 1461 mutex_lock(&data->update_lock);
08c79950 1462 data->pwm_enable[nr] = val;
ec3e5a16
GR		 1463 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1464 reg = w83627ehf_read_value(data,
1465 NCT6775_REG_FAN_MODE[nr]);
1466 reg &= 0x0f;
1467 reg |= (val - 1) << 4;
1468 w83627ehf_write_value(data,
1469 NCT6775_REG_FAN_MODE[nr], reg);
1470 } else {
1471 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1472 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1473 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1474 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1475 }
08c79950
RM		 1476 mutex_unlock(&data->update_lock);
1477 return count;
1478}
1479
1480
1481#define show_tol_temp(reg) \
1482static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1483 char *buf) \
1484{ \
1485 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1486 struct sensor_device_attribute *sensor_attr = \
1487 to_sensor_dev_attr(attr); \
08c79950 1488 int nr = sensor_attr->index; \
bce26c58 1489 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1490}
1491
1492show_tol_temp(tolerance)
1493show_tol_temp(target_temp)
1494
1495static ssize_t
1496store_target_temp(struct device *dev, struct device_attribute *attr,
1497 const char *buf, size_t count)
1498{
1ea6dd38 1499 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1500 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1501 int nr = sensor_attr->index;
bce26c58
GR		 1502 long val;
1503 int err;
1504
179c4fdb 1505 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1506 if (err < 0)
1507 return err;
1508
2a844c14 1509 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1510
1511 mutex_lock(&data->update_lock);
1512 data->target_temp[nr] = val;
279af1a9 1513 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
08c79950
RM		 1514 mutex_unlock(&data->update_lock);
1515 return count;
1516}
1517
1518static ssize_t
1519store_tolerance(struct device *dev, struct device_attribute *attr,
1520 const char *buf, size_t count)
1521{
1ea6dd38 1522 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 1523 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08c79950
RM		 1524 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1525 int nr = sensor_attr->index;
1526 u16 reg;
bce26c58
GR		 1527 long val;
1528 int err;
1529
179c4fdb 1530 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1531 if (err < 0)
1532 return err;
1533
08c79950 1534 /* Limit the temp to 0C - 15C */
2a844c14 1535 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1536
1537 mutex_lock(&data->update_lock);
ec3e5a16
GR		 1538 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1539 /* Limit tolerance further for NCT6776F */
1540 if (sio_data->kind == nct6776 && val > 7)
1541 val = 7;
1542 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
08c79950 1543 reg = (reg & 0xf0) | val;
ec3e5a16
GR		 1544 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1545 } else {
1546 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1547 if (nr == 1)
1548 reg = (reg & 0x0f) | (val << 4);
1549 else
1550 reg = (reg & 0xf0) | val;
1551 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1552 }
1553 data->tolerance[nr] = val;
08c79950
RM		 1554 mutex_unlock(&data->update_lock);
1555 return count;
1556}
1557
1558static struct sensor_device_attribute sda_pwm[] = {
1559 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1560 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1561 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1562 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1563};
1564
1565static struct sensor_device_attribute sda_pwm_mode[] = {
1566 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1567 store_pwm_mode, 0),
1568 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1569 store_pwm_mode, 1),
1570 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1571 store_pwm_mode, 2),
1572 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1573 store_pwm_mode, 3),
1574};
1575
1576static struct sensor_device_attribute sda_pwm_enable[] = {
1577 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1578 store_pwm_enable, 0),
1579 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1580 store_pwm_enable, 1),
1581 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1582 store_pwm_enable, 2),
1583 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1584 store_pwm_enable, 3),
1585};
1586
1587static struct sensor_device_attribute sda_target_temp[] = {
1588 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1589 store_target_temp, 0),
1590 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1591 store_target_temp, 1),
1592 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1593 store_target_temp, 2),
1594 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1595 store_target_temp, 3),
1596};
1597
1598static struct sensor_device_attribute sda_tolerance[] = {
1599 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1600 store_tolerance, 0),
1601 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1602 store_tolerance, 1),
1603 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1604 store_tolerance, 2),
1605 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1606 store_tolerance, 3),
1607};
1608
08c79950
RM		 1609/* Smart Fan registers */
1610
1611#define fan_functions(reg, REG) \
1612static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1613 char *buf) \
1614{ \
1615 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1616 struct sensor_device_attribute *sensor_attr = \
1617 to_sensor_dev_attr(attr); \
08c79950
RM		 1618 int nr = sensor_attr->index; \
1619 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1620} \
08c79950
RM		 1621static ssize_t \
1622store_##reg(struct device *dev, struct device_attribute *attr, \
1623 const char *buf, size_t count) \
e7e1ca6e 1624{ \
1ea6dd38 1625 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1626 struct sensor_device_attribute *sensor_attr = \
1627 to_sensor_dev_attr(attr); \
08c79950 1628 int nr = sensor_attr->index; \
bce26c58
GR		 1629 unsigned long val; \
1630 int err; \
179c4fdb 1631 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1632 if (err < 0) \
1633 return err; \
2a844c14 1634 val = clamp_val(val, 1, 255); \
08c79950
RM		 1635 mutex_lock(&data->update_lock); \
1636 data->reg[nr] = val; \
da2e0255 1637 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1638 mutex_unlock(&data->update_lock); \
1639 return count; \
1640}
1641
41e9a062
DB		 1642fan_functions(fan_start_output, FAN_START_OUTPUT)
1643fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1644fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1645fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1646
1647#define fan_time_functions(reg, REG) \
1648static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1649 char *buf) \
1650{ \
1651 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1652 struct sensor_device_attribute *sensor_attr = \
1653 to_sensor_dev_attr(attr); \
08c79950
RM		 1654 int nr = sensor_attr->index; \
1655 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1656 step_time_from_reg(data->reg[nr], \
1657 data->pwm_mode[nr])); \
08c79950
RM		 1658} \
1659\
1660static ssize_t \
1661store_##reg(struct device *dev, struct device_attribute *attr, \
1662 const char *buf, size_t count) \
1663{ \
1ea6dd38 1664 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1665 struct sensor_device_attribute *sensor_attr = \
1666 to_sensor_dev_attr(attr); \
08c79950 1667 int nr = sensor_attr->index; \
bce26c58
GR		 1668 unsigned long val; \
1669 int err; \
179c4fdb 1670 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1671 if (err < 0) \
1672 return err; \
1673 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1674 mutex_lock(&data->update_lock); \
1675 data->reg[nr] = val; \
33fa9b62 1676 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1677 mutex_unlock(&data->update_lock); \
1678 return count; \
1679} \
1680
1681fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1682
9bbacbfe 1683static ssize_t name_show(struct device *dev, struct device_attribute *attr,
1ea6dd38
DH		 1684 char *buf)
1685{
1686 struct w83627ehf_data *data = dev_get_drvdata(dev);
1687
1688 return sprintf(buf, "%s\n", data->name);
1689}
9bbacbfe 1690static DEVICE_ATTR_RO(name);
08c79950
RM		 1691
1692static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1693 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1694 store_fan_stop_time, 3),
41e9a062
DB		 1695 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1696 store_fan_start_output, 3),
1697 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1698 store_fan_stop_output, 3),
1699 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1700 store_fan_max_output, 3),
1701 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1702 store_fan_step_output, 3),
08c79950
RM		 1703};
1704
eff7687d
JD		 1705static struct sensor_device_attribute sda_sf3_arrays_fan3[] = {
1706 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1707 store_fan_stop_time, 2),
1708 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1709 store_fan_start_output, 2),
1710 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1711 store_fan_stop_output, 2),
1712};
1713
08c79950
RM		 1714static struct sensor_device_attribute sda_sf3_arrays[] = {
1715 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1716 store_fan_stop_time, 0),
1717 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1718 store_fan_stop_time, 1),
41e9a062
DB		 1719 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1720 store_fan_start_output, 0),
1721 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1722 store_fan_start_output, 1),
41e9a062
DB		 1723 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1724 store_fan_stop_output, 0),
1725 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1726 store_fan_stop_output, 1),
da2e0255 1727};
41e9a062 1728
da2e0255
GR		 1729
1730/*
1731 * pwm1 and pwm3 don't support max and step settings on all chips.
1732 * Need to check support while generating/removing attribute files.
1733 */
1734static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1735 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1736 store_fan_max_output, 0),
1737 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1738 store_fan_step_output, 0),
41e9a062
DB		 1739 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1740 store_fan_max_output, 1),
1741 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1742 store_fan_step_output, 1),
da2e0255
GR		 1743 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1744 store_fan_max_output, 2),
1745 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1746 store_fan_step_output, 2),
08c79950
RM		 1747};
1748
fc18d6c0 1749static ssize_t
9bbacbfe 1750cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
fc18d6c0
JD		 1751{
1752 struct w83627ehf_data *data = dev_get_drvdata(dev);
1753 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1754}
9bbacbfe 1755static DEVICE_ATTR_RO(cpu0_vid);
fc18d6c0 1756
363a12a4
DA		 1757
1758/* Case open detection */
1759
1760static ssize_t
1761show_caseopen(struct device *dev, struct device_attribute *attr, char *buf)
1762{
1763 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1764
1765 return sprintf(buf, "%d\n",
1766 !!(data->caseopen & to_sensor_dev_attr_2(attr)->index));
1767}
1768
1769static ssize_t
1770clear_caseopen(struct device *dev, struct device_attribute *attr,
1771 const char *buf, size_t count)
1772{
1773 struct w83627ehf_data *data = dev_get_drvdata(dev);
1774 unsigned long val;
1775 u16 reg, mask;
1776
179c4fdb 1777 if (kstrtoul(buf, 10, &val) || val != 0)
363a12a4
DA		 1778 return -EINVAL;
1779
1780 mask = to_sensor_dev_attr_2(attr)->nr;
1781
1782 mutex_lock(&data->update_lock);
1783 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1784 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1785 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1786 data->valid = 0; /* Force cache refresh */
1787 mutex_unlock(&data->update_lock);
1788
1789 return count;
1790}
1791
1792static struct sensor_device_attribute_2 sda_caseopen[] = {
1793 SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1794 clear_caseopen, 0x80, 0x10),
1795 SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1796 clear_caseopen, 0x40, 0x40),
1797};
1798
08e7e278 1799/*
1ea6dd38 1800 * Driver and device management
08e7e278
JD		 1801 */
1802
c18beb5b
DH		 1803static void w83627ehf_device_remove_files(struct device *dev)
1804{
8969e84d
GR		 1805 /*
1806 * some entries in the following arrays may not have been used in
1807 * device_create_file(), but device_remove_file() will ignore them
1808 */
c18beb5b 1809 int i;
1ea6dd38 1810 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1811
1812 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1813 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1814 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1815 struct sensor_device_attribute *attr =
1816 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 1817 if (data->REG_FAN_STEP_OUTPUT &&
1818 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
da2e0255
GR		 1819 device_remove_file(dev, &attr->dev_attr);
1820 }
eff7687d
JD		 1821 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++)
1822 device_remove_file(dev, &sda_sf3_arrays_fan3[i].dev_attr);
c18beb5b
DH		 1823 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1824 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1825 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1826 if ((i == 6) && data->in6_skip)
1827 continue;
c18beb5b
DH		 1828 device_remove_file(dev, &sda_in_input[i].dev_attr);
1829 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1830 device_remove_file(dev, &sda_in_min[i].dev_attr);
1831 device_remove_file(dev, &sda_in_max[i].dev_attr);
1832 }
1833 for (i = 0; i < 5; i++) {
1834 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1835 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1836 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1837 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1838 }
237c8d2f 1839 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1840 device_remove_file(dev, &sda_pwm[i].dev_attr);
1841 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1842 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1843 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1844 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1845 }
d36cf32c
GR		 1846 for (i = 0; i < NUM_REG_TEMP; i++) {
1847 if (!(data->have_temp & (1 << i)))
a157d06d
GJ		 1848 continue;
1849 device_remove_file(dev, &sda_temp_input[i].dev_attr);
d36cf32c 1850 device_remove_file(dev, &sda_temp_label[i].dev_attr);
eff7687d
JD		 1851 if (i == 2 && data->temp3_val_only)
1852 continue;
a157d06d
GJ		 1853 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1854 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
ec3e5a16
GR		 1855 if (i > 2)
1856 continue;
a157d06d
GJ		 1857 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1858 device_remove_file(dev, &sda_temp_type[i].dev_attr);
840e191d 1859 device_remove_file(dev, &sda_temp_offset[i].dev_attr);
a157d06d 1860 }
c18beb5b 1861
363a12a4
DA		 1862 device_remove_file(dev, &sda_caseopen[0].dev_attr);
1863 device_remove_file(dev, &sda_caseopen[1].dev_attr);
1864
1ea6dd38 1865 device_remove_file(dev, &dev_attr_name);
cbe311f2 1866 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1867}
08e7e278 1868
1ea6dd38 1869/* Get the monitoring functions started */
6c931ae1 1870static inline void w83627ehf_init_device(struct w83627ehf_data *data,
bf164c58 1871 enum kinds kind)
08e7e278
JD		 1872{
1873 int i;
da667365 1874 u8 tmp, diode;
08e7e278
JD		 1875
1876 /* Start monitoring is needed */
1ea6dd38 1877 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1878 if (!(tmp & 0x01))
1ea6dd38 1879 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1880 tmp | 0x01);
1881
d36cf32c
GR		 1882 /* Enable temperature sensors if needed */
1883 for (i = 0; i < NUM_REG_TEMP; i++) {
1884 if (!(data->have_temp & (1 << i)))
1885 continue;
ec3e5a16 1886 if (!data->reg_temp_config[i])
d36cf32c 1887 continue;
1ea6dd38 1888 tmp = w83627ehf_read_value(data,
ec3e5a16 1889 data->reg_temp_config[i]);
08e7e278 1890 if (tmp & 0x01)
1ea6dd38 1891 w83627ehf_write_value(data,
ec3e5a16 1892 data->reg_temp_config[i],
08e7e278
JD		 1893 tmp & 0xfe);
1894 }
d3130f0e
JD		 1895
1896 /* Enable VBAT monitoring if needed */
1897 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1898 if (!(tmp & 0x01))
1899 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1900
1901 /* Get thermal sensor types */
bf164c58
JD		 1902 switch (kind) {
1903 case w83627ehf:
1904 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1905 break;
eff7687d
JD		 1906 case w83627uhg:
1907 diode = 0x00;
1908 break;
bf164c58
JD		 1909 default:
1910 diode = 0x70;
1911 }
da667365 1912 for (i = 0; i < 3; i++) {
bfa02b0d
GR		 1913 const char *label = NULL;
1914
1915 if (data->temp_label)
1916 label = data->temp_label[data->temp_src[i]];
2265cef2
JD		 1917
1918 /* Digital source overrides analog type */
bfa02b0d 1919 if (label && strncmp(label, "PECI", 4) == 0)
2265cef2 1920 data->temp_type[i] = 6;
bfa02b0d 1921 else if (label && strncmp(label, "AMD", 3) == 0)
2265cef2
JD		 1922 data->temp_type[i] = 5;
1923 else if ((tmp & (0x02 << i)))
bf164c58 1924 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
da667365
JD		 1925 else
1926 data->temp_type[i] = 4; /* thermistor */
1927 }
08e7e278
JD		 1928}
1929
ec3e5a16
GR		 1930static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1931 int r1, int r2)
1932{
ffe3df53
FF		 1933 swap(data->temp_src[r1], data->temp_src[r2]);
1934 swap(data->reg_temp[r1], data->reg_temp[r2]);
1935 swap(data->reg_temp_over[r1], data->reg_temp_over[r2]);
1936 swap(data->reg_temp_hyst[r1], data->reg_temp_hyst[r2]);
1937 swap(data->reg_temp_config[r1], data->reg_temp_config[r2]);
ec3e5a16
GR		 1938}
1939
6c931ae1 1940static void
6ba71de5
JD		 1941w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1942{
1943 int i;
1944
1945 for (i = 0; i < n_temp; i++) {
1946 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1947 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1948 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1949 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1950 }
1951}
1952
6c931ae1 1953static void
03f5de2b
JD		 1954w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1955 struct w83627ehf_data *data)
1956{
1957 int fan3pin, fan4pin, fan4min, fan5pin, regval;
1958
eff7687d
JD		 1959 /* The W83627UHG is simple, only two fan inputs, no config */
1960 if (sio_data->kind == w83627uhg) {
1961 data->has_fan = 0x03; /* fan1 and fan2 */
1962 data->has_fan_min = 0x03;
1963 return;
1964 }
1965
03f5de2b
JD		 1966 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1967 if (sio_data->kind == nct6775) {
1968 /* On NCT6775, fan4 shares pins with the fdc interface */
1969 fan3pin = 1;
1970 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
1971 fan4min = 0;
1972 fan5pin = 0;
1973 } else if (sio_data->kind == nct6776) {
585c0fd8
GR		 1974 bool gpok = superio_inb(sio_data->sioreg, 0x27) & 0x80;
1975
1976 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1977 regval = superio_inb(sio_data->sioreg, SIO_REG_ENABLE);
1978
1979 if (regval & 0x80)
1980 fan3pin = gpok;
1981 else
1982 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
1983
1984 if (regval & 0x40)
1985 fan4pin = gpok;
1986 else
1987 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
1988
1989 if (regval & 0x20)
1990 fan5pin = gpok;
1991 else
1992 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
1993
03f5de2b
JD		 1994 fan4min = fan4pin;
1995 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
1996 fan3pin = 1;
1997 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1998 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
1999 fan4min = fan4pin;
2000 } else {
2001 fan3pin = 1;
2002 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
2003 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2004 fan4min = fan4pin;
2005 }
2006
03f5de2b
JD		 2007 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2008 data->has_fan |= (fan3pin << 2);
2009 data->has_fan_min |= (fan3pin << 2);
2010
2011 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2012 /*
2013 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
2014 * register
2015 */
2016 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
2017 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
2018 } else {
2019 /*
2020 * It looks like fan4 and fan5 pins can be alternatively used
2021 * as fan on/off switches, but fan5 control is write only :/
2022 * We assume that if the serial interface is disabled, designers
2023 * connected fan5 as input unless they are emitting log 1, which
2024 * is not the default.
2025 */
2026 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2027 if ((regval & (1 << 2)) && fan4pin) {
2028 data->has_fan |= (1 << 3);
2029 data->has_fan_min |= (1 << 3);
2030 }
2031 if (!(regval & (1 << 1)) && fan5pin) {
2032 data->has_fan |= (1 << 4);
2033 data->has_fan_min |= (1 << 4);
2034 }
2035 }
2036}
2037
6c931ae1 2038static int w83627ehf_probe(struct platform_device *pdev)
08e7e278 2039{
1ea6dd38 2040 struct device *dev = &pdev->dev;
a8b3a3a5 2041 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
08e7e278 2042 struct w83627ehf_data *data;
1ea6dd38 2043 struct resource *res;
03f5de2b 2044 u8 en_vrm10;
08e7e278
JD		 2045 int i, err = 0;
2046
1ea6dd38
DH		 2047 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2048 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 2049 err = -EBUSY;
1ea6dd38
DH		 2050 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2051 (unsigned long)res->start,
2052 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 2053 goto exit;
2054 }
2055
32260d94
GR		 2056 data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
2057 GFP_KERNEL);
e7e1ca6e 2058 if (!data) {
08e7e278
JD		 2059 err = -ENOMEM;
2060 goto exit_release;
2061 }
08e7e278 2062
1ea6dd38 2063 data->addr = res->start;
9a61bf63 2064 mutex_init(&data->lock);
9a61bf63 2065 mutex_init(&data->update_lock);
1ea6dd38 2066 data->name = w83627ehf_device_names[sio_data->kind];
3300fb4f 2067 data->bank = 0xff; /* Force initial bank selection */
1ea6dd38 2068 platform_set_drvdata(pdev, data);
08e7e278 2069
237c8d2f
GJ		 2070 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
2071 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
eff7687d
JD		 2072 /* 667HG, NCT6775F, and NCT6776F have 3 pwms, and 627UHG has only 2 */
2073 switch (sio_data->kind) {
2074 default:
2075 data->pwm_num = 4;
2076 break;
2077 case w83667hg:
2078 case w83667hg_b:
2079 case nct6775:
2080 case nct6776:
2081 data->pwm_num = 3;
2082 break;
2083 case w83627uhg:
2084 data->pwm_num = 2;
2085 break;
2086 }
08e7e278 2087
6ba71de5 2088 /* Default to 3 temperature inputs, code below will adjust as needed */
d36cf32c 2089 data->have_temp = 0x07;
ec3e5a16
GR		 2090
2091 /* Deal with temperature register setup first. */
2092 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2093 int mask = 0;
2094
2095 /*
2096 * Display temperature sensor output only if it monitors
2097 * a source other than one already reported. Always display
2098 * first three temperature registers, though.
2099 */
2100 for (i = 0; i < NUM_REG_TEMP; i++) {
2101 u8 src;
2102
2103 data->reg_temp[i] = NCT6775_REG_TEMP[i];
2104 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
2105 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
2106 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
2107
2108 src = w83627ehf_read_value(data,
2109 NCT6775_REG_TEMP_SOURCE[i]);
2110 src &= 0x1f;
2111 if (src && !(mask & (1 << src))) {
2112 data->have_temp |= 1 << i;
2113 mask |= 1 << src;
2114 }
2115
2116 data->temp_src[i] = src;
2117
2118 /*
2119 * Now do some register swapping if index 0..2 don't
2120 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
2121 * Idea is to have the first three attributes
2122 * report SYSTIN, CPUIN, and AUXIN if possible
2123 * without overriding the basic system configuration.
2124 */
2125 if (i > 0 && data->temp_src[0] != 1
2126 && data->temp_src[i] == 1)
2127 w82627ehf_swap_tempreg(data, 0, i);
2128 if (i > 1 && data->temp_src[1] != 2
2129 && data->temp_src[i] == 2)
2130 w82627ehf_swap_tempreg(data, 1, i);
2131 if (i > 2 && data->temp_src[2] != 3
2132 && data->temp_src[i] == 3)
2133 w82627ehf_swap_tempreg(data, 2, i);
2134 }
2135 if (sio_data->kind == nct6776) {
2136 /*
2137 * On NCT6776, AUXTIN and VIN3 pins are shared.
2138 * Only way to detect it is to check if AUXTIN is used
2139 * as a temperature source, and if that source is
2140 * enabled.
2141 *
2142 * If that is the case, disable in6, which reports VIN3.
2143 * Otherwise disable temp3.
2144 */
2145 if (data->temp_src[2] == 3) {
2146 u8 reg;
2147
2148 if (data->reg_temp_config[2])
2149 reg = w83627ehf_read_value(data,
2150 data->reg_temp_config[2]);
2151 else
2152 reg = 0; /* Assume AUXTIN is used */
2153
2154 if (reg & 0x01)
2155 data->have_temp &= ~(1 << 2);
2156 else
2157 data->in6_skip = 1;
2158 }
02309ad2
GR		 2159 data->temp_label = nct6776_temp_label;
2160 } else {
2161 data->temp_label = nct6775_temp_label;
ec3e5a16 2162 }
840e191d
GR		 2163 data->have_temp_offset = data->have_temp & 0x07;
2164 for (i = 0; i < 3; i++) {
2165 if (data->temp_src[i] > 3)
2166 data->have_temp_offset &= ~(1 << i);
2167 }
d36cf32c
GR		 2168 } else if (sio_data->kind == w83667hg_b) {
2169 u8 reg;
2170
6ba71de5
JD		 2171 w83627ehf_set_temp_reg_ehf(data, 4);
2172
ec3e5a16
GR		 2173 /*
2174 * Temperature sources are selected with bank 0, registers 0x49
2175 * and 0x4a.
2176 */
d36cf32c
GR		 2177 reg = w83627ehf_read_value(data, 0x4a);
2178 data->temp_src[0] = reg >> 5;
2179 reg = w83627ehf_read_value(data, 0x49);
2180 data->temp_src[1] = reg & 0x07;
ec3e5a16 2181 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 2182
2183 /*
2184 * W83667HG-B has another temperature register at 0x7e.
2185 * The temperature source is selected with register 0x7d.
2186 * Support it if the source differs from already reported
2187 * sources.
2188 */
2189 reg = w83627ehf_read_value(data, 0x7d);
2190 reg &= 0x07;
2191 if (reg != data->temp_src[0] && reg != data->temp_src[1]
2192 && reg != data->temp_src[2]) {
2193 data->temp_src[3] = reg;
2194 data->have_temp |= 1 << 3;
2195 }
2196
2197 /*
2198 * Chip supports either AUXTIN or VIN3. Try to find out which
2199 * one.
2200 */
2201 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
2202 if (data->temp_src[2] == 2 && (reg & 0x01))
2203 data->have_temp &= ~(1 << 2);
2204
2205 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2206 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2207 data->in6_skip = 1;
2208
eff7687d 2209 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2210 data->have_temp_offset = data->have_temp & 0x07;
2211 for (i = 0; i < 3; i++) {
2212 if (data->temp_src[i] > 2)
2213 data->have_temp_offset &= ~(1 << i);
2214 }
eff7687d
JD		 2215 } else if (sio_data->kind == w83627uhg) {
2216 u8 reg;
2217
2218 w83627ehf_set_temp_reg_ehf(data, 3);
2219
2220 /*
aacb6b00 2221 * Temperature sources for temp2 and temp3 are selected with
eff7687d
JD		 2222 * bank 0, registers 0x49 and 0x4a.
2223 */
2224 data->temp_src[0] = 0; /* SYSTIN */
2225 reg = w83627ehf_read_value(data, 0x49) & 0x07;
2226 /* Adjust to have the same mapping as other source registers */
2227 if (reg == 0)
aacb6b00 2228 data->temp_src[1] = 1;
eff7687d 2229 else if (reg >= 2 && reg <= 5)
aacb6b00 2230 data->temp_src[1] = reg + 2;
eff7687d
JD		 2231 else /* should never happen */
2232 data->have_temp &= ~(1 << 1);
2233 reg = w83627ehf_read_value(data, 0x4a);
2234 data->temp_src[2] = reg >> 5;
2235
2236 /*
2237 * Skip temp3 if source is invalid or the same as temp1
2238 * or temp2.
2239 */
2240 if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
2241 data->temp_src[2] == data->temp_src[0] ||
2242 ((data->have_temp & (1 << 1)) &&
2243 data->temp_src[2] == data->temp_src[1]))
2244 data->have_temp &= ~(1 << 2);
2245 else
2246 data->temp3_val_only = 1; /* No limit regs */
2247
2248 data->in6_skip = 1; /* No VIN3 */
2249
d36cf32c 2250 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2251 data->have_temp_offset = data->have_temp & 0x03;
2252 for (i = 0; i < 3; i++) {
2253 if (data->temp_src[i] > 1)
2254 data->have_temp_offset &= ~(1 << i);
2255 }
ec3e5a16 2256 } else {
6ba71de5
JD		 2257 w83627ehf_set_temp_reg_ehf(data, 3);
2258
ec3e5a16 2259 /* Temperature sources are fixed */
6ba71de5
JD		 2260
2261 if (sio_data->kind == w83667hg) {
2262 u8 reg;
2263
2264 /*
2265 * Chip supports either AUXTIN or VIN3. Try to find
2266 * out which one.
2267 */
2268 reg = w83627ehf_read_value(data,
2269 W83627EHF_REG_TEMP_CONFIG[2]);
2270 if (reg & 0x01)
2271 data->have_temp &= ~(1 << 2);
2272 else
2273 data->in6_skip = 1;
ec3e5a16 2274 }
840e191d 2275 data->have_temp_offset = data->have_temp & 0x07;
a157d06d
GJ		 2276 }
2277
ec3e5a16 2278 if (sio_data->kind == nct6775) {
26bc440e
GR		 2279 data->has_fan_div = true;
2280 data->fan_from_reg = fan_from_reg16;
2281 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2282 data->REG_PWM = NCT6775_REG_PWM;
2283 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2284 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2285 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2286 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2287 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2288 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2289 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2290 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2291 } else if (sio_data->kind == nct6776) {
26bc440e
GR		 2292 data->has_fan_div = false;
2293 data->fan_from_reg = fan_from_reg13;
2294 data->fan_from_reg_min = fan_from_reg13;
ec3e5a16
GR		 2295 data->REG_PWM = NCT6775_REG_PWM;
2296 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2297 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2298 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2299 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2300 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2301 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2302 } else if (sio_data->kind == w83667hg_b) {
26bc440e
GR		 2303 data->has_fan_div = true;
2304 data->fan_from_reg = fan_from_reg8;
2305 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2306 data->REG_PWM = W83627EHF_REG_PWM;
2307 data->REG_TARGET = W83627EHF_REG_TARGET;
2308 data->REG_FAN = W83627EHF_REG_FAN;
2309 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2310 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2311 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2312 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2313 data->REG_FAN_MAX_OUTPUT =
2314 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2315 data->REG_FAN_STEP_OUTPUT =
2316 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2317 } else {
26bc440e
GR		 2318 data->has_fan_div = true;
2319 data->fan_from_reg = fan_from_reg8;
2320 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2321 data->REG_PWM = W83627EHF_REG_PWM;
2322 data->REG_TARGET = W83627EHF_REG_TARGET;
2323 data->REG_FAN = W83627EHF_REG_FAN;
2324 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2325 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2326 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2327 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2328 data->REG_FAN_MAX_OUTPUT =
2329 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2330 data->REG_FAN_STEP_OUTPUT =
2331 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2332 }
da2e0255 2333
eff7687d
JD		 2334 /* Setup input voltage scaling factors */
2335 if (sio_data->kind == w83627uhg)
2336 data->scale_in = scale_in_w83627uhg;
2337 else
2338 data->scale_in = scale_in_common;
2339
08e7e278 2340 /* Initialize the chip */
bf164c58 2341 w83627ehf_init_device(data, sio_data->kind);
08e7e278 2342
fc18d6c0 2343 data->vrm = vid_which_vrm();
0d023530
KS		 2344
2345 err = superio_enter(sio_data->sioreg);
2346 if (err)
2347 goto exit_release;
2348
fc18d6c0 2349 /* Read VID value */
ec3e5a16
GR		 2350 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2351 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
8969e84d
GR		 2352 /*
2353 * W83667HG has different pins for VID input and output, so
2354 * we can get the VID input values directly at logical device D
2355 * 0xe3.
2356 */
237c8d2f
GJ		 2357 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2358 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2 2359 err = device_create_file(dev, &dev_attr_cpu0_vid);
0d023530
KS		 2360 if (err) {
2361 superio_exit(sio_data->sioreg);
cbe311f2 2362 goto exit_release;
0d023530 2363 }
eff7687d 2364 } else if (sio_data->kind != w83627uhg) {
237c8d2f
GJ		 2365 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2366 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
8969e84d
GR		 2367 /*
2368 * Set VID input sensibility if needed. In theory the
2369 * BIOS should have set it, but in practice it's not
2370 * always the case. We only do it for the W83627EHF/EHG
2371 * because the W83627DHG is more complex in this
2372 * respect.
2373 */
237c8d2f
GJ		 2374 if (sio_data->kind == w83627ehf) {
2375 en_vrm10 = superio_inb(sio_data->sioreg,
2376 SIO_REG_EN_VRM10);
2377 if ((en_vrm10 & 0x08) && data->vrm == 90) {
b55f3757
GR		 2378 dev_warn(dev,
2379 "Setting VID input voltage to TTL\n");
237c8d2f
GJ		 2380 superio_outb(sio_data->sioreg,
2381 SIO_REG_EN_VRM10,
2382 en_vrm10 & ~0x08);
2383 } else if (!(en_vrm10 & 0x08)
2384 && data->vrm == 100) {
b55f3757
GR		 2385 dev_warn(dev,
2386 "Setting VID input voltage to VRM10\n");
237c8d2f
GJ		 2387 superio_outb(sio_data->sioreg,
2388 SIO_REG_EN_VRM10,
2389 en_vrm10 | 0x08);
2390 }
2391 }
2392
2393 data->vid = superio_inb(sio_data->sioreg,
2394 SIO_REG_VID_DATA);
2395 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2396 data->vid &= 0x3f;
2397
2398 err = device_create_file(dev, &dev_attr_cpu0_vid);
0d023530
KS		 2399 if (err) {
2400 superio_exit(sio_data->sioreg);
237c8d2f 2401 goto exit_release;
0d023530 2402 }
237c8d2f 2403 } else {
b55f3757
GR		 2404 dev_info(dev,
2405 "VID pins in output mode, CPU VID not available\n");
237c8d2f 2406 }
fc18d6c0
JD		 2407 }
2408
d42e869a
ID		 2409 if (fan_debounce &&
2410 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2411 u8 tmp;
2412
2413 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2414 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2415 if (sio_data->kind == nct6776)
2416 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2417 0x3e | tmp);
2418 else
2419 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2420 0x1e | tmp);
2421 pr_info("Enabled fan debounce for chip %s\n", data->name);
2422 }
2423
03f5de2b 2424 w83627ehf_check_fan_inputs(sio_data, data);
08e7e278 2425
0d023530
KS		 2426 superio_exit(sio_data->sioreg);
2427
ea7be66c 2428 /* Read fan clock dividers immediately */
ec3e5a16
GR		 2429 w83627ehf_update_fan_div_common(dev, data);
2430
b84bb518
GR		 2431 /* Read pwm data to save original values */
2432 w83627ehf_update_pwm_common(dev, data);
2433 for (i = 0; i < data->pwm_num; i++)
2434 data->pwm_enable_orig[i] = data->pwm_enable[i];
2435
08e7e278 2436 /* Register sysfs hooks */
e7e1ca6e
GR		 2437 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2438 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2439 if (err)
c18beb5b 2440 goto exit_remove;
e7e1ca6e 2441 }
08c79950 2442
da2e0255
GR		 2443 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2444 struct sensor_device_attribute *attr =
2445 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 2446 if (data->REG_FAN_STEP_OUTPUT &&
2447 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
da2e0255
GR		 2448 err = device_create_file(dev, &attr->dev_attr);
2449 if (err)
2450 goto exit_remove;
2451 }
2452 }
eff7687d
JD		 2453 /* if fan3 and fan4 are enabled create the sf3 files for them */
2454 if ((data->has_fan & (1 << 2)) && data->pwm_num >= 3)
2455 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++) {
2456 err = device_create_file(dev,
2457 &sda_sf3_arrays_fan3[i].dev_attr);
2458 if (err)
2459 goto exit_remove;
2460 }
237c8d2f 2461 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b 2462 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
e7e1ca6e
GR		 2463 err = device_create_file(dev,
2464 &sda_sf3_arrays_fan4[i].dev_attr);
2465 if (err)
c18beb5b
DH		 2466 goto exit_remove;
2467 }
08c79950 2468
a157d06d
GJ		 2469 for (i = 0; i < data->in_num; i++) {
2470 if ((i == 6) && data->in6_skip)
2471 continue;
c18beb5b
DH		 2472 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2473 || (err = device_create_file(dev,
2474 &sda_in_alarm[i].dev_attr))
2475 || (err = device_create_file(dev,
2476 &sda_in_min[i].dev_attr))
2477 || (err = device_create_file(dev,
2478 &sda_in_max[i].dev_attr)))
2479 goto exit_remove;
a157d06d 2480 }
cf0676fe 2481
412fec82 2482 for (i = 0; i < 5; i++) {
08c79950 2483 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 2484 if ((err = device_create_file(dev,
2485 &sda_fan_input[i].dev_attr))
2486 || (err = device_create_file(dev,
ec3e5a16 2487 &sda_fan_alarm[i].dev_attr)))
c18beb5b 2488 goto exit_remove;
ec3e5a16
GR		 2489 if (sio_data->kind != nct6776) {
2490 err = device_create_file(dev,
2491 &sda_fan_div[i].dev_attr);
2492 if (err)
2493 goto exit_remove;
2494 }
2495 if (data->has_fan_min & (1 << i)) {
2496 err = device_create_file(dev,
2497 &sda_fan_min[i].dev_attr);
2498 if (err)
2499 goto exit_remove;
2500 }
237c8d2f 2501 if (i < data->pwm_num &&
c18beb5b
DH		 2502 ((err = device_create_file(dev,
2503 &sda_pwm[i].dev_attr))
2504 || (err = device_create_file(dev,
2505 &sda_pwm_mode[i].dev_attr))
2506 || (err = device_create_file(dev,
2507 &sda_pwm_enable[i].dev_attr))
2508 || (err = device_create_file(dev,
2509 &sda_target_temp[i].dev_attr))
2510 || (err = device_create_file(dev,
2511 &sda_tolerance[i].dev_attr))))
2512 goto exit_remove;
08c79950 2513 }
08e7e278 2514 }
08c79950 2515
d36cf32c
GR		 2516 for (i = 0; i < NUM_REG_TEMP; i++) {
2517 if (!(data->have_temp & (1 << i)))
a157d06d 2518 continue;
d36cf32c
GR		 2519 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2520 if (err)
2521 goto exit_remove;
2522 if (data->temp_label) {
2523 err = device_create_file(dev,
2524 &sda_temp_label[i].dev_attr);
2525 if (err)
2526 goto exit_remove;
2527 }
eff7687d
JD		 2528 if (i == 2 && data->temp3_val_only)
2529 continue;
ec3e5a16
GR		 2530 if (data->reg_temp_over[i]) {
2531 err = device_create_file(dev,
2532 &sda_temp_max[i].dev_attr);
2533 if (err)
2534 goto exit_remove;
2535 }
2536 if (data->reg_temp_hyst[i]) {
2537 err = device_create_file(dev,
2538 &sda_temp_max_hyst[i].dev_attr);
2539 if (err)
2540 goto exit_remove;
2541 }
d36cf32c 2542 if (i > 2)
ec3e5a16
GR		 2543 continue;
2544 if ((err = device_create_file(dev,
a157d06d
GJ		 2545 &sda_temp_alarm[i].dev_attr))
2546 || (err = device_create_file(dev,
2547 &sda_temp_type[i].dev_attr)))
c18beb5b 2548 goto exit_remove;
840e191d
GR		 2549 if (data->have_temp_offset & (1 << i)) {
2550 err = device_create_file(dev,
2551 &sda_temp_offset[i].dev_attr);
2552 if (err)
2553 goto exit_remove;
2554 }
a157d06d 2555 }
c18beb5b 2556
363a12a4
DA		 2557 err = device_create_file(dev, &sda_caseopen[0].dev_attr);
2558 if (err)
2559 goto exit_remove;
2560
2561 if (sio_data->kind == nct6776) {
2562 err = device_create_file(dev, &sda_caseopen[1].dev_attr);
2563 if (err)
2564 goto exit_remove;
2565 }
2566
1ea6dd38
DH		 2567 err = device_create_file(dev, &dev_attr_name);
2568 if (err)
2569 goto exit_remove;
2570
1beeffe4
TJ		 2571 data->hwmon_dev = hwmon_device_register(dev);
2572 if (IS_ERR(data->hwmon_dev)) {
2573 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 2574 goto exit_remove;
2575 }
08e7e278
JD		 2576
2577 return 0;
2578
c18beb5b
DH		 2579exit_remove:
2580 w83627ehf_device_remove_files(dev);
08e7e278 2581exit_release:
1ea6dd38 2582 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 2583exit:
2584 return err;
2585}
2586
281dfd0b 2587static int w83627ehf_remove(struct platform_device *pdev)
08e7e278 2588{
1ea6dd38 2589 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 2590
1beeffe4 2591 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 2592 w83627ehf_device_remove_files(&pdev->dev);
2593 release_region(data->addr, IOREGION_LENGTH);
08e7e278
JD		 2594
2595 return 0;
2596}
2597
7e630bb5
JD		 2598#ifdef CONFIG_PM
2599static int w83627ehf_suspend(struct device *dev)
2600{
2601 struct w83627ehf_data *data = w83627ehf_update_device(dev);
a8b3a3a5 2602 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
7e630bb5
JD		 2603
2604 mutex_lock(&data->update_lock);
2605 data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
2606 if (sio_data->kind == nct6775) {
2607 data->fandiv1 = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
2608 data->fandiv2 = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
2609 }
2610 mutex_unlock(&data->update_lock);
2611
2612 return 0;
2613}
2614
2615static int w83627ehf_resume(struct device *dev)
2616{
2617 struct w83627ehf_data *data = dev_get_drvdata(dev);
a8b3a3a5 2618 struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
7e630bb5
JD		 2619 int i;
2620
2621 mutex_lock(&data->update_lock);
2622 data->bank = 0xff; /* Force initial bank selection */
2623
2624 /* Restore limits */
2625 for (i = 0; i < data->in_num; i++) {
2626 if ((i == 6) && data->in6_skip)
2627 continue;
2628
2629 w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
2630 data->in_min[i]);
2631 w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
2632 data->in_max[i]);
2633 }
2634
2635 for (i = 0; i < 5; i++) {
2636 if (!(data->has_fan_min & (1 << i)))
2637 continue;
2638
2639 w83627ehf_write_value(data, data->REG_FAN_MIN[i],
2640 data->fan_min[i]);
2641 }
2642
2643 for (i = 0; i < NUM_REG_TEMP; i++) {
2644 if (!(data->have_temp & (1 << i)))
2645 continue;
2646
2647 if (data->reg_temp_over[i])
2648 w83627ehf_write_temp(data, data->reg_temp_over[i],
2649 data->temp_max[i]);
2650 if (data->reg_temp_hyst[i])
2651 w83627ehf_write_temp(data, data->reg_temp_hyst[i],
2652 data->temp_max_hyst[i]);
45633fb3
JD		 2653 if (i > 2)
2654 continue;
7e630bb5
JD		 2655 if (data->have_temp_offset & (1 << i))
2656 w83627ehf_write_value(data,
2657 W83627EHF_REG_TEMP_OFFSET[i],
2658 data->temp_offset[i]);
2659 }
2660
2661 /* Restore other settings */
2662 w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
2663 if (sio_data->kind == nct6775) {
2664 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
2665 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
2666 }
2667
2668 /* Force re-reading all values */
2669 data->valid = 0;
2670 mutex_unlock(&data->update_lock);
2671
2672 return 0;
2673}
2674
2675static const struct dev_pm_ops w83627ehf_dev_pm_ops = {
2676 .suspend = w83627ehf_suspend,
2677 .resume = w83627ehf_resume,
e3b20b3f
HJ		 2678 .freeze = w83627ehf_suspend,
2679 .restore = w83627ehf_resume,
7e630bb5
JD		 2680};
2681
2682#define W83627EHF_DEV_PM_OPS (&w83627ehf_dev_pm_ops)
2683#else
2684#define W83627EHF_DEV_PM_OPS NULL
2685#endif /* CONFIG_PM */
2686
1ea6dd38 2687static struct platform_driver w83627ehf_driver = {
cdaf7934 2688 .driver = {
1ea6dd38 2689 .name = DRVNAME,
7e630bb5 2690 .pm = W83627EHF_DEV_PM_OPS,
cdaf7934 2691 },
1ea6dd38 2692 .probe = w83627ehf_probe,
9e5e9b7a 2693 .remove = w83627ehf_remove,
08e7e278
JD		 2694};
2695
1ea6dd38
DH		 2696/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2697static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2698 struct w83627ehf_sio_data *sio_data)
08e7e278 2699{
6f7805a8
UKK		 2700 static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
2701 static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
2702 static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
2703 static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
2704 static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
2705 static const char sio_name_W83667HG[] __initconst = "W83667HG";
2706 static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
2707 static const char sio_name_NCT6775[] __initconst = "NCT6775F";
2708 static const char sio_name_NCT6776[] __initconst = "NCT6776F";
1ea6dd38 2709
08e7e278 2710 u16 val;
1ea6dd38 2711 const char *sio_name;
0d023530 2712 int err;
08e7e278 2713
0d023530
KS		 2714 err = superio_enter(sioaddr);
2715 if (err)
2716 return err;
08e7e278 2717
67b671bc
JD		 2718 if (force_id)
2719 val = force_id;
2720 else
2721 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2722 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2723 switch (val & SIO_ID_MASK) {
657c93b1 2724 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2725 sio_data->kind = w83627ehf;
2726 sio_name = sio_name_W83627EHF;
2727 break;
657c93b1 2728 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2729 sio_data->kind = w83627ehf;
2730 sio_name = sio_name_W83627EHG;
2731 break;
2732 case SIO_W83627DHG_ID:
2733 sio_data->kind = w83627dhg;
2734 sio_name = sio_name_W83627DHG;
657c93b1 2735 break;
c1e48dce
JD		 2736 case SIO_W83627DHG_P_ID:
2737 sio_data->kind = w83627dhg_p;
2738 sio_name = sio_name_W83627DHG_P;
2739 break;
eff7687d
JD		 2740 case SIO_W83627UHG_ID:
2741 sio_data->kind = w83627uhg;
2742 sio_name = sio_name_W83627UHG;
2743 break;
237c8d2f
GJ		 2744 case SIO_W83667HG_ID:
2745 sio_data->kind = w83667hg;
2746 sio_name = sio_name_W83667HG;
2747 break;
c39aedaf
GR		 2748 case SIO_W83667HG_B_ID:
2749 sio_data->kind = w83667hg_b;
2750 sio_name = sio_name_W83667HG_B;
2751 break;
ec3e5a16
GR		 2752 case SIO_NCT6775_ID:
2753 sio_data->kind = nct6775;
2754 sio_name = sio_name_NCT6775;
2755 break;
2756 case SIO_NCT6776_ID:
2757 sio_data->kind = nct6776;
2758 sio_name = sio_name_NCT6776;
2759 break;
657c93b1 2760 default:
9f66036b 2761 if (val != 0xffff)
abdc6fd1 2762 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2763 superio_exit(sioaddr);
08e7e278
JD		 2764 return -ENODEV;
2765 }
2766
1ea6dd38
DH		 2767 /* We have a known chip, find the HWM I/O address */
2768 superio_select(sioaddr, W83627EHF_LD_HWM);
2769 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2770 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2771 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2772 if (*addr == 0) {
abdc6fd1 2773 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2774 superio_exit(sioaddr);
08e7e278
JD		 2775 return -ENODEV;
2776 }
2777
2778 /* Activate logical device if needed */
1ea6dd38 2779 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2780 if (!(val & 0x01)) {
b55f3757 2781 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
1ea6dd38 2782 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2783 }
1ea6dd38
DH		 2784
2785 superio_exit(sioaddr);
abdc6fd1 2786 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2787 sio_data->sioreg = sioaddr;
08e7e278 2788
08e7e278
JD		 2789 return 0;
2790}
2791
8969e84d
GR		 2792/*
2793 * when Super-I/O functions move to a separate file, the Super-I/O
1ea6dd38
DH		 2794 * bus will manage the lifetime of the device and this module will only keep
2795 * track of the w83627ehf driver. But since we platform_device_alloc(), we
8969e84d
GR		 2796 * must keep track of the device
2797 */
1ea6dd38
DH		 2798static struct platform_device *pdev;
2799
08e7e278
JD		 2800static int __init sensors_w83627ehf_init(void)
2801{
1ea6dd38
DH		 2802 int err;
2803 unsigned short address;
2804 struct resource res;
2805 struct w83627ehf_sio_data sio_data;
2806
8969e84d
GR		 2807 /*
2808 * initialize sio_data->kind and sio_data->sioreg.
1ea6dd38
DH		 2809 *
2810 * when Super-I/O functions move to a separate file, the Super-I/O
2811 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
8969e84d
GR		 2812 * w83627ehf hardware monitor, and call probe()
2813 */
1ea6dd38
DH		 2814 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2815 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2816 return -ENODEV;
2817
1ea6dd38
DH		 2818 err = platform_driver_register(&w83627ehf_driver);
2819 if (err)
2820 goto exit;
2821
e7e1ca6e
GR		 2822 pdev = platform_device_alloc(DRVNAME, address);
2823 if (!pdev) {
1ea6dd38 2824 err = -ENOMEM;
abdc6fd1 2825 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2826 goto exit_unregister;
2827 }
2828
2829 err = platform_device_add_data(pdev, &sio_data,
2830 sizeof(struct w83627ehf_sio_data));
2831 if (err) {
abdc6fd1 2832 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2833 goto exit_device_put;
2834 }
2835
2836 memset(&res, 0, sizeof(res));
2837 res.name = DRVNAME;
2838 res.start = address + IOREGION_OFFSET;
2839 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2840 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2841
2842 err = acpi_check_resource_conflict(&res);
2843 if (err)
18632f84 2844 goto exit_device_put;
b9acb64a 2845
1ea6dd38
DH		 2846 err = platform_device_add_resources(pdev, &res, 1);
2847 if (err) {
abdc6fd1 2848 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2849 goto exit_device_put;
2850 }
2851
2852 /* platform_device_add calls probe() */
2853 err = platform_device_add(pdev);
2854 if (err) {
abdc6fd1 2855 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2856 goto exit_device_put;
2857 }
2858
2859 return 0;
2860
2861exit_device_put:
2862 platform_device_put(pdev);
2863exit_unregister:
2864 platform_driver_unregister(&w83627ehf_driver);
2865exit:
2866 return err;
08e7e278
JD		 2867}
2868
2869static void __exit sensors_w83627ehf_exit(void)
2870{
1ea6dd38
DH		 2871 platform_device_unregister(pdev);
2872 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2873}
2874
7c81c60f 2875MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
08e7e278
JD		 2876MODULE_DESCRIPTION("W83627EHF driver");
2877MODULE_LICENSE("GPL");
2878
2879module_init(sensors_w83627ehf_init);
2880module_exit(sensors_w83627ehf_exit);
Linux 6.x block layer and io_uring tree(s)