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Linux 3.5
[linux-2.6-block.git] / drivers / hwmon / w83627ehf.c
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08e7e278 1/*
8969e84d
GR		 2 * w83627ehf - Driver for the hardware monitoring functionality of
3 * the Winbond W83627EHF Super-I/O chip
4 * Copyright (C) 2005-2011 Jean Delvare <khali@linux-fr.org>
5 * Copyright (C) 2006 Yuan Mu (Winbond),
6 * Rudolf Marek <r.marek@assembler.cz>
7 * David Hubbard <david.c.hubbard@gmail.com>
8 * Daniel J Blueman <daniel.blueman@gmail.com>
9 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
10 *
11 * Shamelessly ripped from the w83627hf driver
12 * Copyright (C) 2003 Mark Studebaker
13 *
14 * Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 * in testing and debugging this driver.
16 *
17 * This driver also supports the W83627EHG, which is the lead-free
18 * version of the W83627EHF.
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 * Supports the following chips:
35 *
36 * Chip #vin #fan #pwm #temp chip IDs man ID
37 * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
38 * 0x8860 0xa1
39 * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
40 * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
41 * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
42 * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
43 * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
44 * nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
45 * nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
46 */
08e7e278 47
abdc6fd1
JP		 48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
08e7e278
JD		 50#include <linux/module.h>
51#include <linux/init.h>
52#include <linux/slab.h>
1ea6dd38
DH		 53#include <linux/jiffies.h>
54#include <linux/platform_device.h>
943b0830 55#include <linux/hwmon.h>
412fec82 56#include <linux/hwmon-sysfs.h>
fc18d6c0 57#include <linux/hwmon-vid.h>
943b0830 58#include <linux/err.h>
9a61bf63 59#include <linux/mutex.h>
b9acb64a 60#include <linux/acpi.h>
6055fae8 61#include <linux/io.h>
08e7e278
JD		 62#include "lm75.h"
63
eff7687d
JD		 64enum kinds {
65 w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
66 w83667hg, w83667hg_b, nct6775, nct6776,
67};
08e7e278 68
1ea6dd38 69/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
e7e1ca6e 70static const char * const w83627ehf_device_names[] = {
1ea6dd38
DH		 71 "w83627ehf",
72 "w83627dhg",
c1e48dce 73 "w83627dhg",
eff7687d 74 "w83627uhg",
237c8d2f 75 "w83667hg",
c39aedaf 76 "w83667hg",
ec3e5a16
GR		 77 "nct6775",
78 "nct6776",
1ea6dd38
DH		 79};
80
67b671bc
JD		 81static unsigned short force_id;
82module_param(force_id, ushort, 0);
83MODULE_PARM_DESC(force_id, "Override the detected device ID");
84
d42e869a
ID		 85static unsigned short fan_debounce;
86module_param(fan_debounce, ushort, 0);
87MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
88
1ea6dd38 89#define DRVNAME "w83627ehf"
08e7e278 90
657c93b1 91/*
1ea6dd38 92 * Super-I/O constants and functions
657c93b1 93 */
08e7e278
JD		 94
95#define W83627EHF_LD_HWM 0x0b
e7e1ca6e 96#define W83667HG_LD_VID 0x0d
08e7e278
JD		 97
98#define SIO_REG_LDSEL 0x07 /* Logical device select */
99#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 100#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 101#define SIO_REG_ENABLE 0x30 /* Logical device enable */
102#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 103#define SIO_REG_VID_CTRL 0xF0 /* VID control */
104#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 105
657c93b1
DH		 106#define SIO_W83627EHF_ID 0x8850
107#define SIO_W83627EHG_ID 0x8860
108#define SIO_W83627DHG_ID 0xa020
c1e48dce 109#define SIO_W83627DHG_P_ID 0xb070
eff7687d 110#define SIO_W83627UHG_ID 0xa230
e7e1ca6e 111#define SIO_W83667HG_ID 0xa510
c39aedaf 112#define SIO_W83667HG_B_ID 0xb350
ec3e5a16
GR		 113#define SIO_NCT6775_ID 0xb470
114#define SIO_NCT6776_ID 0xc330
657c93b1 115#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 116
117static inline void
1ea6dd38 118superio_outb(int ioreg, int reg, int val)
08e7e278 119{
1ea6dd38
DH		 120 outb(reg, ioreg);
121 outb(val, ioreg + 1);
08e7e278
JD		 122}
123
124static inline int
1ea6dd38 125superio_inb(int ioreg, int reg)
08e7e278 126{
1ea6dd38
DH		 127 outb(reg, ioreg);
128 return inb(ioreg + 1);
08e7e278
JD		 129}
130
131static inline void
1ea6dd38 132superio_select(int ioreg, int ld)
08e7e278 133{
1ea6dd38
DH		 134 outb(SIO_REG_LDSEL, ioreg);
135 outb(ld, ioreg + 1);
08e7e278
JD		 136}
137
138static inline void
1ea6dd38 139superio_enter(int ioreg)
08e7e278 140{
1ea6dd38
DH		 141 outb(0x87, ioreg);
142 outb(0x87, ioreg);
08e7e278
JD		 143}
144
145static inline void
1ea6dd38 146superio_exit(int ioreg)
08e7e278 147{
022b75a3 148 outb(0xaa, ioreg);
1ea6dd38
DH		 149 outb(0x02, ioreg);
150 outb(0x02, ioreg + 1);
08e7e278
JD		 151}
152
153/*
154 * ISA constants
155 */
156
e7e1ca6e 157#define IOREGION_ALIGNMENT (~7)
1a641fce
JD		 158#define IOREGION_OFFSET 5
159#define IOREGION_LENGTH 2
1ea6dd38
DH		 160#define ADDR_REG_OFFSET 0
161#define DATA_REG_OFFSET 1
08e7e278
JD		 162
163#define W83627EHF_REG_BANK 0x4E
164#define W83627EHF_REG_CONFIG 0x40
657c93b1 165
8969e84d
GR		 166/*
167 * Not currently used:
657c93b1
DH		 168 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
169 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
170 * REG_MAN_ID is at port 0x4f
8969e84d
GR		 171 * REG_CHIP_ID is at port 0x58
172 */
08e7e278
JD		 173
174static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
175static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
176
cf0676fe
RM		 177/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
178#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
179 (0x554 + (((nr) - 7) * 2)))
180#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
181 (0x555 + (((nr) - 7) * 2)))
182#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
183 (0x550 + (nr) - 7))
184
d36cf32c
GR		 185static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
186static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
187static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
188static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
08e7e278
JD		 189
190/* Fan clock dividers are spread over the following five registers */
191#define W83627EHF_REG_FANDIV1 0x47
192#define W83627EHF_REG_FANDIV2 0x4B
193#define W83627EHF_REG_VBAT 0x5D
194#define W83627EHF_REG_DIODE 0x59
195#define W83627EHF_REG_SMI_OVT 0x4C
196
ec3e5a16
GR		 197/* NCT6775F has its own fan divider registers */
198#define NCT6775_REG_FANDIV1 0x506
199#define NCT6775_REG_FANDIV2 0x507
d42e869a 200#define NCT6775_REG_FAN_DEBOUNCE 0xf0
ec3e5a16 201
a4589dbb
JD		 202#define W83627EHF_REG_ALARM1 0x459
203#define W83627EHF_REG_ALARM2 0x45A
204#define W83627EHF_REG_ALARM3 0x45B
205
363a12a4
DA		 206#define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
207#define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
208
08c79950 209/* SmartFan registers */
41e9a062
DB		 210#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
211#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
212
08c79950
RM		 213/* DC or PWM output fan configuration */
214static const u8 W83627EHF_REG_PWM_ENABLE[] = {
215 0x04, /* SYS FAN0 output mode and PWM mode */
216 0x04, /* CPU FAN0 output mode and PWM mode */
217 0x12, /* AUX FAN mode */
41e9a062 218 0x62, /* CPU FAN1 mode */
08c79950
RM		 219};
220
221static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
222static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
223
224/* FAN Duty Cycle, be used to control */
279af1a9
GR		 225static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
226static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
08c79950
RM		 227static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
228
08c79950 229/* Advanced Fan control, some values are common for all fans */
279af1a9
GR		 230static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
231static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
232static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
c39aedaf 233
279af1a9 234static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
c39aedaf 235 = { 0xff, 0x67, 0xff, 0x69 };
279af1a9 236static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
c39aedaf
GR		 237 = { 0xff, 0x68, 0xff, 0x6a };
238
279af1a9
GR		 239static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
240static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
241 = { 0x68, 0x6a, 0x6c };
08c79950 242
840e191d
GR		 243static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
244
ec3e5a16
GR		 245static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
246static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
247static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
248static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
249static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
250static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
251static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
252static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
26bc440e 253static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
ec3e5a16
GR		 254static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
255
256static const u16 NCT6775_REG_TEMP[]
257 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
258static const u16 NCT6775_REG_TEMP_CONFIG[]
259 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
260static const u16 NCT6775_REG_TEMP_HYST[]
261 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
262static const u16 NCT6775_REG_TEMP_OVER[]
263 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
264static const u16 NCT6775_REG_TEMP_SOURCE[]
265 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
266
d36cf32c
GR		 267static const char *const w83667hg_b_temp_label[] = {
268 "SYSTIN",
269 "CPUTIN",
270 "AUXTIN",
271 "AMDTSI",
272 "PECI Agent 1",
273 "PECI Agent 2",
274 "PECI Agent 3",
275 "PECI Agent 4"
276};
277
ec3e5a16
GR		 278static const char *const nct6775_temp_label[] = {
279 "",
280 "SYSTIN",
281 "CPUTIN",
282 "AUXTIN",
283 "AMD SB-TSI",
284 "PECI Agent 0",
285 "PECI Agent 1",
286 "PECI Agent 2",
287 "PECI Agent 3",
288 "PECI Agent 4",
289 "PECI Agent 5",
290 "PECI Agent 6",
291 "PECI Agent 7",
292 "PCH_CHIP_CPU_MAX_TEMP",
293 "PCH_CHIP_TEMP",
294 "PCH_CPU_TEMP",
295 "PCH_MCH_TEMP",
296 "PCH_DIM0_TEMP",
297 "PCH_DIM1_TEMP",
298 "PCH_DIM2_TEMP",
299 "PCH_DIM3_TEMP"
300};
301
302static const char *const nct6776_temp_label[] = {
303 "",
304 "SYSTIN",
305 "CPUTIN",
306 "AUXTIN",
307 "SMBUSMASTER 0",
308 "SMBUSMASTER 1",
309 "SMBUSMASTER 2",
310 "SMBUSMASTER 3",
311 "SMBUSMASTER 4",
312 "SMBUSMASTER 5",
313 "SMBUSMASTER 6",
314 "SMBUSMASTER 7",
315 "PECI Agent 0",
316 "PECI Agent 1",
317 "PCH_CHIP_CPU_MAX_TEMP",
318 "PCH_CHIP_TEMP",
319 "PCH_CPU_TEMP",
320 "PCH_MCH_TEMP",
321 "PCH_DIM0_TEMP",
322 "PCH_DIM1_TEMP",
323 "PCH_DIM2_TEMP",
324 "PCH_DIM3_TEMP",
325 "BYTE_TEMP"
326};
327
328#define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
d36cf32c 329
17296feb 330static int is_word_sized(u16 reg)
bce26c58 331{
ec3e5a16 332 return ((((reg & 0xff00) == 0x100
bce26c58
GR		 333 || (reg & 0xff00) == 0x200)
334 && ((reg & 0x00ff) == 0x50
335 || (reg & 0x00ff) == 0x53
ec3e5a16
GR		 336 || (reg & 0x00ff) == 0x55))
337 || (reg & 0xfff0) == 0x630
338 || reg == 0x640 || reg == 0x642
339 || ((reg & 0xfff0) == 0x650
340 && (reg & 0x000f) >= 0x06)
341 || reg == 0x73 || reg == 0x75 || reg == 0x77
342 );
bce26c58
GR		 343}
344
08e7e278
JD		 345/*
346 * Conversions
347 */
348
08c79950
RM		 349/* 1 is PWM mode, output in ms */
350static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
351{
352 return mode ? 100 * reg : 400 * reg;
353}
354
355static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
356{
357 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
358 (msec + 200) / 400), 1, 255);
359}
360
26bc440e 361static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
08e7e278 362{
26bc440e 363 if (reg == 0 || reg == 255)
08e7e278 364 return 0;
26bc440e
GR		 365 return 1350000U / (reg << divreg);
366}
367
368static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
369{
370 if ((reg & 0xff1f) == 0xff1f)
371 return 0;
372
373 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
374
375 if (reg == 0)
376 return 0;
377
378 return 1350000U / reg;
379}
380
381static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
382{
383 if (reg == 0 || reg == 0xffff)
384 return 0;
385
386 /*
387 * Even though the registers are 16 bit wide, the fan divisor
388 * still applies.
389 */
390 return 1350000U / (reg << divreg);
08e7e278
JD		 391}
392
393static inline unsigned int
394div_from_reg(u8 reg)
395{
396 return 1 << reg;
397}
398
8969e84d
GR		 399/*
400 * Some of the voltage inputs have internal scaling, the tables below
401 * contain 8 (the ADC LSB in mV) * scaling factor * 100
402 */
eff7687d
JD		 403static const u16 scale_in_common[10] = {
404 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
405};
406static const u16 scale_in_w83627uhg[9] = {
407 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
408};
cf0676fe 409
eff7687d 410static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
cf0676fe 411{
eff7687d 412 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
cf0676fe
RM		 413}
414
eff7687d 415static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
cf0676fe 416{
eff7687d 417 return SENSORS_LIMIT(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0,
e7e1ca6e 418 255);
cf0676fe
RM		 419}
420
08e7e278
JD		 421/*
422 * Data structures and manipulation thereof
423 */
424
425struct w83627ehf_data {
1ea6dd38
DH		 426 int addr; /* IO base of hw monitor block */
427 const char *name;
428
1beeffe4 429 struct device *hwmon_dev;
9a61bf63 430 struct mutex lock;
08e7e278 431
ec3e5a16
GR		 432 u16 reg_temp[NUM_REG_TEMP];
433 u16 reg_temp_over[NUM_REG_TEMP];
434 u16 reg_temp_hyst[NUM_REG_TEMP];
435 u16 reg_temp_config[NUM_REG_TEMP];
d36cf32c
GR		 436 u8 temp_src[NUM_REG_TEMP];
437 const char * const *temp_label;
438
279af1a9
GR		 439 const u16 *REG_PWM;
440 const u16 *REG_TARGET;
441 const u16 *REG_FAN;
442 const u16 *REG_FAN_MIN;
443 const u16 *REG_FAN_START_OUTPUT;
444 const u16 *REG_FAN_STOP_OUTPUT;
445 const u16 *REG_FAN_STOP_TIME;
446 const u16 *REG_FAN_MAX_OUTPUT;
447 const u16 *REG_FAN_STEP_OUTPUT;
eff7687d 448 const u16 *scale_in;
da2e0255 449
26bc440e
GR		 450 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
451 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
452
9a61bf63 453 struct mutex update_lock;
08e7e278
JD		 454 char valid; /* !=0 if following fields are valid */
455 unsigned long last_updated; /* In jiffies */
456
457 /* Register values */
83cc8985 458 u8 bank; /* current register bank */
1ea6dd38 459 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 460 u8 in[10]; /* Register value */
461 u8 in_max[10]; /* Register value */
462 u8 in_min[10]; /* Register value */
3382a918 463 unsigned int rpm[5];
ec3e5a16 464 u16 fan_min[5];
08e7e278
JD		 465 u8 fan_div[5];
466 u8 has_fan; /* some fan inputs can be disabled */
ec3e5a16 467 u8 has_fan_min; /* some fans don't have min register */
26bc440e 468 bool has_fan_div;
da667365 469 u8 temp_type[3];
840e191d 470 s8 temp_offset[3];
ec3e5a16
GR		 471 s16 temp[9];
472 s16 temp_max[9];
473 s16 temp_max_hyst[9];
a4589dbb 474 u32 alarms;
363a12a4 475 u8 caseopen;
08c79950
RM		 476
477 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
478 u8 pwm_enable[4]; /* 1->manual
8969e84d
GR		 479 * 2->thermal cruise mode (also called SmartFan I)
480 * 3->fan speed cruise mode
481 * 4->variable thermal cruise (also called
482 * SmartFan III)
483 * 5->enhanced variable thermal cruise (also called
484 * SmartFan IV)
485 */
b84bb518 486 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
237c8d2f 487 u8 pwm_num; /* number of pwm */
08c79950
RM		 488 u8 pwm[4];
489 u8 target_temp[4];
490 u8 tolerance[4];
491
41e9a062
DB		 492 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
493 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
494 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
495 u8 fan_max_output[4]; /* maximum fan speed */
496 u8 fan_step_output[4]; /* rate of change output value */
fc18d6c0
JD		 497
498 u8 vid;
499 u8 vrm;
a157d06d 500
ec3e5a16 501 u16 have_temp;
840e191d 502 u16 have_temp_offset;
eff7687d
JD		 503 u8 in6_skip:1;
504 u8 temp3_val_only:1;
08e7e278
JD		 505};
506
1ea6dd38
DH		 507struct w83627ehf_sio_data {
508 int sioreg;
509 enum kinds kind;
510};
511
83cc8985
GR		 512/*
513 * On older chips, only registers 0x50-0x5f are banked.
514 * On more recent chips, all registers are banked.
515 * Assume that is the case and set the bank number for each access.
516 * Cache the bank number so it only needs to be set if it changes.
517 */
1ea6dd38 518static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 519{
83cc8985
GR		 520 u8 bank = reg >> 8;
521 if (data->bank != bank) {
1ea6dd38 522 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
83cc8985
GR		 523 outb_p(bank, data->addr + DATA_REG_OFFSET);
524 data->bank = bank;
08e7e278
JD		 525 }
526}
527
1ea6dd38 528static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 529{
08e7e278
JD		 530 int res, word_sized = is_word_sized(reg);
531
9a61bf63 532 mutex_lock(&data->lock);
08e7e278 533
1ea6dd38
DH		 534 w83627ehf_set_bank(data, reg);
535 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
536 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 537 if (word_sized) {
538 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 539 data->addr + ADDR_REG_OFFSET);
540 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 541 }
08e7e278 542
9a61bf63 543 mutex_unlock(&data->lock);
08e7e278
JD		 544 return res;
545}
546
e7e1ca6e
GR		 547static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
548 u16 value)
08e7e278 549{
08e7e278
JD		 550 int word_sized = is_word_sized(reg);
551
9a61bf63 552 mutex_lock(&data->lock);
08e7e278 553
1ea6dd38
DH		 554 w83627ehf_set_bank(data, reg);
555 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 556 if (word_sized) {
1ea6dd38 557 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 558 outb_p((reg & 0xff) + 1,
1ea6dd38 559 data->addr + ADDR_REG_OFFSET);
08e7e278 560 }
1ea6dd38 561 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
08e7e278 562
9a61bf63 563 mutex_unlock(&data->lock);
08e7e278
JD		 564 return 0;
565}
566
c5794cfa
JD		 567/* We left-align 8-bit temperature values to make the code simpler */
568static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
569{
570 u16 res;
571
572 res = w83627ehf_read_value(data, reg);
573 if (!is_word_sized(reg))
574 res <<= 8;
575
576 return res;
577}
578
579static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
580 u16 value)
581{
582 if (!is_word_sized(reg))
583 value >>= 8;
584 return w83627ehf_write_value(data, reg, value);
585}
586
ec3e5a16
GR		 587/* This function assumes that the caller holds data->update_lock */
588static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
589{
590 u8 reg;
591
592 switch (nr) {
593 case 0:
594 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
595 | (data->fan_div[0] & 0x7);
596 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
597 break;
598 case 1:
599 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
600 | ((data->fan_div[1] << 4) & 0x70);
601 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
602 case 2:
603 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
604 | (data->fan_div[2] & 0x7);
605 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
606 break;
607 case 3:
608 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
609 | ((data->fan_div[3] << 4) & 0x70);
610 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
611 break;
612 }
613}
614
08e7e278 615/* This function assumes that the caller holds data->update_lock */
1ea6dd38 616static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 617{
08e7e278
JD		 618 u8 reg;
619
620 switch (nr) {
621 case 0:
1ea6dd38 622 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 623 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 624 /* fan5 input control bit is write only, compute the value */
625 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 626 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
627 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 628 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 629 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 630 break;
631 case 1:
1ea6dd38 632 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 633 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 634 /* fan5 input control bit is write only, compute the value */
635 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 636 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
637 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 638 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 639 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 640 break;
641 case 2:
1ea6dd38 642 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 643 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 644 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
645 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 646 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 647 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 648 break;
649 case 3:
1ea6dd38 650 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 651 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 652 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
653 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 654 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 655 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 656 break;
657 case 4:
1ea6dd38 658 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 659 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 660 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 661 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 662 break;
663 }
664}
665
ec3e5a16
GR		 666static void w83627ehf_write_fan_div_common(struct device *dev,
667 struct w83627ehf_data *data, int nr)
668{
669 struct w83627ehf_sio_data *sio_data = dev->platform_data;
670
671 if (sio_data->kind == nct6776)
672 ; /* no dividers, do nothing */
673 else if (sio_data->kind == nct6775)
674 nct6775_write_fan_div(data, nr);
675 else
676 w83627ehf_write_fan_div(data, nr);
677}
678
679static void nct6775_update_fan_div(struct w83627ehf_data *data)
680{
681 u8 i;
682
683 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
684 data->fan_div[0] = i & 0x7;
685 data->fan_div[1] = (i & 0x70) >> 4;
686 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
687 data->fan_div[2] = i & 0x7;
688 if (data->has_fan & (1<<3))
689 data->fan_div[3] = (i & 0x70) >> 4;
690}
691
ea7be66c
MH		 692static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
693{
694 int i;
695
696 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
697 data->fan_div[0] = (i >> 4) & 0x03;
698 data->fan_div[1] = (i >> 6) & 0x03;
699 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
700 data->fan_div[2] = (i >> 6) & 0x03;
701 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
702 data->fan_div[0] |= (i >> 3) & 0x04;
703 data->fan_div[1] |= (i >> 4) & 0x04;
704 data->fan_div[2] |= (i >> 5) & 0x04;
705 if (data->has_fan & ((1 << 3) | (1 << 4))) {
706 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
707 data->fan_div[3] = i & 0x03;
708 data->fan_div[4] = ((i >> 2) & 0x03)
709 | ((i >> 5) & 0x04);
710 }
711 if (data->has_fan & (1 << 3)) {
712 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
713 data->fan_div[3] |= (i >> 5) & 0x04;
714 }
715}
716
ec3e5a16
GR		 717static void w83627ehf_update_fan_div_common(struct device *dev,
718 struct w83627ehf_data *data)
719{
720 struct w83627ehf_sio_data *sio_data = dev->platform_data;
721
722 if (sio_data->kind == nct6776)
723 ; /* no dividers, do nothing */
724 else if (sio_data->kind == nct6775)
725 nct6775_update_fan_div(data);
726 else
727 w83627ehf_update_fan_div(data);
728}
729
730static void nct6775_update_pwm(struct w83627ehf_data *data)
731{
732 int i;
733 int pwmcfg, fanmodecfg;
734
735 for (i = 0; i < data->pwm_num; i++) {
736 pwmcfg = w83627ehf_read_value(data,
737 W83627EHF_REG_PWM_ENABLE[i]);
738 fanmodecfg = w83627ehf_read_value(data,
739 NCT6775_REG_FAN_MODE[i]);
740 data->pwm_mode[i] =
741 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
742 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
743 data->tolerance[i] = fanmodecfg & 0x0f;
744 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
745 }
746}
747
748static void w83627ehf_update_pwm(struct w83627ehf_data *data)
749{
750 int i;
751 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
752
753 for (i = 0; i < data->pwm_num; i++) {
754 if (!(data->has_fan & (1 << i)))
755 continue;
756
757 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
758 if (i != 1) {
759 pwmcfg = w83627ehf_read_value(data,
760 W83627EHF_REG_PWM_ENABLE[i]);
761 tolerance = w83627ehf_read_value(data,
762 W83627EHF_REG_TOLERANCE[i]);
763 }
764 data->pwm_mode[i] =
765 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
766 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
767 & 3) + 1;
768 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
769
770 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
771 }
772}
773
774static void w83627ehf_update_pwm_common(struct device *dev,
775 struct w83627ehf_data *data)
776{
777 struct w83627ehf_sio_data *sio_data = dev->platform_data;
778
779 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
780 nct6775_update_pwm(data);
781 else
782 w83627ehf_update_pwm(data);
783}
784
08e7e278
JD		 785static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
786{
1ea6dd38 787 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16
GR		 788 struct w83627ehf_sio_data *sio_data = dev->platform_data;
789
08e7e278
JD		 790 int i;
791
9a61bf63 792 mutex_lock(&data->update_lock);
08e7e278 793
6b3e4645 794 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 795 || !data->valid) {
796 /* Fan clock dividers */
ec3e5a16 797 w83627ehf_update_fan_div_common(dev, data);
08e7e278 798
cf0676fe 799 /* Measured voltages and limits */
1ea6dd38 800 for (i = 0; i < data->in_num; i++) {
389ef65d
JD		 801 if ((i == 6) && data->in6_skip)
802 continue;
803
1ea6dd38 804 data->in[i] = w83627ehf_read_value(data,
cf0676fe 805 W83627EHF_REG_IN(i));
1ea6dd38 806 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 807 W83627EHF_REG_IN_MIN(i));
1ea6dd38 808 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 809 W83627EHF_REG_IN_MAX(i));
810 }
811
08e7e278
JD		 812 /* Measured fan speeds and limits */
813 for (i = 0; i < 5; i++) {
3382a918
GR		 814 u16 reg;
815
08e7e278
JD		 816 if (!(data->has_fan & (1 << i)))
817 continue;
818
3382a918
GR		 819 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
820 data->rpm[i] = data->fan_from_reg(reg,
821 data->fan_div[i]);
ec3e5a16
GR		 822
823 if (data->has_fan_min & (1 << i))
824 data->fan_min[i] = w83627ehf_read_value(data,
279af1a9 825 data->REG_FAN_MIN[i]);
08e7e278 826
8969e84d
GR		 827 /*
828 * If we failed to measure the fan speed and clock
829 * divider can be increased, let's try that for next
830 * time
831 */
26bc440e 832 if (data->has_fan_div
3382a918
GR		 833 && (reg >= 0xff || (sio_data->kind == nct6775
834 && reg == 0x00))
ec3e5a16 835 && data->fan_div[i] < 0x07) {
e7e1ca6e 836 dev_dbg(dev, "Increasing fan%d "
08e7e278 837 "clock divider from %u to %u\n",
33725ad3 838 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 839 div_from_reg(data->fan_div[i] + 1));
840 data->fan_div[i]++;
ec3e5a16 841 w83627ehf_write_fan_div_common(dev, data, i);
08e7e278 842 /* Preserve min limit if possible */
ec3e5a16
GR		 843 if ((data->has_fan_min & (1 << i))
844 && data->fan_min[i] >= 2
08e7e278 845 && data->fan_min[i] != 255)
1ea6dd38 846 w83627ehf_write_value(data,
279af1a9 847 data->REG_FAN_MIN[i],
08e7e278
JD		 848 (data->fan_min[i] /= 2));
849 }
850 }
851
ec3e5a16
GR		 852 w83627ehf_update_pwm_common(dev, data);
853
da2e0255
GR		 854 for (i = 0; i < data->pwm_num; i++) {
855 if (!(data->has_fan & (1 << i)))
856 continue;
857
ec3e5a16
GR		 858 data->fan_start_output[i] =
859 w83627ehf_read_value(data,
860 data->REG_FAN_START_OUTPUT[i]);
861 data->fan_stop_output[i] =
862 w83627ehf_read_value(data,
863 data->REG_FAN_STOP_OUTPUT[i]);
864 data->fan_stop_time[i] =
865 w83627ehf_read_value(data,
866 data->REG_FAN_STOP_TIME[i]);
867
868 if (data->REG_FAN_MAX_OUTPUT &&
869 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
da2e0255
GR		 870 data->fan_max_output[i] =
871 w83627ehf_read_value(data,
ec3e5a16 872 data->REG_FAN_MAX_OUTPUT[i]);
da2e0255 873
ec3e5a16
GR		 874 if (data->REG_FAN_STEP_OUTPUT &&
875 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
da2e0255
GR		 876 data->fan_step_output[i] =
877 w83627ehf_read_value(data,
ec3e5a16 878 data->REG_FAN_STEP_OUTPUT[i]);
da2e0255 879
08c79950 880 data->target_temp[i] =
1ea6dd38 881 w83627ehf_read_value(data,
279af1a9 882 data->REG_TARGET[i]) &
08c79950 883 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
08c79950
RM		 884 }
885
08e7e278 886 /* Measured temperatures and limits */
d36cf32c
GR		 887 for (i = 0; i < NUM_REG_TEMP; i++) {
888 if (!(data->have_temp & (1 << i)))
889 continue;
c5794cfa 890 data->temp[i] = w83627ehf_read_temp(data,
ec3e5a16
GR		 891 data->reg_temp[i]);
892 if (data->reg_temp_over[i])
893 data->temp_max[i]
c5794cfa 894 = w83627ehf_read_temp(data,
ec3e5a16
GR		 895 data->reg_temp_over[i]);
896 if (data->reg_temp_hyst[i])
897 data->temp_max_hyst[i]
c5794cfa 898 = w83627ehf_read_temp(data,
ec3e5a16 899 data->reg_temp_hyst[i]);
840e191d
GR		 900 if (data->have_temp_offset & (1 << i))
901 data->temp_offset[i]
902 = w83627ehf_read_value(data,
903 W83627EHF_REG_TEMP_OFFSET[i]);
08e7e278
JD		 904 }
905
1ea6dd38 906 data->alarms = w83627ehf_read_value(data,
a4589dbb 907 W83627EHF_REG_ALARM1) |
1ea6dd38 908 (w83627ehf_read_value(data,
a4589dbb 909 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 910 (w83627ehf_read_value(data,
a4589dbb
JD		 911 W83627EHF_REG_ALARM3) << 16);
912
363a12a4
DA		 913 data->caseopen = w83627ehf_read_value(data,
914 W83627EHF_REG_CASEOPEN_DET);
915
08e7e278
JD		 916 data->last_updated = jiffies;
917 data->valid = 1;
918 }
919
9a61bf63 920 mutex_unlock(&data->update_lock);
08e7e278
JD		 921 return data;
922}
923
924/*
925 * Sysfs callback functions
926 */
cf0676fe
RM		 927#define show_in_reg(reg) \
928static ssize_t \
929show_##reg(struct device *dev, struct device_attribute *attr, \
930 char *buf) \
931{ \
932 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 933 struct sensor_device_attribute *sensor_attr = \
934 to_sensor_dev_attr(attr); \
cf0676fe 935 int nr = sensor_attr->index; \
eff7687d
JD		 936 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr, \
937 data->scale_in)); \
cf0676fe
RM		 938}
939show_in_reg(in)
940show_in_reg(in_min)
941show_in_reg(in_max)
942
943#define store_in_reg(REG, reg) \
944static ssize_t \
e7e1ca6e
GR		 945store_in_##reg(struct device *dev, struct device_attribute *attr, \
946 const char *buf, size_t count) \
cf0676fe 947{ \
1ea6dd38 948 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 949 struct sensor_device_attribute *sensor_attr = \
950 to_sensor_dev_attr(attr); \
cf0676fe 951 int nr = sensor_attr->index; \
bce26c58
GR		 952 unsigned long val; \
953 int err; \
179c4fdb 954 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 955 if (err < 0) \
956 return err; \
cf0676fe 957 mutex_lock(&data->update_lock); \
eff7687d 958 data->in_##reg[nr] = in_to_reg(val, nr, data->scale_in); \
1ea6dd38 959 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 960 data->in_##reg[nr]); \
961 mutex_unlock(&data->update_lock); \
962 return count; \
963}
964
965store_in_reg(MIN, min)
966store_in_reg(MAX, max)
967
e7e1ca6e
GR		 968static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
969 char *buf)
a4589dbb
JD		 970{
971 struct w83627ehf_data *data = w83627ehf_update_device(dev);
972 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
973 int nr = sensor_attr->index;
974 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
975}
976
cf0676fe
RM		 977static struct sensor_device_attribute sda_in_input[] = {
978 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
979 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
980 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
981 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
982 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
983 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
984 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
985 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
986 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
987 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
988};
989
a4589dbb
JD		 990static struct sensor_device_attribute sda_in_alarm[] = {
991 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
992 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
993 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
994 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
995 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
996 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
997 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
998 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
999 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
1000 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
1001};
1002
cf0676fe 1003static struct sensor_device_attribute sda_in_min[] = {
e7e1ca6e
GR		 1004 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
1005 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
1006 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
1007 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
1008 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
1009 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
1010 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
1011 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
1012 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
1013 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
cf0676fe
RM		 1014};
1015
1016static struct sensor_device_attribute sda_in_max[] = {
e7e1ca6e
GR		 1017 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
1018 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
1019 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
1020 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
1021 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
1022 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
1023 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
1024 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
1025 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
1026 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
cf0676fe
RM		 1027};
1028
ec3e5a16
GR		 1029static ssize_t
1030show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1031{
1032 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1033 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1034 int nr = sensor_attr->index;
3382a918 1035 return sprintf(buf, "%d\n", data->rpm[nr]);
ec3e5a16
GR		 1036}
1037
1038static ssize_t
1039show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1040{
1041 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1042 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1043 int nr = sensor_attr->index;
1044 return sprintf(buf, "%d\n",
26bc440e
GR		 1045 data->fan_from_reg_min(data->fan_min[nr],
1046 data->fan_div[nr]));
08e7e278 1047}
08e7e278
JD		 1048
1049static ssize_t
412fec82
YM		 1050show_fan_div(struct device *dev, struct device_attribute *attr,
1051 char *buf)
08e7e278
JD		 1052{
1053 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 1054 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1055 int nr = sensor_attr->index;
1056 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 1057}
1058
1059static ssize_t
412fec82
YM		 1060store_fan_min(struct device *dev, struct device_attribute *attr,
1061 const char *buf, size_t count)
08e7e278 1062{
1ea6dd38 1063 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 1064 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1065 int nr = sensor_attr->index;
bce26c58
GR		 1066 unsigned long val;
1067 int err;
08e7e278
JD		 1068 unsigned int reg;
1069 u8 new_div;
1070
179c4fdb 1071 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1072 if (err < 0)
1073 return err;
1074
9a61bf63 1075 mutex_lock(&data->update_lock);
26bc440e
GR		 1076 if (!data->has_fan_div) {
1077 /*
1078 * Only NCT6776F for now, so we know that this is a 13 bit
1079 * register
1080 */
ec3e5a16
GR		 1081 if (!val) {
1082 val = 0xff1f;
1083 } else {
1084 if (val > 1350000U)
1085 val = 135000U;
1086 val = 1350000U / val;
1087 val = (val & 0x1f) | ((val << 3) & 0xff00);
1088 }
1089 data->fan_min[nr] = val;
1090 goto done; /* Leave fan divider alone */
1091 }
08e7e278
JD		 1092 if (!val) {
1093 /* No min limit, alarm disabled */
1094 data->fan_min[nr] = 255;
1095 new_div = data->fan_div[nr]; /* No change */
1096 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1097 } else if ((reg = 1350000U / val) >= 128 * 255) {
8969e84d
GR		 1098 /*
1099 * Speed below this value cannot possibly be represented,
1100 * even with the highest divider (128)
1101 */
08e7e278
JD		 1102 data->fan_min[nr] = 254;
1103 new_div = 7; /* 128 == (1 << 7) */
bce26c58 1104 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
ec3e5a16 1105 "minimum\n", nr + 1, val,
26bc440e 1106 data->fan_from_reg_min(254, 7));
08e7e278 1107 } else if (!reg) {
8969e84d
GR		 1108 /*
1109 * Speed above this value cannot possibly be represented,
1110 * even with the lowest divider (1)
1111 */
08e7e278
JD		 1112 data->fan_min[nr] = 1;
1113 new_div = 0; /* 1 == (1 << 0) */
bce26c58 1114 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
ec3e5a16 1115 "maximum\n", nr + 1, val,
26bc440e 1116 data->fan_from_reg_min(1, 0));
08e7e278 1117 } else {
8969e84d
GR		 1118 /*
1119 * Automatically pick the best divider, i.e. the one such
1120 * that the min limit will correspond to a register value
1121 * in the 96..192 range
1122 */
08e7e278
JD		 1123 new_div = 0;
1124 while (reg > 192 && new_div < 7) {
1125 reg >>= 1;
1126 new_div++;
1127 }
1128 data->fan_min[nr] = reg;
1129 }
1130
8969e84d
GR		 1131 /*
1132 * Write both the fan clock divider (if it changed) and the new
1133 * fan min (unconditionally)
1134 */
08e7e278 1135 if (new_div != data->fan_div[nr]) {
08e7e278
JD		 1136 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1137 nr + 1, div_from_reg(data->fan_div[nr]),
1138 div_from_reg(new_div));
1139 data->fan_div[nr] = new_div;
ec3e5a16 1140 w83627ehf_write_fan_div_common(dev, data, nr);
6b3e4645
JD		 1141 /* Give the chip time to sample a new speed value */
1142 data->last_updated = jiffies;
08e7e278 1143 }
ec3e5a16 1144done:
279af1a9 1145 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
08e7e278 1146 data->fan_min[nr]);
9a61bf63 1147 mutex_unlock(&data->update_lock);
08e7e278
JD		 1148
1149 return count;
1150}
1151
412fec82
YM		 1152static struct sensor_device_attribute sda_fan_input[] = {
1153 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1154 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1155 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1156 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1157 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1158};
08e7e278 1159
a4589dbb
JD		 1160static struct sensor_device_attribute sda_fan_alarm[] = {
1161 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1162 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1163 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1164 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1165 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1166};
1167
412fec82
YM		 1168static struct sensor_device_attribute sda_fan_min[] = {
1169 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1170 store_fan_min, 0),
1171 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1172 store_fan_min, 1),
1173 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1174 store_fan_min, 2),
1175 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1176 store_fan_min, 3),
1177 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1178 store_fan_min, 4),
1179};
08e7e278 1180
412fec82
YM		 1181static struct sensor_device_attribute sda_fan_div[] = {
1182 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1183 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1184 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1185 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1186 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1187};
1188
d36cf32c
GR		 1189static ssize_t
1190show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1191{
1192 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1193 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1194 int nr = sensor_attr->index;
1195 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1196}
1197
ec3e5a16 1198#define show_temp_reg(addr, reg) \
08e7e278 1199static ssize_t \
412fec82
YM		 1200show_##reg(struct device *dev, struct device_attribute *attr, \
1201 char *buf) \
08e7e278
JD		 1202{ \
1203 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1204 struct sensor_device_attribute *sensor_attr = \
1205 to_sensor_dev_attr(attr); \
412fec82 1206 int nr = sensor_attr->index; \
c5794cfa 1207 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->reg[nr])); \
08e7e278 1208}
ec3e5a16
GR		 1209show_temp_reg(reg_temp, temp);
1210show_temp_reg(reg_temp_over, temp_max);
1211show_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1212
ec3e5a16 1213#define store_temp_reg(addr, reg) \
08e7e278 1214static ssize_t \
412fec82
YM		 1215store_##reg(struct device *dev, struct device_attribute *attr, \
1216 const char *buf, size_t count) \
08e7e278 1217{ \
1ea6dd38 1218 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1219 struct sensor_device_attribute *sensor_attr = \
1220 to_sensor_dev_attr(attr); \
412fec82 1221 int nr = sensor_attr->index; \
bce26c58
GR		 1222 int err; \
1223 long val; \
179c4fdb 1224 err = kstrtol(buf, 10, &val); \
bce26c58
GR		 1225 if (err < 0) \
1226 return err; \
9a61bf63 1227 mutex_lock(&data->update_lock); \
c5794cfa
JD		 1228 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1229 w83627ehf_write_temp(data, data->addr[nr], data->reg[nr]); \
9a61bf63 1230 mutex_unlock(&data->update_lock); \
08e7e278
JD		 1231 return count; \
1232}
ec3e5a16
GR		 1233store_temp_reg(reg_temp_over, temp_max);
1234store_temp_reg(reg_temp_hyst, temp_max_hyst);
08e7e278 1235
840e191d
GR		 1236static ssize_t
1237show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
1238{
1239 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1240 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1241
1242 return sprintf(buf, "%d\n",
1243 data->temp_offset[sensor_attr->index] * 1000);
1244}
1245
1246static ssize_t
1247store_temp_offset(struct device *dev, struct device_attribute *attr,
1248 const char *buf, size_t count)
1249{
1250 struct w83627ehf_data *data = dev_get_drvdata(dev);
1251 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1252 int nr = sensor_attr->index;
1253 long val;
1254 int err;
1255
1256 err = kstrtol(buf, 10, &val);
1257 if (err < 0)
1258 return err;
1259
1260 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
1261
1262 mutex_lock(&data->update_lock);
1263 data->temp_offset[nr] = val;
1264 w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[nr], val);
1265 mutex_unlock(&data->update_lock);
1266 return count;
1267}
1268
da667365
JD		 1269static ssize_t
1270show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1271{
1272 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1273 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1274 int nr = sensor_attr->index;
1275 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1276}
1277
a157d06d 1278static struct sensor_device_attribute sda_temp_input[] = {
bce26c58
GR		 1279 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1280 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1281 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
d36cf32c 1282 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
ec3e5a16
GR		 1283 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1284 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1285 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1286 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1287 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
d36cf32c
GR		 1288};
1289
1290static struct sensor_device_attribute sda_temp_label[] = {
1291 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1292 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1293 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1294 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
ec3e5a16
GR		 1295 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1296 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1297 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1298 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1299 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
a157d06d
GJ		 1300};
1301
1302static struct sensor_device_attribute sda_temp_max[] = {
bce26c58 1303 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1304 store_temp_max, 0),
bce26c58 1305 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
412fec82 1306 store_temp_max, 1),
bce26c58
GR		 1307 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1308 store_temp_max, 2),
ec3e5a16
GR		 1309 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1310 store_temp_max, 3),
1311 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1312 store_temp_max, 4),
1313 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1314 store_temp_max, 5),
1315 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1316 store_temp_max, 6),
1317 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1318 store_temp_max, 7),
1319 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1320 store_temp_max, 8),
a157d06d
GJ		 1321};
1322
1323static struct sensor_device_attribute sda_temp_max_hyst[] = {
bce26c58 1324 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1325 store_temp_max_hyst, 0),
bce26c58 1326 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
412fec82 1327 store_temp_max_hyst, 1),
bce26c58
GR		 1328 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1329 store_temp_max_hyst, 2),
ec3e5a16
GR		 1330 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1331 store_temp_max_hyst, 3),
1332 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1333 store_temp_max_hyst, 4),
1334 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1335 store_temp_max_hyst, 5),
1336 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1337 store_temp_max_hyst, 6),
1338 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1339 store_temp_max_hyst, 7),
1340 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1341 store_temp_max_hyst, 8),
a157d06d
GJ		 1342};
1343
1344static struct sensor_device_attribute sda_temp_alarm[] = {
a4589dbb
JD		 1345 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1346 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1347 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
a157d06d
GJ		 1348};
1349
1350static struct sensor_device_attribute sda_temp_type[] = {
da667365
JD		 1351 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1352 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1353 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 1354};
08e7e278 1355
840e191d
GR		 1356static struct sensor_device_attribute sda_temp_offset[] = {
1357 SENSOR_ATTR(temp1_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1358 store_temp_offset, 0),
1359 SENSOR_ATTR(temp2_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1360 store_temp_offset, 1),
1361 SENSOR_ATTR(temp3_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1362 store_temp_offset, 2),
1363};
1364
08c79950 1365#define show_pwm_reg(reg) \
e7e1ca6e
GR		 1366static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1367 char *buf) \
08c79950
RM		 1368{ \
1369 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1370 struct sensor_device_attribute *sensor_attr = \
1371 to_sensor_dev_attr(attr); \
08c79950
RM		 1372 int nr = sensor_attr->index; \
1373 return sprintf(buf, "%d\n", data->reg[nr]); \
1374}
1375
1376show_pwm_reg(pwm_mode)
1377show_pwm_reg(pwm_enable)
1378show_pwm_reg(pwm)
1379
1380static ssize_t
1381store_pwm_mode(struct device *dev, struct device_attribute *attr,
1382 const char *buf, size_t count)
1383{
1ea6dd38 1384 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 1385 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
ad77c3e1 1386 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950 1387 int nr = sensor_attr->index;
bce26c58
GR		 1388 unsigned long val;
1389 int err;
08c79950
RM		 1390 u16 reg;
1391
179c4fdb 1392 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1393 if (err < 0)
1394 return err;
1395
08c79950
RM		 1396 if (val > 1)
1397 return -EINVAL;
ad77c3e1
GR		 1398
1399 /* On NCT67766F, DC mode is only supported for pwm1 */
1400 if (sio_data->kind == nct6776 && nr && val != 1)
1401 return -EINVAL;
1402
08c79950 1403 mutex_lock(&data->update_lock);
1ea6dd38 1404 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 1405 data->pwm_mode[nr] = val;
1406 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1407 if (!val)
1408 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 1409 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 1410 mutex_unlock(&data->update_lock);
1411 return count;
1412}
1413
1414static ssize_t
1415store_pwm(struct device *dev, struct device_attribute *attr,
1416 const char *buf, size_t count)
1417{
1ea6dd38 1418 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1419 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1420 int nr = sensor_attr->index;
bce26c58
GR		 1421 unsigned long val;
1422 int err;
1423
179c4fdb 1424 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1425 if (err < 0)
1426 return err;
1427
1428 val = SENSORS_LIMIT(val, 0, 255);
08c79950
RM		 1429
1430 mutex_lock(&data->update_lock);
1431 data->pwm[nr] = val;
279af1a9 1432 w83627ehf_write_value(data, data->REG_PWM[nr], val);
08c79950
RM		 1433 mutex_unlock(&data->update_lock);
1434 return count;
1435}
1436
1437static ssize_t
1438store_pwm_enable(struct device *dev, struct device_attribute *attr,
1439 const char *buf, size_t count)
1440{
1ea6dd38 1441 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1442 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1443 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1444 int nr = sensor_attr->index;
bce26c58
GR		 1445 unsigned long val;
1446 int err;
08c79950
RM		 1447 u16 reg;
1448
179c4fdb 1449 err = kstrtoul(buf, 10, &val);
bce26c58
GR		 1450 if (err < 0)
1451 return err;
1452
b84bb518 1453 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
08c79950 1454 return -EINVAL;
ec3e5a16
GR		 1455 /* SmartFan III mode is not supported on NCT6776F */
1456 if (sio_data->kind == nct6776 && val == 4)
1457 return -EINVAL;
1458
08c79950 1459 mutex_lock(&data->update_lock);
08c79950 1460 data->pwm_enable[nr] = val;
ec3e5a16
GR		 1461 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1462 reg = w83627ehf_read_value(data,
1463 NCT6775_REG_FAN_MODE[nr]);
1464 reg &= 0x0f;
1465 reg |= (val - 1) << 4;
1466 w83627ehf_write_value(data,
1467 NCT6775_REG_FAN_MODE[nr], reg);
1468 } else {
1469 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1470 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1471 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1472 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1473 }
08c79950
RM		 1474 mutex_unlock(&data->update_lock);
1475 return count;
1476}
1477
1478
1479#define show_tol_temp(reg) \
1480static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1481 char *buf) \
1482{ \
1483 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1484 struct sensor_device_attribute *sensor_attr = \
1485 to_sensor_dev_attr(attr); \
08c79950 1486 int nr = sensor_attr->index; \
bce26c58 1487 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
08c79950
RM		 1488}
1489
1490show_tol_temp(tolerance)
1491show_tol_temp(target_temp)
1492
1493static ssize_t
1494store_target_temp(struct device *dev, struct device_attribute *attr,
1495 const char *buf, size_t count)
1496{
1ea6dd38 1497 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 1498 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1499 int nr = sensor_attr->index;
bce26c58
GR		 1500 long val;
1501 int err;
1502
179c4fdb 1503 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1504 if (err < 0)
1505 return err;
1506
1507 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
08c79950
RM		 1508
1509 mutex_lock(&data->update_lock);
1510 data->target_temp[nr] = val;
279af1a9 1511 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
08c79950
RM		 1512 mutex_unlock(&data->update_lock);
1513 return count;
1514}
1515
1516static ssize_t
1517store_tolerance(struct device *dev, struct device_attribute *attr,
1518 const char *buf, size_t count)
1519{
1ea6dd38 1520 struct w83627ehf_data *data = dev_get_drvdata(dev);
ec3e5a16 1521 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08c79950
RM		 1522 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1523 int nr = sensor_attr->index;
1524 u16 reg;
bce26c58
GR		 1525 long val;
1526 int err;
1527
179c4fdb 1528 err = kstrtol(buf, 10, &val);
bce26c58
GR		 1529 if (err < 0)
1530 return err;
1531
08c79950 1532 /* Limit the temp to 0C - 15C */
bce26c58 1533 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
08c79950
RM		 1534
1535 mutex_lock(&data->update_lock);
ec3e5a16
GR		 1536 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1537 /* Limit tolerance further for NCT6776F */
1538 if (sio_data->kind == nct6776 && val > 7)
1539 val = 7;
1540 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
08c79950 1541 reg = (reg & 0xf0) | val;
ec3e5a16
GR		 1542 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1543 } else {
1544 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1545 if (nr == 1)
1546 reg = (reg & 0x0f) | (val << 4);
1547 else
1548 reg = (reg & 0xf0) | val;
1549 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1550 }
1551 data->tolerance[nr] = val;
08c79950
RM		 1552 mutex_unlock(&data->update_lock);
1553 return count;
1554}
1555
1556static struct sensor_device_attribute sda_pwm[] = {
1557 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1558 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1559 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1560 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1561};
1562
1563static struct sensor_device_attribute sda_pwm_mode[] = {
1564 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1565 store_pwm_mode, 0),
1566 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1567 store_pwm_mode, 1),
1568 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1569 store_pwm_mode, 2),
1570 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1571 store_pwm_mode, 3),
1572};
1573
1574static struct sensor_device_attribute sda_pwm_enable[] = {
1575 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1576 store_pwm_enable, 0),
1577 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1578 store_pwm_enable, 1),
1579 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1580 store_pwm_enable, 2),
1581 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1582 store_pwm_enable, 3),
1583};
1584
1585static struct sensor_device_attribute sda_target_temp[] = {
1586 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1587 store_target_temp, 0),
1588 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1589 store_target_temp, 1),
1590 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1591 store_target_temp, 2),
1592 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1593 store_target_temp, 3),
1594};
1595
1596static struct sensor_device_attribute sda_tolerance[] = {
1597 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1598 store_tolerance, 0),
1599 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1600 store_tolerance, 1),
1601 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1602 store_tolerance, 2),
1603 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1604 store_tolerance, 3),
1605};
1606
08c79950
RM		 1607/* Smart Fan registers */
1608
1609#define fan_functions(reg, REG) \
1610static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1611 char *buf) \
1612{ \
1613 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1614 struct sensor_device_attribute *sensor_attr = \
1615 to_sensor_dev_attr(attr); \
08c79950
RM		 1616 int nr = sensor_attr->index; \
1617 return sprintf(buf, "%d\n", data->reg[nr]); \
e7e1ca6e 1618} \
08c79950
RM		 1619static ssize_t \
1620store_##reg(struct device *dev, struct device_attribute *attr, \
1621 const char *buf, size_t count) \
e7e1ca6e 1622{ \
1ea6dd38 1623 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1624 struct sensor_device_attribute *sensor_attr = \
1625 to_sensor_dev_attr(attr); \
08c79950 1626 int nr = sensor_attr->index; \
bce26c58
GR		 1627 unsigned long val; \
1628 int err; \
179c4fdb 1629 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1630 if (err < 0) \
1631 return err; \
1632 val = SENSORS_LIMIT(val, 1, 255); \
08c79950
RM		 1633 mutex_lock(&data->update_lock); \
1634 data->reg[nr] = val; \
da2e0255 1635 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1636 mutex_unlock(&data->update_lock); \
1637 return count; \
1638}
1639
41e9a062
DB		 1640fan_functions(fan_start_output, FAN_START_OUTPUT)
1641fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1642fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1643fan_functions(fan_step_output, FAN_STEP_OUTPUT)
08c79950
RM		 1644
1645#define fan_time_functions(reg, REG) \
1646static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1647 char *buf) \
1648{ \
1649 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
e7e1ca6e
GR		 1650 struct sensor_device_attribute *sensor_attr = \
1651 to_sensor_dev_attr(attr); \
08c79950
RM		 1652 int nr = sensor_attr->index; \
1653 return sprintf(buf, "%d\n", \
e7e1ca6e
GR		 1654 step_time_from_reg(data->reg[nr], \
1655 data->pwm_mode[nr])); \
08c79950
RM		 1656} \
1657\
1658static ssize_t \
1659store_##reg(struct device *dev, struct device_attribute *attr, \
1660 const char *buf, size_t count) \
1661{ \
1ea6dd38 1662 struct w83627ehf_data *data = dev_get_drvdata(dev); \
e7e1ca6e
GR		 1663 struct sensor_device_attribute *sensor_attr = \
1664 to_sensor_dev_attr(attr); \
08c79950 1665 int nr = sensor_attr->index; \
bce26c58
GR		 1666 unsigned long val; \
1667 int err; \
179c4fdb 1668 err = kstrtoul(buf, 10, &val); \
bce26c58
GR		 1669 if (err < 0) \
1670 return err; \
1671 val = step_time_to_reg(val, data->pwm_mode[nr]); \
08c79950
RM		 1672 mutex_lock(&data->update_lock); \
1673 data->reg[nr] = val; \
33fa9b62 1674 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
08c79950
RM		 1675 mutex_unlock(&data->update_lock); \
1676 return count; \
1677} \
1678
1679fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1680
1ea6dd38
DH		 1681static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1682 char *buf)
1683{
1684 struct w83627ehf_data *data = dev_get_drvdata(dev);
1685
1686 return sprintf(buf, "%s\n", data->name);
1687}
1688static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1689
1690static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1691 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1692 store_fan_stop_time, 3),
41e9a062
DB		 1693 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1694 store_fan_start_output, 3),
1695 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1696 store_fan_stop_output, 3),
1697 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1698 store_fan_max_output, 3),
1699 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1700 store_fan_step_output, 3),
08c79950
RM		 1701};
1702
eff7687d
JD		 1703static struct sensor_device_attribute sda_sf3_arrays_fan3[] = {
1704 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1705 store_fan_stop_time, 2),
1706 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1707 store_fan_start_output, 2),
1708 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1709 store_fan_stop_output, 2),
1710};
1711
08c79950
RM		 1712static struct sensor_device_attribute sda_sf3_arrays[] = {
1713 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1714 store_fan_stop_time, 0),
1715 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1716 store_fan_stop_time, 1),
41e9a062
DB		 1717 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1718 store_fan_start_output, 0),
1719 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1720 store_fan_start_output, 1),
41e9a062
DB		 1721 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1722 store_fan_stop_output, 0),
1723 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1724 store_fan_stop_output, 1),
da2e0255 1725};
41e9a062 1726
da2e0255
GR		 1727
1728/*
1729 * pwm1 and pwm3 don't support max and step settings on all chips.
1730 * Need to check support while generating/removing attribute files.
1731 */
1732static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1733 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1734 store_fan_max_output, 0),
1735 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1736 store_fan_step_output, 0),
41e9a062
DB		 1737 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1738 store_fan_max_output, 1),
1739 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1740 store_fan_step_output, 1),
da2e0255
GR		 1741 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1742 store_fan_max_output, 2),
1743 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1744 store_fan_step_output, 2),
08c79950
RM		 1745};
1746
fc18d6c0
JD		 1747static ssize_t
1748show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1749{
1750 struct w83627ehf_data *data = dev_get_drvdata(dev);
1751 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1752}
1753static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1754
363a12a4
DA		 1755
1756/* Case open detection */
1757
1758static ssize_t
1759show_caseopen(struct device *dev, struct device_attribute *attr, char *buf)
1760{
1761 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1762
1763 return sprintf(buf, "%d\n",
1764 !!(data->caseopen & to_sensor_dev_attr_2(attr)->index));
1765}
1766
1767static ssize_t
1768clear_caseopen(struct device *dev, struct device_attribute *attr,
1769 const char *buf, size_t count)
1770{
1771 struct w83627ehf_data *data = dev_get_drvdata(dev);
1772 unsigned long val;
1773 u16 reg, mask;
1774
179c4fdb 1775 if (kstrtoul(buf, 10, &val) || val != 0)
363a12a4
DA		 1776 return -EINVAL;
1777
1778 mask = to_sensor_dev_attr_2(attr)->nr;
1779
1780 mutex_lock(&data->update_lock);
1781 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1782 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1783 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1784 data->valid = 0; /* Force cache refresh */
1785 mutex_unlock(&data->update_lock);
1786
1787 return count;
1788}
1789
1790static struct sensor_device_attribute_2 sda_caseopen[] = {
1791 SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1792 clear_caseopen, 0x80, 0x10),
1793 SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1794 clear_caseopen, 0x40, 0x40),
1795};
1796
08e7e278 1797/*
1ea6dd38 1798 * Driver and device management
08e7e278
JD		 1799 */
1800
c18beb5b
DH		 1801static void w83627ehf_device_remove_files(struct device *dev)
1802{
8969e84d
GR		 1803 /*
1804 * some entries in the following arrays may not have been used in
1805 * device_create_file(), but device_remove_file() will ignore them
1806 */
c18beb5b 1807 int i;
1ea6dd38 1808 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1809
1810 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1811 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
da2e0255
GR		 1812 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1813 struct sensor_device_attribute *attr =
1814 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 1815 if (data->REG_FAN_STEP_OUTPUT &&
1816 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
da2e0255
GR		 1817 device_remove_file(dev, &attr->dev_attr);
1818 }
eff7687d
JD		 1819 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++)
1820 device_remove_file(dev, &sda_sf3_arrays_fan3[i].dev_attr);
c18beb5b
DH		 1821 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1822 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1823 for (i = 0; i < data->in_num; i++) {
a157d06d
GJ		 1824 if ((i == 6) && data->in6_skip)
1825 continue;
c18beb5b
DH		 1826 device_remove_file(dev, &sda_in_input[i].dev_attr);
1827 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1828 device_remove_file(dev, &sda_in_min[i].dev_attr);
1829 device_remove_file(dev, &sda_in_max[i].dev_attr);
1830 }
1831 for (i = 0; i < 5; i++) {
1832 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1833 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1834 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1835 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1836 }
237c8d2f 1837 for (i = 0; i < data->pwm_num; i++) {
c18beb5b
DH		 1838 device_remove_file(dev, &sda_pwm[i].dev_attr);
1839 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1840 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1841 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1842 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1843 }
d36cf32c
GR		 1844 for (i = 0; i < NUM_REG_TEMP; i++) {
1845 if (!(data->have_temp & (1 << i)))
a157d06d
GJ		 1846 continue;
1847 device_remove_file(dev, &sda_temp_input[i].dev_attr);
d36cf32c 1848 device_remove_file(dev, &sda_temp_label[i].dev_attr);
eff7687d
JD		 1849 if (i == 2 && data->temp3_val_only)
1850 continue;
a157d06d
GJ		 1851 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1852 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
ec3e5a16
GR		 1853 if (i > 2)
1854 continue;
a157d06d
GJ		 1855 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1856 device_remove_file(dev, &sda_temp_type[i].dev_attr);
840e191d 1857 device_remove_file(dev, &sda_temp_offset[i].dev_attr);
a157d06d 1858 }
c18beb5b 1859
363a12a4
DA		 1860 device_remove_file(dev, &sda_caseopen[0].dev_attr);
1861 device_remove_file(dev, &sda_caseopen[1].dev_attr);
1862
1ea6dd38 1863 device_remove_file(dev, &dev_attr_name);
cbe311f2 1864 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1865}
08e7e278 1866
1ea6dd38 1867/* Get the monitoring functions started */
bf164c58
JD		 1868static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data,
1869 enum kinds kind)
08e7e278
JD		 1870{
1871 int i;
da667365 1872 u8 tmp, diode;
08e7e278
JD		 1873
1874 /* Start monitoring is needed */
1ea6dd38 1875 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1876 if (!(tmp & 0x01))
1ea6dd38 1877 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1878 tmp | 0x01);
1879
d36cf32c
GR		 1880 /* Enable temperature sensors if needed */
1881 for (i = 0; i < NUM_REG_TEMP; i++) {
1882 if (!(data->have_temp & (1 << i)))
1883 continue;
ec3e5a16 1884 if (!data->reg_temp_config[i])
d36cf32c 1885 continue;
1ea6dd38 1886 tmp = w83627ehf_read_value(data,
ec3e5a16 1887 data->reg_temp_config[i]);
08e7e278 1888 if (tmp & 0x01)
1ea6dd38 1889 w83627ehf_write_value(data,
ec3e5a16 1890 data->reg_temp_config[i],
08e7e278
JD		 1891 tmp & 0xfe);
1892 }
d3130f0e
JD		 1893
1894 /* Enable VBAT monitoring if needed */
1895 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1896 if (!(tmp & 0x01))
1897 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1898
1899 /* Get thermal sensor types */
bf164c58
JD		 1900 switch (kind) {
1901 case w83627ehf:
1902 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1903 break;
eff7687d
JD		 1904 case w83627uhg:
1905 diode = 0x00;
1906 break;
bf164c58
JD		 1907 default:
1908 diode = 0x70;
1909 }
da667365 1910 for (i = 0; i < 3; i++) {
bfa02b0d
GR		 1911 const char *label = NULL;
1912
1913 if (data->temp_label)
1914 label = data->temp_label[data->temp_src[i]];
2265cef2
JD		 1915
1916 /* Digital source overrides analog type */
bfa02b0d 1917 if (label && strncmp(label, "PECI", 4) == 0)
2265cef2 1918 data->temp_type[i] = 6;
bfa02b0d 1919 else if (label && strncmp(label, "AMD", 3) == 0)
2265cef2
JD		 1920 data->temp_type[i] = 5;
1921 else if ((tmp & (0x02 << i)))
bf164c58 1922 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
da667365
JD		 1923 else
1924 data->temp_type[i] = 4; /* thermistor */
1925 }
08e7e278
JD		 1926}
1927
ec3e5a16
GR		 1928static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1929 int r1, int r2)
1930{
1931 u16 tmp;
1932
1933 tmp = data->temp_src[r1];
1934 data->temp_src[r1] = data->temp_src[r2];
1935 data->temp_src[r2] = tmp;
1936
1937 tmp = data->reg_temp[r1];
1938 data->reg_temp[r1] = data->reg_temp[r2];
1939 data->reg_temp[r2] = tmp;
1940
1941 tmp = data->reg_temp_over[r1];
1942 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1943 data->reg_temp_over[r2] = tmp;
1944
1945 tmp = data->reg_temp_hyst[r1];
1946 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1947 data->reg_temp_hyst[r2] = tmp;
1948
1949 tmp = data->reg_temp_config[r1];
1950 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1951 data->reg_temp_config[r2] = tmp;
1952}
1953
6ba71de5
JD		 1954static void __devinit
1955w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1956{
1957 int i;
1958
1959 for (i = 0; i < n_temp; i++) {
1960 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1961 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1962 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1963 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1964 }
1965}
1966
03f5de2b
JD		 1967static void __devinit
1968w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1969 struct w83627ehf_data *data)
1970{
1971 int fan3pin, fan4pin, fan4min, fan5pin, regval;
1972
eff7687d
JD		 1973 /* The W83627UHG is simple, only two fan inputs, no config */
1974 if (sio_data->kind == w83627uhg) {
1975 data->has_fan = 0x03; /* fan1 and fan2 */
1976 data->has_fan_min = 0x03;
1977 return;
1978 }
1979
03f5de2b
JD		 1980 superio_enter(sio_data->sioreg);
1981
1982 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1983 if (sio_data->kind == nct6775) {
1984 /* On NCT6775, fan4 shares pins with the fdc interface */
1985 fan3pin = 1;
1986 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
1987 fan4min = 0;
1988 fan5pin = 0;
1989 } else if (sio_data->kind == nct6776) {
585c0fd8
GR		 1990 bool gpok = superio_inb(sio_data->sioreg, 0x27) & 0x80;
1991
1992 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1993 regval = superio_inb(sio_data->sioreg, SIO_REG_ENABLE);
1994
1995 if (regval & 0x80)
1996 fan3pin = gpok;
1997 else
1998 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
1999
2000 if (regval & 0x40)
2001 fan4pin = gpok;
2002 else
2003 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
2004
2005 if (regval & 0x20)
2006 fan5pin = gpok;
2007 else
2008 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
2009
03f5de2b
JD		 2010 fan4min = fan4pin;
2011 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
2012 fan3pin = 1;
2013 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
2014 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
2015 fan4min = fan4pin;
2016 } else {
2017 fan3pin = 1;
2018 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
2019 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2020 fan4min = fan4pin;
2021 }
2022
2023 superio_exit(sio_data->sioreg);
2024
2025 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2026 data->has_fan |= (fan3pin << 2);
2027 data->has_fan_min |= (fan3pin << 2);
2028
2029 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2030 /*
2031 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
2032 * register
2033 */
2034 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
2035 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
2036 } else {
2037 /*
2038 * It looks like fan4 and fan5 pins can be alternatively used
2039 * as fan on/off switches, but fan5 control is write only :/
2040 * We assume that if the serial interface is disabled, designers
2041 * connected fan5 as input unless they are emitting log 1, which
2042 * is not the default.
2043 */
2044 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2045 if ((regval & (1 << 2)) && fan4pin) {
2046 data->has_fan |= (1 << 3);
2047 data->has_fan_min |= (1 << 3);
2048 }
2049 if (!(regval & (1 << 1)) && fan5pin) {
2050 data->has_fan |= (1 << 4);
2051 data->has_fan_min |= (1 << 4);
2052 }
2053 }
2054}
2055
1ea6dd38 2056static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 2057{
1ea6dd38
DH		 2058 struct device *dev = &pdev->dev;
2059 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 2060 struct w83627ehf_data *data;
1ea6dd38 2061 struct resource *res;
03f5de2b 2062 u8 en_vrm10;
08e7e278
JD		 2063 int i, err = 0;
2064
1ea6dd38
DH		 2065 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2066 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 2067 err = -EBUSY;
1ea6dd38
DH		 2068 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2069 (unsigned long)res->start,
2070 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 2071 goto exit;
2072 }
2073
32260d94
GR		 2074 data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
2075 GFP_KERNEL);
e7e1ca6e 2076 if (!data) {
08e7e278
JD		 2077 err = -ENOMEM;
2078 goto exit_release;
2079 }
08e7e278 2080
1ea6dd38 2081 data->addr = res->start;
9a61bf63 2082 mutex_init(&data->lock);
9a61bf63 2083 mutex_init(&data->update_lock);
1ea6dd38
DH		 2084 data->name = w83627ehf_device_names[sio_data->kind];
2085 platform_set_drvdata(pdev, data);
08e7e278 2086
237c8d2f
GJ		 2087 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
2088 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
eff7687d
JD		 2089 /* 667HG, NCT6775F, and NCT6776F have 3 pwms, and 627UHG has only 2 */
2090 switch (sio_data->kind) {
2091 default:
2092 data->pwm_num = 4;
2093 break;
2094 case w83667hg:
2095 case w83667hg_b:
2096 case nct6775:
2097 case nct6776:
2098 data->pwm_num = 3;
2099 break;
2100 case w83627uhg:
2101 data->pwm_num = 2;
2102 break;
2103 }
08e7e278 2104
6ba71de5 2105 /* Default to 3 temperature inputs, code below will adjust as needed */
d36cf32c 2106 data->have_temp = 0x07;
ec3e5a16
GR		 2107
2108 /* Deal with temperature register setup first. */
2109 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2110 int mask = 0;
2111
2112 /*
2113 * Display temperature sensor output only if it monitors
2114 * a source other than one already reported. Always display
2115 * first three temperature registers, though.
2116 */
2117 for (i = 0; i < NUM_REG_TEMP; i++) {
2118 u8 src;
2119
2120 data->reg_temp[i] = NCT6775_REG_TEMP[i];
2121 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
2122 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
2123 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
2124
2125 src = w83627ehf_read_value(data,
2126 NCT6775_REG_TEMP_SOURCE[i]);
2127 src &= 0x1f;
2128 if (src && !(mask & (1 << src))) {
2129 data->have_temp |= 1 << i;
2130 mask |= 1 << src;
2131 }
2132
2133 data->temp_src[i] = src;
2134
2135 /*
2136 * Now do some register swapping if index 0..2 don't
2137 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
2138 * Idea is to have the first three attributes
2139 * report SYSTIN, CPUIN, and AUXIN if possible
2140 * without overriding the basic system configuration.
2141 */
2142 if (i > 0 && data->temp_src[0] != 1
2143 && data->temp_src[i] == 1)
2144 w82627ehf_swap_tempreg(data, 0, i);
2145 if (i > 1 && data->temp_src[1] != 2
2146 && data->temp_src[i] == 2)
2147 w82627ehf_swap_tempreg(data, 1, i);
2148 if (i > 2 && data->temp_src[2] != 3
2149 && data->temp_src[i] == 3)
2150 w82627ehf_swap_tempreg(data, 2, i);
2151 }
2152 if (sio_data->kind == nct6776) {
2153 /*
2154 * On NCT6776, AUXTIN and VIN3 pins are shared.
2155 * Only way to detect it is to check if AUXTIN is used
2156 * as a temperature source, and if that source is
2157 * enabled.
2158 *
2159 * If that is the case, disable in6, which reports VIN3.
2160 * Otherwise disable temp3.
2161 */
2162 if (data->temp_src[2] == 3) {
2163 u8 reg;
2164
2165 if (data->reg_temp_config[2])
2166 reg = w83627ehf_read_value(data,
2167 data->reg_temp_config[2]);
2168 else
2169 reg = 0; /* Assume AUXTIN is used */
2170
2171 if (reg & 0x01)
2172 data->have_temp &= ~(1 << 2);
2173 else
2174 data->in6_skip = 1;
2175 }
02309ad2
GR		 2176 data->temp_label = nct6776_temp_label;
2177 } else {
2178 data->temp_label = nct6775_temp_label;
ec3e5a16 2179 }
840e191d
GR		 2180 data->have_temp_offset = data->have_temp & 0x07;
2181 for (i = 0; i < 3; i++) {
2182 if (data->temp_src[i] > 3)
2183 data->have_temp_offset &= ~(1 << i);
2184 }
d36cf32c
GR		 2185 } else if (sio_data->kind == w83667hg_b) {
2186 u8 reg;
2187
6ba71de5
JD		 2188 w83627ehf_set_temp_reg_ehf(data, 4);
2189
ec3e5a16
GR		 2190 /*
2191 * Temperature sources are selected with bank 0, registers 0x49
2192 * and 0x4a.
2193 */
d36cf32c
GR		 2194 reg = w83627ehf_read_value(data, 0x4a);
2195 data->temp_src[0] = reg >> 5;
2196 reg = w83627ehf_read_value(data, 0x49);
2197 data->temp_src[1] = reg & 0x07;
ec3e5a16 2198 data->temp_src[2] = (reg >> 4) & 0x07;
d36cf32c
GR		 2199
2200 /*
2201 * W83667HG-B has another temperature register at 0x7e.
2202 * The temperature source is selected with register 0x7d.
2203 * Support it if the source differs from already reported
2204 * sources.
2205 */
2206 reg = w83627ehf_read_value(data, 0x7d);
2207 reg &= 0x07;
2208 if (reg != data->temp_src[0] && reg != data->temp_src[1]
2209 && reg != data->temp_src[2]) {
2210 data->temp_src[3] = reg;
2211 data->have_temp |= 1 << 3;
2212 }
2213
2214 /*
2215 * Chip supports either AUXTIN or VIN3. Try to find out which
2216 * one.
2217 */
2218 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
2219 if (data->temp_src[2] == 2 && (reg & 0x01))
2220 data->have_temp &= ~(1 << 2);
2221
2222 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2223 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2224 data->in6_skip = 1;
2225
eff7687d 2226 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2227 data->have_temp_offset = data->have_temp & 0x07;
2228 for (i = 0; i < 3; i++) {
2229 if (data->temp_src[i] > 2)
2230 data->have_temp_offset &= ~(1 << i);
2231 }
eff7687d
JD		 2232 } else if (sio_data->kind == w83627uhg) {
2233 u8 reg;
2234
2235 w83627ehf_set_temp_reg_ehf(data, 3);
2236
2237 /*
aacb6b00 2238 * Temperature sources for temp2 and temp3 are selected with
eff7687d
JD		 2239 * bank 0, registers 0x49 and 0x4a.
2240 */
2241 data->temp_src[0] = 0; /* SYSTIN */
2242 reg = w83627ehf_read_value(data, 0x49) & 0x07;
2243 /* Adjust to have the same mapping as other source registers */
2244 if (reg == 0)
aacb6b00 2245 data->temp_src[1] = 1;
eff7687d 2246 else if (reg >= 2 && reg <= 5)
aacb6b00 2247 data->temp_src[1] = reg + 2;
eff7687d
JD		 2248 else /* should never happen */
2249 data->have_temp &= ~(1 << 1);
2250 reg = w83627ehf_read_value(data, 0x4a);
2251 data->temp_src[2] = reg >> 5;
2252
2253 /*
2254 * Skip temp3 if source is invalid or the same as temp1
2255 * or temp2.
2256 */
2257 if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
2258 data->temp_src[2] == data->temp_src[0] ||
2259 ((data->have_temp & (1 << 1)) &&
2260 data->temp_src[2] == data->temp_src[1]))
2261 data->have_temp &= ~(1 << 2);
2262 else
2263 data->temp3_val_only = 1; /* No limit regs */
2264
2265 data->in6_skip = 1; /* No VIN3 */
2266
d36cf32c 2267 data->temp_label = w83667hg_b_temp_label;
840e191d
GR		 2268 data->have_temp_offset = data->have_temp & 0x03;
2269 for (i = 0; i < 3; i++) {
2270 if (data->temp_src[i] > 1)
2271 data->have_temp_offset &= ~(1 << i);
2272 }
ec3e5a16 2273 } else {
6ba71de5
JD		 2274 w83627ehf_set_temp_reg_ehf(data, 3);
2275
ec3e5a16 2276 /* Temperature sources are fixed */
6ba71de5
JD		 2277
2278 if (sio_data->kind == w83667hg) {
2279 u8 reg;
2280
2281 /*
2282 * Chip supports either AUXTIN or VIN3. Try to find
2283 * out which one.
2284 */
2285 reg = w83627ehf_read_value(data,
2286 W83627EHF_REG_TEMP_CONFIG[2]);
2287 if (reg & 0x01)
2288 data->have_temp &= ~(1 << 2);
2289 else
2290 data->in6_skip = 1;
ec3e5a16 2291 }
840e191d 2292 data->have_temp_offset = data->have_temp & 0x07;
a157d06d
GJ		 2293 }
2294
ec3e5a16 2295 if (sio_data->kind == nct6775) {
26bc440e
GR		 2296 data->has_fan_div = true;
2297 data->fan_from_reg = fan_from_reg16;
2298 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2299 data->REG_PWM = NCT6775_REG_PWM;
2300 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2301 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2302 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2303 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2304 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2305 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2306 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2307 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2308 } else if (sio_data->kind == nct6776) {
26bc440e
GR		 2309 data->has_fan_div = false;
2310 data->fan_from_reg = fan_from_reg13;
2311 data->fan_from_reg_min = fan_from_reg13;
ec3e5a16
GR		 2312 data->REG_PWM = NCT6775_REG_PWM;
2313 data->REG_TARGET = NCT6775_REG_TARGET;
26bc440e 2314 data->REG_FAN = NCT6775_REG_FAN;
ec3e5a16
GR		 2315 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2316 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2317 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2318 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2319 } else if (sio_data->kind == w83667hg_b) {
26bc440e
GR		 2320 data->has_fan_div = true;
2321 data->fan_from_reg = fan_from_reg8;
2322 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2323 data->REG_PWM = W83627EHF_REG_PWM;
2324 data->REG_TARGET = W83627EHF_REG_TARGET;
2325 data->REG_FAN = W83627EHF_REG_FAN;
2326 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2327 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2328 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2329 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2330 data->REG_FAN_MAX_OUTPUT =
2331 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2332 data->REG_FAN_STEP_OUTPUT =
2333 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2334 } else {
26bc440e
GR		 2335 data->has_fan_div = true;
2336 data->fan_from_reg = fan_from_reg8;
2337 data->fan_from_reg_min = fan_from_reg8;
ec3e5a16
GR		 2338 data->REG_PWM = W83627EHF_REG_PWM;
2339 data->REG_TARGET = W83627EHF_REG_TARGET;
2340 data->REG_FAN = W83627EHF_REG_FAN;
2341 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2342 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2343 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2344 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
c39aedaf
GR		 2345 data->REG_FAN_MAX_OUTPUT =
2346 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2347 data->REG_FAN_STEP_OUTPUT =
2348 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2349 }
da2e0255 2350
eff7687d
JD		 2351 /* Setup input voltage scaling factors */
2352 if (sio_data->kind == w83627uhg)
2353 data->scale_in = scale_in_w83627uhg;
2354 else
2355 data->scale_in = scale_in_common;
2356
08e7e278 2357 /* Initialize the chip */
bf164c58 2358 w83627ehf_init_device(data, sio_data->kind);
08e7e278 2359
fc18d6c0
JD		 2360 data->vrm = vid_which_vrm();
2361 superio_enter(sio_data->sioreg);
fc18d6c0 2362 /* Read VID value */
ec3e5a16
GR		 2363 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2364 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
8969e84d
GR		 2365 /*
2366 * W83667HG has different pins for VID input and output, so
2367 * we can get the VID input values directly at logical device D
2368 * 0xe3.
2369 */
237c8d2f
GJ		 2370 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2371 data->vid = superio_inb(sio_data->sioreg, 0xe3);
cbe311f2
JD		 2372 err = device_create_file(dev, &dev_attr_cpu0_vid);
2373 if (err)
2374 goto exit_release;
eff7687d 2375 } else if (sio_data->kind != w83627uhg) {
237c8d2f
GJ		 2376 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2377 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
8969e84d
GR		 2378 /*
2379 * Set VID input sensibility if needed. In theory the
2380 * BIOS should have set it, but in practice it's not
2381 * always the case. We only do it for the W83627EHF/EHG
2382 * because the W83627DHG is more complex in this
2383 * respect.
2384 */
237c8d2f
GJ		 2385 if (sio_data->kind == w83627ehf) {
2386 en_vrm10 = superio_inb(sio_data->sioreg,
2387 SIO_REG_EN_VRM10);
2388 if ((en_vrm10 & 0x08) && data->vrm == 90) {
2389 dev_warn(dev, "Setting VID input "
2390 "voltage to TTL\n");
2391 superio_outb(sio_data->sioreg,
2392 SIO_REG_EN_VRM10,
2393 en_vrm10 & ~0x08);
2394 } else if (!(en_vrm10 & 0x08)
2395 && data->vrm == 100) {
2396 dev_warn(dev, "Setting VID input "
2397 "voltage to VRM10\n");
2398 superio_outb(sio_data->sioreg,
2399 SIO_REG_EN_VRM10,
2400 en_vrm10 | 0x08);
2401 }
2402 }
2403
2404 data->vid = superio_inb(sio_data->sioreg,
2405 SIO_REG_VID_DATA);
2406 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2407 data->vid &= 0x3f;
2408
2409 err = device_create_file(dev, &dev_attr_cpu0_vid);
2410 if (err)
2411 goto exit_release;
2412 } else {
2413 dev_info(dev, "VID pins in output mode, CPU VID not "
2414 "available\n");
2415 }
fc18d6c0
JD		 2416 }
2417
d42e869a
ID		 2418 if (fan_debounce &&
2419 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2420 u8 tmp;
2421
2422 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2423 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2424 if (sio_data->kind == nct6776)
2425 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2426 0x3e | tmp);
2427 else
2428 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2429 0x1e | tmp);
2430 pr_info("Enabled fan debounce for chip %s\n", data->name);
2431 }
2432
1ea6dd38 2433 superio_exit(sio_data->sioreg);
08c79950 2434
03f5de2b 2435 w83627ehf_check_fan_inputs(sio_data, data);
08e7e278 2436
ea7be66c 2437 /* Read fan clock dividers immediately */
ec3e5a16
GR		 2438 w83627ehf_update_fan_div_common(dev, data);
2439
b84bb518
GR		 2440 /* Read pwm data to save original values */
2441 w83627ehf_update_pwm_common(dev, data);
2442 for (i = 0; i < data->pwm_num; i++)
2443 data->pwm_enable_orig[i] = data->pwm_enable[i];
2444
08e7e278 2445 /* Register sysfs hooks */
e7e1ca6e
GR		 2446 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2447 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2448 if (err)
c18beb5b 2449 goto exit_remove;
e7e1ca6e 2450 }
08c79950 2451
da2e0255
GR		 2452 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2453 struct sensor_device_attribute *attr =
2454 &sda_sf3_max_step_arrays[i];
ec3e5a16
GR		 2455 if (data->REG_FAN_STEP_OUTPUT &&
2456 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
da2e0255
GR		 2457 err = device_create_file(dev, &attr->dev_attr);
2458 if (err)
2459 goto exit_remove;
2460 }
2461 }
eff7687d
JD		 2462 /* if fan3 and fan4 are enabled create the sf3 files for them */
2463 if ((data->has_fan & (1 << 2)) && data->pwm_num >= 3)
2464 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++) {
2465 err = device_create_file(dev,
2466 &sda_sf3_arrays_fan3[i].dev_attr);
2467 if (err)
2468 goto exit_remove;
2469 }
237c8d2f 2470 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
c18beb5b 2471 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
e7e1ca6e
GR		 2472 err = device_create_file(dev,
2473 &sda_sf3_arrays_fan4[i].dev_attr);
2474 if (err)
c18beb5b
DH		 2475 goto exit_remove;
2476 }
08c79950 2477
a157d06d
GJ		 2478 for (i = 0; i < data->in_num; i++) {
2479 if ((i == 6) && data->in6_skip)
2480 continue;
c18beb5b
DH		 2481 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2482 || (err = device_create_file(dev,
2483 &sda_in_alarm[i].dev_attr))
2484 || (err = device_create_file(dev,
2485 &sda_in_min[i].dev_attr))
2486 || (err = device_create_file(dev,
2487 &sda_in_max[i].dev_attr)))
2488 goto exit_remove;
a157d06d 2489 }
cf0676fe 2490
412fec82 2491 for (i = 0; i < 5; i++) {
08c79950 2492 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 2493 if ((err = device_create_file(dev,
2494 &sda_fan_input[i].dev_attr))
2495 || (err = device_create_file(dev,
ec3e5a16 2496 &sda_fan_alarm[i].dev_attr)))
c18beb5b 2497 goto exit_remove;
ec3e5a16
GR		 2498 if (sio_data->kind != nct6776) {
2499 err = device_create_file(dev,
2500 &sda_fan_div[i].dev_attr);
2501 if (err)
2502 goto exit_remove;
2503 }
2504 if (data->has_fan_min & (1 << i)) {
2505 err = device_create_file(dev,
2506 &sda_fan_min[i].dev_attr);
2507 if (err)
2508 goto exit_remove;
2509 }
237c8d2f 2510 if (i < data->pwm_num &&
c18beb5b
DH		 2511 ((err = device_create_file(dev,
2512 &sda_pwm[i].dev_attr))
2513 || (err = device_create_file(dev,
2514 &sda_pwm_mode[i].dev_attr))
2515 || (err = device_create_file(dev,
2516 &sda_pwm_enable[i].dev_attr))
2517 || (err = device_create_file(dev,
2518 &sda_target_temp[i].dev_attr))
2519 || (err = device_create_file(dev,
2520 &sda_tolerance[i].dev_attr))))
2521 goto exit_remove;
08c79950 2522 }
08e7e278 2523 }
08c79950 2524
d36cf32c
GR		 2525 for (i = 0; i < NUM_REG_TEMP; i++) {
2526 if (!(data->have_temp & (1 << i)))
a157d06d 2527 continue;
d36cf32c
GR		 2528 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2529 if (err)
2530 goto exit_remove;
2531 if (data->temp_label) {
2532 err = device_create_file(dev,
2533 &sda_temp_label[i].dev_attr);
2534 if (err)
2535 goto exit_remove;
2536 }
eff7687d
JD		 2537 if (i == 2 && data->temp3_val_only)
2538 continue;
ec3e5a16
GR		 2539 if (data->reg_temp_over[i]) {
2540 err = device_create_file(dev,
2541 &sda_temp_max[i].dev_attr);
2542 if (err)
2543 goto exit_remove;
2544 }
2545 if (data->reg_temp_hyst[i]) {
2546 err = device_create_file(dev,
2547 &sda_temp_max_hyst[i].dev_attr);
2548 if (err)
2549 goto exit_remove;
2550 }
d36cf32c 2551 if (i > 2)
ec3e5a16
GR		 2552 continue;
2553 if ((err = device_create_file(dev,
a157d06d
GJ		 2554 &sda_temp_alarm[i].dev_attr))
2555 || (err = device_create_file(dev,
2556 &sda_temp_type[i].dev_attr)))
c18beb5b 2557 goto exit_remove;
840e191d
GR		 2558 if (data->have_temp_offset & (1 << i)) {
2559 err = device_create_file(dev,
2560 &sda_temp_offset[i].dev_attr);
2561 if (err)
2562 goto exit_remove;
2563 }
a157d06d 2564 }
c18beb5b 2565
363a12a4
DA		 2566 err = device_create_file(dev, &sda_caseopen[0].dev_attr);
2567 if (err)
2568 goto exit_remove;
2569
2570 if (sio_data->kind == nct6776) {
2571 err = device_create_file(dev, &sda_caseopen[1].dev_attr);
2572 if (err)
2573 goto exit_remove;
2574 }
2575
1ea6dd38
DH		 2576 err = device_create_file(dev, &dev_attr_name);
2577 if (err)
2578 goto exit_remove;
2579
1beeffe4
TJ		 2580 data->hwmon_dev = hwmon_device_register(dev);
2581 if (IS_ERR(data->hwmon_dev)) {
2582 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 2583 goto exit_remove;
2584 }
08e7e278
JD		 2585
2586 return 0;
2587
c18beb5b
DH		 2588exit_remove:
2589 w83627ehf_device_remove_files(dev);
08e7e278 2590exit_release:
32260d94 2591 platform_set_drvdata(pdev, NULL);
1ea6dd38 2592 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 2593exit:
2594 return err;
2595}
2596
1ea6dd38 2597static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 2598{
1ea6dd38 2599 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 2600
1beeffe4 2601 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 2602 w83627ehf_device_remove_files(&pdev->dev);
2603 release_region(data->addr, IOREGION_LENGTH);
2604 platform_set_drvdata(pdev, NULL);
08e7e278
JD		 2605
2606 return 0;
2607}
2608
1ea6dd38 2609static struct platform_driver w83627ehf_driver = {
cdaf7934 2610 .driver = {
87218842 2611 .owner = THIS_MODULE,
1ea6dd38 2612 .name = DRVNAME,
cdaf7934 2613 },
1ea6dd38
DH		 2614 .probe = w83627ehf_probe,
2615 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 2616};
2617
1ea6dd38
DH		 2618/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2619static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2620 struct w83627ehf_sio_data *sio_data)
08e7e278 2621{
6f7805a8
UKK		 2622 static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
2623 static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
2624 static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
2625 static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
2626 static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
2627 static const char sio_name_W83667HG[] __initconst = "W83667HG";
2628 static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
2629 static const char sio_name_NCT6775[] __initconst = "NCT6775F";
2630 static const char sio_name_NCT6776[] __initconst = "NCT6776F";
1ea6dd38 2631
08e7e278 2632 u16 val;
1ea6dd38 2633 const char *sio_name;
08e7e278 2634
1ea6dd38 2635 superio_enter(sioaddr);
08e7e278 2636
67b671bc
JD		 2637 if (force_id)
2638 val = force_id;
2639 else
2640 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2641 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 2642 switch (val & SIO_ID_MASK) {
657c93b1 2643 case SIO_W83627EHF_ID:
1ea6dd38
DH		 2644 sio_data->kind = w83627ehf;
2645 sio_name = sio_name_W83627EHF;
2646 break;
657c93b1 2647 case SIO_W83627EHG_ID:
1ea6dd38
DH		 2648 sio_data->kind = w83627ehf;
2649 sio_name = sio_name_W83627EHG;
2650 break;
2651 case SIO_W83627DHG_ID:
2652 sio_data->kind = w83627dhg;
2653 sio_name = sio_name_W83627DHG;
657c93b1 2654 break;
c1e48dce
JD		 2655 case SIO_W83627DHG_P_ID:
2656 sio_data->kind = w83627dhg_p;
2657 sio_name = sio_name_W83627DHG_P;
2658 break;
eff7687d
JD		 2659 case SIO_W83627UHG_ID:
2660 sio_data->kind = w83627uhg;
2661 sio_name = sio_name_W83627UHG;
2662 break;
237c8d2f
GJ		 2663 case SIO_W83667HG_ID:
2664 sio_data->kind = w83667hg;
2665 sio_name = sio_name_W83667HG;
2666 break;
c39aedaf
GR		 2667 case SIO_W83667HG_B_ID:
2668 sio_data->kind = w83667hg_b;
2669 sio_name = sio_name_W83667HG_B;
2670 break;
ec3e5a16
GR		 2671 case SIO_NCT6775_ID:
2672 sio_data->kind = nct6775;
2673 sio_name = sio_name_NCT6775;
2674 break;
2675 case SIO_NCT6776_ID:
2676 sio_data->kind = nct6776;
2677 sio_name = sio_name_NCT6776;
2678 break;
657c93b1 2679 default:
9f66036b 2680 if (val != 0xffff)
abdc6fd1 2681 pr_debug("unsupported chip ID: 0x%04x\n", val);
1ea6dd38 2682 superio_exit(sioaddr);
08e7e278
JD		 2683 return -ENODEV;
2684 }
2685
1ea6dd38
DH		 2686 /* We have a known chip, find the HWM I/O address */
2687 superio_select(sioaddr, W83627EHF_LD_HWM);
2688 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2689 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 2690 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 2691 if (*addr == 0) {
abdc6fd1 2692 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
1ea6dd38 2693 superio_exit(sioaddr);
08e7e278
JD		 2694 return -ENODEV;
2695 }
2696
2697 /* Activate logical device if needed */
1ea6dd38 2698 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855 2699 if (!(val & 0x01)) {
e7e1ca6e
GR		 2700 pr_warn("Forcibly enabling Super-I/O. "
2701 "Sensor is probably unusable.\n");
1ea6dd38 2702 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 2703 }
1ea6dd38
DH		 2704
2705 superio_exit(sioaddr);
abdc6fd1 2706 pr_info("Found %s chip at %#x\n", sio_name, *addr);
1ea6dd38 2707 sio_data->sioreg = sioaddr;
08e7e278 2708
08e7e278
JD		 2709 return 0;
2710}
2711
8969e84d
GR		 2712/*
2713 * when Super-I/O functions move to a separate file, the Super-I/O
1ea6dd38
DH		 2714 * bus will manage the lifetime of the device and this module will only keep
2715 * track of the w83627ehf driver. But since we platform_device_alloc(), we
8969e84d
GR		 2716 * must keep track of the device
2717 */
1ea6dd38
DH		 2718static struct platform_device *pdev;
2719
08e7e278
JD		 2720static int __init sensors_w83627ehf_init(void)
2721{
1ea6dd38
DH		 2722 int err;
2723 unsigned short address;
2724 struct resource res;
2725 struct w83627ehf_sio_data sio_data;
2726
8969e84d
GR		 2727 /*
2728 * initialize sio_data->kind and sio_data->sioreg.
1ea6dd38
DH		 2729 *
2730 * when Super-I/O functions move to a separate file, the Super-I/O
2731 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
8969e84d
GR		 2732 * w83627ehf hardware monitor, and call probe()
2733 */
1ea6dd38
DH		 2734 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2735 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 2736 return -ENODEV;
2737
1ea6dd38
DH		 2738 err = platform_driver_register(&w83627ehf_driver);
2739 if (err)
2740 goto exit;
2741
e7e1ca6e
GR		 2742 pdev = platform_device_alloc(DRVNAME, address);
2743 if (!pdev) {
1ea6dd38 2744 err = -ENOMEM;
abdc6fd1 2745 pr_err("Device allocation failed\n");
1ea6dd38
DH		 2746 goto exit_unregister;
2747 }
2748
2749 err = platform_device_add_data(pdev, &sio_data,
2750 sizeof(struct w83627ehf_sio_data));
2751 if (err) {
abdc6fd1 2752 pr_err("Platform data allocation failed\n");
1ea6dd38
DH		 2753 goto exit_device_put;
2754 }
2755
2756 memset(&res, 0, sizeof(res));
2757 res.name = DRVNAME;
2758 res.start = address + IOREGION_OFFSET;
2759 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2760 res.flags = IORESOURCE_IO;
b9acb64a
JD		 2761
2762 err = acpi_check_resource_conflict(&res);
2763 if (err)
18632f84 2764 goto exit_device_put;
b9acb64a 2765
1ea6dd38
DH		 2766 err = platform_device_add_resources(pdev, &res, 1);
2767 if (err) {
abdc6fd1 2768 pr_err("Device resource addition failed (%d)\n", err);
1ea6dd38
DH		 2769 goto exit_device_put;
2770 }
2771
2772 /* platform_device_add calls probe() */
2773 err = platform_device_add(pdev);
2774 if (err) {
abdc6fd1 2775 pr_err("Device addition failed (%d)\n", err);
1ea6dd38
DH		 2776 goto exit_device_put;
2777 }
2778
2779 return 0;
2780
2781exit_device_put:
2782 platform_device_put(pdev);
2783exit_unregister:
2784 platform_driver_unregister(&w83627ehf_driver);
2785exit:
2786 return err;
08e7e278
JD		 2787}
2788
2789static void __exit sensors_w83627ehf_exit(void)
2790{
1ea6dd38
DH		 2791 platform_device_unregister(pdev);
2792 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 2793}
2794
2795MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2796MODULE_DESCRIPTION("W83627EHF driver");
2797MODULE_LICENSE("GPL");
2798
2799module_init(sensors_w83627ehf_init);
2800module_exit(sensors_w83627ehf_exit);
Linux 6.x block layer and io_uring tree(s)