Commit | Line | Data |
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08e7e278 JD |
1 | /* |
2 | w83627ehf - Driver for the hardware monitoring functionality of | |
e7e1ca6e | 3 | the Winbond W83627EHF Super-I/O chip |
08e7e278 | 4 | Copyright (C) 2005 Jean Delvare <khali@linux-fr.org> |
3379ceee | 5 | Copyright (C) 2006 Yuan Mu (Winbond), |
e7e1ca6e GR |
6 | Rudolf Marek <r.marek@assembler.cz> |
7 | David Hubbard <david.c.hubbard@gmail.com> | |
41e9a062 | 8 | Daniel J Blueman <daniel.blueman@gmail.com> |
ec3e5a16 | 9 | Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00) |
08e7e278 JD |
10 | |
11 | Shamelessly ripped from the w83627hf driver | |
12 | Copyright (C) 2003 Mark Studebaker | |
13 | ||
14 | Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help | |
15 | in testing and debugging this driver. | |
16 | ||
8dd2d2ca JD |
17 | This driver also supports the W83627EHG, which is the lead-free |
18 | version of the W83627EHF. | |
19 | ||
08e7e278 JD |
20 | This program is free software; you can redistribute it and/or modify |
21 | it under the terms of the GNU General Public License as published by | |
22 | the Free Software Foundation; either version 2 of the License, or | |
23 | (at your option) any later version. | |
24 | ||
25 | This program is distributed in the hope that it will be useful, | |
26 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | GNU General Public License for more details. | |
29 | ||
30 | You should have received a copy of the GNU General Public License | |
31 | along with this program; if not, write to the Free Software | |
32 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | ||
34 | ||
35 | Supports the following chips: | |
36 | ||
657c93b1 DH |
37 | Chip #vin #fan #pwm #temp chip IDs man ID |
38 | w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3 | |
e7e1ca6e | 39 | 0x8860 0xa1 |
657c93b1 | 40 | w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3 |
c1e48dce | 41 | w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3 |
237c8d2f | 42 | w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3 |
d36cf32c | 43 | w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3 |
ec3e5a16 GR |
44 | nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3 |
45 | nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3 | |
08e7e278 JD |
46 | */ |
47 | ||
abdc6fd1 JP |
48 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
49 | ||
08e7e278 JD |
50 | #include <linux/module.h> |
51 | #include <linux/init.h> | |
52 | #include <linux/slab.h> | |
1ea6dd38 DH |
53 | #include <linux/jiffies.h> |
54 | #include <linux/platform_device.h> | |
943b0830 | 55 | #include <linux/hwmon.h> |
412fec82 | 56 | #include <linux/hwmon-sysfs.h> |
fc18d6c0 | 57 | #include <linux/hwmon-vid.h> |
943b0830 | 58 | #include <linux/err.h> |
9a61bf63 | 59 | #include <linux/mutex.h> |
b9acb64a | 60 | #include <linux/acpi.h> |
6055fae8 | 61 | #include <linux/io.h> |
08e7e278 JD |
62 | #include "lm75.h" |
63 | ||
ec3e5a16 GR |
64 | enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg, w83667hg_b, nct6775, |
65 | nct6776 }; | |
08e7e278 | 66 | |
1ea6dd38 | 67 | /* used to set data->name = w83627ehf_device_names[data->sio_kind] */ |
e7e1ca6e | 68 | static const char * const w83627ehf_device_names[] = { |
1ea6dd38 DH |
69 | "w83627ehf", |
70 | "w83627dhg", | |
c1e48dce | 71 | "w83627dhg", |
237c8d2f | 72 | "w83667hg", |
c39aedaf | 73 | "w83667hg", |
ec3e5a16 GR |
74 | "nct6775", |
75 | "nct6776", | |
1ea6dd38 DH |
76 | }; |
77 | ||
67b671bc JD |
78 | static unsigned short force_id; |
79 | module_param(force_id, ushort, 0); | |
80 | MODULE_PARM_DESC(force_id, "Override the detected device ID"); | |
81 | ||
1ea6dd38 | 82 | #define DRVNAME "w83627ehf" |
08e7e278 | 83 | |
657c93b1 | 84 | /* |
1ea6dd38 | 85 | * Super-I/O constants and functions |
657c93b1 | 86 | */ |
08e7e278 JD |
87 | |
88 | #define W83627EHF_LD_HWM 0x0b | |
e7e1ca6e | 89 | #define W83667HG_LD_VID 0x0d |
08e7e278 JD |
90 | |
91 | #define SIO_REG_LDSEL 0x07 /* Logical device select */ | |
92 | #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */ | |
fc18d6c0 | 93 | #define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */ |
08e7e278 JD |
94 | #define SIO_REG_ENABLE 0x30 /* Logical device enable */ |
95 | #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */ | |
fc18d6c0 JD |
96 | #define SIO_REG_VID_CTRL 0xF0 /* VID control */ |
97 | #define SIO_REG_VID_DATA 0xF1 /* VID data */ | |
08e7e278 | 98 | |
657c93b1 DH |
99 | #define SIO_W83627EHF_ID 0x8850 |
100 | #define SIO_W83627EHG_ID 0x8860 | |
101 | #define SIO_W83627DHG_ID 0xa020 | |
c1e48dce | 102 | #define SIO_W83627DHG_P_ID 0xb070 |
e7e1ca6e | 103 | #define SIO_W83667HG_ID 0xa510 |
c39aedaf | 104 | #define SIO_W83667HG_B_ID 0xb350 |
ec3e5a16 GR |
105 | #define SIO_NCT6775_ID 0xb470 |
106 | #define SIO_NCT6776_ID 0xc330 | |
657c93b1 | 107 | #define SIO_ID_MASK 0xFFF0 |
08e7e278 JD |
108 | |
109 | static inline void | |
1ea6dd38 | 110 | superio_outb(int ioreg, int reg, int val) |
08e7e278 | 111 | { |
1ea6dd38 DH |
112 | outb(reg, ioreg); |
113 | outb(val, ioreg + 1); | |
08e7e278 JD |
114 | } |
115 | ||
116 | static inline int | |
1ea6dd38 | 117 | superio_inb(int ioreg, int reg) |
08e7e278 | 118 | { |
1ea6dd38 DH |
119 | outb(reg, ioreg); |
120 | return inb(ioreg + 1); | |
08e7e278 JD |
121 | } |
122 | ||
123 | static inline void | |
1ea6dd38 | 124 | superio_select(int ioreg, int ld) |
08e7e278 | 125 | { |
1ea6dd38 DH |
126 | outb(SIO_REG_LDSEL, ioreg); |
127 | outb(ld, ioreg + 1); | |
08e7e278 JD |
128 | } |
129 | ||
130 | static inline void | |
1ea6dd38 | 131 | superio_enter(int ioreg) |
08e7e278 | 132 | { |
1ea6dd38 DH |
133 | outb(0x87, ioreg); |
134 | outb(0x87, ioreg); | |
08e7e278 JD |
135 | } |
136 | ||
137 | static inline void | |
1ea6dd38 | 138 | superio_exit(int ioreg) |
08e7e278 | 139 | { |
022b75a3 | 140 | outb(0xaa, ioreg); |
1ea6dd38 DH |
141 | outb(0x02, ioreg); |
142 | outb(0x02, ioreg + 1); | |
08e7e278 JD |
143 | } |
144 | ||
145 | /* | |
146 | * ISA constants | |
147 | */ | |
148 | ||
e7e1ca6e | 149 | #define IOREGION_ALIGNMENT (~7) |
1a641fce JD |
150 | #define IOREGION_OFFSET 5 |
151 | #define IOREGION_LENGTH 2 | |
1ea6dd38 DH |
152 | #define ADDR_REG_OFFSET 0 |
153 | #define DATA_REG_OFFSET 1 | |
08e7e278 JD |
154 | |
155 | #define W83627EHF_REG_BANK 0x4E | |
156 | #define W83627EHF_REG_CONFIG 0x40 | |
657c93b1 DH |
157 | |
158 | /* Not currently used: | |
159 | * REG_MAN_ID has the value 0x5ca3 for all supported chips. | |
160 | * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model. | |
161 | * REG_MAN_ID is at port 0x4f | |
162 | * REG_CHIP_ID is at port 0x58 */ | |
08e7e278 JD |
163 | |
164 | static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 }; | |
165 | static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c }; | |
166 | ||
cf0676fe RM |
167 | /* The W83627EHF registers for nr=7,8,9 are in bank 5 */ |
168 | #define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \ | |
169 | (0x554 + (((nr) - 7) * 2))) | |
170 | #define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \ | |
171 | (0x555 + (((nr) - 7) * 2))) | |
172 | #define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \ | |
173 | (0x550 + (nr) - 7)) | |
174 | ||
d36cf32c GR |
175 | static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e }; |
176 | static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 }; | |
177 | static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 }; | |
178 | static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 }; | |
08e7e278 JD |
179 | |
180 | /* Fan clock dividers are spread over the following five registers */ | |
181 | #define W83627EHF_REG_FANDIV1 0x47 | |
182 | #define W83627EHF_REG_FANDIV2 0x4B | |
183 | #define W83627EHF_REG_VBAT 0x5D | |
184 | #define W83627EHF_REG_DIODE 0x59 | |
185 | #define W83627EHF_REG_SMI_OVT 0x4C | |
186 | ||
ec3e5a16 GR |
187 | /* NCT6775F has its own fan divider registers */ |
188 | #define NCT6775_REG_FANDIV1 0x506 | |
189 | #define NCT6775_REG_FANDIV2 0x507 | |
190 | ||
a4589dbb JD |
191 | #define W83627EHF_REG_ALARM1 0x459 |
192 | #define W83627EHF_REG_ALARM2 0x45A | |
193 | #define W83627EHF_REG_ALARM3 0x45B | |
194 | ||
08c79950 | 195 | /* SmartFan registers */ |
41e9a062 DB |
196 | #define W83627EHF_REG_FAN_STEPUP_TIME 0x0f |
197 | #define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e | |
198 | ||
08c79950 RM |
199 | /* DC or PWM output fan configuration */ |
200 | static const u8 W83627EHF_REG_PWM_ENABLE[] = { | |
201 | 0x04, /* SYS FAN0 output mode and PWM mode */ | |
202 | 0x04, /* CPU FAN0 output mode and PWM mode */ | |
203 | 0x12, /* AUX FAN mode */ | |
41e9a062 | 204 | 0x62, /* CPU FAN1 mode */ |
08c79950 RM |
205 | }; |
206 | ||
207 | static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 }; | |
208 | static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 }; | |
209 | ||
210 | /* FAN Duty Cycle, be used to control */ | |
279af1a9 GR |
211 | static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 }; |
212 | static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 }; | |
08c79950 RM |
213 | static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 }; |
214 | ||
08c79950 | 215 | /* Advanced Fan control, some values are common for all fans */ |
279af1a9 GR |
216 | static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 }; |
217 | static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 }; | |
218 | static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 }; | |
c39aedaf | 219 | |
279af1a9 | 220 | static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[] |
c39aedaf | 221 | = { 0xff, 0x67, 0xff, 0x69 }; |
279af1a9 | 222 | static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[] |
c39aedaf GR |
223 | = { 0xff, 0x68, 0xff, 0x6a }; |
224 | ||
279af1a9 GR |
225 | static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b }; |
226 | static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[] | |
227 | = { 0x68, 0x6a, 0x6c }; | |
08c79950 | 228 | |
ec3e5a16 GR |
229 | static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 }; |
230 | static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 }; | |
231 | static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 }; | |
232 | static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 }; | |
233 | static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 }; | |
234 | static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 }; | |
235 | static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a }; | |
236 | static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b }; | |
26bc440e | 237 | static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 }; |
ec3e5a16 GR |
238 | static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642}; |
239 | ||
240 | static const u16 NCT6775_REG_TEMP[] | |
241 | = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d }; | |
242 | static const u16 NCT6775_REG_TEMP_CONFIG[] | |
243 | = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A }; | |
244 | static const u16 NCT6775_REG_TEMP_HYST[] | |
245 | = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D }; | |
246 | static const u16 NCT6775_REG_TEMP_OVER[] | |
247 | = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C }; | |
248 | static const u16 NCT6775_REG_TEMP_SOURCE[] | |
249 | = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 }; | |
250 | ||
d36cf32c GR |
251 | static const char *const w83667hg_b_temp_label[] = { |
252 | "SYSTIN", | |
253 | "CPUTIN", | |
254 | "AUXTIN", | |
255 | "AMDTSI", | |
256 | "PECI Agent 1", | |
257 | "PECI Agent 2", | |
258 | "PECI Agent 3", | |
259 | "PECI Agent 4" | |
260 | }; | |
261 | ||
ec3e5a16 GR |
262 | static const char *const nct6775_temp_label[] = { |
263 | "", | |
264 | "SYSTIN", | |
265 | "CPUTIN", | |
266 | "AUXTIN", | |
267 | "AMD SB-TSI", | |
268 | "PECI Agent 0", | |
269 | "PECI Agent 1", | |
270 | "PECI Agent 2", | |
271 | "PECI Agent 3", | |
272 | "PECI Agent 4", | |
273 | "PECI Agent 5", | |
274 | "PECI Agent 6", | |
275 | "PECI Agent 7", | |
276 | "PCH_CHIP_CPU_MAX_TEMP", | |
277 | "PCH_CHIP_TEMP", | |
278 | "PCH_CPU_TEMP", | |
279 | "PCH_MCH_TEMP", | |
280 | "PCH_DIM0_TEMP", | |
281 | "PCH_DIM1_TEMP", | |
282 | "PCH_DIM2_TEMP", | |
283 | "PCH_DIM3_TEMP" | |
284 | }; | |
285 | ||
286 | static const char *const nct6776_temp_label[] = { | |
287 | "", | |
288 | "SYSTIN", | |
289 | "CPUTIN", | |
290 | "AUXTIN", | |
291 | "SMBUSMASTER 0", | |
292 | "SMBUSMASTER 1", | |
293 | "SMBUSMASTER 2", | |
294 | "SMBUSMASTER 3", | |
295 | "SMBUSMASTER 4", | |
296 | "SMBUSMASTER 5", | |
297 | "SMBUSMASTER 6", | |
298 | "SMBUSMASTER 7", | |
299 | "PECI Agent 0", | |
300 | "PECI Agent 1", | |
301 | "PCH_CHIP_CPU_MAX_TEMP", | |
302 | "PCH_CHIP_TEMP", | |
303 | "PCH_CPU_TEMP", | |
304 | "PCH_MCH_TEMP", | |
305 | "PCH_DIM0_TEMP", | |
306 | "PCH_DIM1_TEMP", | |
307 | "PCH_DIM2_TEMP", | |
308 | "PCH_DIM3_TEMP", | |
309 | "BYTE_TEMP" | |
310 | }; | |
311 | ||
312 | #define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP) | |
d36cf32c | 313 | |
bce26c58 GR |
314 | static inline int is_word_sized(u16 reg) |
315 | { | |
ec3e5a16 | 316 | return ((((reg & 0xff00) == 0x100 |
bce26c58 GR |
317 | || (reg & 0xff00) == 0x200) |
318 | && ((reg & 0x00ff) == 0x50 | |
319 | || (reg & 0x00ff) == 0x53 | |
ec3e5a16 GR |
320 | || (reg & 0x00ff) == 0x55)) |
321 | || (reg & 0xfff0) == 0x630 | |
322 | || reg == 0x640 || reg == 0x642 | |
323 | || ((reg & 0xfff0) == 0x650 | |
324 | && (reg & 0x000f) >= 0x06) | |
325 | || reg == 0x73 || reg == 0x75 || reg == 0x77 | |
326 | ); | |
bce26c58 GR |
327 | } |
328 | ||
08e7e278 JD |
329 | /* |
330 | * Conversions | |
331 | */ | |
332 | ||
08c79950 RM |
333 | /* 1 is PWM mode, output in ms */ |
334 | static inline unsigned int step_time_from_reg(u8 reg, u8 mode) | |
335 | { | |
336 | return mode ? 100 * reg : 400 * reg; | |
337 | } | |
338 | ||
339 | static inline u8 step_time_to_reg(unsigned int msec, u8 mode) | |
340 | { | |
341 | return SENSORS_LIMIT((mode ? (msec + 50) / 100 : | |
342 | (msec + 200) / 400), 1, 255); | |
343 | } | |
344 | ||
26bc440e | 345 | static unsigned int fan_from_reg8(u16 reg, unsigned int divreg) |
08e7e278 | 346 | { |
26bc440e | 347 | if (reg == 0 || reg == 255) |
08e7e278 | 348 | return 0; |
26bc440e GR |
349 | return 1350000U / (reg << divreg); |
350 | } | |
351 | ||
352 | static unsigned int fan_from_reg13(u16 reg, unsigned int divreg) | |
353 | { | |
354 | if ((reg & 0xff1f) == 0xff1f) | |
355 | return 0; | |
356 | ||
357 | reg = (reg & 0x1f) | ((reg & 0xff00) >> 3); | |
358 | ||
359 | if (reg == 0) | |
360 | return 0; | |
361 | ||
362 | return 1350000U / reg; | |
363 | } | |
364 | ||
365 | static unsigned int fan_from_reg16(u16 reg, unsigned int divreg) | |
366 | { | |
367 | if (reg == 0 || reg == 0xffff) | |
368 | return 0; | |
369 | ||
370 | /* | |
371 | * Even though the registers are 16 bit wide, the fan divisor | |
372 | * still applies. | |
373 | */ | |
374 | return 1350000U / (reg << divreg); | |
08e7e278 JD |
375 | } |
376 | ||
377 | static inline unsigned int | |
378 | div_from_reg(u8 reg) | |
379 | { | |
380 | return 1 << reg; | |
381 | } | |
382 | ||
383 | static inline int | |
bce26c58 | 384 | temp_from_reg(u16 reg, s16 regval) |
08e7e278 | 385 | { |
bce26c58 GR |
386 | if (is_word_sized(reg)) |
387 | return LM75_TEMP_FROM_REG(regval); | |
388 | return regval * 1000; | |
08e7e278 JD |
389 | } |
390 | ||
ec3e5a16 | 391 | static inline u16 |
bce26c58 | 392 | temp_to_reg(u16 reg, long temp) |
08e7e278 | 393 | { |
bce26c58 GR |
394 | if (is_word_sized(reg)) |
395 | return LM75_TEMP_TO_REG(temp); | |
396 | return DIV_ROUND_CLOSEST(SENSORS_LIMIT(temp, -127000, 128000), 1000); | |
08e7e278 JD |
397 | } |
398 | ||
cf0676fe RM |
399 | /* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */ |
400 | ||
401 | static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 }; | |
402 | ||
403 | static inline long in_from_reg(u8 reg, u8 nr) | |
404 | { | |
405 | return reg * scale_in[nr]; | |
406 | } | |
407 | ||
408 | static inline u8 in_to_reg(u32 val, u8 nr) | |
409 | { | |
e7e1ca6e GR |
410 | return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0, |
411 | 255); | |
cf0676fe RM |
412 | } |
413 | ||
08e7e278 JD |
414 | /* |
415 | * Data structures and manipulation thereof | |
416 | */ | |
417 | ||
418 | struct w83627ehf_data { | |
1ea6dd38 DH |
419 | int addr; /* IO base of hw monitor block */ |
420 | const char *name; | |
421 | ||
1beeffe4 | 422 | struct device *hwmon_dev; |
9a61bf63 | 423 | struct mutex lock; |
08e7e278 | 424 | |
ec3e5a16 GR |
425 | u16 reg_temp[NUM_REG_TEMP]; |
426 | u16 reg_temp_over[NUM_REG_TEMP]; | |
427 | u16 reg_temp_hyst[NUM_REG_TEMP]; | |
428 | u16 reg_temp_config[NUM_REG_TEMP]; | |
d36cf32c GR |
429 | u8 temp_src[NUM_REG_TEMP]; |
430 | const char * const *temp_label; | |
431 | ||
279af1a9 GR |
432 | const u16 *REG_PWM; |
433 | const u16 *REG_TARGET; | |
434 | const u16 *REG_FAN; | |
435 | const u16 *REG_FAN_MIN; | |
436 | const u16 *REG_FAN_START_OUTPUT; | |
437 | const u16 *REG_FAN_STOP_OUTPUT; | |
438 | const u16 *REG_FAN_STOP_TIME; | |
439 | const u16 *REG_FAN_MAX_OUTPUT; | |
440 | const u16 *REG_FAN_STEP_OUTPUT; | |
da2e0255 | 441 | |
26bc440e GR |
442 | unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg); |
443 | unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg); | |
444 | ||
9a61bf63 | 445 | struct mutex update_lock; |
08e7e278 JD |
446 | char valid; /* !=0 if following fields are valid */ |
447 | unsigned long last_updated; /* In jiffies */ | |
448 | ||
449 | /* Register values */ | |
83cc8985 | 450 | u8 bank; /* current register bank */ |
1ea6dd38 | 451 | u8 in_num; /* number of in inputs we have */ |
cf0676fe RM |
452 | u8 in[10]; /* Register value */ |
453 | u8 in_max[10]; /* Register value */ | |
454 | u8 in_min[10]; /* Register value */ | |
ec3e5a16 GR |
455 | u16 fan[5]; |
456 | u16 fan_min[5]; | |
08e7e278 JD |
457 | u8 fan_div[5]; |
458 | u8 has_fan; /* some fan inputs can be disabled */ | |
ec3e5a16 | 459 | u8 has_fan_min; /* some fans don't have min register */ |
26bc440e | 460 | bool has_fan_div; |
da667365 | 461 | u8 temp_type[3]; |
ec3e5a16 GR |
462 | s16 temp[9]; |
463 | s16 temp_max[9]; | |
464 | s16 temp_max_hyst[9]; | |
a4589dbb | 465 | u32 alarms; |
08c79950 RM |
466 | |
467 | u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */ | |
468 | u8 pwm_enable[4]; /* 1->manual | |
41e9a062 DB |
469 | 2->thermal cruise mode (also called SmartFan I) |
470 | 3->fan speed cruise mode | |
e7e1ca6e | 471 | 4->variable thermal cruise (also called |
b84bb518 GR |
472 | SmartFan III) |
473 | 5->enhanced variable thermal cruise (also called | |
474 | SmartFan IV) */ | |
475 | u8 pwm_enable_orig[4]; /* original value of pwm_enable */ | |
237c8d2f | 476 | u8 pwm_num; /* number of pwm */ |
08c79950 RM |
477 | u8 pwm[4]; |
478 | u8 target_temp[4]; | |
479 | u8 tolerance[4]; | |
480 | ||
41e9a062 DB |
481 | u8 fan_start_output[4]; /* minimum fan speed when spinning up */ |
482 | u8 fan_stop_output[4]; /* minimum fan speed when spinning down */ | |
483 | u8 fan_stop_time[4]; /* time at minimum before disabling fan */ | |
484 | u8 fan_max_output[4]; /* maximum fan speed */ | |
485 | u8 fan_step_output[4]; /* rate of change output value */ | |
fc18d6c0 JD |
486 | |
487 | u8 vid; | |
488 | u8 vrm; | |
a157d06d | 489 | |
ec3e5a16 | 490 | u16 have_temp; |
a157d06d | 491 | u8 in6_skip; |
08e7e278 JD |
492 | }; |
493 | ||
1ea6dd38 DH |
494 | struct w83627ehf_sio_data { |
495 | int sioreg; | |
496 | enum kinds kind; | |
497 | }; | |
498 | ||
83cc8985 GR |
499 | /* |
500 | * On older chips, only registers 0x50-0x5f are banked. | |
501 | * On more recent chips, all registers are banked. | |
502 | * Assume that is the case and set the bank number for each access. | |
503 | * Cache the bank number so it only needs to be set if it changes. | |
504 | */ | |
1ea6dd38 | 505 | static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg) |
08e7e278 | 506 | { |
83cc8985 GR |
507 | u8 bank = reg >> 8; |
508 | if (data->bank != bank) { | |
1ea6dd38 | 509 | outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET); |
83cc8985 GR |
510 | outb_p(bank, data->addr + DATA_REG_OFFSET); |
511 | data->bank = bank; | |
08e7e278 JD |
512 | } |
513 | } | |
514 | ||
1ea6dd38 | 515 | static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg) |
08e7e278 | 516 | { |
08e7e278 JD |
517 | int res, word_sized = is_word_sized(reg); |
518 | ||
9a61bf63 | 519 | mutex_lock(&data->lock); |
08e7e278 | 520 | |
1ea6dd38 DH |
521 | w83627ehf_set_bank(data, reg); |
522 | outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); | |
523 | res = inb_p(data->addr + DATA_REG_OFFSET); | |
08e7e278 JD |
524 | if (word_sized) { |
525 | outb_p((reg & 0xff) + 1, | |
1ea6dd38 DH |
526 | data->addr + ADDR_REG_OFFSET); |
527 | res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET); | |
08e7e278 | 528 | } |
08e7e278 | 529 | |
9a61bf63 | 530 | mutex_unlock(&data->lock); |
08e7e278 JD |
531 | return res; |
532 | } | |
533 | ||
e7e1ca6e GR |
534 | static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, |
535 | u16 value) | |
08e7e278 | 536 | { |
08e7e278 JD |
537 | int word_sized = is_word_sized(reg); |
538 | ||
9a61bf63 | 539 | mutex_lock(&data->lock); |
08e7e278 | 540 | |
1ea6dd38 DH |
541 | w83627ehf_set_bank(data, reg); |
542 | outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); | |
08e7e278 | 543 | if (word_sized) { |
1ea6dd38 | 544 | outb_p(value >> 8, data->addr + DATA_REG_OFFSET); |
08e7e278 | 545 | outb_p((reg & 0xff) + 1, |
1ea6dd38 | 546 | data->addr + ADDR_REG_OFFSET); |
08e7e278 | 547 | } |
1ea6dd38 | 548 | outb_p(value & 0xff, data->addr + DATA_REG_OFFSET); |
08e7e278 | 549 | |
9a61bf63 | 550 | mutex_unlock(&data->lock); |
08e7e278 JD |
551 | return 0; |
552 | } | |
553 | ||
ec3e5a16 GR |
554 | /* This function assumes that the caller holds data->update_lock */ |
555 | static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr) | |
556 | { | |
557 | u8 reg; | |
558 | ||
559 | switch (nr) { | |
560 | case 0: | |
561 | reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70) | |
562 | | (data->fan_div[0] & 0x7); | |
563 | w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg); | |
564 | break; | |
565 | case 1: | |
566 | reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7) | |
567 | | ((data->fan_div[1] << 4) & 0x70); | |
568 | w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg); | |
569 | case 2: | |
570 | reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70) | |
571 | | (data->fan_div[2] & 0x7); | |
572 | w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg); | |
573 | break; | |
574 | case 3: | |
575 | reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7) | |
576 | | ((data->fan_div[3] << 4) & 0x70); | |
577 | w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg); | |
578 | break; | |
579 | } | |
580 | } | |
581 | ||
08e7e278 | 582 | /* This function assumes that the caller holds data->update_lock */ |
1ea6dd38 | 583 | static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr) |
08e7e278 | 584 | { |
08e7e278 JD |
585 | u8 reg; |
586 | ||
587 | switch (nr) { | |
588 | case 0: | |
1ea6dd38 | 589 | reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf) |
08e7e278 | 590 | | ((data->fan_div[0] & 0x03) << 4); |
14992c7e RM |
591 | /* fan5 input control bit is write only, compute the value */ |
592 | reg |= (data->has_fan & (1 << 4)) ? 1 : 0; | |
1ea6dd38 DH |
593 | w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg); |
594 | reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf) | |
08e7e278 | 595 | | ((data->fan_div[0] & 0x04) << 3); |
1ea6dd38 | 596 | w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg); |
08e7e278 JD |
597 | break; |
598 | case 1: | |
1ea6dd38 | 599 | reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f) |
08e7e278 | 600 | | ((data->fan_div[1] & 0x03) << 6); |
14992c7e RM |
601 | /* fan5 input control bit is write only, compute the value */ |
602 | reg |= (data->has_fan & (1 << 4)) ? 1 : 0; | |
1ea6dd38 DH |
603 | w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg); |
604 | reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf) | |
08e7e278 | 605 | | ((data->fan_div[1] & 0x04) << 4); |
1ea6dd38 | 606 | w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg); |
08e7e278 JD |
607 | break; |
608 | case 2: | |
1ea6dd38 | 609 | reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f) |
08e7e278 | 610 | | ((data->fan_div[2] & 0x03) << 6); |
1ea6dd38 DH |
611 | w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg); |
612 | reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f) | |
08e7e278 | 613 | | ((data->fan_div[2] & 0x04) << 5); |
1ea6dd38 | 614 | w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg); |
08e7e278 JD |
615 | break; |
616 | case 3: | |
1ea6dd38 | 617 | reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc) |
08e7e278 | 618 | | (data->fan_div[3] & 0x03); |
1ea6dd38 DH |
619 | w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg); |
620 | reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f) | |
08e7e278 | 621 | | ((data->fan_div[3] & 0x04) << 5); |
1ea6dd38 | 622 | w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg); |
08e7e278 JD |
623 | break; |
624 | case 4: | |
1ea6dd38 | 625 | reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73) |
33725ad3 | 626 | | ((data->fan_div[4] & 0x03) << 2) |
08e7e278 | 627 | | ((data->fan_div[4] & 0x04) << 5); |
1ea6dd38 | 628 | w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg); |
08e7e278 JD |
629 | break; |
630 | } | |
631 | } | |
632 | ||
ec3e5a16 GR |
633 | static void w83627ehf_write_fan_div_common(struct device *dev, |
634 | struct w83627ehf_data *data, int nr) | |
635 | { | |
636 | struct w83627ehf_sio_data *sio_data = dev->platform_data; | |
637 | ||
638 | if (sio_data->kind == nct6776) | |
639 | ; /* no dividers, do nothing */ | |
640 | else if (sio_data->kind == nct6775) | |
641 | nct6775_write_fan_div(data, nr); | |
642 | else | |
643 | w83627ehf_write_fan_div(data, nr); | |
644 | } | |
645 | ||
646 | static void nct6775_update_fan_div(struct w83627ehf_data *data) | |
647 | { | |
648 | u8 i; | |
649 | ||
650 | i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1); | |
651 | data->fan_div[0] = i & 0x7; | |
652 | data->fan_div[1] = (i & 0x70) >> 4; | |
653 | i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2); | |
654 | data->fan_div[2] = i & 0x7; | |
655 | if (data->has_fan & (1<<3)) | |
656 | data->fan_div[3] = (i & 0x70) >> 4; | |
657 | } | |
658 | ||
ea7be66c MH |
659 | static void w83627ehf_update_fan_div(struct w83627ehf_data *data) |
660 | { | |
661 | int i; | |
662 | ||
663 | i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1); | |
664 | data->fan_div[0] = (i >> 4) & 0x03; | |
665 | data->fan_div[1] = (i >> 6) & 0x03; | |
666 | i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2); | |
667 | data->fan_div[2] = (i >> 6) & 0x03; | |
668 | i = w83627ehf_read_value(data, W83627EHF_REG_VBAT); | |
669 | data->fan_div[0] |= (i >> 3) & 0x04; | |
670 | data->fan_div[1] |= (i >> 4) & 0x04; | |
671 | data->fan_div[2] |= (i >> 5) & 0x04; | |
672 | if (data->has_fan & ((1 << 3) | (1 << 4))) { | |
673 | i = w83627ehf_read_value(data, W83627EHF_REG_DIODE); | |
674 | data->fan_div[3] = i & 0x03; | |
675 | data->fan_div[4] = ((i >> 2) & 0x03) | |
676 | | ((i >> 5) & 0x04); | |
677 | } | |
678 | if (data->has_fan & (1 << 3)) { | |
679 | i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT); | |
680 | data->fan_div[3] |= (i >> 5) & 0x04; | |
681 | } | |
682 | } | |
683 | ||
ec3e5a16 GR |
684 | static void w83627ehf_update_fan_div_common(struct device *dev, |
685 | struct w83627ehf_data *data) | |
686 | { | |
687 | struct w83627ehf_sio_data *sio_data = dev->platform_data; | |
688 | ||
689 | if (sio_data->kind == nct6776) | |
690 | ; /* no dividers, do nothing */ | |
691 | else if (sio_data->kind == nct6775) | |
692 | nct6775_update_fan_div(data); | |
693 | else | |
694 | w83627ehf_update_fan_div(data); | |
695 | } | |
696 | ||
697 | static void nct6775_update_pwm(struct w83627ehf_data *data) | |
698 | { | |
699 | int i; | |
700 | int pwmcfg, fanmodecfg; | |
701 | ||
702 | for (i = 0; i < data->pwm_num; i++) { | |
703 | pwmcfg = w83627ehf_read_value(data, | |
704 | W83627EHF_REG_PWM_ENABLE[i]); | |
705 | fanmodecfg = w83627ehf_read_value(data, | |
706 | NCT6775_REG_FAN_MODE[i]); | |
707 | data->pwm_mode[i] = | |
708 | ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1; | |
709 | data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1; | |
710 | data->tolerance[i] = fanmodecfg & 0x0f; | |
711 | data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]); | |
712 | } | |
713 | } | |
714 | ||
715 | static void w83627ehf_update_pwm(struct w83627ehf_data *data) | |
716 | { | |
717 | int i; | |
718 | int pwmcfg = 0, tolerance = 0; /* shut up the compiler */ | |
719 | ||
720 | for (i = 0; i < data->pwm_num; i++) { | |
721 | if (!(data->has_fan & (1 << i))) | |
722 | continue; | |
723 | ||
724 | /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */ | |
725 | if (i != 1) { | |
726 | pwmcfg = w83627ehf_read_value(data, | |
727 | W83627EHF_REG_PWM_ENABLE[i]); | |
728 | tolerance = w83627ehf_read_value(data, | |
729 | W83627EHF_REG_TOLERANCE[i]); | |
730 | } | |
731 | data->pwm_mode[i] = | |
732 | ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1; | |
733 | data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i]) | |
734 | & 3) + 1; | |
735 | data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]); | |
736 | ||
737 | data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f; | |
738 | } | |
739 | } | |
740 | ||
741 | static void w83627ehf_update_pwm_common(struct device *dev, | |
742 | struct w83627ehf_data *data) | |
743 | { | |
744 | struct w83627ehf_sio_data *sio_data = dev->platform_data; | |
745 | ||
746 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) | |
747 | nct6775_update_pwm(data); | |
748 | else | |
749 | w83627ehf_update_pwm(data); | |
750 | } | |
751 | ||
08e7e278 JD |
752 | static struct w83627ehf_data *w83627ehf_update_device(struct device *dev) |
753 | { | |
1ea6dd38 | 754 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
ec3e5a16 GR |
755 | struct w83627ehf_sio_data *sio_data = dev->platform_data; |
756 | ||
08e7e278 JD |
757 | int i; |
758 | ||
9a61bf63 | 759 | mutex_lock(&data->update_lock); |
08e7e278 | 760 | |
6b3e4645 | 761 | if (time_after(jiffies, data->last_updated + HZ + HZ/2) |
08e7e278 JD |
762 | || !data->valid) { |
763 | /* Fan clock dividers */ | |
ec3e5a16 | 764 | w83627ehf_update_fan_div_common(dev, data); |
08e7e278 | 765 | |
cf0676fe | 766 | /* Measured voltages and limits */ |
1ea6dd38 DH |
767 | for (i = 0; i < data->in_num; i++) { |
768 | data->in[i] = w83627ehf_read_value(data, | |
cf0676fe | 769 | W83627EHF_REG_IN(i)); |
1ea6dd38 | 770 | data->in_min[i] = w83627ehf_read_value(data, |
cf0676fe | 771 | W83627EHF_REG_IN_MIN(i)); |
1ea6dd38 | 772 | data->in_max[i] = w83627ehf_read_value(data, |
cf0676fe RM |
773 | W83627EHF_REG_IN_MAX(i)); |
774 | } | |
775 | ||
08e7e278 JD |
776 | /* Measured fan speeds and limits */ |
777 | for (i = 0; i < 5; i++) { | |
778 | if (!(data->has_fan & (1 << i))) | |
779 | continue; | |
780 | ||
1ea6dd38 | 781 | data->fan[i] = w83627ehf_read_value(data, |
ec3e5a16 GR |
782 | data->REG_FAN[i]); |
783 | ||
784 | if (data->has_fan_min & (1 << i)) | |
785 | data->fan_min[i] = w83627ehf_read_value(data, | |
279af1a9 | 786 | data->REG_FAN_MIN[i]); |
08e7e278 JD |
787 | |
788 | /* If we failed to measure the fan speed and clock | |
789 | divider can be increased, let's try that for next | |
790 | time */ | |
26bc440e GR |
791 | if (data->has_fan_div |
792 | && (data->fan[i] >= 0xff | |
ec3e5a16 GR |
793 | || (sio_data->kind == nct6775 |
794 | && data->fan[i] == 0x00)) | |
795 | && data->fan_div[i] < 0x07) { | |
e7e1ca6e | 796 | dev_dbg(dev, "Increasing fan%d " |
08e7e278 | 797 | "clock divider from %u to %u\n", |
33725ad3 | 798 | i + 1, div_from_reg(data->fan_div[i]), |
08e7e278 JD |
799 | div_from_reg(data->fan_div[i] + 1)); |
800 | data->fan_div[i]++; | |
ec3e5a16 | 801 | w83627ehf_write_fan_div_common(dev, data, i); |
08e7e278 | 802 | /* Preserve min limit if possible */ |
ec3e5a16 GR |
803 | if ((data->has_fan_min & (1 << i)) |
804 | && data->fan_min[i] >= 2 | |
08e7e278 | 805 | && data->fan_min[i] != 255) |
1ea6dd38 | 806 | w83627ehf_write_value(data, |
279af1a9 | 807 | data->REG_FAN_MIN[i], |
08e7e278 JD |
808 | (data->fan_min[i] /= 2)); |
809 | } | |
810 | } | |
811 | ||
ec3e5a16 GR |
812 | w83627ehf_update_pwm_common(dev, data); |
813 | ||
da2e0255 GR |
814 | for (i = 0; i < data->pwm_num; i++) { |
815 | if (!(data->has_fan & (1 << i))) | |
816 | continue; | |
817 | ||
ec3e5a16 GR |
818 | data->fan_start_output[i] = |
819 | w83627ehf_read_value(data, | |
820 | data->REG_FAN_START_OUTPUT[i]); | |
821 | data->fan_stop_output[i] = | |
822 | w83627ehf_read_value(data, | |
823 | data->REG_FAN_STOP_OUTPUT[i]); | |
824 | data->fan_stop_time[i] = | |
825 | w83627ehf_read_value(data, | |
826 | data->REG_FAN_STOP_TIME[i]); | |
827 | ||
828 | if (data->REG_FAN_MAX_OUTPUT && | |
829 | data->REG_FAN_MAX_OUTPUT[i] != 0xff) | |
da2e0255 GR |
830 | data->fan_max_output[i] = |
831 | w83627ehf_read_value(data, | |
ec3e5a16 | 832 | data->REG_FAN_MAX_OUTPUT[i]); |
da2e0255 | 833 | |
ec3e5a16 GR |
834 | if (data->REG_FAN_STEP_OUTPUT && |
835 | data->REG_FAN_STEP_OUTPUT[i] != 0xff) | |
da2e0255 GR |
836 | data->fan_step_output[i] = |
837 | w83627ehf_read_value(data, | |
ec3e5a16 | 838 | data->REG_FAN_STEP_OUTPUT[i]); |
da2e0255 | 839 | |
08c79950 | 840 | data->target_temp[i] = |
1ea6dd38 | 841 | w83627ehf_read_value(data, |
279af1a9 | 842 | data->REG_TARGET[i]) & |
08c79950 | 843 | (data->pwm_mode[i] == 1 ? 0x7f : 0xff); |
08c79950 RM |
844 | } |
845 | ||
08e7e278 | 846 | /* Measured temperatures and limits */ |
d36cf32c GR |
847 | for (i = 0; i < NUM_REG_TEMP; i++) { |
848 | if (!(data->have_temp & (1 << i))) | |
849 | continue; | |
ec3e5a16 GR |
850 | data->temp[i] = w83627ehf_read_value(data, |
851 | data->reg_temp[i]); | |
852 | if (data->reg_temp_over[i]) | |
853 | data->temp_max[i] | |
854 | = w83627ehf_read_value(data, | |
855 | data->reg_temp_over[i]); | |
856 | if (data->reg_temp_hyst[i]) | |
857 | data->temp_max_hyst[i] | |
858 | = w83627ehf_read_value(data, | |
859 | data->reg_temp_hyst[i]); | |
08e7e278 JD |
860 | } |
861 | ||
1ea6dd38 | 862 | data->alarms = w83627ehf_read_value(data, |
a4589dbb | 863 | W83627EHF_REG_ALARM1) | |
1ea6dd38 | 864 | (w83627ehf_read_value(data, |
a4589dbb | 865 | W83627EHF_REG_ALARM2) << 8) | |
1ea6dd38 | 866 | (w83627ehf_read_value(data, |
a4589dbb JD |
867 | W83627EHF_REG_ALARM3) << 16); |
868 | ||
08e7e278 JD |
869 | data->last_updated = jiffies; |
870 | data->valid = 1; | |
871 | } | |
872 | ||
9a61bf63 | 873 | mutex_unlock(&data->update_lock); |
08e7e278 JD |
874 | return data; |
875 | } | |
876 | ||
877 | /* | |
878 | * Sysfs callback functions | |
879 | */ | |
cf0676fe RM |
880 | #define show_in_reg(reg) \ |
881 | static ssize_t \ | |
882 | show_##reg(struct device *dev, struct device_attribute *attr, \ | |
883 | char *buf) \ | |
884 | { \ | |
885 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
886 | struct sensor_device_attribute *sensor_attr = \ |
887 | to_sensor_dev_attr(attr); \ | |
cf0676fe RM |
888 | int nr = sensor_attr->index; \ |
889 | return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \ | |
890 | } | |
891 | show_in_reg(in) | |
892 | show_in_reg(in_min) | |
893 | show_in_reg(in_max) | |
894 | ||
895 | #define store_in_reg(REG, reg) \ | |
896 | static ssize_t \ | |
e7e1ca6e GR |
897 | store_in_##reg(struct device *dev, struct device_attribute *attr, \ |
898 | const char *buf, size_t count) \ | |
cf0676fe | 899 | { \ |
1ea6dd38 | 900 | struct w83627ehf_data *data = dev_get_drvdata(dev); \ |
e7e1ca6e GR |
901 | struct sensor_device_attribute *sensor_attr = \ |
902 | to_sensor_dev_attr(attr); \ | |
cf0676fe | 903 | int nr = sensor_attr->index; \ |
bce26c58 GR |
904 | unsigned long val; \ |
905 | int err; \ | |
906 | err = strict_strtoul(buf, 10, &val); \ | |
907 | if (err < 0) \ | |
908 | return err; \ | |
cf0676fe RM |
909 | mutex_lock(&data->update_lock); \ |
910 | data->in_##reg[nr] = in_to_reg(val, nr); \ | |
1ea6dd38 | 911 | w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \ |
cf0676fe RM |
912 | data->in_##reg[nr]); \ |
913 | mutex_unlock(&data->update_lock); \ | |
914 | return count; \ | |
915 | } | |
916 | ||
917 | store_in_reg(MIN, min) | |
918 | store_in_reg(MAX, max) | |
919 | ||
e7e1ca6e GR |
920 | static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, |
921 | char *buf) | |
a4589dbb JD |
922 | { |
923 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
924 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
925 | int nr = sensor_attr->index; | |
926 | return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01); | |
927 | } | |
928 | ||
cf0676fe RM |
929 | static struct sensor_device_attribute sda_in_input[] = { |
930 | SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0), | |
931 | SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1), | |
932 | SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2), | |
933 | SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3), | |
934 | SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4), | |
935 | SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5), | |
936 | SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6), | |
937 | SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7), | |
938 | SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8), | |
939 | SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9), | |
940 | }; | |
941 | ||
a4589dbb JD |
942 | static struct sensor_device_attribute sda_in_alarm[] = { |
943 | SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0), | |
944 | SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1), | |
945 | SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2), | |
946 | SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3), | |
947 | SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8), | |
948 | SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21), | |
949 | SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20), | |
950 | SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16), | |
951 | SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17), | |
952 | SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19), | |
953 | }; | |
954 | ||
cf0676fe | 955 | static struct sensor_device_attribute sda_in_min[] = { |
e7e1ca6e GR |
956 | SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0), |
957 | SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1), | |
958 | SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2), | |
959 | SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3), | |
960 | SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4), | |
961 | SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5), | |
962 | SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6), | |
963 | SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7), | |
964 | SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8), | |
965 | SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9), | |
cf0676fe RM |
966 | }; |
967 | ||
968 | static struct sensor_device_attribute sda_in_max[] = { | |
e7e1ca6e GR |
969 | SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0), |
970 | SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1), | |
971 | SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2), | |
972 | SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3), | |
973 | SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4), | |
974 | SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5), | |
975 | SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6), | |
976 | SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7), | |
977 | SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8), | |
978 | SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9), | |
cf0676fe RM |
979 | }; |
980 | ||
ec3e5a16 GR |
981 | static ssize_t |
982 | show_fan(struct device *dev, struct device_attribute *attr, char *buf) | |
983 | { | |
984 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
985 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
986 | int nr = sensor_attr->index; | |
987 | return sprintf(buf, "%d\n", | |
26bc440e | 988 | data->fan_from_reg(data->fan[nr], data->fan_div[nr])); |
ec3e5a16 GR |
989 | } |
990 | ||
991 | static ssize_t | |
992 | show_fan_min(struct device *dev, struct device_attribute *attr, char *buf) | |
993 | { | |
994 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
995 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
996 | int nr = sensor_attr->index; | |
997 | return sprintf(buf, "%d\n", | |
26bc440e GR |
998 | data->fan_from_reg_min(data->fan_min[nr], |
999 | data->fan_div[nr])); | |
08e7e278 | 1000 | } |
08e7e278 JD |
1001 | |
1002 | static ssize_t | |
412fec82 YM |
1003 | show_fan_div(struct device *dev, struct device_attribute *attr, |
1004 | char *buf) | |
08e7e278 JD |
1005 | { |
1006 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
412fec82 YM |
1007 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1008 | int nr = sensor_attr->index; | |
1009 | return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr])); | |
08e7e278 JD |
1010 | } |
1011 | ||
1012 | static ssize_t | |
412fec82 YM |
1013 | store_fan_min(struct device *dev, struct device_attribute *attr, |
1014 | const char *buf, size_t count) | |
08e7e278 | 1015 | { |
1ea6dd38 | 1016 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
412fec82 YM |
1017 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1018 | int nr = sensor_attr->index; | |
bce26c58 GR |
1019 | unsigned long val; |
1020 | int err; | |
08e7e278 JD |
1021 | unsigned int reg; |
1022 | u8 new_div; | |
1023 | ||
bce26c58 GR |
1024 | err = strict_strtoul(buf, 10, &val); |
1025 | if (err < 0) | |
1026 | return err; | |
1027 | ||
9a61bf63 | 1028 | mutex_lock(&data->update_lock); |
26bc440e GR |
1029 | if (!data->has_fan_div) { |
1030 | /* | |
1031 | * Only NCT6776F for now, so we know that this is a 13 bit | |
1032 | * register | |
1033 | */ | |
ec3e5a16 GR |
1034 | if (!val) { |
1035 | val = 0xff1f; | |
1036 | } else { | |
1037 | if (val > 1350000U) | |
1038 | val = 135000U; | |
1039 | val = 1350000U / val; | |
1040 | val = (val & 0x1f) | ((val << 3) & 0xff00); | |
1041 | } | |
1042 | data->fan_min[nr] = val; | |
1043 | goto done; /* Leave fan divider alone */ | |
1044 | } | |
08e7e278 JD |
1045 | if (!val) { |
1046 | /* No min limit, alarm disabled */ | |
1047 | data->fan_min[nr] = 255; | |
1048 | new_div = data->fan_div[nr]; /* No change */ | |
1049 | dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1); | |
1050 | } else if ((reg = 1350000U / val) >= 128 * 255) { | |
1051 | /* Speed below this value cannot possibly be represented, | |
1052 | even with the highest divider (128) */ | |
1053 | data->fan_min[nr] = 254; | |
1054 | new_div = 7; /* 128 == (1 << 7) */ | |
bce26c58 | 1055 | dev_warn(dev, "fan%u low limit %lu below minimum %u, set to " |
ec3e5a16 | 1056 | "minimum\n", nr + 1, val, |
26bc440e | 1057 | data->fan_from_reg_min(254, 7)); |
08e7e278 JD |
1058 | } else if (!reg) { |
1059 | /* Speed above this value cannot possibly be represented, | |
1060 | even with the lowest divider (1) */ | |
1061 | data->fan_min[nr] = 1; | |
1062 | new_div = 0; /* 1 == (1 << 0) */ | |
bce26c58 | 1063 | dev_warn(dev, "fan%u low limit %lu above maximum %u, set to " |
ec3e5a16 | 1064 | "maximum\n", nr + 1, val, |
26bc440e | 1065 | data->fan_from_reg_min(1, 0)); |
08e7e278 JD |
1066 | } else { |
1067 | /* Automatically pick the best divider, i.e. the one such | |
1068 | that the min limit will correspond to a register value | |
1069 | in the 96..192 range */ | |
1070 | new_div = 0; | |
1071 | while (reg > 192 && new_div < 7) { | |
1072 | reg >>= 1; | |
1073 | new_div++; | |
1074 | } | |
1075 | data->fan_min[nr] = reg; | |
1076 | } | |
1077 | ||
1078 | /* Write both the fan clock divider (if it changed) and the new | |
1079 | fan min (unconditionally) */ | |
1080 | if (new_div != data->fan_div[nr]) { | |
158ce075 JD |
1081 | /* Preserve the fan speed reading */ |
1082 | if (data->fan[nr] != 0xff) { | |
1083 | if (new_div > data->fan_div[nr]) | |
1084 | data->fan[nr] >>= new_div - data->fan_div[nr]; | |
1085 | else if (data->fan[nr] & 0x80) | |
1086 | data->fan[nr] = 0xff; | |
1087 | else | |
1088 | data->fan[nr] <<= data->fan_div[nr] - new_div; | |
1089 | } | |
08e7e278 JD |
1090 | |
1091 | dev_dbg(dev, "fan%u clock divider changed from %u to %u\n", | |
1092 | nr + 1, div_from_reg(data->fan_div[nr]), | |
1093 | div_from_reg(new_div)); | |
1094 | data->fan_div[nr] = new_div; | |
ec3e5a16 | 1095 | w83627ehf_write_fan_div_common(dev, data, nr); |
6b3e4645 JD |
1096 | /* Give the chip time to sample a new speed value */ |
1097 | data->last_updated = jiffies; | |
08e7e278 | 1098 | } |
ec3e5a16 | 1099 | done: |
279af1a9 | 1100 | w83627ehf_write_value(data, data->REG_FAN_MIN[nr], |
08e7e278 | 1101 | data->fan_min[nr]); |
9a61bf63 | 1102 | mutex_unlock(&data->update_lock); |
08e7e278 JD |
1103 | |
1104 | return count; | |
1105 | } | |
1106 | ||
412fec82 YM |
1107 | static struct sensor_device_attribute sda_fan_input[] = { |
1108 | SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0), | |
1109 | SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1), | |
1110 | SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2), | |
1111 | SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3), | |
1112 | SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4), | |
1113 | }; | |
08e7e278 | 1114 | |
a4589dbb JD |
1115 | static struct sensor_device_attribute sda_fan_alarm[] = { |
1116 | SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6), | |
1117 | SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7), | |
1118 | SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11), | |
1119 | SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10), | |
1120 | SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23), | |
1121 | }; | |
1122 | ||
412fec82 YM |
1123 | static struct sensor_device_attribute sda_fan_min[] = { |
1124 | SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1125 | store_fan_min, 0), | |
1126 | SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1127 | store_fan_min, 1), | |
1128 | SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1129 | store_fan_min, 2), | |
1130 | SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1131 | store_fan_min, 3), | |
1132 | SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min, | |
1133 | store_fan_min, 4), | |
1134 | }; | |
08e7e278 | 1135 | |
412fec82 YM |
1136 | static struct sensor_device_attribute sda_fan_div[] = { |
1137 | SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0), | |
1138 | SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1), | |
1139 | SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2), | |
1140 | SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3), | |
1141 | SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4), | |
1142 | }; | |
1143 | ||
d36cf32c GR |
1144 | static ssize_t |
1145 | show_temp_label(struct device *dev, struct device_attribute *attr, char *buf) | |
1146 | { | |
1147 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
1148 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1149 | int nr = sensor_attr->index; | |
1150 | return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]); | |
1151 | } | |
1152 | ||
ec3e5a16 | 1153 | #define show_temp_reg(addr, reg) \ |
08e7e278 | 1154 | static ssize_t \ |
412fec82 YM |
1155 | show_##reg(struct device *dev, struct device_attribute *attr, \ |
1156 | char *buf) \ | |
08e7e278 JD |
1157 | { \ |
1158 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1159 | struct sensor_device_attribute *sensor_attr = \ |
1160 | to_sensor_dev_attr(attr); \ | |
412fec82 | 1161 | int nr = sensor_attr->index; \ |
08e7e278 | 1162 | return sprintf(buf, "%d\n", \ |
ec3e5a16 | 1163 | temp_from_reg(data->addr[nr], data->reg[nr])); \ |
08e7e278 | 1164 | } |
ec3e5a16 GR |
1165 | show_temp_reg(reg_temp, temp); |
1166 | show_temp_reg(reg_temp_over, temp_max); | |
1167 | show_temp_reg(reg_temp_hyst, temp_max_hyst); | |
08e7e278 | 1168 | |
ec3e5a16 | 1169 | #define store_temp_reg(addr, reg) \ |
08e7e278 | 1170 | static ssize_t \ |
412fec82 YM |
1171 | store_##reg(struct device *dev, struct device_attribute *attr, \ |
1172 | const char *buf, size_t count) \ | |
08e7e278 | 1173 | { \ |
1ea6dd38 | 1174 | struct w83627ehf_data *data = dev_get_drvdata(dev); \ |
e7e1ca6e GR |
1175 | struct sensor_device_attribute *sensor_attr = \ |
1176 | to_sensor_dev_attr(attr); \ | |
412fec82 | 1177 | int nr = sensor_attr->index; \ |
bce26c58 GR |
1178 | int err; \ |
1179 | long val; \ | |
1180 | err = strict_strtol(buf, 10, &val); \ | |
1181 | if (err < 0) \ | |
1182 | return err; \ | |
9a61bf63 | 1183 | mutex_lock(&data->update_lock); \ |
ec3e5a16 GR |
1184 | data->reg[nr] = temp_to_reg(data->addr[nr], val); \ |
1185 | w83627ehf_write_value(data, data->addr[nr], \ | |
08e7e278 | 1186 | data->reg[nr]); \ |
9a61bf63 | 1187 | mutex_unlock(&data->update_lock); \ |
08e7e278 JD |
1188 | return count; \ |
1189 | } | |
ec3e5a16 GR |
1190 | store_temp_reg(reg_temp_over, temp_max); |
1191 | store_temp_reg(reg_temp_hyst, temp_max_hyst); | |
08e7e278 | 1192 | |
da667365 JD |
1193 | static ssize_t |
1194 | show_temp_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1195 | { | |
1196 | struct w83627ehf_data *data = w83627ehf_update_device(dev); | |
1197 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1198 | int nr = sensor_attr->index; | |
1199 | return sprintf(buf, "%d\n", (int)data->temp_type[nr]); | |
1200 | } | |
1201 | ||
a157d06d | 1202 | static struct sensor_device_attribute sda_temp_input[] = { |
bce26c58 GR |
1203 | SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0), |
1204 | SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1), | |
1205 | SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2), | |
d36cf32c | 1206 | SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3), |
ec3e5a16 GR |
1207 | SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4), |
1208 | SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5), | |
1209 | SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6), | |
1210 | SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7), | |
1211 | SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8), | |
d36cf32c GR |
1212 | }; |
1213 | ||
1214 | static struct sensor_device_attribute sda_temp_label[] = { | |
1215 | SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0), | |
1216 | SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1), | |
1217 | SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2), | |
1218 | SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3), | |
ec3e5a16 GR |
1219 | SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4), |
1220 | SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5), | |
1221 | SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6), | |
1222 | SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7), | |
1223 | SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8), | |
a157d06d GJ |
1224 | }; |
1225 | ||
1226 | static struct sensor_device_attribute sda_temp_max[] = { | |
bce26c58 | 1227 | SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max, |
412fec82 | 1228 | store_temp_max, 0), |
bce26c58 | 1229 | SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max, |
412fec82 | 1230 | store_temp_max, 1), |
bce26c58 GR |
1231 | SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max, |
1232 | store_temp_max, 2), | |
ec3e5a16 GR |
1233 | SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max, |
1234 | store_temp_max, 3), | |
1235 | SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1236 | store_temp_max, 4), | |
1237 | SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1238 | store_temp_max, 5), | |
1239 | SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1240 | store_temp_max, 6), | |
1241 | SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1242 | store_temp_max, 7), | |
1243 | SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max, | |
1244 | store_temp_max, 8), | |
a157d06d GJ |
1245 | }; |
1246 | ||
1247 | static struct sensor_device_attribute sda_temp_max_hyst[] = { | |
bce26c58 | 1248 | SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, |
412fec82 | 1249 | store_temp_max_hyst, 0), |
bce26c58 | 1250 | SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, |
412fec82 | 1251 | store_temp_max_hyst, 1), |
bce26c58 GR |
1252 | SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, |
1253 | store_temp_max_hyst, 2), | |
ec3e5a16 GR |
1254 | SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, |
1255 | store_temp_max_hyst, 3), | |
1256 | SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1257 | store_temp_max_hyst, 4), | |
1258 | SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1259 | store_temp_max_hyst, 5), | |
1260 | SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1261 | store_temp_max_hyst, 6), | |
1262 | SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1263 | store_temp_max_hyst, 7), | |
1264 | SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst, | |
1265 | store_temp_max_hyst, 8), | |
a157d06d GJ |
1266 | }; |
1267 | ||
1268 | static struct sensor_device_attribute sda_temp_alarm[] = { | |
a4589dbb JD |
1269 | SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4), |
1270 | SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5), | |
1271 | SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13), | |
a157d06d GJ |
1272 | }; |
1273 | ||
1274 | static struct sensor_device_attribute sda_temp_type[] = { | |
da667365 JD |
1275 | SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0), |
1276 | SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1), | |
1277 | SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2), | |
412fec82 | 1278 | }; |
08e7e278 | 1279 | |
08c79950 | 1280 | #define show_pwm_reg(reg) \ |
e7e1ca6e GR |
1281 | static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ |
1282 | char *buf) \ | |
08c79950 RM |
1283 | { \ |
1284 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1285 | struct sensor_device_attribute *sensor_attr = \ |
1286 | to_sensor_dev_attr(attr); \ | |
08c79950 RM |
1287 | int nr = sensor_attr->index; \ |
1288 | return sprintf(buf, "%d\n", data->reg[nr]); \ | |
1289 | } | |
1290 | ||
1291 | show_pwm_reg(pwm_mode) | |
1292 | show_pwm_reg(pwm_enable) | |
1293 | show_pwm_reg(pwm) | |
1294 | ||
1295 | static ssize_t | |
1296 | store_pwm_mode(struct device *dev, struct device_attribute *attr, | |
1297 | const char *buf, size_t count) | |
1298 | { | |
1ea6dd38 | 1299 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
08c79950 RM |
1300 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1301 | int nr = sensor_attr->index; | |
bce26c58 GR |
1302 | unsigned long val; |
1303 | int err; | |
08c79950 RM |
1304 | u16 reg; |
1305 | ||
bce26c58 GR |
1306 | err = strict_strtoul(buf, 10, &val); |
1307 | if (err < 0) | |
1308 | return err; | |
1309 | ||
08c79950 RM |
1310 | if (val > 1) |
1311 | return -EINVAL; | |
1312 | mutex_lock(&data->update_lock); | |
1ea6dd38 | 1313 | reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]); |
08c79950 RM |
1314 | data->pwm_mode[nr] = val; |
1315 | reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]); | |
1316 | if (!val) | |
1317 | reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr]; | |
1ea6dd38 | 1318 | w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg); |
08c79950 RM |
1319 | mutex_unlock(&data->update_lock); |
1320 | return count; | |
1321 | } | |
1322 | ||
1323 | static ssize_t | |
1324 | store_pwm(struct device *dev, struct device_attribute *attr, | |
1325 | const char *buf, size_t count) | |
1326 | { | |
1ea6dd38 | 1327 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
08c79950 RM |
1328 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1329 | int nr = sensor_attr->index; | |
bce26c58 GR |
1330 | unsigned long val; |
1331 | int err; | |
1332 | ||
1333 | err = strict_strtoul(buf, 10, &val); | |
1334 | if (err < 0) | |
1335 | return err; | |
1336 | ||
1337 | val = SENSORS_LIMIT(val, 0, 255); | |
08c79950 RM |
1338 | |
1339 | mutex_lock(&data->update_lock); | |
1340 | data->pwm[nr] = val; | |
279af1a9 | 1341 | w83627ehf_write_value(data, data->REG_PWM[nr], val); |
08c79950 RM |
1342 | mutex_unlock(&data->update_lock); |
1343 | return count; | |
1344 | } | |
1345 | ||
1346 | static ssize_t | |
1347 | store_pwm_enable(struct device *dev, struct device_attribute *attr, | |
1348 | const char *buf, size_t count) | |
1349 | { | |
1ea6dd38 | 1350 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
ec3e5a16 | 1351 | struct w83627ehf_sio_data *sio_data = dev->platform_data; |
08c79950 RM |
1352 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1353 | int nr = sensor_attr->index; | |
bce26c58 GR |
1354 | unsigned long val; |
1355 | int err; | |
08c79950 RM |
1356 | u16 reg; |
1357 | ||
bce26c58 GR |
1358 | err = strict_strtoul(buf, 10, &val); |
1359 | if (err < 0) | |
1360 | return err; | |
1361 | ||
b84bb518 | 1362 | if (!val || (val > 4 && val != data->pwm_enable_orig[nr])) |
08c79950 | 1363 | return -EINVAL; |
ec3e5a16 GR |
1364 | /* SmartFan III mode is not supported on NCT6776F */ |
1365 | if (sio_data->kind == nct6776 && val == 4) | |
1366 | return -EINVAL; | |
1367 | ||
08c79950 | 1368 | mutex_lock(&data->update_lock); |
08c79950 | 1369 | data->pwm_enable[nr] = val; |
ec3e5a16 GR |
1370 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { |
1371 | reg = w83627ehf_read_value(data, | |
1372 | NCT6775_REG_FAN_MODE[nr]); | |
1373 | reg &= 0x0f; | |
1374 | reg |= (val - 1) << 4; | |
1375 | w83627ehf_write_value(data, | |
1376 | NCT6775_REG_FAN_MODE[nr], reg); | |
1377 | } else { | |
1378 | reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]); | |
1379 | reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]); | |
1380 | reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr]; | |
1381 | w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg); | |
1382 | } | |
08c79950 RM |
1383 | mutex_unlock(&data->update_lock); |
1384 | return count; | |
1385 | } | |
1386 | ||
1387 | ||
1388 | #define show_tol_temp(reg) \ | |
1389 | static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ | |
1390 | char *buf) \ | |
1391 | { \ | |
1392 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1393 | struct sensor_device_attribute *sensor_attr = \ |
1394 | to_sensor_dev_attr(attr); \ | |
08c79950 | 1395 | int nr = sensor_attr->index; \ |
bce26c58 | 1396 | return sprintf(buf, "%d\n", data->reg[nr] * 1000); \ |
08c79950 RM |
1397 | } |
1398 | ||
1399 | show_tol_temp(tolerance) | |
1400 | show_tol_temp(target_temp) | |
1401 | ||
1402 | static ssize_t | |
1403 | store_target_temp(struct device *dev, struct device_attribute *attr, | |
1404 | const char *buf, size_t count) | |
1405 | { | |
1ea6dd38 | 1406 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
08c79950 RM |
1407 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1408 | int nr = sensor_attr->index; | |
bce26c58 GR |
1409 | long val; |
1410 | int err; | |
1411 | ||
1412 | err = strict_strtol(buf, 10, &val); | |
1413 | if (err < 0) | |
1414 | return err; | |
1415 | ||
1416 | val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127); | |
08c79950 RM |
1417 | |
1418 | mutex_lock(&data->update_lock); | |
1419 | data->target_temp[nr] = val; | |
279af1a9 | 1420 | w83627ehf_write_value(data, data->REG_TARGET[nr], val); |
08c79950 RM |
1421 | mutex_unlock(&data->update_lock); |
1422 | return count; | |
1423 | } | |
1424 | ||
1425 | static ssize_t | |
1426 | store_tolerance(struct device *dev, struct device_attribute *attr, | |
1427 | const char *buf, size_t count) | |
1428 | { | |
1ea6dd38 | 1429 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
ec3e5a16 | 1430 | struct w83627ehf_sio_data *sio_data = dev->platform_data; |
08c79950 RM |
1431 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1432 | int nr = sensor_attr->index; | |
1433 | u16 reg; | |
bce26c58 GR |
1434 | long val; |
1435 | int err; | |
1436 | ||
1437 | err = strict_strtol(buf, 10, &val); | |
1438 | if (err < 0) | |
1439 | return err; | |
1440 | ||
08c79950 | 1441 | /* Limit the temp to 0C - 15C */ |
bce26c58 | 1442 | val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15); |
08c79950 RM |
1443 | |
1444 | mutex_lock(&data->update_lock); | |
ec3e5a16 GR |
1445 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { |
1446 | /* Limit tolerance further for NCT6776F */ | |
1447 | if (sio_data->kind == nct6776 && val > 7) | |
1448 | val = 7; | |
1449 | reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]); | |
08c79950 | 1450 | reg = (reg & 0xf0) | val; |
ec3e5a16 GR |
1451 | w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg); |
1452 | } else { | |
1453 | reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]); | |
1454 | if (nr == 1) | |
1455 | reg = (reg & 0x0f) | (val << 4); | |
1456 | else | |
1457 | reg = (reg & 0xf0) | val; | |
1458 | w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg); | |
1459 | } | |
1460 | data->tolerance[nr] = val; | |
08c79950 RM |
1461 | mutex_unlock(&data->update_lock); |
1462 | return count; | |
1463 | } | |
1464 | ||
1465 | static struct sensor_device_attribute sda_pwm[] = { | |
1466 | SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0), | |
1467 | SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1), | |
1468 | SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2), | |
1469 | SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3), | |
1470 | }; | |
1471 | ||
1472 | static struct sensor_device_attribute sda_pwm_mode[] = { | |
1473 | SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode, | |
1474 | store_pwm_mode, 0), | |
1475 | SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode, | |
1476 | store_pwm_mode, 1), | |
1477 | SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode, | |
1478 | store_pwm_mode, 2), | |
1479 | SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode, | |
1480 | store_pwm_mode, 3), | |
1481 | }; | |
1482 | ||
1483 | static struct sensor_device_attribute sda_pwm_enable[] = { | |
1484 | SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable, | |
1485 | store_pwm_enable, 0), | |
1486 | SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable, | |
1487 | store_pwm_enable, 1), | |
1488 | SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable, | |
1489 | store_pwm_enable, 2), | |
1490 | SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable, | |
1491 | store_pwm_enable, 3), | |
1492 | }; | |
1493 | ||
1494 | static struct sensor_device_attribute sda_target_temp[] = { | |
1495 | SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp, | |
1496 | store_target_temp, 0), | |
1497 | SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp, | |
1498 | store_target_temp, 1), | |
1499 | SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp, | |
1500 | store_target_temp, 2), | |
1501 | SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp, | |
1502 | store_target_temp, 3), | |
1503 | }; | |
1504 | ||
1505 | static struct sensor_device_attribute sda_tolerance[] = { | |
1506 | SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance, | |
1507 | store_tolerance, 0), | |
1508 | SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance, | |
1509 | store_tolerance, 1), | |
1510 | SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance, | |
1511 | store_tolerance, 2), | |
1512 | SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance, | |
1513 | store_tolerance, 3), | |
1514 | }; | |
1515 | ||
08c79950 RM |
1516 | /* Smart Fan registers */ |
1517 | ||
1518 | #define fan_functions(reg, REG) \ | |
1519 | static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ | |
1520 | char *buf) \ | |
1521 | { \ | |
1522 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1523 | struct sensor_device_attribute *sensor_attr = \ |
1524 | to_sensor_dev_attr(attr); \ | |
08c79950 RM |
1525 | int nr = sensor_attr->index; \ |
1526 | return sprintf(buf, "%d\n", data->reg[nr]); \ | |
e7e1ca6e | 1527 | } \ |
08c79950 RM |
1528 | static ssize_t \ |
1529 | store_##reg(struct device *dev, struct device_attribute *attr, \ | |
1530 | const char *buf, size_t count) \ | |
e7e1ca6e | 1531 | { \ |
1ea6dd38 | 1532 | struct w83627ehf_data *data = dev_get_drvdata(dev); \ |
e7e1ca6e GR |
1533 | struct sensor_device_attribute *sensor_attr = \ |
1534 | to_sensor_dev_attr(attr); \ | |
08c79950 | 1535 | int nr = sensor_attr->index; \ |
bce26c58 GR |
1536 | unsigned long val; \ |
1537 | int err; \ | |
1538 | err = strict_strtoul(buf, 10, &val); \ | |
1539 | if (err < 0) \ | |
1540 | return err; \ | |
1541 | val = SENSORS_LIMIT(val, 1, 255); \ | |
08c79950 RM |
1542 | mutex_lock(&data->update_lock); \ |
1543 | data->reg[nr] = val; \ | |
da2e0255 | 1544 | w83627ehf_write_value(data, data->REG_##REG[nr], val); \ |
08c79950 RM |
1545 | mutex_unlock(&data->update_lock); \ |
1546 | return count; \ | |
1547 | } | |
1548 | ||
41e9a062 DB |
1549 | fan_functions(fan_start_output, FAN_START_OUTPUT) |
1550 | fan_functions(fan_stop_output, FAN_STOP_OUTPUT) | |
1551 | fan_functions(fan_max_output, FAN_MAX_OUTPUT) | |
1552 | fan_functions(fan_step_output, FAN_STEP_OUTPUT) | |
08c79950 RM |
1553 | |
1554 | #define fan_time_functions(reg, REG) \ | |
1555 | static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ | |
1556 | char *buf) \ | |
1557 | { \ | |
1558 | struct w83627ehf_data *data = w83627ehf_update_device(dev); \ | |
e7e1ca6e GR |
1559 | struct sensor_device_attribute *sensor_attr = \ |
1560 | to_sensor_dev_attr(attr); \ | |
08c79950 RM |
1561 | int nr = sensor_attr->index; \ |
1562 | return sprintf(buf, "%d\n", \ | |
e7e1ca6e GR |
1563 | step_time_from_reg(data->reg[nr], \ |
1564 | data->pwm_mode[nr])); \ | |
08c79950 RM |
1565 | } \ |
1566 | \ | |
1567 | static ssize_t \ | |
1568 | store_##reg(struct device *dev, struct device_attribute *attr, \ | |
1569 | const char *buf, size_t count) \ | |
1570 | { \ | |
1ea6dd38 | 1571 | struct w83627ehf_data *data = dev_get_drvdata(dev); \ |
e7e1ca6e GR |
1572 | struct sensor_device_attribute *sensor_attr = \ |
1573 | to_sensor_dev_attr(attr); \ | |
08c79950 | 1574 | int nr = sensor_attr->index; \ |
bce26c58 GR |
1575 | unsigned long val; \ |
1576 | int err; \ | |
1577 | err = strict_strtoul(buf, 10, &val); \ | |
1578 | if (err < 0) \ | |
1579 | return err; \ | |
1580 | val = step_time_to_reg(val, data->pwm_mode[nr]); \ | |
08c79950 RM |
1581 | mutex_lock(&data->update_lock); \ |
1582 | data->reg[nr] = val; \ | |
1ea6dd38 | 1583 | w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \ |
08c79950 RM |
1584 | mutex_unlock(&data->update_lock); \ |
1585 | return count; \ | |
1586 | } \ | |
1587 | ||
1588 | fan_time_functions(fan_stop_time, FAN_STOP_TIME) | |
1589 | ||
1ea6dd38 DH |
1590 | static ssize_t show_name(struct device *dev, struct device_attribute *attr, |
1591 | char *buf) | |
1592 | { | |
1593 | struct w83627ehf_data *data = dev_get_drvdata(dev); | |
1594 | ||
1595 | return sprintf(buf, "%s\n", data->name); | |
1596 | } | |
1597 | static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); | |
08c79950 RM |
1598 | |
1599 | static struct sensor_device_attribute sda_sf3_arrays_fan4[] = { | |
1600 | SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time, | |
1601 | store_fan_stop_time, 3), | |
41e9a062 DB |
1602 | SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output, |
1603 | store_fan_start_output, 3), | |
1604 | SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output, | |
1605 | store_fan_stop_output, 3), | |
1606 | SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output, | |
1607 | store_fan_max_output, 3), | |
1608 | SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output, | |
1609 | store_fan_step_output, 3), | |
08c79950 RM |
1610 | }; |
1611 | ||
1612 | static struct sensor_device_attribute sda_sf3_arrays[] = { | |
1613 | SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time, | |
1614 | store_fan_stop_time, 0), | |
1615 | SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time, | |
1616 | store_fan_stop_time, 1), | |
1617 | SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time, | |
1618 | store_fan_stop_time, 2), | |
41e9a062 DB |
1619 | SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output, |
1620 | store_fan_start_output, 0), | |
1621 | SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output, | |
1622 | store_fan_start_output, 1), | |
1623 | SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output, | |
1624 | store_fan_start_output, 2), | |
1625 | SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output, | |
1626 | store_fan_stop_output, 0), | |
1627 | SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output, | |
1628 | store_fan_stop_output, 1), | |
1629 | SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output, | |
1630 | store_fan_stop_output, 2), | |
da2e0255 | 1631 | }; |
41e9a062 | 1632 | |
da2e0255 GR |
1633 | |
1634 | /* | |
1635 | * pwm1 and pwm3 don't support max and step settings on all chips. | |
1636 | * Need to check support while generating/removing attribute files. | |
1637 | */ | |
1638 | static struct sensor_device_attribute sda_sf3_max_step_arrays[] = { | |
1639 | SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output, | |
1640 | store_fan_max_output, 0), | |
1641 | SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output, | |
1642 | store_fan_step_output, 0), | |
41e9a062 DB |
1643 | SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output, |
1644 | store_fan_max_output, 1), | |
1645 | SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output, | |
1646 | store_fan_step_output, 1), | |
da2e0255 GR |
1647 | SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output, |
1648 | store_fan_max_output, 2), | |
1649 | SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output, | |
1650 | store_fan_step_output, 2), | |
08c79950 RM |
1651 | }; |
1652 | ||
fc18d6c0 JD |
1653 | static ssize_t |
1654 | show_vid(struct device *dev, struct device_attribute *attr, char *buf) | |
1655 | { | |
1656 | struct w83627ehf_data *data = dev_get_drvdata(dev); | |
1657 | return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm)); | |
1658 | } | |
1659 | static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL); | |
1660 | ||
08e7e278 | 1661 | /* |
1ea6dd38 | 1662 | * Driver and device management |
08e7e278 JD |
1663 | */ |
1664 | ||
c18beb5b DH |
1665 | static void w83627ehf_device_remove_files(struct device *dev) |
1666 | { | |
1667 | /* some entries in the following arrays may not have been used in | |
1668 | * device_create_file(), but device_remove_file() will ignore them */ | |
1669 | int i; | |
1ea6dd38 | 1670 | struct w83627ehf_data *data = dev_get_drvdata(dev); |
c18beb5b DH |
1671 | |
1672 | for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) | |
1673 | device_remove_file(dev, &sda_sf3_arrays[i].dev_attr); | |
da2e0255 GR |
1674 | for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) { |
1675 | struct sensor_device_attribute *attr = | |
1676 | &sda_sf3_max_step_arrays[i]; | |
ec3e5a16 GR |
1677 | if (data->REG_FAN_STEP_OUTPUT && |
1678 | data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) | |
da2e0255 GR |
1679 | device_remove_file(dev, &attr->dev_attr); |
1680 | } | |
c18beb5b DH |
1681 | for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) |
1682 | device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr); | |
1ea6dd38 | 1683 | for (i = 0; i < data->in_num; i++) { |
a157d06d GJ |
1684 | if ((i == 6) && data->in6_skip) |
1685 | continue; | |
c18beb5b DH |
1686 | device_remove_file(dev, &sda_in_input[i].dev_attr); |
1687 | device_remove_file(dev, &sda_in_alarm[i].dev_attr); | |
1688 | device_remove_file(dev, &sda_in_min[i].dev_attr); | |
1689 | device_remove_file(dev, &sda_in_max[i].dev_attr); | |
1690 | } | |
1691 | for (i = 0; i < 5; i++) { | |
1692 | device_remove_file(dev, &sda_fan_input[i].dev_attr); | |
1693 | device_remove_file(dev, &sda_fan_alarm[i].dev_attr); | |
1694 | device_remove_file(dev, &sda_fan_div[i].dev_attr); | |
1695 | device_remove_file(dev, &sda_fan_min[i].dev_attr); | |
1696 | } | |
237c8d2f | 1697 | for (i = 0; i < data->pwm_num; i++) { |
c18beb5b DH |
1698 | device_remove_file(dev, &sda_pwm[i].dev_attr); |
1699 | device_remove_file(dev, &sda_pwm_mode[i].dev_attr); | |
1700 | device_remove_file(dev, &sda_pwm_enable[i].dev_attr); | |
1701 | device_remove_file(dev, &sda_target_temp[i].dev_attr); | |
1702 | device_remove_file(dev, &sda_tolerance[i].dev_attr); | |
1703 | } | |
d36cf32c GR |
1704 | for (i = 0; i < NUM_REG_TEMP; i++) { |
1705 | if (!(data->have_temp & (1 << i))) | |
a157d06d GJ |
1706 | continue; |
1707 | device_remove_file(dev, &sda_temp_input[i].dev_attr); | |
d36cf32c | 1708 | device_remove_file(dev, &sda_temp_label[i].dev_attr); |
a157d06d GJ |
1709 | device_remove_file(dev, &sda_temp_max[i].dev_attr); |
1710 | device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr); | |
ec3e5a16 GR |
1711 | if (i > 2) |
1712 | continue; | |
a157d06d GJ |
1713 | device_remove_file(dev, &sda_temp_alarm[i].dev_attr); |
1714 | device_remove_file(dev, &sda_temp_type[i].dev_attr); | |
1715 | } | |
c18beb5b | 1716 | |
1ea6dd38 | 1717 | device_remove_file(dev, &dev_attr_name); |
cbe311f2 | 1718 | device_remove_file(dev, &dev_attr_cpu0_vid); |
1ea6dd38 | 1719 | } |
08e7e278 | 1720 | |
1ea6dd38 DH |
1721 | /* Get the monitoring functions started */ |
1722 | static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data) | |
08e7e278 JD |
1723 | { |
1724 | int i; | |
da667365 | 1725 | u8 tmp, diode; |
08e7e278 JD |
1726 | |
1727 | /* Start monitoring is needed */ | |
1ea6dd38 | 1728 | tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG); |
08e7e278 | 1729 | if (!(tmp & 0x01)) |
1ea6dd38 | 1730 | w83627ehf_write_value(data, W83627EHF_REG_CONFIG, |
08e7e278 JD |
1731 | tmp | 0x01); |
1732 | ||
d36cf32c GR |
1733 | /* Enable temperature sensors if needed */ |
1734 | for (i = 0; i < NUM_REG_TEMP; i++) { | |
1735 | if (!(data->have_temp & (1 << i))) | |
1736 | continue; | |
ec3e5a16 | 1737 | if (!data->reg_temp_config[i]) |
d36cf32c | 1738 | continue; |
1ea6dd38 | 1739 | tmp = w83627ehf_read_value(data, |
ec3e5a16 | 1740 | data->reg_temp_config[i]); |
08e7e278 | 1741 | if (tmp & 0x01) |
1ea6dd38 | 1742 | w83627ehf_write_value(data, |
ec3e5a16 | 1743 | data->reg_temp_config[i], |
08e7e278 JD |
1744 | tmp & 0xfe); |
1745 | } | |
d3130f0e JD |
1746 | |
1747 | /* Enable VBAT monitoring if needed */ | |
1748 | tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT); | |
1749 | if (!(tmp & 0x01)) | |
1750 | w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01); | |
da667365 JD |
1751 | |
1752 | /* Get thermal sensor types */ | |
1753 | diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE); | |
1754 | for (i = 0; i < 3; i++) { | |
1755 | if ((tmp & (0x02 << i))) | |
1756 | data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2; | |
1757 | else | |
1758 | data->temp_type[i] = 4; /* thermistor */ | |
1759 | } | |
08e7e278 JD |
1760 | } |
1761 | ||
ec3e5a16 GR |
1762 | static void w82627ehf_swap_tempreg(struct w83627ehf_data *data, |
1763 | int r1, int r2) | |
1764 | { | |
1765 | u16 tmp; | |
1766 | ||
1767 | tmp = data->temp_src[r1]; | |
1768 | data->temp_src[r1] = data->temp_src[r2]; | |
1769 | data->temp_src[r2] = tmp; | |
1770 | ||
1771 | tmp = data->reg_temp[r1]; | |
1772 | data->reg_temp[r1] = data->reg_temp[r2]; | |
1773 | data->reg_temp[r2] = tmp; | |
1774 | ||
1775 | tmp = data->reg_temp_over[r1]; | |
1776 | data->reg_temp_over[r1] = data->reg_temp_over[r2]; | |
1777 | data->reg_temp_over[r2] = tmp; | |
1778 | ||
1779 | tmp = data->reg_temp_hyst[r1]; | |
1780 | data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2]; | |
1781 | data->reg_temp_hyst[r2] = tmp; | |
1782 | ||
1783 | tmp = data->reg_temp_config[r1]; | |
1784 | data->reg_temp_config[r1] = data->reg_temp_config[r2]; | |
1785 | data->reg_temp_config[r2] = tmp; | |
1786 | } | |
1787 | ||
1ea6dd38 | 1788 | static int __devinit w83627ehf_probe(struct platform_device *pdev) |
08e7e278 | 1789 | { |
1ea6dd38 DH |
1790 | struct device *dev = &pdev->dev; |
1791 | struct w83627ehf_sio_data *sio_data = dev->platform_data; | |
08e7e278 | 1792 | struct w83627ehf_data *data; |
1ea6dd38 | 1793 | struct resource *res; |
ec3e5a16 | 1794 | u8 fan3pin, fan4pin, fan4min, fan5pin, en_vrm10; |
08e7e278 JD |
1795 | int i, err = 0; |
1796 | ||
1ea6dd38 DH |
1797 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); |
1798 | if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) { | |
08e7e278 | 1799 | err = -EBUSY; |
1ea6dd38 DH |
1800 | dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", |
1801 | (unsigned long)res->start, | |
1802 | (unsigned long)res->start + IOREGION_LENGTH - 1); | |
08e7e278 JD |
1803 | goto exit; |
1804 | } | |
1805 | ||
e7e1ca6e GR |
1806 | data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL); |
1807 | if (!data) { | |
08e7e278 JD |
1808 | err = -ENOMEM; |
1809 | goto exit_release; | |
1810 | } | |
08e7e278 | 1811 | |
1ea6dd38 | 1812 | data->addr = res->start; |
9a61bf63 | 1813 | mutex_init(&data->lock); |
9a61bf63 | 1814 | mutex_init(&data->update_lock); |
1ea6dd38 DH |
1815 | data->name = w83627ehf_device_names[sio_data->kind]; |
1816 | platform_set_drvdata(pdev, data); | |
08e7e278 | 1817 | |
237c8d2f GJ |
1818 | /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */ |
1819 | data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9; | |
ec3e5a16 | 1820 | /* 667HG, NCT6775F, and NCT6776F have 3 pwms */ |
c39aedaf | 1821 | data->pwm_num = (sio_data->kind == w83667hg |
ec3e5a16 GR |
1822 | || sio_data->kind == w83667hg_b |
1823 | || sio_data->kind == nct6775 | |
1824 | || sio_data->kind == nct6776) ? 3 : 4; | |
08e7e278 | 1825 | |
d36cf32c | 1826 | data->have_temp = 0x07; |
a157d06d | 1827 | /* Check temp3 configuration bit for 667HG */ |
d36cf32c GR |
1828 | if (sio_data->kind == w83667hg) { |
1829 | u8 reg; | |
1830 | ||
1831 | reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]); | |
1832 | if (reg & 0x01) | |
1833 | data->have_temp &= ~(1 << 2); | |
1834 | else | |
ec3e5a16 GR |
1835 | data->in6_skip = 1; /* either temp3 or in6 */ |
1836 | } | |
1837 | ||
1838 | /* Deal with temperature register setup first. */ | |
1839 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { | |
1840 | int mask = 0; | |
1841 | ||
1842 | /* | |
1843 | * Display temperature sensor output only if it monitors | |
1844 | * a source other than one already reported. Always display | |
1845 | * first three temperature registers, though. | |
1846 | */ | |
1847 | for (i = 0; i < NUM_REG_TEMP; i++) { | |
1848 | u8 src; | |
1849 | ||
1850 | data->reg_temp[i] = NCT6775_REG_TEMP[i]; | |
1851 | data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i]; | |
1852 | data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i]; | |
1853 | data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i]; | |
1854 | ||
1855 | src = w83627ehf_read_value(data, | |
1856 | NCT6775_REG_TEMP_SOURCE[i]); | |
1857 | src &= 0x1f; | |
1858 | if (src && !(mask & (1 << src))) { | |
1859 | data->have_temp |= 1 << i; | |
1860 | mask |= 1 << src; | |
1861 | } | |
1862 | ||
1863 | data->temp_src[i] = src; | |
1864 | ||
1865 | /* | |
1866 | * Now do some register swapping if index 0..2 don't | |
1867 | * point to SYSTIN(1), CPUIN(2), and AUXIN(3). | |
1868 | * Idea is to have the first three attributes | |
1869 | * report SYSTIN, CPUIN, and AUXIN if possible | |
1870 | * without overriding the basic system configuration. | |
1871 | */ | |
1872 | if (i > 0 && data->temp_src[0] != 1 | |
1873 | && data->temp_src[i] == 1) | |
1874 | w82627ehf_swap_tempreg(data, 0, i); | |
1875 | if (i > 1 && data->temp_src[1] != 2 | |
1876 | && data->temp_src[i] == 2) | |
1877 | w82627ehf_swap_tempreg(data, 1, i); | |
1878 | if (i > 2 && data->temp_src[2] != 3 | |
1879 | && data->temp_src[i] == 3) | |
1880 | w82627ehf_swap_tempreg(data, 2, i); | |
1881 | } | |
1882 | if (sio_data->kind == nct6776) { | |
1883 | /* | |
1884 | * On NCT6776, AUXTIN and VIN3 pins are shared. | |
1885 | * Only way to detect it is to check if AUXTIN is used | |
1886 | * as a temperature source, and if that source is | |
1887 | * enabled. | |
1888 | * | |
1889 | * If that is the case, disable in6, which reports VIN3. | |
1890 | * Otherwise disable temp3. | |
1891 | */ | |
1892 | if (data->temp_src[2] == 3) { | |
1893 | u8 reg; | |
1894 | ||
1895 | if (data->reg_temp_config[2]) | |
1896 | reg = w83627ehf_read_value(data, | |
1897 | data->reg_temp_config[2]); | |
1898 | else | |
1899 | reg = 0; /* Assume AUXTIN is used */ | |
1900 | ||
1901 | if (reg & 0x01) | |
1902 | data->have_temp &= ~(1 << 2); | |
1903 | else | |
1904 | data->in6_skip = 1; | |
1905 | } | |
1906 | } | |
1907 | ||
1908 | data->temp_label = nct6776_temp_label; | |
d36cf32c GR |
1909 | } else if (sio_data->kind == w83667hg_b) { |
1910 | u8 reg; | |
1911 | ||
ec3e5a16 GR |
1912 | /* |
1913 | * Temperature sources are selected with bank 0, registers 0x49 | |
1914 | * and 0x4a. | |
1915 | */ | |
1916 | for (i = 0; i < ARRAY_SIZE(W83627EHF_REG_TEMP); i++) { | |
1917 | data->reg_temp[i] = W83627EHF_REG_TEMP[i]; | |
1918 | data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i]; | |
1919 | data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i]; | |
1920 | data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i]; | |
1921 | } | |
d36cf32c GR |
1922 | reg = w83627ehf_read_value(data, 0x4a); |
1923 | data->temp_src[0] = reg >> 5; | |
1924 | reg = w83627ehf_read_value(data, 0x49); | |
1925 | data->temp_src[1] = reg & 0x07; | |
ec3e5a16 | 1926 | data->temp_src[2] = (reg >> 4) & 0x07; |
d36cf32c GR |
1927 | |
1928 | /* | |
1929 | * W83667HG-B has another temperature register at 0x7e. | |
1930 | * The temperature source is selected with register 0x7d. | |
1931 | * Support it if the source differs from already reported | |
1932 | * sources. | |
1933 | */ | |
1934 | reg = w83627ehf_read_value(data, 0x7d); | |
1935 | reg &= 0x07; | |
1936 | if (reg != data->temp_src[0] && reg != data->temp_src[1] | |
1937 | && reg != data->temp_src[2]) { | |
1938 | data->temp_src[3] = reg; | |
1939 | data->have_temp |= 1 << 3; | |
1940 | } | |
1941 | ||
1942 | /* | |
1943 | * Chip supports either AUXTIN or VIN3. Try to find out which | |
1944 | * one. | |
1945 | */ | |
1946 | reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]); | |
1947 | if (data->temp_src[2] == 2 && (reg & 0x01)) | |
1948 | data->have_temp &= ~(1 << 2); | |
1949 | ||
1950 | if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2))) | |
1951 | || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3)))) | |
1952 | data->in6_skip = 1; | |
1953 | ||
1954 | data->temp_label = w83667hg_b_temp_label; | |
ec3e5a16 GR |
1955 | } else { |
1956 | /* Temperature sources are fixed */ | |
1957 | for (i = 0; i < 3; i++) { | |
1958 | data->reg_temp[i] = W83627EHF_REG_TEMP[i]; | |
1959 | data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i]; | |
1960 | data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i]; | |
1961 | data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i]; | |
1962 | } | |
a157d06d GJ |
1963 | } |
1964 | ||
ec3e5a16 | 1965 | if (sio_data->kind == nct6775) { |
26bc440e GR |
1966 | data->has_fan_div = true; |
1967 | data->fan_from_reg = fan_from_reg16; | |
1968 | data->fan_from_reg_min = fan_from_reg8; | |
ec3e5a16 GR |
1969 | data->REG_PWM = NCT6775_REG_PWM; |
1970 | data->REG_TARGET = NCT6775_REG_TARGET; | |
26bc440e | 1971 | data->REG_FAN = NCT6775_REG_FAN; |
ec3e5a16 GR |
1972 | data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN; |
1973 | data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT; | |
1974 | data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT; | |
1975 | data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME; | |
1976 | data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT; | |
1977 | data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT; | |
1978 | } else if (sio_data->kind == nct6776) { | |
26bc440e GR |
1979 | data->has_fan_div = false; |
1980 | data->fan_from_reg = fan_from_reg13; | |
1981 | data->fan_from_reg_min = fan_from_reg13; | |
ec3e5a16 GR |
1982 | data->REG_PWM = NCT6775_REG_PWM; |
1983 | data->REG_TARGET = NCT6775_REG_TARGET; | |
26bc440e | 1984 | data->REG_FAN = NCT6775_REG_FAN; |
ec3e5a16 GR |
1985 | data->REG_FAN_MIN = NCT6776_REG_FAN_MIN; |
1986 | data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT; | |
1987 | data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT; | |
1988 | data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME; | |
1989 | } else if (sio_data->kind == w83667hg_b) { | |
26bc440e GR |
1990 | data->has_fan_div = true; |
1991 | data->fan_from_reg = fan_from_reg8; | |
1992 | data->fan_from_reg_min = fan_from_reg8; | |
ec3e5a16 GR |
1993 | data->REG_PWM = W83627EHF_REG_PWM; |
1994 | data->REG_TARGET = W83627EHF_REG_TARGET; | |
1995 | data->REG_FAN = W83627EHF_REG_FAN; | |
1996 | data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN; | |
1997 | data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT; | |
1998 | data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT; | |
1999 | data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME; | |
c39aedaf GR |
2000 | data->REG_FAN_MAX_OUTPUT = |
2001 | W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B; | |
2002 | data->REG_FAN_STEP_OUTPUT = | |
2003 | W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B; | |
2004 | } else { | |
26bc440e GR |
2005 | data->has_fan_div = true; |
2006 | data->fan_from_reg = fan_from_reg8; | |
2007 | data->fan_from_reg_min = fan_from_reg8; | |
ec3e5a16 GR |
2008 | data->REG_PWM = W83627EHF_REG_PWM; |
2009 | data->REG_TARGET = W83627EHF_REG_TARGET; | |
2010 | data->REG_FAN = W83627EHF_REG_FAN; | |
2011 | data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN; | |
2012 | data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT; | |
2013 | data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT; | |
2014 | data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME; | |
c39aedaf GR |
2015 | data->REG_FAN_MAX_OUTPUT = |
2016 | W83627EHF_REG_FAN_MAX_OUTPUT_COMMON; | |
2017 | data->REG_FAN_STEP_OUTPUT = | |
2018 | W83627EHF_REG_FAN_STEP_OUTPUT_COMMON; | |
2019 | } | |
da2e0255 | 2020 | |
08e7e278 | 2021 | /* Initialize the chip */ |
1ea6dd38 | 2022 | w83627ehf_init_device(data); |
08e7e278 | 2023 | |
fc18d6c0 JD |
2024 | data->vrm = vid_which_vrm(); |
2025 | superio_enter(sio_data->sioreg); | |
fc18d6c0 | 2026 | /* Read VID value */ |
ec3e5a16 GR |
2027 | if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b || |
2028 | sio_data->kind == nct6775 || sio_data->kind == nct6776) { | |
237c8d2f GJ |
2029 | /* W83667HG has different pins for VID input and output, so |
2030 | we can get the VID input values directly at logical device D | |
2031 | 0xe3. */ | |
2032 | superio_select(sio_data->sioreg, W83667HG_LD_VID); | |
2033 | data->vid = superio_inb(sio_data->sioreg, 0xe3); | |
cbe311f2 JD |
2034 | err = device_create_file(dev, &dev_attr_cpu0_vid); |
2035 | if (err) | |
2036 | goto exit_release; | |
58e6e781 | 2037 | } else { |
237c8d2f GJ |
2038 | superio_select(sio_data->sioreg, W83627EHF_LD_HWM); |
2039 | if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) { | |
2040 | /* Set VID input sensibility if needed. In theory the | |
2041 | BIOS should have set it, but in practice it's not | |
2042 | always the case. We only do it for the W83627EHF/EHG | |
2043 | because the W83627DHG is more complex in this | |
2044 | respect. */ | |
2045 | if (sio_data->kind == w83627ehf) { | |
2046 | en_vrm10 = superio_inb(sio_data->sioreg, | |
2047 | SIO_REG_EN_VRM10); | |
2048 | if ((en_vrm10 & 0x08) && data->vrm == 90) { | |
2049 | dev_warn(dev, "Setting VID input " | |
2050 | "voltage to TTL\n"); | |
2051 | superio_outb(sio_data->sioreg, | |
2052 | SIO_REG_EN_VRM10, | |
2053 | en_vrm10 & ~0x08); | |
2054 | } else if (!(en_vrm10 & 0x08) | |
2055 | && data->vrm == 100) { | |
2056 | dev_warn(dev, "Setting VID input " | |
2057 | "voltage to VRM10\n"); | |
2058 | superio_outb(sio_data->sioreg, | |
2059 | SIO_REG_EN_VRM10, | |
2060 | en_vrm10 | 0x08); | |
2061 | } | |
2062 | } | |
2063 | ||
2064 | data->vid = superio_inb(sio_data->sioreg, | |
2065 | SIO_REG_VID_DATA); | |
2066 | if (sio_data->kind == w83627ehf) /* 6 VID pins only */ | |
2067 | data->vid &= 0x3f; | |
2068 | ||
2069 | err = device_create_file(dev, &dev_attr_cpu0_vid); | |
2070 | if (err) | |
2071 | goto exit_release; | |
2072 | } else { | |
2073 | dev_info(dev, "VID pins in output mode, CPU VID not " | |
2074 | "available\n"); | |
2075 | } | |
fc18d6c0 JD |
2076 | } |
2077 | ||
08c79950 | 2078 | /* fan4 and fan5 share some pins with the GPIO and serial flash */ |
ec3e5a16 GR |
2079 | if (sio_data->kind == nct6775) { |
2080 | /* On NCT6775, fan4 shares pins with the fdc interface */ | |
2081 | fan3pin = 1; | |
2082 | fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80); | |
2083 | fan4min = 0; | |
2084 | fan5pin = 0; | |
2085 | } else if (sio_data->kind == nct6776) { | |
2086 | fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40); | |
2087 | fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01); | |
2088 | fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02); | |
2089 | fan4min = fan4pin; | |
2090 | } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) { | |
2091 | fan3pin = 1; | |
237c8d2f | 2092 | fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40; |
ec3e5a16 GR |
2093 | fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20; |
2094 | fan4min = fan4pin; | |
237c8d2f | 2095 | } else { |
ec3e5a16 | 2096 | fan3pin = 1; |
237c8d2f | 2097 | fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06); |
ec3e5a16 GR |
2098 | fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02); |
2099 | fan4min = fan4pin; | |
237c8d2f | 2100 | } |
1ea6dd38 | 2101 | superio_exit(sio_data->sioreg); |
08c79950 | 2102 | |
08e7e278 | 2103 | /* It looks like fan4 and fan5 pins can be alternatively used |
14992c7e RM |
2104 | as fan on/off switches, but fan5 control is write only :/ |
2105 | We assume that if the serial interface is disabled, designers | |
2106 | connected fan5 as input unless they are emitting log 1, which | |
2107 | is not the default. */ | |
08c79950 | 2108 | |
ec3e5a16 GR |
2109 | data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */ |
2110 | ||
2111 | data->has_fan |= (fan3pin << 2); | |
2112 | data->has_fan_min |= (fan3pin << 2); | |
2113 | ||
2114 | /* | |
2115 | * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1 register | |
2116 | */ | |
2117 | if (sio_data->kind == nct6775 || sio_data->kind == nct6776) { | |
2118 | data->has_fan |= (fan4pin << 3) | (fan5pin << 4); | |
2119 | data->has_fan_min |= (fan4min << 3) | (fan5pin << 4); | |
2120 | } else { | |
2121 | i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1); | |
2122 | if ((i & (1 << 2)) && fan4pin) { | |
2123 | data->has_fan |= (1 << 3); | |
2124 | data->has_fan_min |= (1 << 3); | |
2125 | } | |
2126 | if (!(i & (1 << 1)) && fan5pin) { | |
2127 | data->has_fan |= (1 << 4); | |
2128 | data->has_fan_min |= (1 << 4); | |
2129 | } | |
2130 | } | |
08e7e278 | 2131 | |
ea7be66c | 2132 | /* Read fan clock dividers immediately */ |
ec3e5a16 GR |
2133 | w83627ehf_update_fan_div_common(dev, data); |
2134 | ||
2135 | /* Read pwm data to save original values */ | |
2136 | w83627ehf_update_pwm_common(dev, data); | |
2137 | for (i = 0; i < data->pwm_num; i++) | |
2138 | data->pwm_enable_orig[i] = data->pwm_enable[i]; | |
ea7be66c | 2139 | |
b84bb518 GR |
2140 | /* Read pwm data to save original values */ |
2141 | w83627ehf_update_pwm_common(dev, data); | |
2142 | for (i = 0; i < data->pwm_num; i++) | |
2143 | data->pwm_enable_orig[i] = data->pwm_enable[i]; | |
2144 | ||
08e7e278 | 2145 | /* Register sysfs hooks */ |
e7e1ca6e GR |
2146 | for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) { |
2147 | err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr); | |
2148 | if (err) | |
c18beb5b | 2149 | goto exit_remove; |
e7e1ca6e | 2150 | } |
08c79950 | 2151 | |
da2e0255 GR |
2152 | for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) { |
2153 | struct sensor_device_attribute *attr = | |
2154 | &sda_sf3_max_step_arrays[i]; | |
ec3e5a16 GR |
2155 | if (data->REG_FAN_STEP_OUTPUT && |
2156 | data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) { | |
da2e0255 GR |
2157 | err = device_create_file(dev, &attr->dev_attr); |
2158 | if (err) | |
2159 | goto exit_remove; | |
2160 | } | |
2161 | } | |
08c79950 | 2162 | /* if fan4 is enabled create the sf3 files for it */ |
237c8d2f | 2163 | if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4) |
c18beb5b | 2164 | for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) { |
e7e1ca6e GR |
2165 | err = device_create_file(dev, |
2166 | &sda_sf3_arrays_fan4[i].dev_attr); | |
2167 | if (err) | |
c18beb5b DH |
2168 | goto exit_remove; |
2169 | } | |
08c79950 | 2170 | |
a157d06d GJ |
2171 | for (i = 0; i < data->in_num; i++) { |
2172 | if ((i == 6) && data->in6_skip) | |
2173 | continue; | |
c18beb5b DH |
2174 | if ((err = device_create_file(dev, &sda_in_input[i].dev_attr)) |
2175 | || (err = device_create_file(dev, | |
2176 | &sda_in_alarm[i].dev_attr)) | |
2177 | || (err = device_create_file(dev, | |
2178 | &sda_in_min[i].dev_attr)) | |
2179 | || (err = device_create_file(dev, | |
2180 | &sda_in_max[i].dev_attr))) | |
2181 | goto exit_remove; | |
a157d06d | 2182 | } |
cf0676fe | 2183 | |
412fec82 | 2184 | for (i = 0; i < 5; i++) { |
08c79950 | 2185 | if (data->has_fan & (1 << i)) { |
c18beb5b DH |
2186 | if ((err = device_create_file(dev, |
2187 | &sda_fan_input[i].dev_attr)) | |
2188 | || (err = device_create_file(dev, | |
ec3e5a16 | 2189 | &sda_fan_alarm[i].dev_attr))) |
c18beb5b | 2190 | goto exit_remove; |
ec3e5a16 GR |
2191 | if (sio_data->kind != nct6776) { |
2192 | err = device_create_file(dev, | |
2193 | &sda_fan_div[i].dev_attr); | |
2194 | if (err) | |
2195 | goto exit_remove; | |
2196 | } | |
2197 | if (data->has_fan_min & (1 << i)) { | |
2198 | err = device_create_file(dev, | |
2199 | &sda_fan_min[i].dev_attr); | |
2200 | if (err) | |
2201 | goto exit_remove; | |
2202 | } | |
237c8d2f | 2203 | if (i < data->pwm_num && |
c18beb5b DH |
2204 | ((err = device_create_file(dev, |
2205 | &sda_pwm[i].dev_attr)) | |
2206 | || (err = device_create_file(dev, | |
2207 | &sda_pwm_mode[i].dev_attr)) | |
2208 | || (err = device_create_file(dev, | |
2209 | &sda_pwm_enable[i].dev_attr)) | |
2210 | || (err = device_create_file(dev, | |
2211 | &sda_target_temp[i].dev_attr)) | |
2212 | || (err = device_create_file(dev, | |
2213 | &sda_tolerance[i].dev_attr)))) | |
2214 | goto exit_remove; | |
08c79950 | 2215 | } |
08e7e278 | 2216 | } |
08c79950 | 2217 | |
d36cf32c GR |
2218 | for (i = 0; i < NUM_REG_TEMP; i++) { |
2219 | if (!(data->have_temp & (1 << i))) | |
a157d06d | 2220 | continue; |
d36cf32c GR |
2221 | err = device_create_file(dev, &sda_temp_input[i].dev_attr); |
2222 | if (err) | |
2223 | goto exit_remove; | |
2224 | if (data->temp_label) { | |
2225 | err = device_create_file(dev, | |
2226 | &sda_temp_label[i].dev_attr); | |
2227 | if (err) | |
2228 | goto exit_remove; | |
2229 | } | |
ec3e5a16 GR |
2230 | if (data->reg_temp_over[i]) { |
2231 | err = device_create_file(dev, | |
2232 | &sda_temp_max[i].dev_attr); | |
2233 | if (err) | |
2234 | goto exit_remove; | |
2235 | } | |
2236 | if (data->reg_temp_hyst[i]) { | |
2237 | err = device_create_file(dev, | |
2238 | &sda_temp_max_hyst[i].dev_attr); | |
2239 | if (err) | |
2240 | goto exit_remove; | |
2241 | } | |
d36cf32c | 2242 | if (i > 2) |
ec3e5a16 GR |
2243 | continue; |
2244 | if ((err = device_create_file(dev, | |
a157d06d GJ |
2245 | &sda_temp_alarm[i].dev_attr)) |
2246 | || (err = device_create_file(dev, | |
2247 | &sda_temp_type[i].dev_attr))) | |
c18beb5b | 2248 | goto exit_remove; |
a157d06d | 2249 | } |
c18beb5b | 2250 | |
1ea6dd38 DH |
2251 | err = device_create_file(dev, &dev_attr_name); |
2252 | if (err) | |
2253 | goto exit_remove; | |
2254 | ||
1beeffe4 TJ |
2255 | data->hwmon_dev = hwmon_device_register(dev); |
2256 | if (IS_ERR(data->hwmon_dev)) { | |
2257 | err = PTR_ERR(data->hwmon_dev); | |
c18beb5b DH |
2258 | goto exit_remove; |
2259 | } | |
08e7e278 JD |
2260 | |
2261 | return 0; | |
2262 | ||
c18beb5b DH |
2263 | exit_remove: |
2264 | w83627ehf_device_remove_files(dev); | |
08e7e278 | 2265 | kfree(data); |
1ea6dd38 | 2266 | platform_set_drvdata(pdev, NULL); |
08e7e278 | 2267 | exit_release: |
1ea6dd38 | 2268 | release_region(res->start, IOREGION_LENGTH); |
08e7e278 JD |
2269 | exit: |
2270 | return err; | |
2271 | } | |
2272 | ||
1ea6dd38 | 2273 | static int __devexit w83627ehf_remove(struct platform_device *pdev) |
08e7e278 | 2274 | { |
1ea6dd38 | 2275 | struct w83627ehf_data *data = platform_get_drvdata(pdev); |
08e7e278 | 2276 | |
1beeffe4 | 2277 | hwmon_device_unregister(data->hwmon_dev); |
1ea6dd38 DH |
2278 | w83627ehf_device_remove_files(&pdev->dev); |
2279 | release_region(data->addr, IOREGION_LENGTH); | |
2280 | platform_set_drvdata(pdev, NULL); | |
943b0830 | 2281 | kfree(data); |
08e7e278 JD |
2282 | |
2283 | return 0; | |
2284 | } | |
2285 | ||
1ea6dd38 | 2286 | static struct platform_driver w83627ehf_driver = { |
cdaf7934 | 2287 | .driver = { |
87218842 | 2288 | .owner = THIS_MODULE, |
1ea6dd38 | 2289 | .name = DRVNAME, |
cdaf7934 | 2290 | }, |
1ea6dd38 DH |
2291 | .probe = w83627ehf_probe, |
2292 | .remove = __devexit_p(w83627ehf_remove), | |
08e7e278 JD |
2293 | }; |
2294 | ||
1ea6dd38 DH |
2295 | /* w83627ehf_find() looks for a '627 in the Super-I/O config space */ |
2296 | static int __init w83627ehf_find(int sioaddr, unsigned short *addr, | |
2297 | struct w83627ehf_sio_data *sio_data) | |
08e7e278 | 2298 | { |
1ea6dd38 DH |
2299 | static const char __initdata sio_name_W83627EHF[] = "W83627EHF"; |
2300 | static const char __initdata sio_name_W83627EHG[] = "W83627EHG"; | |
2301 | static const char __initdata sio_name_W83627DHG[] = "W83627DHG"; | |
c1e48dce | 2302 | static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P"; |
237c8d2f | 2303 | static const char __initdata sio_name_W83667HG[] = "W83667HG"; |
c39aedaf | 2304 | static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B"; |
ec3e5a16 GR |
2305 | static const char __initdata sio_name_NCT6775[] = "NCT6775F"; |
2306 | static const char __initdata sio_name_NCT6776[] = "NCT6776F"; | |
1ea6dd38 | 2307 | |
08e7e278 | 2308 | u16 val; |
1ea6dd38 | 2309 | const char *sio_name; |
08e7e278 | 2310 | |
1ea6dd38 | 2311 | superio_enter(sioaddr); |
08e7e278 | 2312 | |
67b671bc JD |
2313 | if (force_id) |
2314 | val = force_id; | |
2315 | else | |
2316 | val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) | |
2317 | | superio_inb(sioaddr, SIO_REG_DEVID + 1); | |
657c93b1 | 2318 | switch (val & SIO_ID_MASK) { |
657c93b1 | 2319 | case SIO_W83627EHF_ID: |
1ea6dd38 DH |
2320 | sio_data->kind = w83627ehf; |
2321 | sio_name = sio_name_W83627EHF; | |
2322 | break; | |
657c93b1 | 2323 | case SIO_W83627EHG_ID: |
1ea6dd38 DH |
2324 | sio_data->kind = w83627ehf; |
2325 | sio_name = sio_name_W83627EHG; | |
2326 | break; | |
2327 | case SIO_W83627DHG_ID: | |
2328 | sio_data->kind = w83627dhg; | |
2329 | sio_name = sio_name_W83627DHG; | |
657c93b1 | 2330 | break; |
c1e48dce JD |
2331 | case SIO_W83627DHG_P_ID: |
2332 | sio_data->kind = w83627dhg_p; | |
2333 | sio_name = sio_name_W83627DHG_P; | |
2334 | break; | |
237c8d2f GJ |
2335 | case SIO_W83667HG_ID: |
2336 | sio_data->kind = w83667hg; | |
2337 | sio_name = sio_name_W83667HG; | |
2338 | break; | |
c39aedaf GR |
2339 | case SIO_W83667HG_B_ID: |
2340 | sio_data->kind = w83667hg_b; | |
2341 | sio_name = sio_name_W83667HG_B; | |
2342 | break; | |
ec3e5a16 GR |
2343 | case SIO_NCT6775_ID: |
2344 | sio_data->kind = nct6775; | |
2345 | sio_name = sio_name_NCT6775; | |
2346 | break; | |
2347 | case SIO_NCT6776_ID: | |
2348 | sio_data->kind = nct6776; | |
2349 | sio_name = sio_name_NCT6776; | |
2350 | break; | |
657c93b1 | 2351 | default: |
9f66036b | 2352 | if (val != 0xffff) |
abdc6fd1 | 2353 | pr_debug("unsupported chip ID: 0x%04x\n", val); |
1ea6dd38 | 2354 | superio_exit(sioaddr); |
08e7e278 JD |
2355 | return -ENODEV; |
2356 | } | |
2357 | ||
1ea6dd38 DH |
2358 | /* We have a known chip, find the HWM I/O address */ |
2359 | superio_select(sioaddr, W83627EHF_LD_HWM); | |
2360 | val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8) | |
2361 | | superio_inb(sioaddr, SIO_REG_ADDR + 1); | |
1a641fce | 2362 | *addr = val & IOREGION_ALIGNMENT; |
2d8672c5 | 2363 | if (*addr == 0) { |
abdc6fd1 | 2364 | pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n"); |
1ea6dd38 | 2365 | superio_exit(sioaddr); |
08e7e278 JD |
2366 | return -ENODEV; |
2367 | } | |
2368 | ||
2369 | /* Activate logical device if needed */ | |
1ea6dd38 | 2370 | val = superio_inb(sioaddr, SIO_REG_ENABLE); |
475ef855 | 2371 | if (!(val & 0x01)) { |
e7e1ca6e GR |
2372 | pr_warn("Forcibly enabling Super-I/O. " |
2373 | "Sensor is probably unusable.\n"); | |
1ea6dd38 | 2374 | superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01); |
475ef855 | 2375 | } |
1ea6dd38 DH |
2376 | |
2377 | superio_exit(sioaddr); | |
abdc6fd1 | 2378 | pr_info("Found %s chip at %#x\n", sio_name, *addr); |
1ea6dd38 | 2379 | sio_data->sioreg = sioaddr; |
08e7e278 | 2380 | |
08e7e278 JD |
2381 | return 0; |
2382 | } | |
2383 | ||
1ea6dd38 DH |
2384 | /* when Super-I/O functions move to a separate file, the Super-I/O |
2385 | * bus will manage the lifetime of the device and this module will only keep | |
2386 | * track of the w83627ehf driver. But since we platform_device_alloc(), we | |
2387 | * must keep track of the device */ | |
2388 | static struct platform_device *pdev; | |
2389 | ||
08e7e278 JD |
2390 | static int __init sensors_w83627ehf_init(void) |
2391 | { | |
1ea6dd38 DH |
2392 | int err; |
2393 | unsigned short address; | |
2394 | struct resource res; | |
2395 | struct w83627ehf_sio_data sio_data; | |
2396 | ||
2397 | /* initialize sio_data->kind and sio_data->sioreg. | |
2398 | * | |
2399 | * when Super-I/O functions move to a separate file, the Super-I/O | |
2400 | * driver will probe 0x2e and 0x4e and auto-detect the presence of a | |
2401 | * w83627ehf hardware monitor, and call probe() */ | |
2402 | if (w83627ehf_find(0x2e, &address, &sio_data) && | |
2403 | w83627ehf_find(0x4e, &address, &sio_data)) | |
08e7e278 JD |
2404 | return -ENODEV; |
2405 | ||
1ea6dd38 DH |
2406 | err = platform_driver_register(&w83627ehf_driver); |
2407 | if (err) | |
2408 | goto exit; | |
2409 | ||
e7e1ca6e GR |
2410 | pdev = platform_device_alloc(DRVNAME, address); |
2411 | if (!pdev) { | |
1ea6dd38 | 2412 | err = -ENOMEM; |
abdc6fd1 | 2413 | pr_err("Device allocation failed\n"); |
1ea6dd38 DH |
2414 | goto exit_unregister; |
2415 | } | |
2416 | ||
2417 | err = platform_device_add_data(pdev, &sio_data, | |
2418 | sizeof(struct w83627ehf_sio_data)); | |
2419 | if (err) { | |
abdc6fd1 | 2420 | pr_err("Platform data allocation failed\n"); |
1ea6dd38 DH |
2421 | goto exit_device_put; |
2422 | } | |
2423 | ||
2424 | memset(&res, 0, sizeof(res)); | |
2425 | res.name = DRVNAME; | |
2426 | res.start = address + IOREGION_OFFSET; | |
2427 | res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1; | |
2428 | res.flags = IORESOURCE_IO; | |
b9acb64a JD |
2429 | |
2430 | err = acpi_check_resource_conflict(&res); | |
2431 | if (err) | |
18632f84 | 2432 | goto exit_device_put; |
b9acb64a | 2433 | |
1ea6dd38 DH |
2434 | err = platform_device_add_resources(pdev, &res, 1); |
2435 | if (err) { | |
abdc6fd1 | 2436 | pr_err("Device resource addition failed (%d)\n", err); |
1ea6dd38 DH |
2437 | goto exit_device_put; |
2438 | } | |
2439 | ||
2440 | /* platform_device_add calls probe() */ | |
2441 | err = platform_device_add(pdev); | |
2442 | if (err) { | |
abdc6fd1 | 2443 | pr_err("Device addition failed (%d)\n", err); |
1ea6dd38 DH |
2444 | goto exit_device_put; |
2445 | } | |
2446 | ||
2447 | return 0; | |
2448 | ||
2449 | exit_device_put: | |
2450 | platform_device_put(pdev); | |
2451 | exit_unregister: | |
2452 | platform_driver_unregister(&w83627ehf_driver); | |
2453 | exit: | |
2454 | return err; | |
08e7e278 JD |
2455 | } |
2456 | ||
2457 | static void __exit sensors_w83627ehf_exit(void) | |
2458 | { | |
1ea6dd38 DH |
2459 | platform_device_unregister(pdev); |
2460 | platform_driver_unregister(&w83627ehf_driver); | |
08e7e278 JD |
2461 | } |
2462 | ||
2463 | MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>"); | |
2464 | MODULE_DESCRIPTION("W83627EHF driver"); | |
2465 | MODULE_LICENSE("GPL"); | |
2466 | ||
2467 | module_init(sensors_w83627ehf_init); | |
2468 | module_exit(sensors_w83627ehf_exit); |