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hwmon: (tmp401) Use regmap
[linux-block.git] / drivers / hwmon / tmp401.c
CommitLineData
74ba9207 1// SPDX-License-Identifier: GPL-2.0-or-later
ab2b79d5
HG		 2/* tmp401.c
3 *
4 * Copyright (C) 2007,2008 Hans de Goede <hdegoede@redhat.com>
fce0758f
AP		 5 * Preliminary tmp411 support by:
6 * Gabriel Konat, Sander Leget, Wouter Willems
7 * Copyright (C) 2009 Andre Prendel <andre.prendel@gmx.de>
ab2b79d5 8 *
29dd3b64
GR		 9 * Cleanup and support for TMP431 and TMP432 by Guenter Roeck
10 * Copyright (c) 2013 Guenter Roeck <linux@roeck-us.net>
ab2b79d5
HG		 11 */
12
13/*
14 * Driver for the Texas Instruments TMP401 SMBUS temperature sensor IC.
15 *
16 * Note this IC is in some aspect similar to the LM90, but it has quite a
17 * few differences too, for example the local temp has a higher resolution
18 * and thus has 16 bits registers for its value and limit instead of 8 bits.
19 */
20
947e9271 21#include <linux/bitops.h>
ca53e764 22#include <linux/err.h>
ab2b79d5
HG		 23#include <linux/i2c.h>
24#include <linux/hwmon.h>
ca53e764
GR		 25#include <linux/init.h>
26#include <linux/module.h>
ab2b79d5 27#include <linux/mutex.h>
50152fb6 28#include <linux/regmap.h>
ca53e764 29#include <linux/slab.h>
ab2b79d5
HG		 30
31/* Addresses to scan */
9aecac04 32static const unsigned short normal_i2c[] = { 0x48, 0x49, 0x4a, 0x4c, 0x4d,
907a6d58 33 0x4e, 0x4f, I2C_CLIENT_END };
ab2b79d5 34
38d9f06c 35enum chips { tmp401, tmp411, tmp431, tmp432, tmp435 };
ab2b79d5
HG		 36
37/*
38 * The TMP401 registers, note some registers have different addresses for
39 * reading and writing
40 */
41#define TMP401_STATUS 0x02
42#define TMP401_CONFIG_READ 0x03
43#define TMP401_CONFIG_WRITE 0x09
44#define TMP401_CONVERSION_RATE_READ 0x04
45#define TMP401_CONVERSION_RATE_WRITE 0x0A
46#define TMP401_TEMP_CRIT_HYST 0x21
ab2b79d5
HG		 47#define TMP401_MANUFACTURER_ID_REG 0xFE
48#define TMP401_DEVICE_ID_REG 0xFF
49
bcb31e68 50static const u8 TMP401_TEMP_MSB_READ[7][3] = {
29dd3b64
GR		 51 { 0x00, 0x01, 0x23 }, /* temp */
52 { 0x06, 0x08, 0x16 }, /* low limit */
53 { 0x05, 0x07, 0x15 }, /* high limit */
bcb31e68
GR		 54 { 0x20, 0x19, 0x1a }, /* therm (crit) limit */
55 { 0x30, 0x34, 0x00 }, /* lowest */
ca53e764 56 { 0x32, 0xf6, 0x00 }, /* highest */
29dd3b64
GR		 57};
58
bcb31e68
GR		 59static const u8 TMP401_TEMP_MSB_WRITE[7][3] = {
60 { 0x00, 0x00, 0x00 }, /* temp (unused) */
29dd3b64
GR		 61 { 0x0C, 0x0E, 0x16 }, /* low limit */
62 { 0x0B, 0x0D, 0x15 }, /* high limit */
bcb31e68
GR		 63 { 0x20, 0x19, 0x1a }, /* therm (crit) limit */
64 { 0x30, 0x34, 0x00 }, /* lowest */
ca53e764 65 { 0x32, 0xf6, 0x00 }, /* highest */
29dd3b64
GR		 66};
67
29dd3b64
GR		 68/* [0] = fault, [1] = low, [2] = high, [3] = therm/crit */
69static const u8 TMP432_STATUS_REG[] = {
70 0x1b, 0x36, 0x35, 0x37 };
71
ab2b79d5 72/* Flags */
947e9271
GR		 73#define TMP401_CONFIG_RANGE BIT(2)
74#define TMP401_CONFIG_SHUTDOWN BIT(6)
75#define TMP401_STATUS_LOCAL_CRIT BIT(0)
76#define TMP401_STATUS_REMOTE_CRIT BIT(1)
77#define TMP401_STATUS_REMOTE_OPEN BIT(2)
78#define TMP401_STATUS_REMOTE_LOW BIT(3)
79#define TMP401_STATUS_REMOTE_HIGH BIT(4)
80#define TMP401_STATUS_LOCAL_LOW BIT(5)
81#define TMP401_STATUS_LOCAL_HIGH BIT(6)
ab2b79d5 82
29dd3b64
GR		 83/* On TMP432, each status has its own register */
84#define TMP432_STATUS_LOCAL BIT(0)
85#define TMP432_STATUS_REMOTE1 BIT(1)
86#define TMP432_STATUS_REMOTE2 BIT(2)
87
ab2b79d5
HG		 88/* Manufacturer / Device ID's */
89#define TMP401_MANUFACTURER_ID 0x55
90#define TMP401_DEVICE_ID 0x11
4ce5b1fe
GR		 91#define TMP411A_DEVICE_ID 0x12
92#define TMP411B_DEVICE_ID 0x13
93#define TMP411C_DEVICE_ID 0x10
a1fac92b 94#define TMP431_DEVICE_ID 0x31
29dd3b64 95#define TMP432_DEVICE_ID 0x32
06adbaec 96#define TMP435_DEVICE_ID 0x35
ab2b79d5 97
ab2b79d5
HG		 98/*
99 * Driver data (common to all clients)
100 */
101
102static const struct i2c_device_id tmp401_id[] = {
103 { "tmp401", tmp401 },
fce0758f 104 { "tmp411", tmp411 },
a1fac92b 105 { "tmp431", tmp431 },
29dd3b64 106 { "tmp432", tmp432 },
06adbaec 107 { "tmp435", tmp435 },
ab2b79d5
HG		 108 { }
109};
110MODULE_DEVICE_TABLE(i2c, tmp401_id);
111
ab2b79d5
HG		 112/*
113 * Client data (each client gets its own)
114 */
115
116struct tmp401_data {
f3643ac7 117 struct i2c_client *client;
50152fb6 118 struct regmap *regmap;
ab2b79d5 119 struct mutex update_lock;
dc71afe5 120 enum chips kind;
ab2b79d5 121
ca53e764 122 bool extended_range;
0846e30d 123
ca53e764
GR		 124 /* hwmon API configuration data */
125 u32 chip_channel_config[4];
126 struct hwmon_channel_info chip_info;
127 u32 temp_channel_config[4];
128 struct hwmon_channel_info temp_info;
129 const struct hwmon_channel_info *info[3];
130 struct hwmon_chip_info chip;
ab2b79d5
HG		 131};
132
50152fb6 133/* regmap */
ab2b79d5 134
50152fb6 135static bool tmp401_regmap_is_volatile(struct device *dev, unsigned int reg)
ab2b79d5 136{
50152fb6
GR		 137 switch (reg) {
138 case 0: /* local temp msb */
139 case 1: /* remote temp msb */
140 case 2: /* status */
141 case 0x10: /* remote temp lsb */
142 case 0x15: /* local temp lsb */
143 case 0x1b: /* status (tmp432) */
144 case 0x23 ... 0x24: /* remote temp 2 msb / lsb */
145 case 0x30 ... 0x37: /* lowest/highest temp; status (tmp432) */
146 return true;
147 default:
148 return false;
ca53e764 149 }
ab2b79d5
HG		 150}
151
50152fb6 152static int tmp401_reg_read(void *context, unsigned int reg, unsigned int *val)
ea63c2b9 153{
50152fb6 154 struct tmp401_data *data = context;
f3643ac7 155 struct i2c_client *client = data->client;
50152fb6 156 int regval;
ea63c2b9 157
ca53e764
GR		 158 switch (reg) {
159 case 0: /* local temp msb */
160 case 1: /* remote temp msb */
161 case 5: /* local temp high limit msb */
162 case 6: /* local temp low limit msb */
163 case 7: /* remote temp ligh limit msb */
164 case 8: /* remote temp low limit msb */
165 case 0x15: /* remote temp 2 high limit msb */
166 case 0x16: /* remote temp 2 low limit msb */
167 case 0x23: /* remote temp 2 msb */
168 case 0x30: /* local temp minimum, tmp411 */
169 case 0x32: /* local temp maximum, tmp411 */
170 case 0x34: /* remote temp minimum, tmp411 */
171 case 0xf6: /* remote temp maximum, tmp411 (really 0x36) */
172 /* work around register overlap between TMP411 and TMP432 */
173 if (reg == 0xf6)
174 reg = 0x36;
50152fb6
GR		 175 regval = i2c_smbus_read_word_swapped(client, reg);
176 if (regval < 0)
177 return regval;
178 *val = regval;
179 break;
ca53e764
GR		 180 case 0x19: /* critical limits, 8-bit registers */
181 case 0x1a:
182 case 0x20:
183 regval = i2c_smbus_read_byte_data(client, reg);
184 if (regval < 0)
185 return regval;
50152fb6
GR		 186 *val = regval << 8;
187 break;
ca53e764
GR		 188 case 0x1b:
189 case 0x35 ... 0x37:
50152fb6
GR		 190 if (data->kind == tmp432) {
191 regval = i2c_smbus_read_byte_data(client, reg);
192 if (regval < 0)
193 return regval;
194 *val = regval;
195 break;
196 }
ca53e764
GR		 197 /* simulate TMP432 status registers */
198 regval = i2c_smbus_read_byte_data(client, TMP401_STATUS);
199 if (regval < 0)
200 return regval;
50152fb6 201 *val = 0;
ca53e764
GR		 202 switch (reg) {
203 case 0x1b: /* open / fault */
204 if (regval & TMP401_STATUS_REMOTE_OPEN)
50152fb6 205 *val |= BIT(1);
ca53e764
GR		 206 break;
207 case 0x35: /* high limit */
208 if (regval & TMP401_STATUS_LOCAL_HIGH)
50152fb6 209 *val |= BIT(0);
ca53e764 210 if (regval & TMP401_STATUS_REMOTE_HIGH)
50152fb6 211 *val |= BIT(1);
ca53e764
GR		 212 break;
213 case 0x36: /* low limit */
214 if (regval & TMP401_STATUS_LOCAL_LOW)
50152fb6 215 *val |= BIT(0);
ca53e764 216 if (regval & TMP401_STATUS_REMOTE_LOW)
50152fb6 217 *val |= BIT(1);
ca53e764
GR		 218 break;
219 case 0x37: /* therm / crit limit */
220 if (regval & TMP401_STATUS_LOCAL_CRIT)
50152fb6 221 *val |= BIT(0);
ca53e764 222 if (regval & TMP401_STATUS_REMOTE_CRIT)
50152fb6 223 *val |= BIT(1);
ca53e764 224 break;
14f2a665 225 }
50152fb6 226 break;
ca53e764 227 default:
50152fb6
GR		 228 regval = i2c_smbus_read_byte_data(client, reg);
229 if (regval < 0)
230 return regval;
231 *val = regval;
232 break;
ea63c2b9 233 }
50152fb6 234 return 0;
ab2b79d5
HG		 235}
236
50152fb6 237static int tmp401_reg_write(void *context, unsigned int reg, unsigned int val)
ab2b79d5 238{
50152fb6 239 struct tmp401_data *data = context;
ca53e764 240 struct i2c_client *client = data->client;
ab2b79d5 241
ca53e764
GR		 242 switch (reg) {
243 case 0x0b: /* local temp high limit msb */
244 case 0x0c: /* local temp low limit msb */
245 case 0x0d: /* remote temp ligh limit msb */
246 case 0x0e: /* remote temp low limit msb */
247 case 0x15: /* remote temp 2 high limit msb */
248 case 0x16: /* remote temp 2 low limit msb */
249 return i2c_smbus_write_word_swapped(client, reg, val);
250 case 0x19: /* critical limits, 8-bit registers */
251 case 0x1a:
252 case 0x20:
253 return i2c_smbus_write_byte_data(client, reg, val >> 8);
254 default:
255 return i2c_smbus_write_byte_data(client, reg, val);
256 }
ab2b79d5
HG		 257}
258
50152fb6
GR		 259static const struct regmap_config tmp401_regmap_config = {
260 .reg_bits = 8,
261 .val_bits = 16,
262 .cache_type = REGCACHE_RBTREE,
263 .volatile_reg = tmp401_regmap_is_volatile,
264 .reg_read = tmp401_reg_read,
265 .reg_write = tmp401_reg_write,
266};
267
268/* temperature conversion */
269
270static int tmp401_register_to_temp(u16 reg, bool extended)
271{
272 int temp = reg;
273
274 if (extended)
275 temp -= 64 * 256;
276
277 return DIV_ROUND_CLOSEST(temp * 125, 32);
278}
279
280static u16 tmp401_temp_to_register(long temp, bool extended, int zbits)
281{
282 if (extended) {
283 temp = clamp_val(temp, -64000, 191000);
284 temp += 64000;
285 } else {
286 temp = clamp_val(temp, 0, 127000);
287 }
288
289 return DIV_ROUND_CLOSEST(temp * (1 << (8 - zbits)), 1000) << zbits;
290}
291
292/* hwmon API functions */
293
ca53e764
GR		 294static const u8 tmp401_temp_reg_index[] = {
295 [hwmon_temp_input] = 0,
296 [hwmon_temp_min] = 1,
297 [hwmon_temp_max] = 2,
298 [hwmon_temp_crit] = 3,
299 [hwmon_temp_lowest] = 4,
300 [hwmon_temp_highest] = 5,
301};
ab2b79d5 302
ca53e764
GR		 303static const u8 tmp401_status_reg_index[] = {
304 [hwmon_temp_fault] = 0,
305 [hwmon_temp_min_alarm] = 1,
306 [hwmon_temp_max_alarm] = 2,
307 [hwmon_temp_crit_alarm] = 3,
308};
ab2b79d5 309
ca53e764 310static int tmp401_temp_read(struct device *dev, u32 attr, int channel, long *val)
ab2b79d5 311{
f3643ac7 312 struct tmp401_data *data = dev_get_drvdata(dev);
50152fb6
GR		 313 struct regmap *regmap = data->regmap;
314 unsigned int regval;
315 int reg, ret;
ca53e764
GR		 316
317 switch (attr) {
318 case hwmon_temp_input:
319 case hwmon_temp_min:
320 case hwmon_temp_max:
321 case hwmon_temp_crit:
322 case hwmon_temp_lowest:
323 case hwmon_temp_highest:
324 reg = TMP401_TEMP_MSB_READ[tmp401_temp_reg_index[attr]][channel];
50152fb6
GR		 325 ret = regmap_read(regmap, reg, &regval);
326 if (ret < 0)
327 return ret;
ca53e764
GR		 328 *val = tmp401_register_to_temp(regval, data->extended_range);
329 break;
330 case hwmon_temp_crit_hyst:
331 mutex_lock(&data->update_lock);
332 reg = TMP401_TEMP_MSB_READ[3][channel];
50152fb6
GR		 333 ret = regmap_read(regmap, reg, &regval);
334 if (ret < 0)
ca53e764
GR		 335 goto unlock;
336 *val = tmp401_register_to_temp(regval, data->extended_range);
50152fb6
GR		 337 ret = regmap_read(regmap, TMP401_TEMP_CRIT_HYST, &regval);
338 if (ret < 0)
ca53e764
GR		 339 goto unlock;
340 *val -= regval * 1000;
ca53e764
GR		 341unlock:
342 mutex_unlock(&data->update_lock);
50152fb6
GR		 343 if (ret < 0)
344 return ret;
ca53e764
GR		 345 break;
346 case hwmon_temp_fault:
347 case hwmon_temp_min_alarm:
348 case hwmon_temp_max_alarm:
349 case hwmon_temp_crit_alarm:
350 reg = TMP432_STATUS_REG[tmp401_status_reg_index[attr]];
50152fb6
GR		 351 ret = regmap_read(regmap, reg, &regval);
352 if (ret < 0)
353 return ret;
ca53e764
GR		 354 *val = !!(regval & BIT(channel));
355 break;
356 default:
357 return -EOPNOTSUPP;
14f2a665 358 }
ca53e764 359 return 0;
ab2b79d5
HG		 360}
361
ca53e764
GR		 362static int tmp401_temp_write(struct device *dev, u32 attr, int channel,
363 long val)
fce0758f 364{
f3643ac7 365 struct tmp401_data *data = dev_get_drvdata(dev);
50152fb6
GR		 366 struct regmap *regmap = data->regmap;
367 unsigned int regval;
368 int reg, ret, temp;
fce0758f 369
8eb6d90f 370 mutex_lock(&data->update_lock);
ca53e764
GR		 371 switch (attr) {
372 case hwmon_temp_min:
373 case hwmon_temp_max:
374 case hwmon_temp_crit:
375 reg = TMP401_TEMP_MSB_WRITE[tmp401_temp_reg_index[attr]][channel];
376 regval = tmp401_temp_to_register(val, data->extended_range,
377 attr == hwmon_temp_crit ? 8 : 4);
50152fb6
GR		 378 ret = regmap_write(regmap, reg, regval);
379 if (ret)
380 break;
381 /*
382 * Read and write limit registers are different, so we need to
383 * reinitialize the cache.
384 */
385 ret = regmap_reinit_cache(regmap, &tmp401_regmap_config);
ca53e764
GR		 386 break;
387 case hwmon_temp_crit_hyst:
388 if (data->extended_range)
389 val = clamp_val(val, -64000, 191000);
390 else
391 val = clamp_val(val, 0, 127000);
392
393 reg = TMP401_TEMP_MSB_READ[3][channel];
50152fb6 394 ret = regmap_read(regmap, reg, &regval);
ca53e764
GR		 395 if (ret < 0)
396 break;
50152fb6 397 temp = tmp401_register_to_temp(regval, data->extended_range);
ca53e764
GR		 398 val = clamp_val(val, temp - 255000, temp);
399 regval = ((temp - val) + 500) / 1000;
50152fb6 400 ret = regmap_write(regmap, TMP401_TEMP_CRIT_HYST, regval);
ca53e764
GR		 401 break;
402 default:
403 ret = -EOPNOTSUPP;
404 break;
405 }
8eb6d90f 406 mutex_unlock(&data->update_lock);
ca53e764 407 return ret;
fce0758f
AP		 408}
409
ca53e764 410static int tmp401_chip_read(struct device *dev, u32 attr, int channel, long *val)
0846e30d 411{
f3643ac7 412 struct tmp401_data *data = dev_get_drvdata(dev);
50152fb6
GR		 413 u32 regval;
414 int ret;
ca53e764
GR		 415
416 switch (attr) {
417 case hwmon_chip_update_interval:
50152fb6
GR		 418 ret = regmap_read(data->regmap, TMP401_CONVERSION_RATE_READ, &regval);
419 if (ret < 0)
420 return ret;
ca53e764
GR		 421 *val = (1 << (7 - regval)) * 125;
422 break;
423 case hwmon_chip_temp_reset_history:
424 *val = 0;
425 break;
426 default:
427 return -EOPNOTSUPP;
428 }
0846e30d 429
ca53e764 430 return 0;
0846e30d
GR		 431}
432
50152fb6 433static int tmp401_set_convrate(struct regmap *regmap, long val)
0846e30d 434{
0846e30d
GR		 435 int err, rate;
436
0846e30d
GR		 437 /*
438 * For valid rates, interval can be calculated as
439 * interval = (1 << (7 - rate)) * 125;
440 * Rounded rate is therefore
441 * rate = 7 - __fls(interval * 4 / (125 * 3));
442 * Use clamp_val() to avoid overflows, and to ensure valid input
443 * for __fls.
444 */
445 val = clamp_val(val, 125, 16000);
446 rate = 7 - __fls(val * 4 / (125 * 3));
50152fb6 447 err = regmap_write(regmap, TMP401_CONVERSION_RATE_WRITE, rate);
ca53e764
GR		 448 if (err)
449 return err;
50152fb6
GR		 450 /*
451 * Read and write conversion rate registers are different, so we need to
452 * reinitialize the cache.
453 */
454 return regmap_reinit_cache(regmap, &tmp401_regmap_config);
ca53e764
GR		 455}
456
457static int tmp401_chip_write(struct device *dev, u32 attr, int channel, long val)
458{
459 struct tmp401_data *data = dev_get_drvdata(dev);
50152fb6 460 struct regmap *regmap = data->regmap;
ca53e764
GR		 461 int err;
462
0846e30d 463 mutex_lock(&data->update_lock);
ca53e764
GR		 464 switch (attr) {
465 case hwmon_chip_update_interval:
50152fb6 466 err = tmp401_set_convrate(regmap, val);
ca53e764
GR		 467 break;
468 case hwmon_chip_temp_reset_history:
469 if (val != 1) {
470 err = -EINVAL;
471 break;
472 }
473 /*
474 * Reset history by writing any value to any of the
475 * minimum/maximum registers (0x30-0x37).
476 */
50152fb6 477 err = regmap_write(regmap, 0x30, 0);
ca53e764
GR		 478 break;
479 default:
480 err = -EOPNOTSUPP;
481 break;
482 }
0846e30d
GR		 483 mutex_unlock(&data->update_lock);
484
ca53e764 485 return err;
0846e30d
GR		 486}
487
ca53e764
GR		 488static int tmp401_read(struct device *dev, enum hwmon_sensor_types type,
489 u32 attr, int channel, long *val)
490{
491 switch (type) {
492 case hwmon_chip:
493 return tmp401_chip_read(dev, attr, channel, val);
494 case hwmon_temp:
495 return tmp401_temp_read(dev, attr, channel, val);
496 default:
497 return -EOPNOTSUPP;
498 }
499}
b4e665c7 500
ca53e764
GR		 501static int tmp401_write(struct device *dev, enum hwmon_sensor_types type,
502 u32 attr, int channel, long val)
503{
504 switch (type) {
505 case hwmon_chip:
506 return tmp401_chip_write(dev, attr, channel, val);
507 case hwmon_temp:
508 return tmp401_temp_write(dev, attr, channel, val);
509 default:
510 return -EOPNOTSUPP;
511 }
512}
fce0758f 513
ca53e764
GR		 514static umode_t tmp401_is_visible(const void *data, enum hwmon_sensor_types type,
515 u32 attr, int channel)
516{
517 switch (type) {
518 case hwmon_chip:
519 switch (attr) {
520 case hwmon_chip_update_interval:
521 case hwmon_chip_temp_reset_history:
522 return 0644;
523 default:
524 break;
525 }
526 break;
527 case hwmon_temp:
528 switch (attr) {
529 case hwmon_temp_input:
530 case hwmon_temp_min_alarm:
531 case hwmon_temp_max_alarm:
532 case hwmon_temp_crit_alarm:
533 case hwmon_temp_fault:
534 case hwmon_temp_lowest:
535 case hwmon_temp_highest:
536 return 0444;
537 case hwmon_temp_min:
538 case hwmon_temp_max:
539 case hwmon_temp_crit:
540 case hwmon_temp_crit_hyst:
541 return 0644;
542 default:
543 break;
544 }
545 break;
546 default:
547 break;
548 }
549 return 0;
550}
29dd3b64 551
ca53e764
GR		 552static const struct hwmon_ops tmp401_ops = {
553 .is_visible = tmp401_is_visible,
554 .read = tmp401_read,
555 .write = tmp401_write,
29dd3b64
GR		 556};
557
50152fb6
GR		 558/* chip initialization, detect, probe */
559
560static int tmp401_init_client(struct tmp401_data *data)
ab2b79d5 561{
50152fb6
GR		 562 struct regmap *regmap = data->regmap;
563 u32 config, config_orig;
564 int ret;
ab2b79d5 565
50152fb6
GR		 566 /* Set conversion rate to 2 Hz */
567 ret = regmap_write(regmap, TMP401_CONVERSION_RATE_WRITE, 5);
568 if (ret < 0)
569 return ret;
ab2b79d5
HG		 570
571 /* Start conversions (disable shutdown if necessary) */
50152fb6
GR		 572 ret = regmap_read(regmap, TMP401_CONFIG_READ, &config);
573 if (ret < 0)
574 return ret;
ab2b79d5
HG		 575
576 config_orig = config;
577 config &= ~TMP401_CONFIG_SHUTDOWN;
578
ca53e764
GR		 579 data->extended_range = !!(config & TMP401_CONFIG_RANGE);
580
ab2b79d5 581 if (config != config_orig)
50152fb6 582 ret = regmap_write(regmap, TMP401_CONFIG_WRITE, config);
90652efe 583
50152fb6 584 return ret;
ab2b79d5
HG		 585}
586
310ec792 587static int tmp401_detect(struct i2c_client *client,
ab2b79d5
HG		 588 struct i2c_board_info *info)
589{
dbe73c8f 590 enum chips kind;
ab2b79d5 591 struct i2c_adapter *adapter = client->adapter;
dbe73c8f 592 u8 reg;
ab2b79d5
HG		 593
594 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
595 return -ENODEV;
596
597 /* Detect and identify the chip */
dbe73c8f
JD		 598 reg = i2c_smbus_read_byte_data(client, TMP401_MANUFACTURER_ID_REG);
599 if (reg != TMP401_MANUFACTURER_ID)
600 return -ENODEV;
ab2b79d5 601
dbe73c8f 602 reg = i2c_smbus_read_byte_data(client, TMP401_DEVICE_ID_REG);
ab2b79d5 603
dbe73c8f
JD		 604 switch (reg) {
605 case TMP401_DEVICE_ID:
a1fac92b
GR		 606 if (client->addr != 0x4c)
607 return -ENODEV;
dbe73c8f
JD		 608 kind = tmp401;
609 break;
4ce5b1fe
GR		 610 case TMP411A_DEVICE_ID:
611 if (client->addr != 0x4c)
612 return -ENODEV;
613 kind = tmp411;
614 break;
615 case TMP411B_DEVICE_ID:
616 if (client->addr != 0x4d)
617 return -ENODEV;
618 kind = tmp411;
619 break;
620 case TMP411C_DEVICE_ID:
621 if (client->addr != 0x4e)
622 return -ENODEV;
dbe73c8f
JD		 623 kind = tmp411;
624 break;
a1fac92b 625 case TMP431_DEVICE_ID:
907a6d58 626 if (client->addr != 0x4c && client->addr != 0x4d)
a1fac92b
GR		 627 return -ENODEV;
628 kind = tmp431;
629 break;
29dd3b64 630 case TMP432_DEVICE_ID:
907a6d58 631 if (client->addr != 0x4c && client->addr != 0x4d)
29dd3b64
GR		 632 return -ENODEV;
633 kind = tmp432;
634 break;
06adbaec 635 case TMP435_DEVICE_ID:
06adbaec
PT		 636 kind = tmp435;
637 break;
dbe73c8f
JD		 638 default:
639 return -ENODEV;
ab2b79d5 640 }
dbe73c8f
JD		 641
642 reg = i2c_smbus_read_byte_data(client, TMP401_CONFIG_READ);
643 if (reg & 0x1b)
644 return -ENODEV;
645
646 reg = i2c_smbus_read_byte_data(client, TMP401_CONVERSION_RATE_READ);
647 /* Datasheet says: 0x1-0x6 */
648 if (reg > 15)
649 return -ENODEV;
650
dc71afe5 651 strlcpy(info->type, tmp401_id[kind].name, I2C_NAME_SIZE);
ab2b79d5
HG		 652
653 return 0;
654}
655
67487038 656static int tmp401_probe(struct i2c_client *client)
ab2b79d5 657{
06adbaec 658 static const char * const names[] = {
38d9f06c 659 "TMP401", "TMP411", "TMP431", "TMP432", "TMP435"
06adbaec 660 };
b4e665c7 661 struct device *dev = &client->dev;
ca53e764 662 struct hwmon_channel_info *info;
f3643ac7 663 struct device *hwmon_dev;
ab2b79d5 664 struct tmp401_data *data;
ca53e764 665 int status;
ab2b79d5 666
b4e665c7 667 data = devm_kzalloc(dev, sizeof(struct tmp401_data), GFP_KERNEL);
ab2b79d5
HG		 668 if (!data)
669 return -ENOMEM;
670
f3643ac7 671 data->client = client;
ab2b79d5 672 mutex_init(&data->update_lock);
67487038 673 data->kind = i2c_match_id(tmp401_id, client)->driver_data;
ab2b79d5 674
50152fb6
GR		 675 data->regmap = devm_regmap_init(dev, NULL, data, &tmp401_regmap_config);
676 if (IS_ERR(data->regmap))
677 return PTR_ERR(data->regmap);
678
ca53e764
GR		 679 /* initialize configuration data */
680 data->chip.ops = &tmp401_ops;
681 data->chip.info = data->info;
682
683 data->info[0] = &data->chip_info;
684 data->info[1] = &data->temp_info;
685
686 info = &data->chip_info;
687 info->type = hwmon_chip;
688 info->config = data->chip_channel_config;
689
690 data->chip_channel_config[0] = HWMON_C_UPDATE_INTERVAL;
691
692 info = &data->temp_info;
693 info->type = hwmon_temp;
694 info->config = data->temp_channel_config;
695
696 data->temp_channel_config[0] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
697 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
698 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM;
699 data->temp_channel_config[1] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
700 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
701 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT;
702
703 if (data->kind == tmp411) {
704 data->temp_channel_config[0] |= HWMON_T_HIGHEST | HWMON_T_LOWEST;
705 data->temp_channel_config[1] |= HWMON_T_HIGHEST | HWMON_T_LOWEST;
706 data->chip_channel_config[0] |= HWMON_C_TEMP_RESET_HISTORY;
707 }
708
709 if (data->kind == tmp432) {
710 data->temp_channel_config[2] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
711 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
712 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT;
713 }
714
ab2b79d5 715 /* Initialize the TMP401 chip */
50152fb6 716 status = tmp401_init_client(data);
90652efe
BG		 717 if (status < 0)
718 return status;
ab2b79d5 719
ca53e764
GR		 720 hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data,
721 &data->chip, NULL);
f3643ac7
GR		 722 if (IS_ERR(hwmon_dev))
723 return PTR_ERR(hwmon_dev);
ab2b79d5 724
b4e665c7 725 dev_info(dev, "Detected TI %s chip\n", names[data->kind]);
ab2b79d5
HG		 726
727 return 0;
ab2b79d5
HG		 728}
729
ea63c2b9
AP		 730static struct i2c_driver tmp401_driver = {
731 .class = I2C_CLASS_HWMON,
732 .driver = {
733 .name = "tmp401",
734 },
67487038 735 .probe_new = tmp401_probe,
ea63c2b9
AP		 736 .id_table = tmp401_id,
737 .detect = tmp401_detect,
738 .address_list = normal_i2c,
739};
ab2b79d5 740
f0967eea 741module_i2c_driver(tmp401_driver);
ab2b79d5
HG		 742
743MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
744MODULE_DESCRIPTION("Texas Instruments TMP401 temperature sensor driver");
745MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)