Commit | Line | Data |
---|---|---|
1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
28ff2f7a | 2 | /*************************************************************************** |
312869ec | 3 | * Copyright (C) 2010-2012 Hans de Goede <hdegoede@redhat.com> * |
28ff2f7a | 4 | * * |
28ff2f7a HG |
5 | ***************************************************************************/ |
6 | ||
7 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
8 | ||
9 | #include <linux/module.h> | |
393935ba | 10 | #include <linux/mod_devicetable.h> |
28ff2f7a HG |
11 | #include <linux/init.h> |
12 | #include <linux/platform_device.h> | |
393935ba | 13 | #include <linux/dmi.h> |
28ff2f7a HG |
14 | #include <linux/err.h> |
15 | #include <linux/io.h> | |
16 | #include <linux/acpi.h> | |
17 | #include <linux/delay.h> | |
312869ec HG |
18 | #include <linux/fs.h> |
19 | #include <linux/watchdog.h> | |
312869ec | 20 | #include <linux/uaccess.h> |
312869ec | 21 | #include <linux/slab.h> |
28ff2f7a HG |
22 | #include "sch56xx-common.h" |
23 | ||
393935ba AW |
24 | static bool ignore_dmi; |
25 | module_param(ignore_dmi, bool, 0); | |
26 | MODULE_PARM_DESC(ignore_dmi, "Omit DMI check for supported devices (default=0)"); | |
27 | ||
989c9c67 AW |
28 | static bool nowayout = WATCHDOG_NOWAYOUT; |
29 | module_param(nowayout, bool, 0); | |
312869ec HG |
30 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
31 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
32 | ||
28ff2f7a HG |
33 | #define SIO_SCH56XX_LD_EM 0x0C /* Embedded uController Logical Dev */ |
34 | #define SIO_UNLOCK_KEY 0x55 /* Key to enable Super-I/O */ | |
35 | #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */ | |
36 | ||
37 | #define SIO_REG_LDSEL 0x07 /* Logical device select */ | |
38 | #define SIO_REG_DEVID 0x20 /* Device ID */ | |
39 | #define SIO_REG_ENABLE 0x30 /* Logical device enable */ | |
40 | #define SIO_REG_ADDR 0x66 /* Logical device address (2 bytes) */ | |
41 | ||
42 | #define SIO_SCH5627_ID 0xC6 /* Chipset ID */ | |
0772a640 | 43 | #define SIO_SCH5636_ID 0xC7 /* Chipset ID */ |
28ff2f7a | 44 | |
312869ec | 45 | #define REGION_LENGTH 10 |
28ff2f7a HG |
46 | |
47 | #define SCH56XX_CMD_READ 0x02 | |
48 | #define SCH56XX_CMD_WRITE 0x03 | |
49 | ||
312869ec HG |
50 | /* Watchdog registers */ |
51 | #define SCH56XX_REG_WDOG_PRESET 0x58B | |
52 | #define SCH56XX_REG_WDOG_CONTROL 0x58C | |
53 | #define SCH56XX_WDOG_TIME_BASE_SEC 0x01 | |
54 | #define SCH56XX_REG_WDOG_OUTPUT_ENABLE 0x58E | |
55 | #define SCH56XX_WDOG_OUTPUT_ENABLE 0x02 | |
56 | ||
57 | struct sch56xx_watchdog_data { | |
58 | u16 addr; | |
312869ec | 59 | struct mutex *io_lock; |
fb551405 HG |
60 | struct watchdog_info wdinfo; |
61 | struct watchdog_device wddev; | |
312869ec HG |
62 | u8 watchdog_preset; |
63 | u8 watchdog_control; | |
64 | u8 watchdog_output_enable; | |
65 | }; | |
66 | ||
28ff2f7a HG |
67 | static struct platform_device *sch56xx_pdev; |
68 | ||
69 | /* Super I/O functions */ | |
70 | static inline int superio_inb(int base, int reg) | |
71 | { | |
72 | outb(reg, base); | |
73 | return inb(base + 1); | |
74 | } | |
75 | ||
76 | static inline int superio_enter(int base) | |
77 | { | |
78 | /* Don't step on other drivers' I/O space by accident */ | |
79 | if (!request_muxed_region(base, 2, "sch56xx")) { | |
80 | pr_err("I/O address 0x%04x already in use\n", base); | |
81 | return -EBUSY; | |
82 | } | |
83 | ||
84 | outb(SIO_UNLOCK_KEY, base); | |
85 | ||
86 | return 0; | |
87 | } | |
88 | ||
89 | static inline void superio_select(int base, int ld) | |
90 | { | |
91 | outb(SIO_REG_LDSEL, base); | |
92 | outb(ld, base + 1); | |
93 | } | |
94 | ||
95 | static inline void superio_exit(int base) | |
96 | { | |
97 | outb(SIO_LOCK_KEY, base); | |
98 | release_region(base, 2); | |
99 | } | |
100 | ||
101 | static int sch56xx_send_cmd(u16 addr, u8 cmd, u16 reg, u8 v) | |
102 | { | |
103 | u8 val; | |
104 | int i; | |
105 | /* | |
106 | * According to SMSC for the commands we use the maximum time for | |
107 | * the EM to respond is 15 ms, but testing shows in practice it | |
108 | * responds within 15-32 reads, so we first busy poll, and if | |
109 | * that fails sleep a bit and try again until we are way past | |
110 | * the 15 ms maximum response time. | |
111 | */ | |
112 | const int max_busy_polls = 64; | |
113 | const int max_lazy_polls = 32; | |
114 | ||
115 | /* (Optional) Write-Clear the EC to Host Mailbox Register */ | |
116 | val = inb(addr + 1); | |
117 | outb(val, addr + 1); | |
118 | ||
119 | /* Set Mailbox Address Pointer to first location in Region 1 */ | |
120 | outb(0x00, addr + 2); | |
121 | outb(0x80, addr + 3); | |
122 | ||
123 | /* Write Request Packet Header */ | |
124 | outb(cmd, addr + 4); /* VREG Access Type read:0x02 write:0x03 */ | |
125 | outb(0x01, addr + 5); /* # of Entries: 1 Byte (8-bit) */ | |
126 | outb(0x04, addr + 2); /* Mailbox AP to first data entry loc. */ | |
127 | ||
128 | /* Write Value field */ | |
129 | if (cmd == SCH56XX_CMD_WRITE) | |
130 | outb(v, addr + 4); | |
131 | ||
132 | /* Write Address field */ | |
133 | outb(reg & 0xff, addr + 6); | |
134 | outb(reg >> 8, addr + 7); | |
135 | ||
136 | /* Execute the Random Access Command */ | |
137 | outb(0x01, addr); /* Write 01h to the Host-to-EC register */ | |
138 | ||
139 | /* EM Interface Polling "Algorithm" */ | |
140 | for (i = 0; i < max_busy_polls + max_lazy_polls; i++) { | |
141 | if (i >= max_busy_polls) | |
799c3e1e | 142 | usleep_range(1000, 2000); |
28ff2f7a HG |
143 | /* Read Interrupt source Register */ |
144 | val = inb(addr + 8); | |
145 | /* Write Clear the interrupt source bits */ | |
146 | if (val) | |
147 | outb(val, addr + 8); | |
148 | /* Command Completed ? */ | |
149 | if (val & 0x01) | |
150 | break; | |
151 | } | |
152 | if (i == max_busy_polls + max_lazy_polls) { | |
b55f3757 GR |
153 | pr_err("Max retries exceeded reading virtual register 0x%04hx (%d)\n", |
154 | reg, 1); | |
28ff2f7a HG |
155 | return -EIO; |
156 | } | |
157 | ||
158 | /* | |
159 | * According to SMSC we may need to retry this, but sofar I've always | |
160 | * seen this succeed in 1 try. | |
161 | */ | |
162 | for (i = 0; i < max_busy_polls; i++) { | |
163 | /* Read EC-to-Host Register */ | |
164 | val = inb(addr + 1); | |
165 | /* Command Completed ? */ | |
166 | if (val == 0x01) | |
167 | break; | |
168 | ||
169 | if (i == 0) | |
b55f3757 GR |
170 | pr_warn("EC reports: 0x%02x reading virtual register 0x%04hx\n", |
171 | (unsigned int)val, reg); | |
28ff2f7a HG |
172 | } |
173 | if (i == max_busy_polls) { | |
b55f3757 GR |
174 | pr_err("Max retries exceeded reading virtual register 0x%04hx (%d)\n", |
175 | reg, 2); | |
28ff2f7a HG |
176 | return -EIO; |
177 | } | |
178 | ||
179 | /* | |
180 | * According to the SMSC app note we should now do: | |
181 | * | |
182 | * Set Mailbox Address Pointer to first location in Region 1 * | |
183 | * outb(0x00, addr + 2); | |
184 | * outb(0x80, addr + 3); | |
185 | * | |
186 | * But if we do that things don't work, so let's not. | |
187 | */ | |
188 | ||
189 | /* Read Value field */ | |
190 | if (cmd == SCH56XX_CMD_READ) | |
191 | return inb(addr + 4); | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | int sch56xx_read_virtual_reg(u16 addr, u16 reg) | |
197 | { | |
198 | return sch56xx_send_cmd(addr, SCH56XX_CMD_READ, reg, 0); | |
199 | } | |
200 | EXPORT_SYMBOL(sch56xx_read_virtual_reg); | |
201 | ||
202 | int sch56xx_write_virtual_reg(u16 addr, u16 reg, u8 val) | |
203 | { | |
204 | return sch56xx_send_cmd(addr, SCH56XX_CMD_WRITE, reg, val); | |
205 | } | |
206 | EXPORT_SYMBOL(sch56xx_write_virtual_reg); | |
207 | ||
208 | int sch56xx_read_virtual_reg16(u16 addr, u16 reg) | |
209 | { | |
210 | int lsb, msb; | |
211 | ||
212 | /* Read LSB first, this will cause the matching MSB to be latched */ | |
213 | lsb = sch56xx_read_virtual_reg(addr, reg); | |
214 | if (lsb < 0) | |
215 | return lsb; | |
216 | ||
217 | msb = sch56xx_read_virtual_reg(addr, reg + 1); | |
218 | if (msb < 0) | |
219 | return msb; | |
220 | ||
221 | return lsb | (msb << 8); | |
222 | } | |
223 | EXPORT_SYMBOL(sch56xx_read_virtual_reg16); | |
224 | ||
225 | int sch56xx_read_virtual_reg12(u16 addr, u16 msb_reg, u16 lsn_reg, | |
226 | int high_nibble) | |
227 | { | |
228 | int msb, lsn; | |
229 | ||
230 | /* Read MSB first, this will cause the matching LSN to be latched */ | |
231 | msb = sch56xx_read_virtual_reg(addr, msb_reg); | |
232 | if (msb < 0) | |
233 | return msb; | |
234 | ||
235 | lsn = sch56xx_read_virtual_reg(addr, lsn_reg); | |
236 | if (lsn < 0) | |
237 | return lsn; | |
238 | ||
239 | if (high_nibble) | |
240 | return (msb << 4) | (lsn >> 4); | |
241 | else | |
242 | return (msb << 4) | (lsn & 0x0f); | |
243 | } | |
244 | EXPORT_SYMBOL(sch56xx_read_virtual_reg12); | |
245 | ||
312869ec HG |
246 | /* |
247 | * Watchdog routines | |
248 | */ | |
249 | ||
fb551405 HG |
250 | static int watchdog_set_timeout(struct watchdog_device *wddev, |
251 | unsigned int timeout) | |
312869ec | 252 | { |
fb551405 HG |
253 | struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev); |
254 | unsigned int resolution; | |
312869ec | 255 | u8 control; |
fb551405 | 256 | int ret; |
312869ec HG |
257 | |
258 | /* 1 second or 60 second resolution? */ | |
259 | if (timeout <= 255) | |
260 | resolution = 1; | |
261 | else | |
262 | resolution = 60; | |
263 | ||
264 | if (timeout < resolution || timeout > (resolution * 255)) | |
265 | return -EINVAL; | |
266 | ||
312869ec HG |
267 | if (resolution == 1) |
268 | control = data->watchdog_control | SCH56XX_WDOG_TIME_BASE_SEC; | |
269 | else | |
270 | control = data->watchdog_control & ~SCH56XX_WDOG_TIME_BASE_SEC; | |
271 | ||
272 | if (data->watchdog_control != control) { | |
273 | mutex_lock(data->io_lock); | |
274 | ret = sch56xx_write_virtual_reg(data->addr, | |
275 | SCH56XX_REG_WDOG_CONTROL, | |
276 | control); | |
277 | mutex_unlock(data->io_lock); | |
278 | if (ret) | |
fb551405 | 279 | return ret; |
312869ec HG |
280 | |
281 | data->watchdog_control = control; | |
282 | } | |
283 | ||
284 | /* | |
285 | * Remember new timeout value, but do not write as that (re)starts | |
286 | * the watchdog countdown. | |
287 | */ | |
288 | data->watchdog_preset = DIV_ROUND_UP(timeout, resolution); | |
fb551405 | 289 | wddev->timeout = data->watchdog_preset * resolution; |
312869ec | 290 | |
fb551405 | 291 | return 0; |
312869ec HG |
292 | } |
293 | ||
fb551405 | 294 | static int watchdog_start(struct watchdog_device *wddev) |
312869ec | 295 | { |
fb551405 | 296 | struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev); |
312869ec HG |
297 | int ret; |
298 | u8 val; | |
299 | ||
312869ec HG |
300 | /* |
301 | * The sch56xx's watchdog cannot really be started / stopped | |
302 | * it is always running, but we can avoid the timer expiring | |
303 | * from causing a system reset by clearing the output enable bit. | |
304 | * | |
305 | * The sch56xx's watchdog will set the watchdog event bit, bit 0 | |
306 | * of the second interrupt source register (at base-address + 9), | |
307 | * when the timer expires. | |
308 | * | |
309 | * This will only cause a system reset if the 0-1 flank happens when | |
310 | * output enable is true. Setting output enable after the flank will | |
311 | * not cause a reset, nor will the timer expiring a second time. | |
312 | * This means we must clear the watchdog event bit in case it is set. | |
313 | * | |
314 | * The timer may still be running (after a recent watchdog_stop) and | |
315 | * mere milliseconds away from expiring, so the timer must be reset | |
316 | * first! | |
317 | */ | |
318 | ||
319 | mutex_lock(data->io_lock); | |
320 | ||
321 | /* 1. Reset the watchdog countdown counter */ | |
322 | ret = sch56xx_write_virtual_reg(data->addr, SCH56XX_REG_WDOG_PRESET, | |
323 | data->watchdog_preset); | |
324 | if (ret) | |
325 | goto leave; | |
326 | ||
85a2e40c HG |
327 | /* 2. Enable output */ |
328 | val = data->watchdog_output_enable | SCH56XX_WDOG_OUTPUT_ENABLE; | |
329 | ret = sch56xx_write_virtual_reg(data->addr, | |
330 | SCH56XX_REG_WDOG_OUTPUT_ENABLE, val); | |
331 | if (ret) | |
332 | goto leave; | |
312869ec | 333 | |
85a2e40c | 334 | data->watchdog_output_enable = val; |
312869ec HG |
335 | |
336 | /* 3. Clear the watchdog event bit if set */ | |
337 | val = inb(data->addr + 9); | |
338 | if (val & 0x01) | |
339 | outb(0x01, data->addr + 9); | |
340 | ||
341 | leave: | |
342 | mutex_unlock(data->io_lock); | |
312869ec HG |
343 | return ret; |
344 | } | |
345 | ||
fb551405 | 346 | static int watchdog_trigger(struct watchdog_device *wddev) |
312869ec | 347 | { |
fb551405 | 348 | struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev); |
312869ec HG |
349 | int ret; |
350 | ||
312869ec HG |
351 | /* Reset the watchdog countdown counter */ |
352 | mutex_lock(data->io_lock); | |
353 | ret = sch56xx_write_virtual_reg(data->addr, SCH56XX_REG_WDOG_PRESET, | |
354 | data->watchdog_preset); | |
355 | mutex_unlock(data->io_lock); | |
fb551405 | 356 | |
312869ec HG |
357 | return ret; |
358 | } | |
359 | ||
fb551405 | 360 | static int watchdog_stop(struct watchdog_device *wddev) |
312869ec | 361 | { |
fb551405 | 362 | struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev); |
312869ec HG |
363 | int ret = 0; |
364 | u8 val; | |
365 | ||
85a2e40c HG |
366 | val = data->watchdog_output_enable & ~SCH56XX_WDOG_OUTPUT_ENABLE; |
367 | mutex_lock(data->io_lock); | |
368 | ret = sch56xx_write_virtual_reg(data->addr, | |
369 | SCH56XX_REG_WDOG_OUTPUT_ENABLE, val); | |
370 | mutex_unlock(data->io_lock); | |
371 | if (ret) | |
372 | return ret; | |
312869ec | 373 | |
85a2e40c HG |
374 | data->watchdog_output_enable = val; |
375 | return 0; | |
312869ec HG |
376 | } |
377 | ||
fb551405 HG |
378 | static const struct watchdog_ops watchdog_ops = { |
379 | .owner = THIS_MODULE, | |
380 | .start = watchdog_start, | |
381 | .stop = watchdog_stop, | |
382 | .ping = watchdog_trigger, | |
383 | .set_timeout = watchdog_set_timeout, | |
312869ec HG |
384 | }; |
385 | ||
2be5f0d7 AW |
386 | void sch56xx_watchdog_register(struct device *parent, u16 addr, u32 revision, |
387 | struct mutex *io_lock, int check_enabled) | |
312869ec HG |
388 | { |
389 | struct sch56xx_watchdog_data *data; | |
fb551405 | 390 | int err, control, output_enable; |
312869ec HG |
391 | |
392 | /* Cache the watchdog registers */ | |
393 | mutex_lock(io_lock); | |
394 | control = | |
395 | sch56xx_read_virtual_reg(addr, SCH56XX_REG_WDOG_CONTROL); | |
396 | output_enable = | |
397 | sch56xx_read_virtual_reg(addr, SCH56XX_REG_WDOG_OUTPUT_ENABLE); | |
398 | mutex_unlock(io_lock); | |
399 | ||
400 | if (control < 0) | |
2be5f0d7 | 401 | return; |
312869ec | 402 | if (output_enable < 0) |
2be5f0d7 | 403 | return; |
312869ec HG |
404 | if (check_enabled && !(output_enable & SCH56XX_WDOG_OUTPUT_ENABLE)) { |
405 | pr_warn("Watchdog not enabled by BIOS, not registering\n"); | |
2be5f0d7 | 406 | return; |
312869ec HG |
407 | } |
408 | ||
2be5f0d7 | 409 | data = devm_kzalloc(parent, sizeof(struct sch56xx_watchdog_data), GFP_KERNEL); |
312869ec | 410 | if (!data) |
2be5f0d7 | 411 | return; |
312869ec HG |
412 | |
413 | data->addr = addr; | |
312869ec | 414 | data->io_lock = io_lock; |
312869ec | 415 | |
6df5cba5 | 416 | strscpy(data->wdinfo.identity, "sch56xx watchdog", sizeof(data->wdinfo.identity)); |
fb551405 HG |
417 | data->wdinfo.firmware_version = revision; |
418 | data->wdinfo.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT; | |
419 | if (!nowayout) | |
420 | data->wdinfo.options |= WDIOF_MAGICCLOSE; | |
421 | ||
422 | data->wddev.info = &data->wdinfo; | |
423 | data->wddev.ops = &watchdog_ops; | |
424 | data->wddev.parent = parent; | |
425 | data->wddev.timeout = 60; | |
426 | data->wddev.min_timeout = 1; | |
427 | data->wddev.max_timeout = 255 * 60; | |
989c9c67 | 428 | watchdog_set_nowayout(&data->wddev, nowayout); |
fb551405 | 429 | if (output_enable & SCH56XX_WDOG_OUTPUT_ENABLE) |
647d6f09 | 430 | set_bit(WDOG_HW_RUNNING, &data->wddev.status); |
fb551405 HG |
431 | |
432 | /* Since the watchdog uses a downcounter there is no register to read | |
433 | the BIOS set timeout from (if any was set at all) -> | |
434 | Choose a preset which will give us a 1 minute timeout */ | |
435 | if (control & SCH56XX_WDOG_TIME_BASE_SEC) | |
436 | data->watchdog_preset = 60; /* seconds */ | |
437 | else | |
438 | data->watchdog_preset = 1; /* minute */ | |
312869ec | 439 | |
fb551405 HG |
440 | data->watchdog_control = control; |
441 | data->watchdog_output_enable = output_enable; | |
312869ec | 442 | |
fb551405 | 443 | watchdog_set_drvdata(&data->wddev, data); |
2be5f0d7 | 444 | err = devm_watchdog_register_device(parent, &data->wddev); |
312869ec HG |
445 | if (err) { |
446 | pr_err("Registering watchdog chardev: %d\n", err); | |
2be5f0d7 | 447 | devm_kfree(parent, data); |
312869ec | 448 | } |
312869ec HG |
449 | } |
450 | EXPORT_SYMBOL(sch56xx_watchdog_register); | |
451 | ||
312869ec HG |
452 | /* |
453 | * platform dev find, add and remove functions | |
454 | */ | |
455 | ||
313829ee | 456 | static int __init sch56xx_find(int sioaddr, const char **name) |
28ff2f7a HG |
457 | { |
458 | u8 devid; | |
313829ee | 459 | unsigned short address; |
28ff2f7a HG |
460 | int err; |
461 | ||
462 | err = superio_enter(sioaddr); | |
463 | if (err) | |
464 | return err; | |
465 | ||
466 | devid = superio_inb(sioaddr, SIO_REG_DEVID); | |
467 | switch (devid) { | |
468 | case SIO_SCH5627_ID: | |
469 | *name = "sch5627"; | |
470 | break; | |
0772a640 HG |
471 | case SIO_SCH5636_ID: |
472 | *name = "sch5636"; | |
473 | break; | |
28ff2f7a HG |
474 | default: |
475 | pr_debug("Unsupported device id: 0x%02x\n", | |
476 | (unsigned int)devid); | |
477 | err = -ENODEV; | |
478 | goto exit; | |
479 | } | |
480 | ||
481 | superio_select(sioaddr, SIO_SCH56XX_LD_EM); | |
482 | ||
483 | if (!(superio_inb(sioaddr, SIO_REG_ENABLE) & 0x01)) { | |
484 | pr_warn("Device not activated\n"); | |
485 | err = -ENODEV; | |
486 | goto exit; | |
487 | } | |
488 | ||
489 | /* | |
490 | * Warning the order of the low / high byte is the other way around | |
491 | * as on most other superio devices!! | |
492 | */ | |
313829ee | 493 | address = superio_inb(sioaddr, SIO_REG_ADDR) | |
28ff2f7a | 494 | superio_inb(sioaddr, SIO_REG_ADDR + 1) << 8; |
313829ee | 495 | if (address == 0) { |
28ff2f7a HG |
496 | pr_warn("Base address not set\n"); |
497 | err = -ENODEV; | |
498 | goto exit; | |
499 | } | |
313829ee | 500 | err = address; |
28ff2f7a HG |
501 | |
502 | exit: | |
503 | superio_exit(sioaddr); | |
504 | return err; | |
505 | } | |
506 | ||
313829ee | 507 | static int __init sch56xx_device_add(int address, const char *name) |
28ff2f7a HG |
508 | { |
509 | struct resource res = { | |
510 | .start = address, | |
511 | .end = address + REGION_LENGTH - 1, | |
5c1c78e0 | 512 | .name = name, |
28ff2f7a HG |
513 | .flags = IORESOURCE_IO, |
514 | }; | |
515 | int err; | |
516 | ||
28ff2f7a HG |
517 | err = acpi_check_resource_conflict(&res); |
518 | if (err) | |
5c1c78e0 | 519 | return err; |
28ff2f7a | 520 | |
5c1c78e0 | 521 | sch56xx_pdev = platform_device_register_simple(name, -1, &res, 1); |
28ff2f7a | 522 | |
5c1c78e0 | 523 | return PTR_ERR_OR_ZERO(sch56xx_pdev); |
28ff2f7a HG |
524 | } |
525 | ||
fd2d53c3 AW |
526 | static const struct dmi_system_id sch56xx_dmi_override_table[] __initconst = { |
527 | { | |
528 | .matches = { | |
529 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
530 | DMI_MATCH(DMI_PRODUCT_NAME, "CELSIUS W380"), | |
531 | }, | |
532 | }, | |
533 | { | |
534 | .matches = { | |
535 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
536 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO P710"), | |
537 | }, | |
538 | }, | |
539 | { | |
540 | .matches = { | |
541 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
542 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO E9900"), | |
543 | }, | |
544 | }, | |
545 | { } | |
546 | }; | |
547 | ||
393935ba AW |
548 | /* For autoloading only */ |
549 | static const struct dmi_system_id sch56xx_dmi_table[] __initconst = { | |
550 | { | |
551 | .matches = { | |
552 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
553 | }, | |
554 | }, | |
555 | { } | |
556 | }; | |
557 | MODULE_DEVICE_TABLE(dmi, sch56xx_dmi_table); | |
558 | ||
28ff2f7a HG |
559 | static int __init sch56xx_init(void) |
560 | { | |
313829ee | 561 | const char *name = NULL; |
393935ba | 562 | int address; |
313829ee | 563 | |
393935ba AW |
564 | if (!ignore_dmi) { |
565 | if (!dmi_check_system(sch56xx_dmi_table)) | |
566 | return -ENODEV; | |
567 | ||
fd2d53c3 AW |
568 | if (!dmi_check_system(sch56xx_dmi_override_table)) { |
569 | /* | |
570 | * Some machines like the Esprimo P720 and Esprimo C700 have | |
571 | * onboard devices named " Antiope"/" Theseus" instead of | |
572 | * "Antiope"/"Theseus", so we need to check for both. | |
573 | */ | |
574 | if (!dmi_find_device(DMI_DEV_TYPE_OTHER, "Antiope", NULL) && | |
575 | !dmi_find_device(DMI_DEV_TYPE_OTHER, " Antiope", NULL) && | |
576 | !dmi_find_device(DMI_DEV_TYPE_OTHER, "Theseus", NULL) && | |
577 | !dmi_find_device(DMI_DEV_TYPE_OTHER, " Theseus", NULL)) | |
578 | return -ENODEV; | |
579 | } | |
393935ba AW |
580 | } |
581 | ||
582 | /* | |
583 | * Some devices like the Esprimo C700 have both onboard devices, | |
584 | * so we still have to check manually | |
585 | */ | |
313829ee GR |
586 | address = sch56xx_find(0x4e, &name); |
587 | if (address < 0) | |
588 | address = sch56xx_find(0x2e, &name); | |
589 | if (address < 0) | |
590 | return address; | |
28ff2f7a HG |
591 | |
592 | return sch56xx_device_add(address, name); | |
593 | } | |
594 | ||
595 | static void __exit sch56xx_exit(void) | |
596 | { | |
597 | platform_device_unregister(sch56xx_pdev); | |
598 | } | |
599 | ||
600 | MODULE_DESCRIPTION("SMSC SCH56xx Hardware Monitoring Common Code"); | |
601 | MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); | |
602 | MODULE_LICENSE("GPL"); | |
603 | ||
604 | module_init(sch56xx_init); | |
605 | module_exit(sch56xx_exit); |