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f1fd4a4d TM |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2014-2018 Nuvoton Technology corporation. | |
3 | ||
4 | #include <linux/clk.h> | |
5 | #include <linux/device.h> | |
6 | #include <linux/hwmon.h> | |
7 | #include <linux/hwmon-sysfs.h> | |
8 | #include <linux/interrupt.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of_address.h> | |
12 | #include <linux/of_irq.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/sysfs.h> | |
16 | #include <linux/thermal.h> | |
17 | ||
18 | /* NPCM7XX PWM registers */ | |
19 | #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) | |
20 | ||
21 | #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00) | |
22 | #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04) | |
23 | #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08) | |
24 | #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \ | |
25 | (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch))) | |
26 | #define NPCM7XX_PWM_REG_CMRx(base, n, ch) \ | |
27 | (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch))) | |
28 | #define NPCM7XX_PWM_REG_PDRx(base, n, ch) \ | |
29 | (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch))) | |
30 | #define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C) | |
31 | #define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40) | |
32 | ||
33 | #define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3) | |
34 | #define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11) | |
35 | #define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15) | |
36 | #define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19) | |
37 | ||
38 | #define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2) | |
39 | #define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10) | |
40 | #define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14) | |
41 | #define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18) | |
42 | ||
43 | #define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0) | |
44 | #define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8) | |
45 | #define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12) | |
46 | #define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16) | |
47 | ||
48 | /* Define the maximum PWM channel number */ | |
49 | #define NPCM7XX_PWM_MAX_CHN_NUM 8 | |
50 | #define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4 | |
51 | #define NPCM7XX_PWM_MAX_MODULES 2 | |
52 | ||
53 | /* Define the Counter Register, value = 100 for match 100% */ | |
54 | #define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 255 | |
f21c8e75 | 55 | #define NPCM7XX_PWM_CMR_DEFAULT_NUM 255 |
f1fd4a4d TM |
56 | #define NPCM7XX_PWM_CMR_MAX 255 |
57 | ||
58 | /* default all PWM channels PRESCALE2 = 1 */ | |
59 | #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x4 | |
60 | #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x40 | |
61 | #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x400 | |
62 | #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x4000 | |
63 | ||
64 | #define PWM_OUTPUT_FREQ_25KHZ 25000 | |
65 | #define PWN_CNT_DEFAULT 256 | |
66 | #define MIN_PRESCALE1 2 | |
67 | #define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8 | |
68 | ||
69 | #define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \ | |
70 | NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \ | |
71 | NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \ | |
72 | NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3) | |
73 | ||
74 | #define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \ | |
75 | NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \ | |
76 | NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \ | |
77 | NPCM7XX_PWM_CTRL_CH3_MODE_BIT) | |
78 | ||
79 | /* NPCM7XX FAN Tacho registers */ | |
80 | #define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) | |
81 | ||
82 | #define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00) | |
83 | #define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02) | |
84 | #define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04) | |
85 | #define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06) | |
86 | #define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08) | |
87 | #define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A) | |
88 | #define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C) | |
89 | #define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E) | |
90 | #define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10) | |
91 | #define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12) | |
92 | #define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14) | |
93 | #define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16) | |
94 | #define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18) | |
95 | #define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A) | |
96 | #define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C) | |
97 | ||
98 | #define NPCM7XX_FAN_TCKC_CLKX_NONE 0 | |
99 | #define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0) | |
100 | #define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3) | |
101 | ||
102 | #define NPCM7XX_FAN_TMCTRL_TBEN BIT(6) | |
103 | #define NPCM7XX_FAN_TMCTRL_TAEN BIT(5) | |
104 | #define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4) | |
105 | #define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3) | |
106 | #define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2) | |
107 | ||
108 | #define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0) | |
109 | #define NPCM7XX_FAN_TICLR_TFCLR BIT(5) | |
110 | #define NPCM7XX_FAN_TICLR_TECLR BIT(4) | |
111 | #define NPCM7XX_FAN_TICLR_TDCLR BIT(3) | |
112 | #define NPCM7XX_FAN_TICLR_TCCLR BIT(2) | |
113 | #define NPCM7XX_FAN_TICLR_TBCLR BIT(1) | |
114 | #define NPCM7XX_FAN_TICLR_TACLR BIT(0) | |
115 | ||
116 | #define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0) | |
117 | #define NPCM7XX_FAN_TIEN_TFIEN BIT(5) | |
118 | #define NPCM7XX_FAN_TIEN_TEIEN BIT(4) | |
119 | #define NPCM7XX_FAN_TIEN_TDIEN BIT(3) | |
120 | #define NPCM7XX_FAN_TIEN_TCIEN BIT(2) | |
121 | #define NPCM7XX_FAN_TIEN_TBIEN BIT(1) | |
122 | #define NPCM7XX_FAN_TIEN_TAIEN BIT(0) | |
123 | ||
124 | #define NPCM7XX_FAN_TICTRL_TFPND BIT(5) | |
125 | #define NPCM7XX_FAN_TICTRL_TEPND BIT(4) | |
126 | #define NPCM7XX_FAN_TICTRL_TDPND BIT(3) | |
127 | #define NPCM7XX_FAN_TICTRL_TCPND BIT(2) | |
128 | #define NPCM7XX_FAN_TICTRL_TBPND BIT(1) | |
129 | #define NPCM7XX_FAN_TICTRL_TAPND BIT(0) | |
130 | ||
131 | #define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7) | |
132 | #define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6) | |
133 | #define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5) | |
134 | #define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4) | |
135 | #define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3) | |
136 | #define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2) | |
137 | #define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1) | |
138 | #define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0) | |
139 | ||
140 | /* FAN General Definition */ | |
141 | /* Define the maximum FAN channel number */ | |
142 | #define NPCM7XX_FAN_MAX_MODULE 8 | |
143 | #define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2 | |
144 | #define NPCM7XX_FAN_MAX_CHN_NUM 16 | |
145 | ||
146 | /* | |
147 | * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us) | |
148 | * Timeout 94ms ~= 0x5000 | |
149 | * (The minimum FAN speed could to support ~640RPM/pulse 1, | |
150 | * 320RPM/pulse 2, ...-- 10.6Hz) | |
151 | */ | |
152 | #define NPCM7XX_FAN_TIMEOUT 0x5000 | |
153 | #define NPCM7XX_FAN_TCNT 0xFFFF | |
154 | #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT) | |
155 | #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT) | |
156 | ||
157 | #define NPCM7XX_FAN_POLL_TIMER_200MS 200 | |
158 | #define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2 | |
159 | #define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0 | |
160 | #define NPCM7XX_FAN_CLK_PRESCALE 255 | |
161 | ||
162 | #define NPCM7XX_FAN_CMPA 0 | |
163 | #define NPCM7XX_FAN_CMPB 1 | |
164 | ||
165 | /* Obtain the fan number */ | |
166 | #define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp)) | |
167 | ||
168 | /* fan sample status */ | |
169 | #define FAN_DISABLE 0xFF | |
170 | #define FAN_INIT 0x00 | |
171 | #define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01 | |
172 | #define FAN_ENOUGH_SAMPLE 0x02 | |
173 | ||
174 | struct npcm7xx_fan_dev { | |
175 | u8 fan_st_flg; | |
176 | u8 fan_pls_per_rev; | |
177 | u16 fan_cnt; | |
178 | u32 fan_cnt_tmp; | |
179 | }; | |
180 | ||
181 | struct npcm7xx_cooling_device { | |
182 | char name[THERMAL_NAME_LENGTH]; | |
183 | struct npcm7xx_pwm_fan_data *data; | |
184 | struct thermal_cooling_device *tcdev; | |
185 | int pwm_port; | |
186 | u8 *cooling_levels; | |
187 | u8 max_state; | |
188 | u8 cur_state; | |
189 | }; | |
190 | ||
191 | struct npcm7xx_pwm_fan_data { | |
192 | void __iomem *pwm_base; | |
193 | void __iomem *fan_base; | |
194 | unsigned long pwm_clk_freq; | |
195 | unsigned long fan_clk_freq; | |
196 | struct clk *pwm_clk; | |
197 | struct clk *fan_clk; | |
198 | struct mutex pwm_lock[NPCM7XX_PWM_MAX_MODULES]; | |
199 | spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE]; | |
200 | int fan_irq[NPCM7XX_FAN_MAX_MODULE]; | |
201 | bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM]; | |
202 | bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM]; | |
203 | u32 input_clk_freq; | |
204 | struct timer_list fan_timer; | |
205 | struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM]; | |
206 | struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM]; | |
207 | u8 fan_select; | |
208 | }; | |
209 | ||
210 | static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data, | |
211 | int channel, u16 val) | |
212 | { | |
213 | u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); | |
214 | u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); | |
215 | u32 tmp_buf, ctrl_en_bit, env_bit; | |
216 | ||
217 | /* | |
218 | * Config PWM Comparator register for setting duty cycle | |
219 | */ | |
220 | mutex_lock(&data->pwm_lock[module]); | |
221 | ||
222 | /* write new CMR value */ | |
223 | iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch)); | |
224 | tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module)); | |
225 | ||
226 | switch (pwm_ch) { | |
227 | case 0: | |
228 | ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT; | |
229 | env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT; | |
230 | break; | |
231 | case 1: | |
232 | ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT; | |
233 | env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT; | |
234 | break; | |
235 | case 2: | |
236 | ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT; | |
237 | env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT; | |
238 | break; | |
239 | case 3: | |
240 | ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT; | |
241 | env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT; | |
242 | break; | |
243 | default: | |
244 | mutex_unlock(&data->pwm_lock[module]); | |
245 | return -ENODEV; | |
246 | } | |
247 | ||
248 | if (val == 0) { | |
249 | /* Disable PWM */ | |
250 | tmp_buf &= ~ctrl_en_bit; | |
251 | tmp_buf |= env_bit; | |
252 | } else { | |
253 | /* Enable PWM */ | |
254 | tmp_buf |= ctrl_en_bit; | |
255 | tmp_buf &= ~env_bit; | |
256 | } | |
257 | ||
258 | iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module)); | |
259 | mutex_unlock(&data->pwm_lock[module]); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data, | |
265 | u8 fan, u8 cmp) | |
266 | { | |
267 | u8 fan_id; | |
268 | u8 reg_mode; | |
269 | u8 reg_int; | |
270 | unsigned long flags; | |
271 | ||
272 | fan_id = NPCM7XX_FAN_INPUT(fan, cmp); | |
273 | ||
274 | /* to check whether any fan tach is enable */ | |
275 | if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) { | |
276 | /* reset status */ | |
277 | spin_lock_irqsave(&data->fan_lock[fan], flags); | |
278 | ||
279 | data->fan_dev[fan_id].fan_st_flg = FAN_INIT; | |
280 | reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); | |
281 | ||
282 | /* | |
283 | * the interrupt enable bits do not need to be cleared before | |
284 | * it sets, the interrupt enable bits are cleared only on reset. | |
285 | * the clock unit control register is behaving in the same | |
286 | * manner that the interrupt enable register behave. | |
287 | */ | |
288 | if (cmp == NPCM7XX_FAN_CMPA) { | |
289 | /* enable interrupt */ | |
290 | iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN | | |
291 | NPCM7XX_FAN_TIEN_TEIEN), | |
292 | NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); | |
293 | ||
294 | reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB | |
295 | | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, | |
296 | fan)); | |
297 | ||
298 | /* start to Capture */ | |
299 | iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base, | |
300 | fan)); | |
301 | } else { | |
302 | /* enable interrupt */ | |
303 | iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN | | |
304 | NPCM7XX_FAN_TIEN_TFIEN), | |
305 | NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); | |
306 | ||
307 | reg_mode = | |
308 | NPCM7XX_FAN_TCKC_CLK2_APB | |
309 | | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, | |
310 | fan)); | |
311 | ||
312 | /* start to Capture */ | |
313 | iowrite8(reg_mode, | |
314 | NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); | |
315 | } | |
316 | ||
317 | spin_unlock_irqrestore(&data->fan_lock[fan], flags); | |
318 | } | |
319 | } | |
320 | ||
321 | /* | |
322 | * Enable a background timer to poll fan tach value, (200ms * 4) | |
323 | * to polling all fan | |
324 | */ | |
325 | static void npcm7xx_fan_polling(struct timer_list *t) | |
326 | { | |
327 | struct npcm7xx_pwm_fan_data *data; | |
328 | int i; | |
329 | ||
330 | data = from_timer(data, t, fan_timer); | |
331 | ||
332 | /* | |
333 | * Polling two module per one round, | |
334 | * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415 | |
335 | */ | |
336 | for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE; | |
337 | i = i + 4) { | |
338 | /* clear the flag and reset the counter (TCNT) */ | |
339 | iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL, | |
340 | NPCM7XX_FAN_REG_TICLR(data->fan_base, i)); | |
341 | ||
342 | if (data->fan_present[i * 2]) { | |
343 | iowrite16(NPCM7XX_FAN_TCNT, | |
344 | NPCM7XX_FAN_REG_TCNT1(data->fan_base, i)); | |
345 | npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA); | |
346 | } | |
347 | if (data->fan_present[(i * 2) + 1]) { | |
348 | iowrite16(NPCM7XX_FAN_TCNT, | |
349 | NPCM7XX_FAN_REG_TCNT2(data->fan_base, i)); | |
350 | npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB); | |
351 | } | |
352 | } | |
353 | ||
354 | data->fan_select++; | |
355 | data->fan_select &= 0x3; | |
356 | ||
357 | /* reset the timer interval */ | |
358 | data->fan_timer.expires = jiffies + | |
359 | msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS); | |
360 | add_timer(&data->fan_timer); | |
361 | } | |
362 | ||
363 | static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data, | |
364 | u8 fan, u8 cmp, u8 fan_id, u8 flag_int, | |
365 | u8 flag_mode, u8 flag_clear) | |
366 | { | |
367 | u8 reg_int; | |
368 | u8 reg_mode; | |
369 | u16 fan_cap; | |
370 | ||
371 | if (cmp == NPCM7XX_FAN_CMPA) | |
372 | fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan)); | |
373 | else | |
374 | fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan)); | |
375 | ||
376 | /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */ | |
377 | iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan)); | |
378 | ||
379 | if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) { | |
380 | /* First capture, drop it */ | |
381 | data->fan_dev[fan_id].fan_st_flg = | |
382 | FAN_PREPARE_TO_GET_FIRST_CAPTURE; | |
383 | ||
384 | /* reset counter */ | |
385 | data->fan_dev[fan_id].fan_cnt_tmp = 0; | |
386 | } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) { | |
387 | /* | |
388 | * collect the enough sample, | |
389 | * (ex: 2 pulse fan need to get 2 sample) | |
390 | */ | |
391 | data->fan_dev[fan_id].fan_cnt_tmp += | |
392 | (NPCM7XX_FAN_TCNT - fan_cap); | |
393 | ||
394 | data->fan_dev[fan_id].fan_st_flg++; | |
395 | } else { | |
396 | /* get enough sample or fan disable */ | |
397 | if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) { | |
398 | data->fan_dev[fan_id].fan_cnt_tmp += | |
399 | (NPCM7XX_FAN_TCNT - fan_cap); | |
400 | ||
401 | /* compute finial average cnt per pulse */ | |
402 | data->fan_dev[fan_id].fan_cnt = | |
403 | data->fan_dev[fan_id].fan_cnt_tmp / | |
404 | FAN_ENOUGH_SAMPLE; | |
405 | ||
406 | data->fan_dev[fan_id].fan_st_flg = FAN_INIT; | |
407 | } | |
408 | ||
409 | reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); | |
410 | ||
411 | /* disable interrupt */ | |
412 | iowrite8((reg_int & ~flag_int), | |
413 | NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); | |
414 | reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); | |
415 | ||
416 | /* stop capturing */ | |
417 | iowrite8((reg_mode & ~flag_mode), | |
418 | NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); | |
419 | } | |
420 | } | |
421 | ||
422 | static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data, | |
423 | u8 fan, u8 cmp, u8 flag) | |
424 | { | |
425 | u8 reg_int; | |
426 | u8 reg_mode; | |
427 | u8 flag_timeout; | |
428 | u8 flag_cap; | |
429 | u8 flag_clear; | |
430 | u8 flag_int; | |
431 | u8 flag_mode; | |
432 | u8 fan_id; | |
433 | ||
434 | fan_id = NPCM7XX_FAN_INPUT(fan, cmp); | |
435 | ||
436 | if (cmp == NPCM7XX_FAN_CMPA) { | |
437 | flag_cap = NPCM7XX_FAN_TICTRL_TAPND; | |
438 | flag_timeout = NPCM7XX_FAN_TICTRL_TEPND; | |
439 | flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN; | |
440 | flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB; | |
441 | flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR; | |
442 | } else { | |
443 | flag_cap = NPCM7XX_FAN_TICTRL_TBPND; | |
444 | flag_timeout = NPCM7XX_FAN_TICTRL_TFPND; | |
445 | flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN; | |
446 | flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB; | |
447 | flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR; | |
448 | } | |
449 | ||
450 | if (flag & flag_timeout) { | |
451 | reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); | |
452 | ||
453 | /* disable interrupt */ | |
454 | iowrite8((reg_int & ~flag_int), | |
455 | NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); | |
456 | ||
457 | /* clear interrupt flag */ | |
458 | iowrite8(flag_clear, | |
459 | NPCM7XX_FAN_REG_TICLR(data->fan_base, fan)); | |
460 | ||
461 | reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); | |
462 | ||
463 | /* stop capturing */ | |
464 | iowrite8((reg_mode & ~flag_mode), | |
465 | NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); | |
466 | ||
467 | /* | |
468 | * If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't | |
469 | * connect or speed is lower than 10.6Hz (320RPM/pulse2). | |
470 | * In these situation, the RPM output should be zero. | |
471 | */ | |
472 | data->fan_dev[fan_id].fan_cnt = 0; | |
473 | } else { | |
474 | /* input capture is occurred */ | |
475 | if (flag & flag_cap) | |
476 | npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int, | |
477 | flag_mode, flag_clear); | |
478 | } | |
479 | } | |
480 | ||
481 | static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id) | |
482 | { | |
483 | struct npcm7xx_pwm_fan_data *data = dev_id; | |
484 | unsigned long flags; | |
485 | int module; | |
486 | u8 flag; | |
487 | ||
488 | module = irq - data->fan_irq[0]; | |
489 | spin_lock_irqsave(&data->fan_lock[module], flags); | |
490 | ||
491 | flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module)); | |
492 | if (flag > 0) { | |
493 | npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag); | |
494 | npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag); | |
495 | spin_unlock_irqrestore(&data->fan_lock[module], flags); | |
496 | return IRQ_HANDLED; | |
497 | } | |
498 | ||
499 | spin_unlock_irqrestore(&data->fan_lock[module], flags); | |
500 | ||
501 | return IRQ_NONE; | |
502 | } | |
503 | ||
504 | static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel, | |
505 | long *val) | |
506 | { | |
507 | struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); | |
508 | u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); | |
509 | u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); | |
510 | ||
511 | switch (attr) { | |
512 | case hwmon_pwm_input: | |
513 | *val = ioread32 | |
514 | (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch)); | |
515 | return 0; | |
516 | default: | |
517 | return -EOPNOTSUPP; | |
518 | } | |
519 | } | |
520 | ||
521 | static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel, | |
522 | long val) | |
523 | { | |
524 | struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); | |
525 | int err; | |
526 | ||
527 | switch (attr) { | |
528 | case hwmon_pwm_input: | |
529 | if (val < 0 || val > NPCM7XX_PWM_CMR_MAX) | |
530 | return -EINVAL; | |
531 | err = npcm7xx_pwm_config_set(data, channel, (u16)val); | |
532 | break; | |
533 | default: | |
534 | err = -EOPNOTSUPP; | |
535 | break; | |
536 | } | |
537 | ||
538 | return err; | |
539 | } | |
540 | ||
541 | static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel) | |
542 | { | |
543 | const struct npcm7xx_pwm_fan_data *data = _data; | |
544 | ||
545 | if (!data->pwm_present[channel]) | |
546 | return 0; | |
547 | ||
548 | switch (attr) { | |
549 | case hwmon_pwm_input: | |
550 | return 0644; | |
551 | default: | |
552 | return 0; | |
553 | } | |
554 | } | |
555 | ||
556 | static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel, | |
557 | long *val) | |
558 | { | |
559 | struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); | |
560 | ||
561 | switch (attr) { | |
562 | case hwmon_fan_input: | |
563 | *val = 0; | |
564 | if (data->fan_dev[channel].fan_cnt <= 0) | |
565 | return data->fan_dev[channel].fan_cnt; | |
566 | ||
567 | /* Convert the raw reading to RPM */ | |
568 | if (data->fan_dev[channel].fan_cnt > 0 && | |
569 | data->fan_dev[channel].fan_pls_per_rev > 0) | |
570 | *val = ((data->input_clk_freq * 60) / | |
571 | (data->fan_dev[channel].fan_cnt * | |
572 | data->fan_dev[channel].fan_pls_per_rev)); | |
573 | return 0; | |
574 | default: | |
575 | return -EOPNOTSUPP; | |
576 | } | |
577 | } | |
578 | ||
579 | static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel) | |
580 | { | |
581 | const struct npcm7xx_pwm_fan_data *data = _data; | |
582 | ||
583 | if (!data->fan_present[channel]) | |
584 | return 0; | |
585 | ||
586 | switch (attr) { | |
587 | case hwmon_fan_input: | |
588 | return 0444; | |
589 | default: | |
590 | return 0; | |
591 | } | |
592 | } | |
593 | ||
594 | static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type, | |
595 | u32 attr, int channel, long *val) | |
596 | { | |
597 | switch (type) { | |
598 | case hwmon_pwm: | |
599 | return npcm7xx_read_pwm(dev, attr, channel, val); | |
600 | case hwmon_fan: | |
601 | return npcm7xx_read_fan(dev, attr, channel, val); | |
602 | default: | |
603 | return -EOPNOTSUPP; | |
604 | } | |
605 | } | |
606 | ||
607 | static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type, | |
608 | u32 attr, int channel, long val) | |
609 | { | |
610 | switch (type) { | |
611 | case hwmon_pwm: | |
612 | return npcm7xx_write_pwm(dev, attr, channel, val); | |
613 | default: | |
614 | return -EOPNOTSUPP; | |
615 | } | |
616 | } | |
617 | ||
618 | static umode_t npcm7xx_is_visible(const void *data, | |
619 | enum hwmon_sensor_types type, | |
620 | u32 attr, int channel) | |
621 | { | |
622 | switch (type) { | |
623 | case hwmon_pwm: | |
624 | return npcm7xx_pwm_is_visible(data, attr, channel); | |
625 | case hwmon_fan: | |
626 | return npcm7xx_fan_is_visible(data, attr, channel); | |
627 | default: | |
628 | return 0; | |
629 | } | |
630 | } | |
631 | ||
f1fd4a4d | 632 | static const struct hwmon_channel_info *npcm7xx_info[] = { |
dfeace08 GR |
633 | HWMON_CHANNEL_INFO(pwm, |
634 | HWMON_PWM_INPUT, | |
635 | HWMON_PWM_INPUT, | |
636 | HWMON_PWM_INPUT, | |
637 | HWMON_PWM_INPUT, | |
638 | HWMON_PWM_INPUT, | |
639 | HWMON_PWM_INPUT, | |
640 | HWMON_PWM_INPUT, | |
641 | HWMON_PWM_INPUT), | |
642 | HWMON_CHANNEL_INFO(fan, | |
643 | HWMON_F_INPUT, | |
644 | HWMON_F_INPUT, | |
645 | HWMON_F_INPUT, | |
646 | HWMON_F_INPUT, | |
647 | HWMON_F_INPUT, | |
648 | HWMON_F_INPUT, | |
649 | HWMON_F_INPUT, | |
650 | HWMON_F_INPUT, | |
651 | HWMON_F_INPUT, | |
652 | HWMON_F_INPUT, | |
653 | HWMON_F_INPUT, | |
654 | HWMON_F_INPUT, | |
655 | HWMON_F_INPUT, | |
656 | HWMON_F_INPUT, | |
657 | HWMON_F_INPUT, | |
658 | HWMON_F_INPUT), | |
f1fd4a4d TM |
659 | NULL |
660 | }; | |
661 | ||
662 | static const struct hwmon_ops npcm7xx_hwmon_ops = { | |
663 | .is_visible = npcm7xx_is_visible, | |
664 | .read = npcm7xx_read, | |
665 | .write = npcm7xx_write, | |
666 | }; | |
667 | ||
668 | static const struct hwmon_chip_info npcm7xx_chip_info = { | |
669 | .ops = &npcm7xx_hwmon_ops, | |
670 | .info = npcm7xx_info, | |
671 | }; | |
672 | ||
673 | static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data) | |
674 | { | |
675 | int m, ch; | |
676 | u32 prescale_val, output_freq; | |
677 | ||
678 | data->pwm_clk_freq = clk_get_rate(data->pwm_clk); | |
679 | ||
680 | /* Adjust NPCM7xx PWMs output frequency to ~25Khz */ | |
681 | output_freq = data->pwm_clk_freq / PWN_CNT_DEFAULT; | |
682 | prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ); | |
683 | ||
684 | /* If prescale_val = 0, then the prescale output clock is stopped */ | |
685 | if (prescale_val < MIN_PRESCALE1) | |
686 | prescale_val = MIN_PRESCALE1; | |
687 | /* | |
688 | * prescale_val need to decrement in one because in the PWM Prescale | |
689 | * register the Prescale value increment by one | |
690 | */ | |
691 | prescale_val--; | |
692 | ||
693 | /* Setting PWM Prescale Register value register to both modules */ | |
694 | prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01); | |
695 | ||
696 | for (m = 0; m < NPCM7XX_PWM_MAX_MODULES ; m++) { | |
697 | iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m)); | |
698 | iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT, | |
699 | NPCM7XX_PWM_REG_CSR(data->pwm_base, m)); | |
700 | iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT, | |
701 | NPCM7XX_PWM_REG_CR(data->pwm_base, m)); | |
702 | ||
703 | for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) { | |
704 | iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM, | |
705 | NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch)); | |
706 | } | |
707 | } | |
708 | ||
709 | return output_freq / ((prescale_val & 0xf) + 1); | |
710 | } | |
711 | ||
712 | static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data) | |
713 | { | |
714 | int md; | |
715 | int ch; | |
716 | int i; | |
717 | u32 apb_clk_freq; | |
718 | ||
719 | for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) { | |
720 | /* stop FAN0~7 clock */ | |
721 | iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE, | |
722 | NPCM7XX_FAN_REG_TCKC(data->fan_base, md)); | |
723 | ||
724 | /* disable all interrupt */ | |
725 | iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md)); | |
726 | ||
727 | /* clear all interrupt */ | |
728 | iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL, | |
729 | NPCM7XX_FAN_REG_TICLR(data->fan_base, md)); | |
730 | ||
731 | /* set FAN0~7 clock prescaler */ | |
732 | iowrite8(NPCM7XX_FAN_CLK_PRESCALE, | |
733 | NPCM7XX_FAN_REG_TPRSC(data->fan_base, md)); | |
734 | ||
735 | /* set FAN0~7 mode (high-to-low transition) */ | |
736 | iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN | | |
737 | NPCM7XX_FAN_TMCTRL_TAEN), | |
738 | NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md)); | |
739 | ||
740 | /* set FAN0~7 Initial Count/Cap */ | |
741 | iowrite16(NPCM7XX_FAN_TCNT, | |
742 | NPCM7XX_FAN_REG_TCNT1(data->fan_base, md)); | |
743 | iowrite16(NPCM7XX_FAN_TCNT, | |
744 | NPCM7XX_FAN_REG_TCNT2(data->fan_base, md)); | |
745 | ||
746 | /* set FAN0~7 compare (equal to count) */ | |
747 | iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN), | |
748 | NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md)); | |
749 | ||
750 | /* set FAN0~7 compare value */ | |
751 | iowrite16(NPCM7XX_FAN_TCPA, | |
752 | NPCM7XX_FAN_REG_TCPA(data->fan_base, md)); | |
753 | iowrite16(NPCM7XX_FAN_TCPB, | |
754 | NPCM7XX_FAN_REG_TCPB(data->fan_base, md)); | |
755 | ||
756 | /* set FAN0~7 fan input FANIN 0~15 */ | |
757 | iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT, | |
758 | NPCM7XX_FAN_REG_TINASEL(data->fan_base, md)); | |
759 | iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT, | |
760 | NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md)); | |
761 | ||
762 | for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) { | |
763 | ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i; | |
764 | data->fan_dev[ch].fan_st_flg = FAN_DISABLE; | |
765 | data->fan_dev[ch].fan_pls_per_rev = | |
766 | NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION; | |
767 | data->fan_dev[ch].fan_cnt = 0; | |
768 | } | |
769 | } | |
770 | ||
771 | apb_clk_freq = clk_get_rate(data->fan_clk); | |
772 | ||
773 | /* Fan tach input clock = APB clock / prescalar, default is 255. */ | |
774 | data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1); | |
775 | } | |
776 | ||
777 | static int | |
778 | npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev, | |
779 | unsigned long *state) | |
780 | { | |
781 | struct npcm7xx_cooling_device *cdev = tcdev->devdata; | |
782 | ||
783 | *state = cdev->max_state; | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
788 | static int | |
789 | npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev, | |
790 | unsigned long *state) | |
791 | { | |
792 | struct npcm7xx_cooling_device *cdev = tcdev->devdata; | |
793 | ||
794 | *state = cdev->cur_state; | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | static int | |
800 | npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev, | |
801 | unsigned long state) | |
802 | { | |
803 | struct npcm7xx_cooling_device *cdev = tcdev->devdata; | |
804 | int ret; | |
805 | ||
806 | if (state > cdev->max_state) | |
807 | return -EINVAL; | |
808 | ||
809 | cdev->cur_state = state; | |
810 | ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port, | |
811 | cdev->cooling_levels[cdev->cur_state]); | |
812 | ||
813 | return ret; | |
814 | } | |
815 | ||
816 | static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = { | |
817 | .get_max_state = npcm7xx_pwm_cz_get_max_state, | |
818 | .get_cur_state = npcm7xx_pwm_cz_get_cur_state, | |
819 | .set_cur_state = npcm7xx_pwm_cz_set_cur_state, | |
820 | }; | |
821 | ||
822 | static int npcm7xx_create_pwm_cooling(struct device *dev, | |
823 | struct device_node *child, | |
824 | struct npcm7xx_pwm_fan_data *data, | |
825 | u32 pwm_port, u8 num_levels) | |
826 | { | |
827 | int ret; | |
828 | struct npcm7xx_cooling_device *cdev; | |
829 | ||
830 | cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); | |
831 | if (!cdev) | |
832 | return -ENOMEM; | |
833 | ||
834 | cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); | |
835 | if (!cdev->cooling_levels) | |
836 | return -ENOMEM; | |
837 | ||
838 | cdev->max_state = num_levels - 1; | |
839 | ret = of_property_read_u8_array(child, "cooling-levels", | |
840 | cdev->cooling_levels, | |
841 | num_levels); | |
842 | if (ret) { | |
843 | dev_err(dev, "Property 'cooling-levels' cannot be read.\n"); | |
844 | return ret; | |
845 | } | |
0debe4d0 | 846 | snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child, |
f1fd4a4d TM |
847 | pwm_port); |
848 | ||
0b2a785d GR |
849 | cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child, |
850 | cdev->name, cdev, &npcm7xx_pwm_cool_ops); | |
f1fd4a4d TM |
851 | if (IS_ERR(cdev->tcdev)) |
852 | return PTR_ERR(cdev->tcdev); | |
853 | ||
854 | cdev->data = data; | |
855 | cdev->pwm_port = pwm_port; | |
856 | ||
857 | data->cdev[pwm_port] = cdev; | |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
862 | static int npcm7xx_en_pwm_fan(struct device *dev, | |
863 | struct device_node *child, | |
864 | struct npcm7xx_pwm_fan_data *data) | |
865 | { | |
866 | u8 *fan_ch; | |
867 | u32 pwm_port; | |
868 | int ret, fan_cnt; | |
869 | u8 index, ch; | |
870 | ||
871 | ret = of_property_read_u32(child, "reg", &pwm_port); | |
872 | if (ret) | |
873 | return ret; | |
874 | ||
875 | data->pwm_present[pwm_port] = true; | |
876 | ret = npcm7xx_pwm_config_set(data, pwm_port, | |
877 | NPCM7XX_PWM_CMR_DEFAULT_NUM); | |
878 | ||
879 | ret = of_property_count_u8_elems(child, "cooling-levels"); | |
880 | if (ret > 0) { | |
881 | ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port, | |
882 | ret); | |
883 | if (ret) | |
884 | return ret; | |
885 | } | |
886 | ||
887 | fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch"); | |
888 | if (fan_cnt < 1) | |
889 | return -EINVAL; | |
890 | ||
329e0989 | 891 | fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL); |
f1fd4a4d TM |
892 | if (!fan_ch) |
893 | return -ENOMEM; | |
894 | ||
895 | ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt); | |
896 | if (ret) | |
897 | return ret; | |
898 | ||
899 | for (ch = 0; ch < fan_cnt; ch++) { | |
900 | index = fan_ch[ch]; | |
901 | data->fan_present[index] = true; | |
902 | data->fan_dev[index].fan_st_flg = FAN_INIT; | |
903 | } | |
904 | ||
905 | return 0; | |
906 | } | |
907 | ||
908 | static int npcm7xx_pwm_fan_probe(struct platform_device *pdev) | |
909 | { | |
910 | struct device *dev = &pdev->dev; | |
911 | struct device_node *np, *child; | |
912 | struct npcm7xx_pwm_fan_data *data; | |
913 | struct resource *res; | |
914 | struct device *hwmon; | |
915 | char name[20]; | |
916 | int ret, cnt; | |
917 | u32 output_freq; | |
918 | u32 i; | |
919 | ||
920 | np = dev->of_node; | |
921 | ||
922 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
923 | if (!data) | |
924 | return -ENOMEM; | |
925 | ||
926 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); | |
927 | if (!res) { | |
928 | dev_err(dev, "pwm resource not found\n"); | |
929 | return -ENODEV; | |
930 | } | |
931 | ||
932 | data->pwm_base = devm_ioremap_resource(dev, res); | |
933 | dev_dbg(dev, "pwm base resource is %pR\n", res); | |
934 | if (IS_ERR(data->pwm_base)) | |
935 | return PTR_ERR(data->pwm_base); | |
936 | ||
937 | data->pwm_clk = devm_clk_get(dev, "pwm"); | |
938 | if (IS_ERR(data->pwm_clk)) { | |
939 | dev_err(dev, "couldn't get pwm clock\n"); | |
940 | return PTR_ERR(data->pwm_clk); | |
941 | } | |
942 | ||
943 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan"); | |
944 | if (!res) { | |
945 | dev_err(dev, "fan resource not found\n"); | |
946 | return -ENODEV; | |
947 | } | |
948 | ||
949 | data->fan_base = devm_ioremap_resource(dev, res); | |
950 | dev_dbg(dev, "fan base resource is %pR\n", res); | |
951 | if (IS_ERR(data->fan_base)) | |
952 | return PTR_ERR(data->fan_base); | |
953 | ||
954 | data->fan_clk = devm_clk_get(dev, "fan"); | |
955 | if (IS_ERR(data->fan_clk)) { | |
956 | dev_err(dev, "couldn't get fan clock\n"); | |
957 | return PTR_ERR(data->fan_clk); | |
958 | } | |
959 | ||
960 | output_freq = npcm7xx_pwm_init(data); | |
961 | npcm7xx_fan_init(data); | |
962 | ||
963 | for (cnt = 0; cnt < NPCM7XX_PWM_MAX_MODULES ; cnt++) | |
964 | mutex_init(&data->pwm_lock[cnt]); | |
965 | ||
966 | for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) { | |
967 | spin_lock_init(&data->fan_lock[i]); | |
968 | ||
969 | data->fan_irq[i] = platform_get_irq(pdev, i); | |
f2ff7cea | 970 | if (data->fan_irq[i] < 0) |
f1fd4a4d | 971 | return data->fan_irq[i]; |
f1fd4a4d TM |
972 | |
973 | sprintf(name, "NPCM7XX-FAN-MD%d", i); | |
974 | ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr, | |
975 | 0, name, (void *)data); | |
976 | if (ret) { | |
977 | dev_err(dev, "register IRQ fan%d failed\n", i); | |
978 | return ret; | |
979 | } | |
980 | } | |
981 | ||
982 | for_each_child_of_node(np, child) { | |
983 | ret = npcm7xx_en_pwm_fan(dev, child, data); | |
984 | if (ret) { | |
985 | dev_err(dev, "enable pwm and fan failed\n"); | |
986 | of_node_put(child); | |
987 | return ret; | |
988 | } | |
989 | } | |
990 | ||
991 | hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan", | |
992 | data, &npcm7xx_chip_info, | |
993 | NULL); | |
994 | if (IS_ERR(hwmon)) { | |
995 | dev_err(dev, "unable to register hwmon device\n"); | |
996 | return PTR_ERR(hwmon); | |
997 | } | |
998 | ||
999 | for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) { | |
1000 | if (data->fan_present[i]) { | |
1001 | /* fan timer initialization */ | |
1002 | data->fan_timer.expires = jiffies + | |
1003 | msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS); | |
1004 | timer_setup(&data->fan_timer, | |
1005 | npcm7xx_fan_polling, 0); | |
1006 | add_timer(&data->fan_timer); | |
1007 | break; | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n", | |
1012 | output_freq, data->input_clk_freq); | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | static const struct of_device_id of_pwm_fan_match_table[] = { | |
1018 | { .compatible = "nuvoton,npcm750-pwm-fan", }, | |
1019 | {}, | |
1020 | }; | |
1021 | MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table); | |
1022 | ||
1023 | static struct platform_driver npcm7xx_pwm_fan_driver = { | |
1024 | .probe = npcm7xx_pwm_fan_probe, | |
1025 | .driver = { | |
1026 | .name = "npcm7xx_pwm_fan", | |
1027 | .of_match_table = of_pwm_fan_match_table, | |
1028 | }, | |
1029 | }; | |
1030 | ||
1031 | module_platform_driver(npcm7xx_pwm_fan_driver); | |
1032 | ||
1033 | MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver"); | |
1034 | MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); | |
1035 | MODULE_LICENSE("GPL v2"); |