Commit | Line | Data |
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9de2e2e8 GR |
1 | /* |
2 | * nct6775 - Driver for the hardware monitoring functionality of | |
3 | * Nuvoton NCT677x Super-I/O chips | |
4 | * | |
5 | * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net> | |
6 | * | |
7 | * Derived from w83627ehf driver | |
7c81c60f | 8 | * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de> |
9de2e2e8 GR |
9 | * Copyright (C) 2006 Yuan Mu (Winbond), |
10 | * Rudolf Marek <r.marek@assembler.cz> | |
11 | * David Hubbard <david.c.hubbard@gmail.com> | |
12 | * Daniel J Blueman <daniel.blueman@gmail.com> | |
13 | * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00) | |
14 | * | |
15 | * Shamelessly ripped from the w83627hf driver | |
16 | * Copyright (C) 2003 Mark Studebaker | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
31 | * | |
32 | * | |
33 | * Supports the following chips: | |
34 | * | |
35 | * Chip #vin #fan #pwm #temp chip IDs man ID | |
6c009501 | 36 | * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3 |
9de2e2e8 GR |
37 | * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3 |
38 | * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3 | |
39 | * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3 | |
578ab5f0 | 40 | * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3 |
8aefb93f | 41 | * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3 |
cd1faefa | 42 | * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3 |
9de2e2e8 GR |
43 | * |
44 | * #temp lists the number of monitored temperature sources (first value) plus | |
45 | * the number of directly connectable temperature sensors (second value). | |
46 | */ | |
47 | ||
48 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
49 | ||
50 | #include <linux/module.h> | |
51 | #include <linux/init.h> | |
52 | #include <linux/slab.h> | |
53 | #include <linux/jiffies.h> | |
54 | #include <linux/platform_device.h> | |
55 | #include <linux/hwmon.h> | |
56 | #include <linux/hwmon-sysfs.h> | |
57 | #include <linux/hwmon-vid.h> | |
58 | #include <linux/err.h> | |
59 | #include <linux/mutex.h> | |
60 | #include <linux/acpi.h> | |
25cdd99d | 61 | #include <linux/dmi.h> |
9de2e2e8 GR |
62 | #include <linux/io.h> |
63 | #include "lm75.h" | |
64 | ||
aa136e5d GR |
65 | #define USE_ALTERNATE |
66 | ||
cd1faefa | 67 | enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793 }; |
9de2e2e8 GR |
68 | |
69 | /* used to set data->name = nct6775_device_names[data->sio_kind] */ | |
70 | static const char * const nct6775_device_names[] = { | |
6c009501 | 71 | "nct6106", |
9de2e2e8 GR |
72 | "nct6775", |
73 | "nct6776", | |
74 | "nct6779", | |
578ab5f0 | 75 | "nct6791", |
8aefb93f | 76 | "nct6792", |
cd1faefa GR |
77 | "nct6793", |
78 | }; | |
79 | ||
80 | static const char * const nct6775_sio_names[] __initconst = { | |
81 | "NCT6106D", | |
82 | "NCT6775F", | |
83 | "NCT6776D/F", | |
84 | "NCT6779D", | |
85 | "NCT6791D", | |
86 | "NCT6792D", | |
87 | "NCT6793D", | |
9de2e2e8 GR |
88 | }; |
89 | ||
90 | static unsigned short force_id; | |
91 | module_param(force_id, ushort, 0); | |
92 | MODULE_PARM_DESC(force_id, "Override the detected device ID"); | |
93 | ||
47ece964 GR |
94 | static unsigned short fan_debounce; |
95 | module_param(fan_debounce, ushort, 0); | |
96 | MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal"); | |
97 | ||
9de2e2e8 GR |
98 | #define DRVNAME "nct6775" |
99 | ||
100 | /* | |
101 | * Super-I/O constants and functions | |
102 | */ | |
103 | ||
a6bd5878 | 104 | #define NCT6775_LD_ACPI 0x0a |
9de2e2e8 GR |
105 | #define NCT6775_LD_HWM 0x0b |
106 | #define NCT6775_LD_VID 0x0d | |
107 | ||
108 | #define SIO_REG_LDSEL 0x07 /* Logical device select */ | |
109 | #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */ | |
110 | #define SIO_REG_ENABLE 0x30 /* Logical device enable */ | |
111 | #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */ | |
112 | ||
6c009501 | 113 | #define SIO_NCT6106_ID 0xc450 |
9de2e2e8 GR |
114 | #define SIO_NCT6775_ID 0xb470 |
115 | #define SIO_NCT6776_ID 0xc330 | |
116 | #define SIO_NCT6779_ID 0xc560 | |
578ab5f0 | 117 | #define SIO_NCT6791_ID 0xc800 |
8aefb93f | 118 | #define SIO_NCT6792_ID 0xc910 |
cd1faefa | 119 | #define SIO_NCT6793_ID 0xd120 |
9de2e2e8 GR |
120 | #define SIO_ID_MASK 0xFFF0 |
121 | ||
77eb5b37 GR |
122 | enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 }; |
123 | ||
9de2e2e8 GR |
124 | static inline void |
125 | superio_outb(int ioreg, int reg, int val) | |
126 | { | |
127 | outb(reg, ioreg); | |
128 | outb(val, ioreg + 1); | |
129 | } | |
130 | ||
131 | static inline int | |
132 | superio_inb(int ioreg, int reg) | |
133 | { | |
134 | outb(reg, ioreg); | |
135 | return inb(ioreg + 1); | |
136 | } | |
137 | ||
138 | static inline void | |
139 | superio_select(int ioreg, int ld) | |
140 | { | |
141 | outb(SIO_REG_LDSEL, ioreg); | |
142 | outb(ld, ioreg + 1); | |
143 | } | |
144 | ||
145 | static inline int | |
146 | superio_enter(int ioreg) | |
147 | { | |
148 | /* | |
149 | * Try to reserve <ioreg> and <ioreg + 1> for exclusive access. | |
150 | */ | |
151 | if (!request_muxed_region(ioreg, 2, DRVNAME)) | |
152 | return -EBUSY; | |
153 | ||
154 | outb(0x87, ioreg); | |
155 | outb(0x87, ioreg); | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | static inline void | |
161 | superio_exit(int ioreg) | |
162 | { | |
163 | outb(0xaa, ioreg); | |
164 | outb(0x02, ioreg); | |
165 | outb(0x02, ioreg + 1); | |
166 | release_region(ioreg, 2); | |
167 | } | |
168 | ||
169 | /* | |
170 | * ISA constants | |
171 | */ | |
172 | ||
173 | #define IOREGION_ALIGNMENT (~7) | |
174 | #define IOREGION_OFFSET 5 | |
175 | #define IOREGION_LENGTH 2 | |
176 | #define ADDR_REG_OFFSET 0 | |
177 | #define DATA_REG_OFFSET 1 | |
178 | ||
179 | #define NCT6775_REG_BANK 0x4E | |
180 | #define NCT6775_REG_CONFIG 0x40 | |
181 | ||
182 | /* | |
183 | * Not currently used: | |
184 | * REG_MAN_ID has the value 0x5ca3 for all supported chips. | |
185 | * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model. | |
186 | * REG_MAN_ID is at port 0x4f | |
187 | * REG_CHIP_ID is at port 0x58 | |
188 | */ | |
189 | ||
aa136e5d GR |
190 | #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/ |
191 | #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */ | |
192 | ||
6c009501 | 193 | #define NUM_REG_ALARM 7 /* Max number of alarm registers */ |
30846993 | 194 | #define NUM_REG_BEEP 5 /* Max number of beep registers */ |
9de2e2e8 | 195 | |
578ab5f0 DB |
196 | #define NUM_FAN 6 |
197 | ||
7ce4190c GR |
198 | #define TEMP_SOURCE_VIRTUAL 0x1f |
199 | ||
9de2e2e8 GR |
200 | /* Common and NCT6775 specific data */ |
201 | ||
202 | /* Voltage min/max registers for nr=7..14 are in bank 5 */ | |
203 | ||
204 | static const u16 NCT6775_REG_IN_MAX[] = { | |
205 | 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a, | |
206 | 0x55c, 0x55e, 0x560, 0x562 }; | |
207 | static const u16 NCT6775_REG_IN_MIN[] = { | |
208 | 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b, | |
209 | 0x55d, 0x55f, 0x561, 0x563 }; | |
210 | static const u16 NCT6775_REG_IN[] = { | |
211 | 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552 | |
212 | }; | |
213 | ||
214 | #define NCT6775_REG_VBAT 0x5D | |
aa136e5d | 215 | #define NCT6775_REG_DIODE 0x5E |
6c009501 | 216 | #define NCT6775_DIODE_MASK 0x02 |
9de2e2e8 | 217 | |
1c65dc36 GR |
218 | #define NCT6775_REG_FANDIV1 0x506 |
219 | #define NCT6775_REG_FANDIV2 0x507 | |
220 | ||
47ece964 GR |
221 | #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0 |
222 | ||
9de2e2e8 GR |
223 | static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B }; |
224 | ||
30846993 | 225 | /* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */ |
9de2e2e8 GR |
226 | |
227 | static const s8 NCT6775_ALARM_BITS[] = { | |
228 | 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */ | |
229 | 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */ | |
230 | -1, /* unused */ | |
41fa9a94 | 231 | 6, 7, 11, -1, -1, /* fan1..fan5 */ |
9de2e2e8 GR |
232 | -1, -1, -1, /* unused */ |
233 | 4, 5, 13, -1, -1, -1, /* temp1..temp6 */ | |
234 | 12, -1 }; /* intrusion0, intrusion1 */ | |
235 | ||
1c65dc36 | 236 | #define FAN_ALARM_BASE 16 |
aa136e5d | 237 | #define TEMP_ALARM_BASE 24 |
a6bd5878 GR |
238 | #define INTRUSION_ALARM_BASE 30 |
239 | ||
30846993 GR |
240 | static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e }; |
241 | ||
242 | /* | |
243 | * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures, | |
244 | * 30..31 intrusion | |
245 | */ | |
246 | static const s8 NCT6775_BEEP_BITS[] = { | |
247 | 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */ | |
248 | 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */ | |
249 | 21, /* global beep enable */ | |
250 | 6, 7, 11, 28, -1, /* fan1..fan5 */ | |
251 | -1, -1, -1, /* unused */ | |
252 | 4, 5, 13, -1, -1, -1, /* temp1..temp6 */ | |
253 | 12, -1 }; /* intrusion0, intrusion1 */ | |
254 | ||
255 | #define BEEP_ENABLE_BASE 15 | |
256 | ||
a6bd5878 GR |
257 | static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee }; |
258 | static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 }; | |
259 | ||
77eb5b37 GR |
260 | /* DC or PWM output fan configuration */ |
261 | static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 }; | |
262 | static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 }; | |
263 | ||
cdcaeceb | 264 | /* Advanced Fan control, some values are common for all fans */ |
77eb5b37 | 265 | |
578ab5f0 DB |
266 | static const u16 NCT6775_REG_TARGET[] = { |
267 | 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01 }; | |
268 | static const u16 NCT6775_REG_FAN_MODE[] = { | |
269 | 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02 }; | |
cdcaeceb | 270 | static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = { |
578ab5f0 | 271 | 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03 }; |
cdcaeceb | 272 | static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = { |
578ab5f0 | 273 | 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04 }; |
cdcaeceb | 274 | static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { |
578ab5f0 DB |
275 | 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05 }; |
276 | static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { | |
277 | 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06 }; | |
cdcaeceb GR |
278 | static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a }; |
279 | static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b }; | |
280 | ||
281 | static const u16 NCT6775_REG_FAN_STOP_TIME[] = { | |
578ab5f0 DB |
282 | 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07 }; |
283 | static const u16 NCT6775_REG_PWM[] = { | |
284 | 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09 }; | |
285 | static const u16 NCT6775_REG_PWM_READ[] = { | |
286 | 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09 }; | |
77eb5b37 | 287 | |
1c65dc36 GR |
288 | static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 }; |
289 | static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d }; | |
5c25d954 | 290 | static const u16 NCT6775_REG_FAN_PULSES[] = { 0x641, 0x642, 0x643, 0x644, 0 }; |
578ab5f0 | 291 | static const u16 NCT6775_FAN_PULSE_SHIFT[] = { 0, 0, 0, 0, 0, 0 }; |
1c65dc36 | 292 | |
aa136e5d GR |
293 | static const u16 NCT6775_REG_TEMP[] = { |
294 | 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d }; | |
295 | ||
d1a284b7 GR |
296 | static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 }; |
297 | ||
aa136e5d GR |
298 | static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = { |
299 | 0, 0x152, 0x252, 0x628, 0x629, 0x62A }; | |
300 | static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = { | |
301 | 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D }; | |
302 | static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = { | |
303 | 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C }; | |
304 | ||
305 | static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = { | |
306 | 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 }; | |
307 | ||
cdcaeceb | 308 | static const u16 NCT6775_REG_TEMP_SEL[] = { |
578ab5f0 | 309 | 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00 }; |
cdcaeceb | 310 | |
bbd8decd | 311 | static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = { |
578ab5f0 | 312 | 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 }; |
bbd8decd | 313 | static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = { |
578ab5f0 | 314 | 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a }; |
bbd8decd | 315 | static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = { |
578ab5f0 | 316 | 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b }; |
bbd8decd | 317 | static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = { |
578ab5f0 | 318 | 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c }; |
bbd8decd | 319 | static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = { |
578ab5f0 | 320 | 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d }; |
bbd8decd | 321 | |
aa136e5d GR |
322 | static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 }; |
323 | ||
cdcaeceb | 324 | static const u16 NCT6775_REG_AUTO_TEMP[] = { |
578ab5f0 | 325 | 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21 }; |
cdcaeceb | 326 | static const u16 NCT6775_REG_AUTO_PWM[] = { |
578ab5f0 | 327 | 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27 }; |
cdcaeceb GR |
328 | |
329 | #define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p)) | |
330 | #define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p)) | |
331 | ||
332 | static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 }; | |
333 | ||
334 | static const u16 NCT6775_REG_CRITICAL_TEMP[] = { | |
578ab5f0 | 335 | 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35 }; |
cdcaeceb | 336 | static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = { |
578ab5f0 | 337 | 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38 }; |
cdcaeceb | 338 | |
aa136e5d GR |
339 | static const char *const nct6775_temp_label[] = { |
340 | "", | |
341 | "SYSTIN", | |
342 | "CPUTIN", | |
343 | "AUXTIN", | |
344 | "AMD SB-TSI", | |
345 | "PECI Agent 0", | |
346 | "PECI Agent 1", | |
347 | "PECI Agent 2", | |
348 | "PECI Agent 3", | |
349 | "PECI Agent 4", | |
350 | "PECI Agent 5", | |
351 | "PECI Agent 6", | |
352 | "PECI Agent 7", | |
353 | "PCH_CHIP_CPU_MAX_TEMP", | |
354 | "PCH_CHIP_TEMP", | |
355 | "PCH_CPU_TEMP", | |
356 | "PCH_MCH_TEMP", | |
357 | "PCH_DIM0_TEMP", | |
358 | "PCH_DIM1_TEMP", | |
359 | "PCH_DIM2_TEMP", | |
360 | "PCH_DIM3_TEMP" | |
361 | }; | |
362 | ||
363 | static const u16 NCT6775_REG_TEMP_ALTERNATE[ARRAY_SIZE(nct6775_temp_label) - 1] | |
364 | = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x661, 0x662, 0x664 }; | |
365 | ||
366 | static const u16 NCT6775_REG_TEMP_CRIT[ARRAY_SIZE(nct6775_temp_label) - 1] | |
367 | = { 0, 0, 0, 0, 0xa00, 0xa01, 0xa02, 0xa03, 0xa04, 0xa05, 0xa06, | |
368 | 0xa07 }; | |
369 | ||
9de2e2e8 GR |
370 | /* NCT6776 specific data */ |
371 | ||
728d2940 GR |
372 | /* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */ |
373 | #define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME | |
374 | #define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME | |
375 | ||
9de2e2e8 GR |
376 | static const s8 NCT6776_ALARM_BITS[] = { |
377 | 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */ | |
378 | 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */ | |
379 | -1, /* unused */ | |
380 | 6, 7, 11, 10, 23, /* fan1..fan5 */ | |
381 | -1, -1, -1, /* unused */ | |
382 | 4, 5, 13, -1, -1, -1, /* temp1..temp6 */ | |
383 | 12, 9 }; /* intrusion0, intrusion1 */ | |
384 | ||
30846993 GR |
385 | static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 }; |
386 | ||
387 | static const s8 NCT6776_BEEP_BITS[] = { | |
388 | 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */ | |
389 | 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */ | |
390 | 24, /* global beep enable */ | |
391 | 25, 26, 27, 28, 29, /* fan1..fan5 */ | |
392 | -1, -1, -1, /* unused */ | |
393 | 16, 17, 18, 19, 20, 21, /* temp1..temp6 */ | |
394 | 30, 31 }; /* intrusion0, intrusion1 */ | |
395 | ||
cdcaeceb | 396 | static const u16 NCT6776_REG_TOLERANCE_H[] = { |
578ab5f0 | 397 | 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c }; |
cdcaeceb | 398 | |
578ab5f0 DB |
399 | static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 }; |
400 | static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 }; | |
77eb5b37 | 401 | |
1c65dc36 | 402 | static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642 }; |
5c25d954 | 403 | static const u16 NCT6776_REG_FAN_PULSES[] = { 0x644, 0x645, 0x646, 0, 0 }; |
1c65dc36 | 404 | |
bbd8decd | 405 | static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = { |
578ab5f0 | 406 | 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e }; |
bbd8decd | 407 | |
aa136e5d GR |
408 | static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = { |
409 | 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A }; | |
410 | ||
411 | static const char *const nct6776_temp_label[] = { | |
412 | "", | |
413 | "SYSTIN", | |
414 | "CPUTIN", | |
415 | "AUXTIN", | |
416 | "SMBUSMASTER 0", | |
417 | "SMBUSMASTER 1", | |
418 | "SMBUSMASTER 2", | |
419 | "SMBUSMASTER 3", | |
420 | "SMBUSMASTER 4", | |
421 | "SMBUSMASTER 5", | |
422 | "SMBUSMASTER 6", | |
423 | "SMBUSMASTER 7", | |
424 | "PECI Agent 0", | |
425 | "PECI Agent 1", | |
426 | "PCH_CHIP_CPU_MAX_TEMP", | |
427 | "PCH_CHIP_TEMP", | |
428 | "PCH_CPU_TEMP", | |
429 | "PCH_MCH_TEMP", | |
430 | "PCH_DIM0_TEMP", | |
431 | "PCH_DIM1_TEMP", | |
432 | "PCH_DIM2_TEMP", | |
433 | "PCH_DIM3_TEMP", | |
434 | "BYTE_TEMP" | |
435 | }; | |
436 | ||
437 | static const u16 NCT6776_REG_TEMP_ALTERNATE[ARRAY_SIZE(nct6776_temp_label) - 1] | |
438 | = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x401, 0x402, 0x404 }; | |
439 | ||
440 | static const u16 NCT6776_REG_TEMP_CRIT[ARRAY_SIZE(nct6776_temp_label) - 1] | |
441 | = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x709, 0x70a }; | |
442 | ||
9de2e2e8 GR |
443 | /* NCT6779 specific data */ |
444 | ||
445 | static const u16 NCT6779_REG_IN[] = { | |
446 | 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487, | |
447 | 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e }; | |
448 | ||
449 | static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = { | |
450 | 0x459, 0x45A, 0x45B, 0x568 }; | |
451 | ||
452 | static const s8 NCT6779_ALARM_BITS[] = { | |
453 | 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */ | |
454 | 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */ | |
455 | -1, /* unused */ | |
456 | 6, 7, 11, 10, 23, /* fan1..fan5 */ | |
457 | -1, -1, -1, /* unused */ | |
458 | 4, 5, 13, -1, -1, -1, /* temp1..temp6 */ | |
459 | 12, 9 }; /* intrusion0, intrusion1 */ | |
460 | ||
30846993 GR |
461 | static const s8 NCT6779_BEEP_BITS[] = { |
462 | 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */ | |
463 | 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */ | |
464 | 24, /* global beep enable */ | |
465 | 25, 26, 27, 28, 29, /* fan1..fan5 */ | |
466 | -1, -1, -1, /* unused */ | |
467 | 16, 17, -1, -1, -1, -1, /* temp1..temp6 */ | |
468 | 30, 31 }; /* intrusion0, intrusion1 */ | |
469 | ||
578ab5f0 DB |
470 | static const u16 NCT6779_REG_FAN[] = { |
471 | 0x4b0, 0x4b2, 0x4b4, 0x4b6, 0x4b8, 0x4ba }; | |
5c25d954 | 472 | static const u16 NCT6779_REG_FAN_PULSES[] = { |
578ab5f0 | 473 | 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 }; |
1c65dc36 | 474 | |
cdcaeceb | 475 | static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = { |
578ab5f0 | 476 | 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36 }; |
6c009501 | 477 | #define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01 |
cdcaeceb | 478 | static const u16 NCT6779_REG_CRITICAL_PWM[] = { |
578ab5f0 | 479 | 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37 }; |
cdcaeceb | 480 | |
aa136e5d | 481 | static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 }; |
d1a284b7 | 482 | static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b }; |
aa136e5d GR |
483 | static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = { |
484 | 0x18, 0x152 }; | |
485 | static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = { | |
486 | 0x3a, 0x153 }; | |
487 | static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = { | |
488 | 0x39, 0x155 }; | |
489 | ||
490 | static const u16 NCT6779_REG_TEMP_OFFSET[] = { | |
491 | 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c }; | |
492 | ||
493 | static const char *const nct6779_temp_label[] = { | |
494 | "", | |
495 | "SYSTIN", | |
496 | "CPUTIN", | |
497 | "AUXTIN0", | |
498 | "AUXTIN1", | |
499 | "AUXTIN2", | |
500 | "AUXTIN3", | |
501 | "", | |
502 | "SMBUSMASTER 0", | |
503 | "SMBUSMASTER 1", | |
504 | "SMBUSMASTER 2", | |
505 | "SMBUSMASTER 3", | |
506 | "SMBUSMASTER 4", | |
507 | "SMBUSMASTER 5", | |
508 | "SMBUSMASTER 6", | |
509 | "SMBUSMASTER 7", | |
510 | "PECI Agent 0", | |
511 | "PECI Agent 1", | |
512 | "PCH_CHIP_CPU_MAX_TEMP", | |
513 | "PCH_CHIP_TEMP", | |
514 | "PCH_CPU_TEMP", | |
515 | "PCH_MCH_TEMP", | |
516 | "PCH_DIM0_TEMP", | |
517 | "PCH_DIM1_TEMP", | |
518 | "PCH_DIM2_TEMP", | |
519 | "PCH_DIM3_TEMP", | |
9a38371a GR |
520 | "BYTE_TEMP", |
521 | "", | |
522 | "", | |
523 | "", | |
524 | "", | |
525 | "Virtual_TEMP" | |
aa136e5d GR |
526 | }; |
527 | ||
9a38371a GR |
528 | #define NCT6779_NUM_LABELS (ARRAY_SIZE(nct6779_temp_label) - 5) |
529 | #define NCT6791_NUM_LABELS ARRAY_SIZE(nct6779_temp_label) | |
530 | ||
531 | static const u16 NCT6779_REG_TEMP_ALTERNATE[NCT6791_NUM_LABELS - 1] | |
aa136e5d GR |
532 | = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0, |
533 | 0, 0, 0, 0, 0, 0, 0, 0, | |
534 | 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407, | |
535 | 0x408, 0 }; | |
536 | ||
9a38371a | 537 | static const u16 NCT6779_REG_TEMP_CRIT[NCT6791_NUM_LABELS - 1] |
aa136e5d GR |
538 | = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x709, 0x70a }; |
539 | ||
578ab5f0 DB |
540 | /* NCT6791 specific data */ |
541 | ||
542 | #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28 | |
543 | ||
cc76dee1 GR |
544 | static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[6] = { 0, 0x239 }; |
545 | static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[6] = { 0, 0x23a }; | |
546 | static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[6] = { 0, 0x23b }; | |
547 | static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[6] = { 0, 0x23c }; | |
548 | static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[6] = { 0, 0x23d }; | |
549 | static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[6] = { 0, 0x23e }; | |
550 | ||
578ab5f0 DB |
551 | static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = { |
552 | 0x459, 0x45A, 0x45B, 0x568, 0x45D }; | |
553 | ||
554 | static const s8 NCT6791_ALARM_BITS[] = { | |
555 | 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */ | |
556 | 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */ | |
557 | -1, /* unused */ | |
558 | 6, 7, 11, 10, 23, 33, /* fan1..fan6 */ | |
559 | -1, -1, /* unused */ | |
560 | 4, 5, 13, -1, -1, -1, /* temp1..temp6 */ | |
561 | 12, 9 }; /* intrusion0, intrusion1 */ | |
562 | ||
cd1faefa | 563 | /* NCT6792/NCT6793 specific data */ |
8aefb93f GR |
564 | |
565 | static const u16 NCT6792_REG_TEMP_MON[] = { | |
566 | 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d }; | |
567 | static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = { | |
568 | 0xb2, 0xb3, 0xb4, 0xb5, 0xbf }; | |
578ab5f0 | 569 | |
50224f4d GR |
570 | static const char *const nct6792_temp_label[] = { |
571 | "", | |
572 | "SYSTIN", | |
573 | "CPUTIN", | |
574 | "AUXTIN0", | |
575 | "AUXTIN1", | |
576 | "AUXTIN2", | |
577 | "AUXTIN3", | |
578 | "", | |
579 | "SMBUSMASTER 0", | |
580 | "SMBUSMASTER 1", | |
581 | "SMBUSMASTER 2", | |
582 | "SMBUSMASTER 3", | |
583 | "SMBUSMASTER 4", | |
584 | "SMBUSMASTER 5", | |
585 | "SMBUSMASTER 6", | |
586 | "SMBUSMASTER 7", | |
587 | "PECI Agent 0", | |
588 | "PECI Agent 1", | |
589 | "PCH_CHIP_CPU_MAX_TEMP", | |
590 | "PCH_CHIP_TEMP", | |
591 | "PCH_CPU_TEMP", | |
592 | "PCH_MCH_TEMP", | |
593 | "PCH_DIM0_TEMP", | |
594 | "PCH_DIM1_TEMP", | |
595 | "PCH_DIM2_TEMP", | |
596 | "PCH_DIM3_TEMP", | |
597 | "BYTE_TEMP", | |
598 | "PECI Agent 0 Calibration", | |
599 | "PECI Agent 1 Calibration", | |
600 | "", | |
601 | "", | |
602 | "Virtual_TEMP" | |
603 | }; | |
604 | ||
605 | static const char *const nct6793_temp_label[] = { | |
606 | "", | |
607 | "SYSTIN", | |
608 | "CPUTIN", | |
609 | "AUXTIN0", | |
610 | "AUXTIN1", | |
611 | "AUXTIN2", | |
612 | "AUXTIN3", | |
613 | "", | |
614 | "SMBUSMASTER 0", | |
615 | "SMBUSMASTER 1", | |
616 | "", | |
617 | "", | |
618 | "", | |
619 | "", | |
620 | "", | |
621 | "", | |
622 | "PECI Agent 0", | |
623 | "PECI Agent 1", | |
624 | "PCH_CHIP_CPU_MAX_TEMP", | |
625 | "PCH_CHIP_TEMP", | |
626 | "PCH_CPU_TEMP", | |
627 | "PCH_MCH_TEMP", | |
628 | "Agent0 Dimm0 ", | |
629 | "Agent0 Dimm1", | |
630 | "Agent1 Dimm0", | |
631 | "Agent1 Dimm1", | |
632 | "BYTE_TEMP0", | |
633 | "BYTE_TEMP1", | |
634 | "PECI Agent 0 Calibration", | |
635 | "PECI Agent 1 Calibration", | |
636 | "", | |
637 | "Virtual_TEMP" | |
638 | }; | |
639 | ||
6c009501 GR |
640 | /* NCT6102D/NCT6106D specific data */ |
641 | ||
642 | #define NCT6106_REG_VBAT 0x318 | |
643 | #define NCT6106_REG_DIODE 0x319 | |
644 | #define NCT6106_DIODE_MASK 0x01 | |
645 | ||
646 | static const u16 NCT6106_REG_IN_MAX[] = { | |
647 | 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 }; | |
648 | static const u16 NCT6106_REG_IN_MIN[] = { | |
649 | 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 }; | |
650 | static const u16 NCT6106_REG_IN[] = { | |
651 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 }; | |
652 | ||
653 | static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 }; | |
d1a284b7 | 654 | static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a }; |
6c009501 GR |
655 | static const u16 NCT6106_REG_TEMP_HYST[] = { |
656 | 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 }; | |
657 | static const u16 NCT6106_REG_TEMP_OVER[] = { | |
b7a61353 GR |
658 | 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 }; |
659 | static const u16 NCT6106_REG_TEMP_CRIT_L[] = { | |
660 | 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 }; | |
661 | static const u16 NCT6106_REG_TEMP_CRIT_H[] = { | |
662 | 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 }; | |
6c009501 GR |
663 | static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 }; |
664 | static const u16 NCT6106_REG_TEMP_CONFIG[] = { | |
665 | 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc }; | |
666 | ||
667 | static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 }; | |
668 | static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 }; | |
669 | static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6, 0, 0 }; | |
670 | static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4, 0, 0 }; | |
671 | ||
672 | static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 }; | |
673 | static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 }; | |
674 | static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 }; | |
675 | static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c }; | |
676 | static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 }; | |
677 | static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 }; | |
678 | static const u16 NCT6106_REG_TEMP_SOURCE[] = { | |
679 | 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 }; | |
680 | ||
681 | static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a }; | |
682 | static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = { | |
683 | 0x11b, 0x12b, 0x13b }; | |
684 | ||
685 | static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c }; | |
686 | #define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10 | |
687 | static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d }; | |
688 | ||
689 | static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 }; | |
690 | static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 }; | |
691 | static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 }; | |
692 | static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 }; | |
693 | static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 }; | |
694 | static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 }; | |
695 | ||
696 | static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 }; | |
697 | ||
698 | static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 }; | |
699 | static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 }; | |
700 | static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a }; | |
701 | static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c }; | |
702 | static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c }; | |
703 | static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d }; | |
704 | ||
705 | static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 }; | |
706 | static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 }; | |
707 | ||
708 | static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = { | |
709 | 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d }; | |
710 | ||
711 | static const s8 NCT6106_ALARM_BITS[] = { | |
712 | 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */ | |
713 | 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */ | |
714 | -1, /* unused */ | |
715 | 32, 33, 34, -1, -1, /* fan1..fan5 */ | |
716 | -1, -1, -1, /* unused */ | |
717 | 16, 17, 18, 19, 20, 21, /* temp1..temp6 */ | |
718 | 48, -1 /* intrusion0, intrusion1 */ | |
719 | }; | |
720 | ||
30846993 GR |
721 | static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = { |
722 | 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 }; | |
723 | ||
724 | static const s8 NCT6106_BEEP_BITS[] = { | |
725 | 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */ | |
726 | 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */ | |
727 | 32, /* global beep enable */ | |
728 | 24, 25, 26, 27, 28, /* fan1..fan5 */ | |
729 | -1, -1, -1, /* unused */ | |
730 | 16, 17, 18, 19, 20, 21, /* temp1..temp6 */ | |
731 | 34, -1 /* intrusion0, intrusion1 */ | |
732 | }; | |
733 | ||
6c009501 GR |
734 | static const u16 NCT6106_REG_TEMP_ALTERNATE[ARRAY_SIZE(nct6776_temp_label) - 1] |
735 | = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x51, 0x52, 0x54 }; | |
736 | ||
737 | static const u16 NCT6106_REG_TEMP_CRIT[ARRAY_SIZE(nct6776_temp_label) - 1] | |
738 | = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x204, 0x205 }; | |
739 | ||
77eb5b37 GR |
740 | static enum pwm_enable reg_to_pwm_enable(int pwm, int mode) |
741 | { | |
742 | if (mode == 0 && pwm == 255) | |
743 | return off; | |
744 | return mode + 1; | |
745 | } | |
746 | ||
747 | static int pwm_enable_to_reg(enum pwm_enable mode) | |
748 | { | |
749 | if (mode == off) | |
750 | return 0; | |
751 | return mode - 1; | |
752 | } | |
753 | ||
9de2e2e8 GR |
754 | /* |
755 | * Conversions | |
756 | */ | |
757 | ||
cdcaeceb GR |
758 | /* 1 is DC mode, output in ms */ |
759 | static unsigned int step_time_from_reg(u8 reg, u8 mode) | |
760 | { | |
761 | return mode ? 400 * reg : 100 * reg; | |
762 | } | |
763 | ||
764 | static u8 step_time_to_reg(unsigned int msec, u8 mode) | |
765 | { | |
766 | return clamp_val((mode ? (msec + 200) / 400 : | |
767 | (msec + 50) / 100), 1, 255); | |
768 | } | |
769 | ||
1c65dc36 GR |
770 | static unsigned int fan_from_reg8(u16 reg, unsigned int divreg) |
771 | { | |
772 | if (reg == 0 || reg == 255) | |
773 | return 0; | |
774 | return 1350000U / (reg << divreg); | |
775 | } | |
776 | ||
777 | static unsigned int fan_from_reg13(u16 reg, unsigned int divreg) | |
778 | { | |
779 | if ((reg & 0xff1f) == 0xff1f) | |
780 | return 0; | |
781 | ||
782 | reg = (reg & 0x1f) | ((reg & 0xff00) >> 3); | |
783 | ||
784 | if (reg == 0) | |
785 | return 0; | |
786 | ||
787 | return 1350000U / reg; | |
788 | } | |
789 | ||
790 | static unsigned int fan_from_reg16(u16 reg, unsigned int divreg) | |
791 | { | |
792 | if (reg == 0 || reg == 0xffff) | |
793 | return 0; | |
794 | ||
795 | /* | |
796 | * Even though the registers are 16 bit wide, the fan divisor | |
797 | * still applies. | |
798 | */ | |
799 | return 1350000U / (reg << divreg); | |
800 | } | |
801 | ||
cdcaeceb GR |
802 | static u16 fan_to_reg(u32 fan, unsigned int divreg) |
803 | { | |
804 | if (!fan) | |
805 | return 0; | |
806 | ||
807 | return (1350000U / fan) >> divreg; | |
808 | } | |
809 | ||
1c65dc36 GR |
810 | static inline unsigned int |
811 | div_from_reg(u8 reg) | |
812 | { | |
813 | return 1 << reg; | |
814 | } | |
815 | ||
9de2e2e8 GR |
816 | /* |
817 | * Some of the voltage inputs have internal scaling, the tables below | |
818 | * contain 8 (the ADC LSB in mV) * scaling factor * 100 | |
819 | */ | |
820 | static const u16 scale_in[15] = { | |
821 | 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800, | |
822 | 800, 800 | |
823 | }; | |
824 | ||
825 | static inline long in_from_reg(u8 reg, u8 nr) | |
826 | { | |
827 | return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100); | |
828 | } | |
829 | ||
830 | static inline u8 in_to_reg(u32 val, u8 nr) | |
831 | { | |
832 | return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255); | |
833 | } | |
834 | ||
835 | /* | |
836 | * Data structures and manipulation thereof | |
837 | */ | |
838 | ||
839 | struct nct6775_data { | |
840 | int addr; /* IO base of hw monitor block */ | |
df612d5f | 841 | int sioreg; /* SIO register address */ |
9de2e2e8 GR |
842 | enum kinds kind; |
843 | const char *name; | |
844 | ||
615fc8cb | 845 | const struct attribute_group *groups[6]; |
9de2e2e8 | 846 | |
b7a61353 GR |
847 | u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst, |
848 | * 3=temp_crit, 4=temp_lcrit | |
aa136e5d GR |
849 | */ |
850 | u8 temp_src[NUM_TEMP]; | |
851 | u16 reg_temp_config[NUM_TEMP]; | |
852 | const char * const *temp_label; | |
853 | int temp_label_num; | |
854 | ||
9de2e2e8 GR |
855 | u16 REG_CONFIG; |
856 | u16 REG_VBAT; | |
aa136e5d | 857 | u16 REG_DIODE; |
6c009501 | 858 | u8 DIODE_MASK; |
9de2e2e8 GR |
859 | |
860 | const s8 *ALARM_BITS; | |
30846993 | 861 | const s8 *BEEP_BITS; |
9de2e2e8 GR |
862 | |
863 | const u16 *REG_VIN; | |
864 | const u16 *REG_IN_MINMAX[2]; | |
865 | ||
cdcaeceb | 866 | const u16 *REG_TARGET; |
1c65dc36 | 867 | const u16 *REG_FAN; |
77eb5b37 | 868 | const u16 *REG_FAN_MODE; |
1c65dc36 | 869 | const u16 *REG_FAN_MIN; |
5c25d954 | 870 | const u16 *REG_FAN_PULSES; |
6c009501 | 871 | const u16 *FAN_PULSE_SHIFT; |
cdcaeceb GR |
872 | const u16 *REG_FAN_TIME[3]; |
873 | ||
874 | const u16 *REG_TOLERANCE_H; | |
aa136e5d | 875 | |
77eb5b37 GR |
876 | const u8 *REG_PWM_MODE; |
877 | const u8 *PWM_MODE_MASK; | |
878 | ||
bbd8decd GR |
879 | const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor, |
880 | * [3]=pwm_max, [4]=pwm_step, | |
881 | * [5]=weight_duty_step, [6]=weight_duty_base | |
cdcaeceb | 882 | */ |
77eb5b37 GR |
883 | const u16 *REG_PWM_READ; |
884 | ||
6c009501 GR |
885 | const u16 *REG_CRITICAL_PWM_ENABLE; |
886 | u8 CRITICAL_PWM_ENABLE_MASK; | |
887 | const u16 *REG_CRITICAL_PWM; | |
888 | ||
cdcaeceb GR |
889 | const u16 *REG_AUTO_TEMP; |
890 | const u16 *REG_AUTO_PWM; | |
891 | ||
892 | const u16 *REG_CRITICAL_TEMP; | |
893 | const u16 *REG_CRITICAL_TEMP_TOLERANCE; | |
894 | ||
1c65dc36 | 895 | const u16 *REG_TEMP_SOURCE; /* temp register sources */ |
cdcaeceb | 896 | const u16 *REG_TEMP_SEL; |
bbd8decd GR |
897 | const u16 *REG_WEIGHT_TEMP_SEL; |
898 | const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */ | |
899 | ||
aa136e5d GR |
900 | const u16 *REG_TEMP_OFFSET; |
901 | ||
9de2e2e8 | 902 | const u16 *REG_ALARM; |
30846993 | 903 | const u16 *REG_BEEP; |
9de2e2e8 | 904 | |
1c65dc36 GR |
905 | unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg); |
906 | unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg); | |
907 | ||
9de2e2e8 GR |
908 | struct mutex update_lock; |
909 | bool valid; /* true if following fields are valid */ | |
910 | unsigned long last_updated; /* In jiffies */ | |
911 | ||
912 | /* Register values */ | |
913 | u8 bank; /* current register bank */ | |
914 | u8 in_num; /* number of in inputs we have */ | |
915 | u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */ | |
578ab5f0 DB |
916 | unsigned int rpm[NUM_FAN]; |
917 | u16 fan_min[NUM_FAN]; | |
918 | u8 fan_pulses[NUM_FAN]; | |
919 | u8 fan_div[NUM_FAN]; | |
77eb5b37 | 920 | u8 has_pwm; |
1c65dc36 GR |
921 | u8 has_fan; /* some fan inputs can be disabled */ |
922 | u8 has_fan_min; /* some fans don't have min register */ | |
923 | bool has_fan_div; | |
9de2e2e8 | 924 | |
6c009501 | 925 | u8 num_temp_alarms; /* 2, 3, or 6 */ |
30846993 | 926 | u8 num_temp_beeps; /* 2, 3, or 6 */ |
aa136e5d GR |
927 | u8 temp_fixed_num; /* 3 or 6 */ |
928 | u8 temp_type[NUM_TEMP_FIXED]; | |
929 | s8 temp_offset[NUM_TEMP_FIXED]; | |
f58876ac DC |
930 | s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst, |
931 | * 3=temp_crit, 4=temp_lcrit */ | |
9de2e2e8 | 932 | u64 alarms; |
30846993 | 933 | u64 beeps; |
9de2e2e8 | 934 | |
77eb5b37 | 935 | u8 pwm_num; /* number of pwm */ |
578ab5f0 DB |
936 | u8 pwm_mode[NUM_FAN]; /* 1->DC variable voltage, |
937 | * 0->PWM variable duty cycle | |
938 | */ | |
939 | enum pwm_enable pwm_enable[NUM_FAN]; | |
77eb5b37 GR |
940 | /* 0->off |
941 | * 1->manual | |
942 | * 2->thermal cruise mode (also called SmartFan I) | |
943 | * 3->fan speed cruise mode | |
944 | * 4->SmartFan III | |
945 | * 5->enhanced variable thermal cruise (SmartFan IV) | |
946 | */ | |
578ab5f0 DB |
947 | u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor, |
948 | * [3]=pwm_max, [4]=pwm_step, | |
949 | * [5]=weight_duty_step, [6]=weight_duty_base | |
950 | */ | |
cdcaeceb | 951 | |
578ab5f0 | 952 | u8 target_temp[NUM_FAN]; |
cdcaeceb | 953 | u8 target_temp_mask; |
578ab5f0 DB |
954 | u32 target_speed[NUM_FAN]; |
955 | u32 target_speed_tolerance[NUM_FAN]; | |
cdcaeceb GR |
956 | u8 speed_tolerance_limit; |
957 | ||
578ab5f0 | 958 | u8 temp_tolerance[2][NUM_FAN]; |
cdcaeceb GR |
959 | u8 tolerance_mask; |
960 | ||
578ab5f0 | 961 | u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */ |
cdcaeceb GR |
962 | |
963 | /* Automatic fan speed control registers */ | |
964 | int auto_pwm_num; | |
578ab5f0 DB |
965 | u8 auto_pwm[NUM_FAN][7]; |
966 | u8 auto_temp[NUM_FAN][7]; | |
967 | u8 pwm_temp_sel[NUM_FAN]; | |
968 | u8 pwm_weight_temp_sel[NUM_FAN]; | |
969 | u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol, | |
970 | * 2->temp_base | |
971 | */ | |
77eb5b37 | 972 | |
9de2e2e8 GR |
973 | u8 vid; |
974 | u8 vrm; | |
975 | ||
f73cf632 GR |
976 | bool have_vid; |
977 | ||
aa136e5d GR |
978 | u16 have_temp; |
979 | u16 have_temp_fixed; | |
9de2e2e8 | 980 | u16 have_in; |
48e93182 | 981 | |
84d19d92 GR |
982 | /* Remember extra register values over suspend/resume */ |
983 | u8 vbat; | |
984 | u8 fandiv1; | |
985 | u8 fandiv2; | |
d2a14ea5 | 986 | u8 sio_reg_enable; |
9de2e2e8 GR |
987 | }; |
988 | ||
989 | struct nct6775_sio_data { | |
990 | int sioreg; | |
991 | enum kinds kind; | |
992 | }; | |
993 | ||
f73cf632 GR |
994 | struct sensor_device_template { |
995 | struct device_attribute dev_attr; | |
996 | union { | |
997 | struct { | |
998 | u8 nr; | |
999 | u8 index; | |
1000 | } s; | |
1001 | int index; | |
1002 | } u; | |
1003 | bool s2; /* true if both index and nr are used */ | |
1004 | }; | |
1005 | ||
1006 | struct sensor_device_attr_u { | |
1007 | union { | |
1008 | struct sensor_device_attribute a1; | |
1009 | struct sensor_device_attribute_2 a2; | |
1010 | } u; | |
1011 | char name[32]; | |
1012 | }; | |
1013 | ||
1014 | #define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \ | |
1015 | .attr = {.name = _template, .mode = _mode }, \ | |
1016 | .show = _show, \ | |
1017 | .store = _store, \ | |
1018 | } | |
1019 | ||
1020 | #define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \ | |
1021 | { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \ | |
1022 | .u.index = _index, \ | |
1023 | .s2 = false } | |
1024 | ||
1025 | #define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \ | |
1026 | _nr, _index) \ | |
1027 | { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \ | |
1028 | .u.s.index = _index, \ | |
1029 | .u.s.nr = _nr, \ | |
1030 | .s2 = true } | |
1031 | ||
1032 | #define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \ | |
1033 | static struct sensor_device_template sensor_dev_template_##_name \ | |
1034 | = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \ | |
1035 | _index) | |
1036 | ||
1037 | #define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \ | |
1038 | _nr, _index) \ | |
1039 | static struct sensor_device_template sensor_dev_template_##_name \ | |
1040 | = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \ | |
1041 | _nr, _index) | |
1042 | ||
1043 | struct sensor_template_group { | |
1044 | struct sensor_device_template **templates; | |
1045 | umode_t (*is_visible)(struct kobject *, struct attribute *, int); | |
1046 | int base; | |
1047 | }; | |
1048 | ||
1049 | static struct attribute_group * | |
c60fdf85 JL |
1050 | nct6775_create_attr_group(struct device *dev, |
1051 | const struct sensor_template_group *tg, | |
f73cf632 GR |
1052 | int repeat) |
1053 | { | |
1054 | struct attribute_group *group; | |
1055 | struct sensor_device_attr_u *su; | |
1056 | struct sensor_device_attribute *a; | |
1057 | struct sensor_device_attribute_2 *a2; | |
1058 | struct attribute **attrs; | |
1059 | struct sensor_device_template **t; | |
1e687e80 | 1060 | int i, count; |
f73cf632 GR |
1061 | |
1062 | if (repeat <= 0) | |
1063 | return ERR_PTR(-EINVAL); | |
1064 | ||
1065 | t = tg->templates; | |
1066 | for (count = 0; *t; t++, count++) | |
1067 | ; | |
1068 | ||
1069 | if (count == 0) | |
1070 | return ERR_PTR(-EINVAL); | |
1071 | ||
1072 | group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL); | |
1073 | if (group == NULL) | |
1074 | return ERR_PTR(-ENOMEM); | |
1075 | ||
1076 | attrs = devm_kzalloc(dev, sizeof(*attrs) * (repeat * count + 1), | |
1077 | GFP_KERNEL); | |
1078 | if (attrs == NULL) | |
1079 | return ERR_PTR(-ENOMEM); | |
1080 | ||
1081 | su = devm_kzalloc(dev, sizeof(*su) * repeat * count, | |
1082 | GFP_KERNEL); | |
1083 | if (su == NULL) | |
1084 | return ERR_PTR(-ENOMEM); | |
1085 | ||
1086 | group->attrs = attrs; | |
1087 | group->is_visible = tg->is_visible; | |
1088 | ||
1089 | for (i = 0; i < repeat; i++) { | |
1090 | t = tg->templates; | |
1e687e80 | 1091 | while (*t != NULL) { |
f73cf632 GR |
1092 | snprintf(su->name, sizeof(su->name), |
1093 | (*t)->dev_attr.attr.name, tg->base + i); | |
1094 | if ((*t)->s2) { | |
1095 | a2 = &su->u.a2; | |
1b63bf61 | 1096 | sysfs_attr_init(&a2->dev_attr.attr); |
f73cf632 GR |
1097 | a2->dev_attr.attr.name = su->name; |
1098 | a2->nr = (*t)->u.s.nr + i; | |
1099 | a2->index = (*t)->u.s.index; | |
1100 | a2->dev_attr.attr.mode = | |
1101 | (*t)->dev_attr.attr.mode; | |
1102 | a2->dev_attr.show = (*t)->dev_attr.show; | |
1103 | a2->dev_attr.store = (*t)->dev_attr.store; | |
1104 | *attrs = &a2->dev_attr.attr; | |
1105 | } else { | |
1106 | a = &su->u.a1; | |
1b63bf61 | 1107 | sysfs_attr_init(&a->dev_attr.attr); |
f73cf632 GR |
1108 | a->dev_attr.attr.name = su->name; |
1109 | a->index = (*t)->u.index + i; | |
1110 | a->dev_attr.attr.mode = | |
1111 | (*t)->dev_attr.attr.mode; | |
1112 | a->dev_attr.show = (*t)->dev_attr.show; | |
1113 | a->dev_attr.store = (*t)->dev_attr.store; | |
1114 | *attrs = &a->dev_attr.attr; | |
1115 | } | |
1116 | attrs++; | |
1117 | su++; | |
1118 | t++; | |
1119 | } | |
1120 | } | |
1121 | ||
f73cf632 GR |
1122 | return group; |
1123 | } | |
1124 | ||
9de2e2e8 GR |
1125 | static bool is_word_sized(struct nct6775_data *data, u16 reg) |
1126 | { | |
1127 | switch (data->kind) { | |
6c009501 GR |
1128 | case nct6106: |
1129 | return reg == 0x20 || reg == 0x22 || reg == 0x24 || | |
1130 | reg == 0xe0 || reg == 0xe2 || reg == 0xe4 || | |
1131 | reg == 0x111 || reg == 0x121 || reg == 0x131; | |
9de2e2e8 GR |
1132 | case nct6775: |
1133 | return (((reg & 0xff00) == 0x100 || | |
1134 | (reg & 0xff00) == 0x200) && | |
1135 | ((reg & 0x00ff) == 0x50 || | |
1136 | (reg & 0x00ff) == 0x53 || | |
1137 | (reg & 0x00ff) == 0x55)) || | |
1138 | (reg & 0xfff0) == 0x630 || | |
1139 | reg == 0x640 || reg == 0x642 || | |
1140 | reg == 0x662 || | |
1141 | ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) || | |
1142 | reg == 0x73 || reg == 0x75 || reg == 0x77; | |
1143 | case nct6776: | |
1144 | return (((reg & 0xff00) == 0x100 || | |
1145 | (reg & 0xff00) == 0x200) && | |
1146 | ((reg & 0x00ff) == 0x50 || | |
1147 | (reg & 0x00ff) == 0x53 || | |
1148 | (reg & 0x00ff) == 0x55)) || | |
1149 | (reg & 0xfff0) == 0x630 || | |
1150 | reg == 0x402 || | |
1151 | reg == 0x640 || reg == 0x642 || | |
1152 | ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) || | |
1153 | reg == 0x73 || reg == 0x75 || reg == 0x77; | |
1154 | case nct6779: | |
578ab5f0 | 1155 | case nct6791: |
8aefb93f | 1156 | case nct6792: |
cd1faefa | 1157 | case nct6793: |
9de2e2e8 | 1158 | return reg == 0x150 || reg == 0x153 || reg == 0x155 || |
578ab5f0 | 1159 | ((reg & 0xfff0) == 0x4b0 && (reg & 0x000f) < 0x0b) || |
9de2e2e8 GR |
1160 | reg == 0x402 || |
1161 | reg == 0x63a || reg == 0x63c || reg == 0x63e || | |
1162 | reg == 0x640 || reg == 0x642 || | |
1163 | reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 || | |
8aefb93f | 1164 | reg == 0x7b || reg == 0x7d; |
9de2e2e8 GR |
1165 | } |
1166 | return false; | |
1167 | } | |
1168 | ||
1169 | /* | |
1170 | * On older chips, only registers 0x50-0x5f are banked. | |
1171 | * On more recent chips, all registers are banked. | |
1172 | * Assume that is the case and set the bank number for each access. | |
1173 | * Cache the bank number so it only needs to be set if it changes. | |
1174 | */ | |
1175 | static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg) | |
1176 | { | |
1177 | u8 bank = reg >> 8; | |
9cd892bc | 1178 | |
9de2e2e8 GR |
1179 | if (data->bank != bank) { |
1180 | outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET); | |
1181 | outb_p(bank, data->addr + DATA_REG_OFFSET); | |
1182 | data->bank = bank; | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | static u16 nct6775_read_value(struct nct6775_data *data, u16 reg) | |
1187 | { | |
1188 | int res, word_sized = is_word_sized(data, reg); | |
1189 | ||
9de2e2e8 GR |
1190 | nct6775_set_bank(data, reg); |
1191 | outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); | |
1192 | res = inb_p(data->addr + DATA_REG_OFFSET); | |
1193 | if (word_sized) { | |
1194 | outb_p((reg & 0xff) + 1, | |
1195 | data->addr + ADDR_REG_OFFSET); | |
1196 | res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET); | |
1197 | } | |
9de2e2e8 GR |
1198 | return res; |
1199 | } | |
1200 | ||
1201 | static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value) | |
1202 | { | |
1203 | int word_sized = is_word_sized(data, reg); | |
1204 | ||
9de2e2e8 GR |
1205 | nct6775_set_bank(data, reg); |
1206 | outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); | |
1207 | if (word_sized) { | |
1208 | outb_p(value >> 8, data->addr + DATA_REG_OFFSET); | |
1209 | outb_p((reg & 0xff) + 1, | |
1210 | data->addr + ADDR_REG_OFFSET); | |
1211 | } | |
1212 | outb_p(value & 0xff, data->addr + DATA_REG_OFFSET); | |
9de2e2e8 GR |
1213 | return 0; |
1214 | } | |
1215 | ||
aa136e5d GR |
1216 | /* We left-align 8-bit temperature values to make the code simpler */ |
1217 | static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg) | |
1218 | { | |
1219 | u16 res; | |
1220 | ||
1221 | res = nct6775_read_value(data, reg); | |
1222 | if (!is_word_sized(data, reg)) | |
1223 | res <<= 8; | |
1224 | ||
1225 | return res; | |
1226 | } | |
1227 | ||
1228 | static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value) | |
1229 | { | |
1230 | if (!is_word_sized(data, reg)) | |
1231 | value >>= 8; | |
1232 | return nct6775_write_value(data, reg, value); | |
1233 | } | |
1234 | ||
1c65dc36 GR |
1235 | /* This function assumes that the caller holds data->update_lock */ |
1236 | static void nct6775_write_fan_div(struct nct6775_data *data, int nr) | |
1237 | { | |
1238 | u8 reg; | |
1239 | ||
1240 | switch (nr) { | |
1241 | case 0: | |
1242 | reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70) | |
1243 | | (data->fan_div[0] & 0x7); | |
1244 | nct6775_write_value(data, NCT6775_REG_FANDIV1, reg); | |
1245 | break; | |
1246 | case 1: | |
1247 | reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7) | |
1248 | | ((data->fan_div[1] << 4) & 0x70); | |
1249 | nct6775_write_value(data, NCT6775_REG_FANDIV1, reg); | |
1250 | break; | |
1251 | case 2: | |
1252 | reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70) | |
1253 | | (data->fan_div[2] & 0x7); | |
1254 | nct6775_write_value(data, NCT6775_REG_FANDIV2, reg); | |
1255 | break; | |
1256 | case 3: | |
1257 | reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7) | |
1258 | | ((data->fan_div[3] << 4) & 0x70); | |
1259 | nct6775_write_value(data, NCT6775_REG_FANDIV2, reg); | |
1260 | break; | |
1261 | } | |
1262 | } | |
1263 | ||
1264 | static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr) | |
1265 | { | |
1266 | if (data->kind == nct6775) | |
1267 | nct6775_write_fan_div(data, nr); | |
1268 | } | |
1269 | ||
1270 | static void nct6775_update_fan_div(struct nct6775_data *data) | |
1271 | { | |
1272 | u8 i; | |
1273 | ||
1274 | i = nct6775_read_value(data, NCT6775_REG_FANDIV1); | |
1275 | data->fan_div[0] = i & 0x7; | |
1276 | data->fan_div[1] = (i & 0x70) >> 4; | |
1277 | i = nct6775_read_value(data, NCT6775_REG_FANDIV2); | |
1278 | data->fan_div[2] = i & 0x7; | |
6445e660 | 1279 | if (data->has_fan & (1 << 3)) |
1c65dc36 GR |
1280 | data->fan_div[3] = (i & 0x70) >> 4; |
1281 | } | |
1282 | ||
1283 | static void nct6775_update_fan_div_common(struct nct6775_data *data) | |
1284 | { | |
1285 | if (data->kind == nct6775) | |
1286 | nct6775_update_fan_div(data); | |
1287 | } | |
1288 | ||
1289 | static void nct6775_init_fan_div(struct nct6775_data *data) | |
1290 | { | |
1291 | int i; | |
1292 | ||
1293 | nct6775_update_fan_div_common(data); | |
1294 | /* | |
1295 | * For all fans, start with highest divider value if the divider | |
1296 | * register is not initialized. This ensures that we get a | |
1297 | * reading from the fan count register, even if it is not optimal. | |
1298 | * We'll compute a better divider later on. | |
1299 | */ | |
c409fd43 | 1300 | for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) { |
1c65dc36 GR |
1301 | if (!(data->has_fan & (1 << i))) |
1302 | continue; | |
1303 | if (data->fan_div[i] == 0) { | |
1304 | data->fan_div[i] = 7; | |
1305 | nct6775_write_fan_div_common(data, i); | |
1306 | } | |
1307 | } | |
1308 | } | |
1309 | ||
1310 | static void nct6775_init_fan_common(struct device *dev, | |
1311 | struct nct6775_data *data) | |
1312 | { | |
1313 | int i; | |
1314 | u8 reg; | |
1315 | ||
1316 | if (data->has_fan_div) | |
1317 | nct6775_init_fan_div(data); | |
1318 | ||
1319 | /* | |
1320 | * If fan_min is not set (0), set it to 0xff to disable it. This | |
1321 | * prevents the unnecessary warning when fanX_min is reported as 0. | |
1322 | */ | |
c409fd43 | 1323 | for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) { |
1c65dc36 GR |
1324 | if (data->has_fan_min & (1 << i)) { |
1325 | reg = nct6775_read_value(data, data->REG_FAN_MIN[i]); | |
1326 | if (!reg) | |
1327 | nct6775_write_value(data, data->REG_FAN_MIN[i], | |
1328 | data->has_fan_div ? 0xff | |
1329 | : 0xff1f); | |
1330 | } | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | static void nct6775_select_fan_div(struct device *dev, | |
1335 | struct nct6775_data *data, int nr, u16 reg) | |
1336 | { | |
1337 | u8 fan_div = data->fan_div[nr]; | |
1338 | u16 fan_min; | |
1339 | ||
1340 | if (!data->has_fan_div) | |
1341 | return; | |
1342 | ||
1343 | /* | |
1344 | * If we failed to measure the fan speed, or the reported value is not | |
1345 | * in the optimal range, and the clock divider can be modified, | |
1346 | * let's try that for next time. | |
1347 | */ | |
1348 | if (reg == 0x00 && fan_div < 0x07) | |
1349 | fan_div++; | |
1350 | else if (reg != 0x00 && reg < 0x30 && fan_div > 0) | |
1351 | fan_div--; | |
1352 | ||
1353 | if (fan_div != data->fan_div[nr]) { | |
1354 | dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n", | |
1355 | nr + 1, div_from_reg(data->fan_div[nr]), | |
1356 | div_from_reg(fan_div)); | |
1357 | ||
1358 | /* Preserve min limit if possible */ | |
1359 | if (data->has_fan_min & (1 << nr)) { | |
1360 | fan_min = data->fan_min[nr]; | |
1361 | if (fan_div > data->fan_div[nr]) { | |
1362 | if (fan_min != 255 && fan_min > 1) | |
1363 | fan_min >>= 1; | |
1364 | } else { | |
1365 | if (fan_min != 255) { | |
1366 | fan_min <<= 1; | |
1367 | if (fan_min > 254) | |
1368 | fan_min = 254; | |
1369 | } | |
1370 | } | |
1371 | if (fan_min != data->fan_min[nr]) { | |
1372 | data->fan_min[nr] = fan_min; | |
1373 | nct6775_write_value(data, data->REG_FAN_MIN[nr], | |
1374 | fan_min); | |
1375 | } | |
1376 | } | |
1377 | data->fan_div[nr] = fan_div; | |
1378 | nct6775_write_fan_div_common(data, nr); | |
1379 | } | |
1380 | } | |
1381 | ||
77eb5b37 GR |
1382 | static void nct6775_update_pwm(struct device *dev) |
1383 | { | |
1384 | struct nct6775_data *data = dev_get_drvdata(dev); | |
1385 | int i, j; | |
cdcaeceb | 1386 | int fanmodecfg, reg; |
77eb5b37 GR |
1387 | bool duty_is_dc; |
1388 | ||
1389 | for (i = 0; i < data->pwm_num; i++) { | |
1390 | if (!(data->has_pwm & (1 << i))) | |
1391 | continue; | |
1392 | ||
1393 | duty_is_dc = data->REG_PWM_MODE[i] && | |
1394 | (nct6775_read_value(data, data->REG_PWM_MODE[i]) | |
1395 | & data->PWM_MODE_MASK[i]); | |
1396 | data->pwm_mode[i] = duty_is_dc; | |
1397 | ||
1398 | fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]); | |
1399 | for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) { | |
1400 | if (data->REG_PWM[j] && data->REG_PWM[j][i]) { | |
1401 | data->pwm[j][i] | |
1402 | = nct6775_read_value(data, | |
1403 | data->REG_PWM[j][i]); | |
1404 | } | |
1405 | } | |
1406 | ||
1407 | data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i], | |
1408 | (fanmodecfg >> 4) & 7); | |
cdcaeceb GR |
1409 | |
1410 | if (!data->temp_tolerance[0][i] || | |
1411 | data->pwm_enable[i] != speed_cruise) | |
1412 | data->temp_tolerance[0][i] = fanmodecfg & 0x0f; | |
1413 | if (!data->target_speed_tolerance[i] || | |
1414 | data->pwm_enable[i] == speed_cruise) { | |
1415 | u8 t = fanmodecfg & 0x0f; | |
9cd892bc | 1416 | |
cdcaeceb GR |
1417 | if (data->REG_TOLERANCE_H) { |
1418 | t |= (nct6775_read_value(data, | |
1419 | data->REG_TOLERANCE_H[i]) & 0x70) >> 1; | |
1420 | } | |
1421 | data->target_speed_tolerance[i] = t; | |
1422 | } | |
1423 | ||
1424 | data->temp_tolerance[1][i] = | |
1425 | nct6775_read_value(data, | |
1426 | data->REG_CRITICAL_TEMP_TOLERANCE[i]); | |
1427 | ||
1428 | reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]); | |
1429 | data->pwm_temp_sel[i] = reg & 0x1f; | |
1430 | /* If fan can stop, report floor as 0 */ | |
1431 | if (reg & 0x80) | |
1432 | data->pwm[2][i] = 0; | |
bbd8decd | 1433 | |
cc76dee1 GR |
1434 | if (!data->REG_WEIGHT_TEMP_SEL[i]) |
1435 | continue; | |
1436 | ||
bbd8decd GR |
1437 | reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]); |
1438 | data->pwm_weight_temp_sel[i] = reg & 0x1f; | |
1439 | /* If weight is disabled, report weight source as 0 */ | |
1440 | if (j == 1 && !(reg & 0x80)) | |
1441 | data->pwm_weight_temp_sel[i] = 0; | |
1442 | ||
1443 | /* Weight temp data */ | |
c409fd43 | 1444 | for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) { |
bbd8decd GR |
1445 | data->weight_temp[j][i] |
1446 | = nct6775_read_value(data, | |
1447 | data->REG_WEIGHT_TEMP[j][i]); | |
1448 | } | |
cdcaeceb GR |
1449 | } |
1450 | } | |
1451 | ||
1452 | static void nct6775_update_pwm_limits(struct device *dev) | |
1453 | { | |
1454 | struct nct6775_data *data = dev_get_drvdata(dev); | |
1455 | int i, j; | |
1456 | u8 reg; | |
1457 | u16 reg_t; | |
1458 | ||
1459 | for (i = 0; i < data->pwm_num; i++) { | |
1460 | if (!(data->has_pwm & (1 << i))) | |
1461 | continue; | |
1462 | ||
c409fd43 | 1463 | for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) { |
cdcaeceb GR |
1464 | data->fan_time[j][i] = |
1465 | nct6775_read_value(data, data->REG_FAN_TIME[j][i]); | |
1466 | } | |
1467 | ||
1468 | reg_t = nct6775_read_value(data, data->REG_TARGET[i]); | |
1469 | /* Update only in matching mode or if never updated */ | |
1470 | if (!data->target_temp[i] || | |
1471 | data->pwm_enable[i] == thermal_cruise) | |
1472 | data->target_temp[i] = reg_t & data->target_temp_mask; | |
1473 | if (!data->target_speed[i] || | |
1474 | data->pwm_enable[i] == speed_cruise) { | |
1475 | if (data->REG_TOLERANCE_H) { | |
1476 | reg_t |= (nct6775_read_value(data, | |
1477 | data->REG_TOLERANCE_H[i]) & 0x0f) << 8; | |
1478 | } | |
1479 | data->target_speed[i] = reg_t; | |
1480 | } | |
1481 | ||
1482 | for (j = 0; j < data->auto_pwm_num; j++) { | |
1483 | data->auto_pwm[i][j] = | |
1484 | nct6775_read_value(data, | |
1485 | NCT6775_AUTO_PWM(data, i, j)); | |
1486 | data->auto_temp[i][j] = | |
1487 | nct6775_read_value(data, | |
1488 | NCT6775_AUTO_TEMP(data, i, j)); | |
1489 | } | |
1490 | ||
1491 | /* critical auto_pwm temperature data */ | |
1492 | data->auto_temp[i][data->auto_pwm_num] = | |
1493 | nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]); | |
1494 | ||
1495 | switch (data->kind) { | |
1496 | case nct6775: | |
1497 | reg = nct6775_read_value(data, | |
1498 | NCT6775_REG_CRITICAL_ENAB[i]); | |
1499 | data->auto_pwm[i][data->auto_pwm_num] = | |
1500 | (reg & 0x02) ? 0xff : 0x00; | |
1501 | break; | |
1502 | case nct6776: | |
1503 | data->auto_pwm[i][data->auto_pwm_num] = 0xff; | |
1504 | break; | |
6c009501 | 1505 | case nct6106: |
cdcaeceb | 1506 | case nct6779: |
578ab5f0 | 1507 | case nct6791: |
8aefb93f | 1508 | case nct6792: |
cd1faefa | 1509 | case nct6793: |
cdcaeceb | 1510 | reg = nct6775_read_value(data, |
6c009501 GR |
1511 | data->REG_CRITICAL_PWM_ENABLE[i]); |
1512 | if (reg & data->CRITICAL_PWM_ENABLE_MASK) | |
1513 | reg = nct6775_read_value(data, | |
1514 | data->REG_CRITICAL_PWM[i]); | |
cdcaeceb | 1515 | else |
6c009501 GR |
1516 | reg = 0xff; |
1517 | data->auto_pwm[i][data->auto_pwm_num] = reg; | |
cdcaeceb GR |
1518 | break; |
1519 | } | |
77eb5b37 GR |
1520 | } |
1521 | } | |
1522 | ||
9de2e2e8 GR |
1523 | static struct nct6775_data *nct6775_update_device(struct device *dev) |
1524 | { | |
1525 | struct nct6775_data *data = dev_get_drvdata(dev); | |
aa136e5d | 1526 | int i, j; |
9de2e2e8 GR |
1527 | |
1528 | mutex_lock(&data->update_lock); | |
1529 | ||
6445e660 | 1530 | if (time_after(jiffies, data->last_updated + HZ + HZ / 2) |
9de2e2e8 | 1531 | || !data->valid) { |
1c65dc36 GR |
1532 | /* Fan clock dividers */ |
1533 | nct6775_update_fan_div_common(data); | |
1534 | ||
9de2e2e8 GR |
1535 | /* Measured voltages and limits */ |
1536 | for (i = 0; i < data->in_num; i++) { | |
1537 | if (!(data->have_in & (1 << i))) | |
1538 | continue; | |
1539 | ||
1540 | data->in[i][0] = nct6775_read_value(data, | |
1541 | data->REG_VIN[i]); | |
1542 | data->in[i][1] = nct6775_read_value(data, | |
1543 | data->REG_IN_MINMAX[0][i]); | |
1544 | data->in[i][2] = nct6775_read_value(data, | |
1545 | data->REG_IN_MINMAX[1][i]); | |
1546 | } | |
1547 | ||
1c65dc36 | 1548 | /* Measured fan speeds and limits */ |
c409fd43 | 1549 | for (i = 0; i < ARRAY_SIZE(data->rpm); i++) { |
1c65dc36 GR |
1550 | u16 reg; |
1551 | ||
1552 | if (!(data->has_fan & (1 << i))) | |
1553 | continue; | |
1554 | ||
1555 | reg = nct6775_read_value(data, data->REG_FAN[i]); | |
1556 | data->rpm[i] = data->fan_from_reg(reg, | |
1557 | data->fan_div[i]); | |
1558 | ||
1559 | if (data->has_fan_min & (1 << i)) | |
1560 | data->fan_min[i] = nct6775_read_value(data, | |
1561 | data->REG_FAN_MIN[i]); | |
5c25d954 | 1562 | data->fan_pulses[i] = |
6c009501 GR |
1563 | (nct6775_read_value(data, data->REG_FAN_PULSES[i]) |
1564 | >> data->FAN_PULSE_SHIFT[i]) & 0x03; | |
1c65dc36 GR |
1565 | |
1566 | nct6775_select_fan_div(dev, data, i, reg); | |
1567 | } | |
1568 | ||
77eb5b37 | 1569 | nct6775_update_pwm(dev); |
cdcaeceb | 1570 | nct6775_update_pwm_limits(dev); |
77eb5b37 | 1571 | |
aa136e5d GR |
1572 | /* Measured temperatures and limits */ |
1573 | for (i = 0; i < NUM_TEMP; i++) { | |
1574 | if (!(data->have_temp & (1 << i))) | |
1575 | continue; | |
c409fd43 | 1576 | for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) { |
aa136e5d GR |
1577 | if (data->reg_temp[j][i]) |
1578 | data->temp[j][i] | |
1579 | = nct6775_read_temp(data, | |
1580 | data->reg_temp[j][i]); | |
1581 | } | |
45a5b3a1 GR |
1582 | if (i >= NUM_TEMP_FIXED || |
1583 | !(data->have_temp_fixed & (1 << i))) | |
aa136e5d GR |
1584 | continue; |
1585 | data->temp_offset[i] | |
1586 | = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]); | |
1587 | } | |
1588 | ||
9de2e2e8 GR |
1589 | data->alarms = 0; |
1590 | for (i = 0; i < NUM_REG_ALARM; i++) { | |
1591 | u8 alarm; | |
9cd892bc | 1592 | |
9de2e2e8 GR |
1593 | if (!data->REG_ALARM[i]) |
1594 | continue; | |
1595 | alarm = nct6775_read_value(data, data->REG_ALARM[i]); | |
1596 | data->alarms |= ((u64)alarm) << (i << 3); | |
1597 | } | |
1598 | ||
30846993 GR |
1599 | data->beeps = 0; |
1600 | for (i = 0; i < NUM_REG_BEEP; i++) { | |
1601 | u8 beep; | |
9cd892bc | 1602 | |
30846993 GR |
1603 | if (!data->REG_BEEP[i]) |
1604 | continue; | |
1605 | beep = nct6775_read_value(data, data->REG_BEEP[i]); | |
1606 | data->beeps |= ((u64)beep) << (i << 3); | |
1607 | } | |
1608 | ||
9de2e2e8 GR |
1609 | data->last_updated = jiffies; |
1610 | data->valid = true; | |
1611 | } | |
1612 | ||
1613 | mutex_unlock(&data->update_lock); | |
1614 | return data; | |
1615 | } | |
1616 | ||
1617 | /* | |
1618 | * Sysfs callback functions | |
1619 | */ | |
1620 | static ssize_t | |
1621 | show_in_reg(struct device *dev, struct device_attribute *attr, char *buf) | |
1622 | { | |
1623 | struct nct6775_data *data = nct6775_update_device(dev); | |
1624 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
9de2e2e8 | 1625 | int index = sattr->index; |
9cd892bc GR |
1626 | int nr = sattr->nr; |
1627 | ||
9de2e2e8 GR |
1628 | return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr)); |
1629 | } | |
1630 | ||
1631 | static ssize_t | |
1632 | store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf, | |
1633 | size_t count) | |
1634 | { | |
1635 | struct nct6775_data *data = dev_get_drvdata(dev); | |
1636 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
9de2e2e8 | 1637 | int index = sattr->index; |
9cd892bc | 1638 | int nr = sattr->nr; |
9de2e2e8 | 1639 | unsigned long val; |
9cd892bc GR |
1640 | int err; |
1641 | ||
1642 | err = kstrtoul(buf, 10, &val); | |
9de2e2e8 GR |
1643 | if (err < 0) |
1644 | return err; | |
1645 | mutex_lock(&data->update_lock); | |
1646 | data->in[nr][index] = in_to_reg(val, nr); | |
6445e660 | 1647 | nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr], |
9de2e2e8 GR |
1648 | data->in[nr][index]); |
1649 | mutex_unlock(&data->update_lock); | |
1650 | return count; | |
1651 | } | |
1652 | ||
1653 | static ssize_t | |
1654 | show_alarm(struct device *dev, struct device_attribute *attr, char *buf) | |
1655 | { | |
1656 | struct nct6775_data *data = nct6775_update_device(dev); | |
1657 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1658 | int nr = data->ALARM_BITS[sattr->index]; | |
9cd892bc | 1659 | |
9de2e2e8 GR |
1660 | return sprintf(buf, "%u\n", |
1661 | (unsigned int)((data->alarms >> nr) & 0x01)); | |
1662 | } | |
1663 | ||
b1d2bff6 GR |
1664 | static int find_temp_source(struct nct6775_data *data, int index, int count) |
1665 | { | |
1666 | int source = data->temp_src[index]; | |
1667 | int nr; | |
1668 | ||
1669 | for (nr = 0; nr < count; nr++) { | |
1670 | int src; | |
1671 | ||
1672 | src = nct6775_read_value(data, | |
1673 | data->REG_TEMP_SOURCE[nr]) & 0x1f; | |
1674 | if (src == source) | |
1675 | return nr; | |
1676 | } | |
e8ab508c | 1677 | return -ENODEV; |
b1d2bff6 GR |
1678 | } |
1679 | ||
1680 | static ssize_t | |
1681 | show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf) | |
1682 | { | |
1683 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1684 | struct nct6775_data *data = nct6775_update_device(dev); | |
1685 | unsigned int alarm = 0; | |
1686 | int nr; | |
1687 | ||
1688 | /* | |
1689 | * For temperatures, there is no fixed mapping from registers to alarm | |
1690 | * bits. Alarm bits are determined by the temperature source mapping. | |
1691 | */ | |
1692 | nr = find_temp_source(data, sattr->index, data->num_temp_alarms); | |
1693 | if (nr >= 0) { | |
1694 | int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE]; | |
9cd892bc | 1695 | |
b1d2bff6 GR |
1696 | alarm = (data->alarms >> bit) & 0x01; |
1697 | } | |
1698 | return sprintf(buf, "%u\n", alarm); | |
1699 | } | |
1700 | ||
30846993 GR |
1701 | static ssize_t |
1702 | show_beep(struct device *dev, struct device_attribute *attr, char *buf) | |
1703 | { | |
1704 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1705 | struct nct6775_data *data = nct6775_update_device(dev); | |
1706 | int nr = data->BEEP_BITS[sattr->index]; | |
1707 | ||
1708 | return sprintf(buf, "%u\n", | |
1709 | (unsigned int)((data->beeps >> nr) & 0x01)); | |
1710 | } | |
1711 | ||
1712 | static ssize_t | |
1713 | store_beep(struct device *dev, struct device_attribute *attr, const char *buf, | |
1714 | size_t count) | |
1715 | { | |
1716 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
1717 | struct nct6775_data *data = dev_get_drvdata(dev); | |
1718 | int nr = data->BEEP_BITS[sattr->index]; | |
1719 | int regindex = nr >> 3; | |
1720 | unsigned long val; | |
9cd892bc | 1721 | int err; |
30846993 | 1722 | |
9cd892bc | 1723 | err = kstrtoul(buf, 10, &val); |
30846993 GR |
1724 | if (err < 0) |
1725 | return err; | |
1726 | if (val > 1) | |
1727 | return -EINVAL; | |
1728 | ||
1729 | mutex_lock(&data->update_lock); | |
1730 | if (val) | |
1731 | data->beeps |= (1ULL << nr); | |
1732 | else | |
1733 | data->beeps &= ~(1ULL << nr); | |
1734 | nct6775_write_value(data, data->REG_BEEP[regindex], | |
1735 | (data->beeps >> (regindex << 3)) & 0xff); | |
1736 | mutex_unlock(&data->update_lock); | |
1737 | return count; | |
1738 | } | |
1739 | ||
1740 | static ssize_t | |
1741 | show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf) | |
1742 | { | |
1743 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1744 | struct nct6775_data *data = nct6775_update_device(dev); | |
1745 | unsigned int beep = 0; | |
1746 | int nr; | |
1747 | ||
1748 | /* | |
1749 | * For temperatures, there is no fixed mapping from registers to beep | |
1750 | * enable bits. Beep enable bits are determined by the temperature | |
1751 | * source mapping. | |
1752 | */ | |
1753 | nr = find_temp_source(data, sattr->index, data->num_temp_beeps); | |
1754 | if (nr >= 0) { | |
1755 | int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE]; | |
9cd892bc | 1756 | |
30846993 GR |
1757 | beep = (data->beeps >> bit) & 0x01; |
1758 | } | |
1759 | return sprintf(buf, "%u\n", beep); | |
1760 | } | |
1761 | ||
1762 | static ssize_t | |
1763 | store_temp_beep(struct device *dev, struct device_attribute *attr, | |
1764 | const char *buf, size_t count) | |
1765 | { | |
1766 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
1767 | struct nct6775_data *data = dev_get_drvdata(dev); | |
1768 | int nr, bit, regindex; | |
1769 | unsigned long val; | |
9cd892bc | 1770 | int err; |
30846993 | 1771 | |
9cd892bc | 1772 | err = kstrtoul(buf, 10, &val); |
30846993 GR |
1773 | if (err < 0) |
1774 | return err; | |
1775 | if (val > 1) | |
1776 | return -EINVAL; | |
1777 | ||
1778 | nr = find_temp_source(data, sattr->index, data->num_temp_beeps); | |
1779 | if (nr < 0) | |
e8ab508c | 1780 | return nr; |
30846993 GR |
1781 | |
1782 | bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE]; | |
1783 | regindex = bit >> 3; | |
1784 | ||
1785 | mutex_lock(&data->update_lock); | |
1786 | if (val) | |
1787 | data->beeps |= (1ULL << bit); | |
1788 | else | |
1789 | data->beeps &= ~(1ULL << bit); | |
1790 | nct6775_write_value(data, data->REG_BEEP[regindex], | |
1791 | (data->beeps >> (regindex << 3)) & 0xff); | |
1792 | mutex_unlock(&data->update_lock); | |
1793 | ||
1794 | return count; | |
1795 | } | |
1796 | ||
f73cf632 GR |
1797 | static umode_t nct6775_in_is_visible(struct kobject *kobj, |
1798 | struct attribute *attr, int index) | |
1799 | { | |
1800 | struct device *dev = container_of(kobj, struct device, kobj); | |
1801 | struct nct6775_data *data = dev_get_drvdata(dev); | |
30846993 | 1802 | int in = index / 5; /* voltage index */ |
f73cf632 GR |
1803 | |
1804 | if (!(data->have_in & (1 << in))) | |
1805 | return 0; | |
1806 | ||
1807 | return attr->mode; | |
1808 | } | |
1809 | ||
1810 | SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0); | |
1811 | SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0); | |
30846993 GR |
1812 | SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep, |
1813 | 0); | |
f73cf632 GR |
1814 | SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg, |
1815 | store_in_reg, 0, 1); | |
1816 | SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg, | |
1817 | store_in_reg, 0, 2); | |
1818 | ||
1819 | /* | |
1820 | * nct6775_in_is_visible uses the index into the following array | |
1821 | * to determine if attributes should be created or not. | |
1822 | * Any change in order or content must be matched. | |
1823 | */ | |
1824 | static struct sensor_device_template *nct6775_attributes_in_template[] = { | |
1825 | &sensor_dev_template_in_input, | |
1826 | &sensor_dev_template_in_alarm, | |
30846993 | 1827 | &sensor_dev_template_in_beep, |
f73cf632 GR |
1828 | &sensor_dev_template_in_min, |
1829 | &sensor_dev_template_in_max, | |
1830 | NULL | |
9de2e2e8 GR |
1831 | }; |
1832 | ||
c60fdf85 | 1833 | static const struct sensor_template_group nct6775_in_template_group = { |
f73cf632 GR |
1834 | .templates = nct6775_attributes_in_template, |
1835 | .is_visible = nct6775_in_is_visible, | |
9de2e2e8 GR |
1836 | }; |
1837 | ||
1c65dc36 GR |
1838 | static ssize_t |
1839 | show_fan(struct device *dev, struct device_attribute *attr, char *buf) | |
1840 | { | |
1841 | struct nct6775_data *data = nct6775_update_device(dev); | |
1842 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1843 | int nr = sattr->index; | |
9cd892bc | 1844 | |
1c65dc36 GR |
1845 | return sprintf(buf, "%d\n", data->rpm[nr]); |
1846 | } | |
1847 | ||
1848 | static ssize_t | |
1849 | show_fan_min(struct device *dev, struct device_attribute *attr, char *buf) | |
1850 | { | |
1851 | struct nct6775_data *data = nct6775_update_device(dev); | |
1852 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1853 | int nr = sattr->index; | |
9cd892bc | 1854 | |
1c65dc36 GR |
1855 | return sprintf(buf, "%d\n", |
1856 | data->fan_from_reg_min(data->fan_min[nr], | |
1857 | data->fan_div[nr])); | |
1858 | } | |
1859 | ||
1860 | static ssize_t | |
1861 | show_fan_div(struct device *dev, struct device_attribute *attr, char *buf) | |
1862 | { | |
1863 | struct nct6775_data *data = nct6775_update_device(dev); | |
1864 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1865 | int nr = sattr->index; | |
9cd892bc | 1866 | |
1c65dc36 GR |
1867 | return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr])); |
1868 | } | |
1869 | ||
1870 | static ssize_t | |
1871 | store_fan_min(struct device *dev, struct device_attribute *attr, | |
1872 | const char *buf, size_t count) | |
1873 | { | |
1874 | struct nct6775_data *data = dev_get_drvdata(dev); | |
1875 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1876 | int nr = sattr->index; | |
1877 | unsigned long val; | |
1c65dc36 GR |
1878 | unsigned int reg; |
1879 | u8 new_div; | |
9cd892bc | 1880 | int err; |
1c65dc36 GR |
1881 | |
1882 | err = kstrtoul(buf, 10, &val); | |
1883 | if (err < 0) | |
1884 | return err; | |
1885 | ||
1886 | mutex_lock(&data->update_lock); | |
1887 | if (!data->has_fan_div) { | |
1888 | /* NCT6776F or NCT6779D; we know this is a 13 bit register */ | |
1889 | if (!val) { | |
1890 | val = 0xff1f; | |
1891 | } else { | |
1892 | if (val > 1350000U) | |
1893 | val = 135000U; | |
1894 | val = 1350000U / val; | |
1895 | val = (val & 0x1f) | ((val << 3) & 0xff00); | |
1896 | } | |
1897 | data->fan_min[nr] = val; | |
1898 | goto write_min; /* Leave fan divider alone */ | |
1899 | } | |
1900 | if (!val) { | |
1901 | /* No min limit, alarm disabled */ | |
1902 | data->fan_min[nr] = 255; | |
1903 | new_div = data->fan_div[nr]; /* No change */ | |
1904 | dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1); | |
1905 | goto write_div; | |
1906 | } | |
1907 | reg = 1350000U / val; | |
1908 | if (reg >= 128 * 255) { | |
1909 | /* | |
1910 | * Speed below this value cannot possibly be represented, | |
1911 | * even with the highest divider (128) | |
1912 | */ | |
1913 | data->fan_min[nr] = 254; | |
1914 | new_div = 7; /* 128 == (1 << 7) */ | |
1915 | dev_warn(dev, | |
1916 | "fan%u low limit %lu below minimum %u, set to minimum\n", | |
1917 | nr + 1, val, data->fan_from_reg_min(254, 7)); | |
1918 | } else if (!reg) { | |
1919 | /* | |
1920 | * Speed above this value cannot possibly be represented, | |
1921 | * even with the lowest divider (1) | |
1922 | */ | |
1923 | data->fan_min[nr] = 1; | |
1924 | new_div = 0; /* 1 == (1 << 0) */ | |
1925 | dev_warn(dev, | |
1926 | "fan%u low limit %lu above maximum %u, set to maximum\n", | |
1927 | nr + 1, val, data->fan_from_reg_min(1, 0)); | |
1928 | } else { | |
1929 | /* | |
1930 | * Automatically pick the best divider, i.e. the one such | |
1931 | * that the min limit will correspond to a register value | |
1932 | * in the 96..192 range | |
1933 | */ | |
1934 | new_div = 0; | |
1935 | while (reg > 192 && new_div < 7) { | |
1936 | reg >>= 1; | |
1937 | new_div++; | |
1938 | } | |
1939 | data->fan_min[nr] = reg; | |
1940 | } | |
1941 | ||
1942 | write_div: | |
1943 | /* | |
1944 | * Write both the fan clock divider (if it changed) and the new | |
1945 | * fan min (unconditionally) | |
1946 | */ | |
1947 | if (new_div != data->fan_div[nr]) { | |
1948 | dev_dbg(dev, "fan%u clock divider changed from %u to %u\n", | |
1949 | nr + 1, div_from_reg(data->fan_div[nr]), | |
1950 | div_from_reg(new_div)); | |
1951 | data->fan_div[nr] = new_div; | |
1952 | nct6775_write_fan_div_common(data, nr); | |
1953 | /* Give the chip time to sample a new speed value */ | |
1954 | data->last_updated = jiffies; | |
1955 | } | |
1956 | ||
1957 | write_min: | |
1958 | nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]); | |
1959 | mutex_unlock(&data->update_lock); | |
1960 | ||
1961 | return count; | |
1962 | } | |
1963 | ||
5c25d954 GR |
1964 | static ssize_t |
1965 | show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf) | |
1966 | { | |
1967 | struct nct6775_data *data = nct6775_update_device(dev); | |
1968 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1969 | int p = data->fan_pulses[sattr->index]; | |
1970 | ||
1971 | return sprintf(buf, "%d\n", p ? : 4); | |
1972 | } | |
1973 | ||
1974 | static ssize_t | |
1975 | store_fan_pulses(struct device *dev, struct device_attribute *attr, | |
1976 | const char *buf, size_t count) | |
1977 | { | |
1978 | struct nct6775_data *data = dev_get_drvdata(dev); | |
1979 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
1980 | int nr = sattr->index; | |
1981 | unsigned long val; | |
1982 | int err; | |
6c009501 | 1983 | u8 reg; |
5c25d954 GR |
1984 | |
1985 | err = kstrtoul(buf, 10, &val); | |
1986 | if (err < 0) | |
1987 | return err; | |
1988 | ||
1989 | if (val > 4) | |
1990 | return -EINVAL; | |
1991 | ||
1992 | mutex_lock(&data->update_lock); | |
1993 | data->fan_pulses[nr] = val & 3; | |
6c009501 GR |
1994 | reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]); |
1995 | reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]); | |
1996 | reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr]; | |
1997 | nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg); | |
5c25d954 GR |
1998 | mutex_unlock(&data->update_lock); |
1999 | ||
2000 | return count; | |
2001 | } | |
2002 | ||
f73cf632 GR |
2003 | static umode_t nct6775_fan_is_visible(struct kobject *kobj, |
2004 | struct attribute *attr, int index) | |
2005 | { | |
2006 | struct device *dev = container_of(kobj, struct device, kobj); | |
2007 | struct nct6775_data *data = dev_get_drvdata(dev); | |
30846993 GR |
2008 | int fan = index / 6; /* fan index */ |
2009 | int nr = index % 6; /* attribute index */ | |
1c65dc36 | 2010 | |
f73cf632 GR |
2011 | if (!(data->has_fan & (1 << fan))) |
2012 | return 0; | |
1c65dc36 | 2013 | |
f73cf632 GR |
2014 | if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1) |
2015 | return 0; | |
30846993 | 2016 | if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1) |
f73cf632 | 2017 | return 0; |
30846993 GR |
2018 | if (nr == 4 && !(data->has_fan_min & (1 << fan))) |
2019 | return 0; | |
2020 | if (nr == 5 && data->kind != nct6775) | |
f73cf632 GR |
2021 | return 0; |
2022 | ||
2023 | return attr->mode; | |
2024 | } | |
1c65dc36 | 2025 | |
f73cf632 GR |
2026 | SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0); |
2027 | SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL, | |
2028 | FAN_ALARM_BASE); | |
30846993 GR |
2029 | SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep, |
2030 | store_beep, FAN_ALARM_BASE); | |
f73cf632 GR |
2031 | SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses, |
2032 | store_fan_pulses, 0); | |
2033 | SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min, | |
2034 | store_fan_min, 0); | |
2035 | SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0); | |
2036 | ||
2037 | /* | |
2038 | * nct6775_fan_is_visible uses the index into the following array | |
2039 | * to determine if attributes should be created or not. | |
2040 | * Any change in order or content must be matched. | |
2041 | */ | |
2042 | static struct sensor_device_template *nct6775_attributes_fan_template[] = { | |
2043 | &sensor_dev_template_fan_input, | |
2044 | &sensor_dev_template_fan_alarm, /* 1 */ | |
30846993 | 2045 | &sensor_dev_template_fan_beep, /* 2 */ |
f73cf632 | 2046 | &sensor_dev_template_fan_pulses, |
30846993 GR |
2047 | &sensor_dev_template_fan_min, /* 4 */ |
2048 | &sensor_dev_template_fan_div, /* 5 */ | |
f73cf632 | 2049 | NULL |
5c25d954 GR |
2050 | }; |
2051 | ||
c60fdf85 | 2052 | static const struct sensor_template_group nct6775_fan_template_group = { |
f73cf632 GR |
2053 | .templates = nct6775_attributes_fan_template, |
2054 | .is_visible = nct6775_fan_is_visible, | |
2055 | .base = 1, | |
1c65dc36 GR |
2056 | }; |
2057 | ||
aa136e5d GR |
2058 | static ssize_t |
2059 | show_temp_label(struct device *dev, struct device_attribute *attr, char *buf) | |
2060 | { | |
2061 | struct nct6775_data *data = nct6775_update_device(dev); | |
2062 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2063 | int nr = sattr->index; | |
9cd892bc | 2064 | |
aa136e5d GR |
2065 | return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]); |
2066 | } | |
2067 | ||
2068 | static ssize_t | |
2069 | show_temp(struct device *dev, struct device_attribute *attr, char *buf) | |
2070 | { | |
2071 | struct nct6775_data *data = nct6775_update_device(dev); | |
2072 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2073 | int nr = sattr->nr; | |
2074 | int index = sattr->index; | |
2075 | ||
2076 | return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr])); | |
2077 | } | |
2078 | ||
2079 | static ssize_t | |
2080 | store_temp(struct device *dev, struct device_attribute *attr, const char *buf, | |
2081 | size_t count) | |
2082 | { | |
2083 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2084 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2085 | int nr = sattr->nr; | |
2086 | int index = sattr->index; | |
2087 | int err; | |
2088 | long val; | |
2089 | ||
2090 | err = kstrtol(buf, 10, &val); | |
2091 | if (err < 0) | |
2092 | return err; | |
2093 | ||
2094 | mutex_lock(&data->update_lock); | |
2095 | data->temp[index][nr] = LM75_TEMP_TO_REG(val); | |
2096 | nct6775_write_temp(data, data->reg_temp[index][nr], | |
2097 | data->temp[index][nr]); | |
2098 | mutex_unlock(&data->update_lock); | |
2099 | return count; | |
2100 | } | |
2101 | ||
2102 | static ssize_t | |
2103 | show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf) | |
2104 | { | |
2105 | struct nct6775_data *data = nct6775_update_device(dev); | |
2106 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2107 | ||
2108 | return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000); | |
2109 | } | |
2110 | ||
2111 | static ssize_t | |
2112 | store_temp_offset(struct device *dev, struct device_attribute *attr, | |
2113 | const char *buf, size_t count) | |
2114 | { | |
2115 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2116 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2117 | int nr = sattr->index; | |
2118 | long val; | |
2119 | int err; | |
2120 | ||
2121 | err = kstrtol(buf, 10, &val); | |
2122 | if (err < 0) | |
2123 | return err; | |
2124 | ||
2125 | val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127); | |
2126 | ||
2127 | mutex_lock(&data->update_lock); | |
2128 | data->temp_offset[nr] = val; | |
2129 | nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val); | |
2130 | mutex_unlock(&data->update_lock); | |
2131 | ||
2132 | return count; | |
2133 | } | |
2134 | ||
2135 | static ssize_t | |
2136 | show_temp_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2137 | { | |
2138 | struct nct6775_data *data = nct6775_update_device(dev); | |
2139 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2140 | int nr = sattr->index; | |
9cd892bc | 2141 | |
aa136e5d GR |
2142 | return sprintf(buf, "%d\n", (int)data->temp_type[nr]); |
2143 | } | |
2144 | ||
2145 | static ssize_t | |
2146 | store_temp_type(struct device *dev, struct device_attribute *attr, | |
2147 | const char *buf, size_t count) | |
2148 | { | |
2149 | struct nct6775_data *data = nct6775_update_device(dev); | |
2150 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2151 | int nr = sattr->index; | |
2152 | unsigned long val; | |
2153 | int err; | |
6c009501 | 2154 | u8 vbat, diode, vbit, dbit; |
aa136e5d GR |
2155 | |
2156 | err = kstrtoul(buf, 10, &val); | |
2157 | if (err < 0) | |
2158 | return err; | |
2159 | ||
2160 | if (val != 1 && val != 3 && val != 4) | |
2161 | return -EINVAL; | |
2162 | ||
2163 | mutex_lock(&data->update_lock); | |
2164 | ||
2165 | data->temp_type[nr] = val; | |
6c009501 GR |
2166 | vbit = 0x02 << nr; |
2167 | dbit = data->DIODE_MASK << nr; | |
2168 | vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit; | |
2169 | diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit; | |
aa136e5d GR |
2170 | switch (val) { |
2171 | case 1: /* CPU diode (diode, current mode) */ | |
6c009501 GR |
2172 | vbat |= vbit; |
2173 | diode |= dbit; | |
aa136e5d GR |
2174 | break; |
2175 | case 3: /* diode, voltage mode */ | |
6c009501 | 2176 | vbat |= dbit; |
aa136e5d GR |
2177 | break; |
2178 | case 4: /* thermistor */ | |
2179 | break; | |
2180 | } | |
2181 | nct6775_write_value(data, data->REG_VBAT, vbat); | |
2182 | nct6775_write_value(data, data->REG_DIODE, diode); | |
2183 | ||
2184 | mutex_unlock(&data->update_lock); | |
2185 | return count; | |
2186 | } | |
2187 | ||
f73cf632 GR |
2188 | static umode_t nct6775_temp_is_visible(struct kobject *kobj, |
2189 | struct attribute *attr, int index) | |
2190 | { | |
2191 | struct device *dev = container_of(kobj, struct device, kobj); | |
2192 | struct nct6775_data *data = dev_get_drvdata(dev); | |
30846993 GR |
2193 | int temp = index / 10; /* temp index */ |
2194 | int nr = index % 10; /* attribute index */ | |
aa136e5d | 2195 | |
f73cf632 GR |
2196 | if (!(data->have_temp & (1 << temp))) |
2197 | return 0; | |
aa136e5d | 2198 | |
f73cf632 GR |
2199 | if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0) |
2200 | return 0; /* alarm */ | |
aa136e5d | 2201 | |
30846993 GR |
2202 | if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0) |
2203 | return 0; /* beep */ | |
2204 | ||
2205 | if (nr == 4 && !data->reg_temp[1][temp]) /* max */ | |
f73cf632 | 2206 | return 0; |
aa136e5d | 2207 | |
30846993 | 2208 | if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */ |
f73cf632 | 2209 | return 0; |
aa136e5d | 2210 | |
30846993 | 2211 | if (nr == 6 && !data->reg_temp[3][temp]) /* crit */ |
f73cf632 GR |
2212 | return 0; |
2213 | ||
30846993 | 2214 | if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */ |
b7a61353 GR |
2215 | return 0; |
2216 | ||
2217 | /* offset and type only apply to fixed sensors */ | |
30846993 | 2218 | if (nr > 7 && !(data->have_temp_fixed & (1 << temp))) |
f73cf632 | 2219 | return 0; |
aa136e5d | 2220 | |
f73cf632 GR |
2221 | return attr->mode; |
2222 | } | |
2223 | ||
2224 | SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0); | |
2225 | SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0); | |
2226 | SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp, | |
2227 | store_temp, 0, 1); | |
2228 | SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR, | |
2229 | show_temp, store_temp, 0, 2); | |
2230 | SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp, | |
2231 | store_temp, 0, 3); | |
b7a61353 GR |
2232 | SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp, |
2233 | store_temp, 0, 4); | |
f73cf632 GR |
2234 | SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR, |
2235 | show_temp_offset, store_temp_offset, 0); | |
2236 | SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type, | |
2237 | store_temp_type, 0); | |
2238 | SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0); | |
30846993 GR |
2239 | SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep, |
2240 | store_temp_beep, 0); | |
f73cf632 GR |
2241 | |
2242 | /* | |
2243 | * nct6775_temp_is_visible uses the index into the following array | |
2244 | * to determine if attributes should be created or not. | |
2245 | * Any change in order or content must be matched. | |
2246 | */ | |
2247 | static struct sensor_device_template *nct6775_attributes_temp_template[] = { | |
2248 | &sensor_dev_template_temp_input, | |
2249 | &sensor_dev_template_temp_label, | |
2250 | &sensor_dev_template_temp_alarm, /* 2 */ | |
30846993 GR |
2251 | &sensor_dev_template_temp_beep, /* 3 */ |
2252 | &sensor_dev_template_temp_max, /* 4 */ | |
2253 | &sensor_dev_template_temp_max_hyst, /* 5 */ | |
2254 | &sensor_dev_template_temp_crit, /* 6 */ | |
2255 | &sensor_dev_template_temp_lcrit, /* 7 */ | |
2256 | &sensor_dev_template_temp_offset, /* 8 */ | |
2257 | &sensor_dev_template_temp_type, /* 9 */ | |
f73cf632 | 2258 | NULL |
aa136e5d GR |
2259 | }; |
2260 | ||
c60fdf85 | 2261 | static const struct sensor_template_group nct6775_temp_template_group = { |
f73cf632 GR |
2262 | .templates = nct6775_attributes_temp_template, |
2263 | .is_visible = nct6775_temp_is_visible, | |
2264 | .base = 1, | |
aa136e5d GR |
2265 | }; |
2266 | ||
77eb5b37 GR |
2267 | static ssize_t |
2268 | show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf) | |
2269 | { | |
2270 | struct nct6775_data *data = nct6775_update_device(dev); | |
2271 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2272 | ||
2273 | return sprintf(buf, "%d\n", !data->pwm_mode[sattr->index]); | |
2274 | } | |
2275 | ||
2276 | static ssize_t | |
2277 | store_pwm_mode(struct device *dev, struct device_attribute *attr, | |
2278 | const char *buf, size_t count) | |
2279 | { | |
2280 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2281 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2282 | int nr = sattr->index; | |
2283 | unsigned long val; | |
2284 | int err; | |
2285 | u8 reg; | |
2286 | ||
2287 | err = kstrtoul(buf, 10, &val); | |
2288 | if (err < 0) | |
2289 | return err; | |
2290 | ||
2291 | if (val > 1) | |
2292 | return -EINVAL; | |
2293 | ||
2294 | /* Setting DC mode is not supported for all chips/channels */ | |
2295 | if (data->REG_PWM_MODE[nr] == 0) { | |
2296 | if (val) | |
2297 | return -EINVAL; | |
2298 | return count; | |
2299 | } | |
2300 | ||
2301 | mutex_lock(&data->update_lock); | |
2302 | data->pwm_mode[nr] = val; | |
2303 | reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]); | |
2304 | reg &= ~data->PWM_MODE_MASK[nr]; | |
2305 | if (val) | |
2306 | reg |= data->PWM_MODE_MASK[nr]; | |
2307 | nct6775_write_value(data, data->REG_PWM_MODE[nr], reg); | |
2308 | mutex_unlock(&data->update_lock); | |
2309 | return count; | |
2310 | } | |
2311 | ||
2312 | static ssize_t | |
2313 | show_pwm(struct device *dev, struct device_attribute *attr, char *buf) | |
2314 | { | |
2315 | struct nct6775_data *data = nct6775_update_device(dev); | |
2316 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2317 | int nr = sattr->nr; | |
2318 | int index = sattr->index; | |
2319 | int pwm; | |
2320 | ||
2321 | /* | |
2322 | * For automatic fan control modes, show current pwm readings. | |
2323 | * Otherwise, show the configured value. | |
2324 | */ | |
2325 | if (index == 0 && data->pwm_enable[nr] > manual) | |
2326 | pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]); | |
2327 | else | |
2328 | pwm = data->pwm[index][nr]; | |
2329 | ||
2330 | return sprintf(buf, "%d\n", pwm); | |
2331 | } | |
2332 | ||
2333 | static ssize_t | |
2334 | store_pwm(struct device *dev, struct device_attribute *attr, const char *buf, | |
2335 | size_t count) | |
2336 | { | |
2337 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2338 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2339 | int nr = sattr->nr; | |
2340 | int index = sattr->index; | |
2341 | unsigned long val; | |
bbd8decd GR |
2342 | int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 }; |
2343 | int maxval[7] | |
2344 | = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 }; | |
77eb5b37 | 2345 | int err; |
cdcaeceb | 2346 | u8 reg; |
77eb5b37 GR |
2347 | |
2348 | err = kstrtoul(buf, 10, &val); | |
2349 | if (err < 0) | |
2350 | return err; | |
cdcaeceb | 2351 | val = clamp_val(val, minval[index], maxval[index]); |
77eb5b37 GR |
2352 | |
2353 | mutex_lock(&data->update_lock); | |
2354 | data->pwm[index][nr] = val; | |
2355 | nct6775_write_value(data, data->REG_PWM[index][nr], val); | |
cdcaeceb GR |
2356 | if (index == 2) { /* floor: disable if val == 0 */ |
2357 | reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]); | |
2358 | reg &= 0x7f; | |
2359 | if (val) | |
2360 | reg |= 0x80; | |
2361 | nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg); | |
2362 | } | |
77eb5b37 GR |
2363 | mutex_unlock(&data->update_lock); |
2364 | return count; | |
2365 | } | |
2366 | ||
cdcaeceb GR |
2367 | /* Returns 0 if OK, -EINVAL otherwise */ |
2368 | static int check_trip_points(struct nct6775_data *data, int nr) | |
2369 | { | |
2370 | int i; | |
2371 | ||
2372 | for (i = 0; i < data->auto_pwm_num - 1; i++) { | |
2373 | if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) | |
2374 | return -EINVAL; | |
2375 | } | |
2376 | for (i = 0; i < data->auto_pwm_num - 1; i++) { | |
2377 | if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) | |
2378 | return -EINVAL; | |
2379 | } | |
2380 | /* validate critical temperature and pwm if enabled (pwm > 0) */ | |
2381 | if (data->auto_pwm[nr][data->auto_pwm_num]) { | |
2382 | if (data->auto_temp[nr][data->auto_pwm_num - 1] > | |
2383 | data->auto_temp[nr][data->auto_pwm_num] || | |
2384 | data->auto_pwm[nr][data->auto_pwm_num - 1] > | |
2385 | data->auto_pwm[nr][data->auto_pwm_num]) | |
2386 | return -EINVAL; | |
2387 | } | |
2388 | return 0; | |
2389 | } | |
2390 | ||
2391 | static void pwm_update_registers(struct nct6775_data *data, int nr) | |
2392 | { | |
2393 | u8 reg; | |
2394 | ||
2395 | switch (data->pwm_enable[nr]) { | |
2396 | case off: | |
2397 | case manual: | |
2398 | break; | |
2399 | case speed_cruise: | |
2400 | reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]); | |
2401 | reg = (reg & ~data->tolerance_mask) | | |
2402 | (data->target_speed_tolerance[nr] & data->tolerance_mask); | |
2403 | nct6775_write_value(data, data->REG_FAN_MODE[nr], reg); | |
2404 | nct6775_write_value(data, data->REG_TARGET[nr], | |
2405 | data->target_speed[nr] & 0xff); | |
2406 | if (data->REG_TOLERANCE_H) { | |
2407 | reg = (data->target_speed[nr] >> 8) & 0x0f; | |
2408 | reg |= (data->target_speed_tolerance[nr] & 0x38) << 1; | |
2409 | nct6775_write_value(data, | |
2410 | data->REG_TOLERANCE_H[nr], | |
2411 | reg); | |
2412 | } | |
2413 | break; | |
2414 | case thermal_cruise: | |
2415 | nct6775_write_value(data, data->REG_TARGET[nr], | |
2416 | data->target_temp[nr]); | |
2417 | /* intentional */ | |
2418 | default: | |
2419 | reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]); | |
2420 | reg = (reg & ~data->tolerance_mask) | | |
2421 | data->temp_tolerance[0][nr]; | |
2422 | nct6775_write_value(data, data->REG_FAN_MODE[nr], reg); | |
2423 | break; | |
2424 | } | |
2425 | } | |
2426 | ||
77eb5b37 GR |
2427 | static ssize_t |
2428 | show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf) | |
2429 | { | |
2430 | struct nct6775_data *data = nct6775_update_device(dev); | |
2431 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2432 | ||
2433 | return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]); | |
2434 | } | |
2435 | ||
2436 | static ssize_t | |
2437 | store_pwm_enable(struct device *dev, struct device_attribute *attr, | |
2438 | const char *buf, size_t count) | |
2439 | { | |
2440 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2441 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2442 | int nr = sattr->index; | |
2443 | unsigned long val; | |
2444 | int err; | |
2445 | u16 reg; | |
2446 | ||
2447 | err = kstrtoul(buf, 10, &val); | |
2448 | if (err < 0) | |
2449 | return err; | |
2450 | ||
2451 | if (val > sf4) | |
2452 | return -EINVAL; | |
2453 | ||
2454 | if (val == sf3 && data->kind != nct6775) | |
2455 | return -EINVAL; | |
2456 | ||
cdcaeceb GR |
2457 | if (val == sf4 && check_trip_points(data, nr)) { |
2458 | dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n"); | |
2459 | dev_err(dev, "Adjust trip points and try again\n"); | |
2460 | return -EINVAL; | |
2461 | } | |
2462 | ||
77eb5b37 GR |
2463 | mutex_lock(&data->update_lock); |
2464 | data->pwm_enable[nr] = val; | |
2465 | if (val == off) { | |
2466 | /* | |
2467 | * turn off pwm control: select manual mode, set pwm to maximum | |
2468 | */ | |
2469 | data->pwm[0][nr] = 255; | |
2470 | nct6775_write_value(data, data->REG_PWM[0][nr], 255); | |
2471 | } | |
cdcaeceb | 2472 | pwm_update_registers(data, nr); |
77eb5b37 GR |
2473 | reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]); |
2474 | reg &= 0x0f; | |
2475 | reg |= pwm_enable_to_reg(val) << 4; | |
2476 | nct6775_write_value(data, data->REG_FAN_MODE[nr], reg); | |
2477 | mutex_unlock(&data->update_lock); | |
2478 | return count; | |
2479 | } | |
2480 | ||
cdcaeceb | 2481 | static ssize_t |
bbd8decd | 2482 | show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src) |
cdcaeceb | 2483 | { |
bbd8decd | 2484 | int i, sel = 0; |
cdcaeceb GR |
2485 | |
2486 | for (i = 0; i < NUM_TEMP; i++) { | |
2487 | if (!(data->have_temp & (1 << i))) | |
2488 | continue; | |
2489 | if (src == data->temp_src[i]) { | |
2490 | sel = i + 1; | |
2491 | break; | |
2492 | } | |
2493 | } | |
2494 | ||
2495 | return sprintf(buf, "%d\n", sel); | |
2496 | } | |
2497 | ||
bbd8decd GR |
2498 | static ssize_t |
2499 | show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf) | |
2500 | { | |
2501 | struct nct6775_data *data = nct6775_update_device(dev); | |
2502 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2503 | int index = sattr->index; | |
2504 | ||
2505 | return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]); | |
2506 | } | |
2507 | ||
cdcaeceb GR |
2508 | static ssize_t |
2509 | store_pwm_temp_sel(struct device *dev, struct device_attribute *attr, | |
2510 | const char *buf, size_t count) | |
2511 | { | |
2512 | struct nct6775_data *data = nct6775_update_device(dev); | |
2513 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2514 | int nr = sattr->index; | |
2515 | unsigned long val; | |
2516 | int err, reg, src; | |
2517 | ||
2518 | err = kstrtoul(buf, 10, &val); | |
2519 | if (err < 0) | |
2520 | return err; | |
2521 | if (val == 0 || val > NUM_TEMP) | |
2522 | return -EINVAL; | |
2523 | if (!(data->have_temp & (1 << (val - 1))) || !data->temp_src[val - 1]) | |
2524 | return -EINVAL; | |
2525 | ||
2526 | mutex_lock(&data->update_lock); | |
2527 | src = data->temp_src[val - 1]; | |
2528 | data->pwm_temp_sel[nr] = src; | |
2529 | reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]); | |
2530 | reg &= 0xe0; | |
2531 | reg |= src; | |
2532 | nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg); | |
2533 | mutex_unlock(&data->update_lock); | |
2534 | ||
2535 | return count; | |
2536 | } | |
2537 | ||
bbd8decd GR |
2538 | static ssize_t |
2539 | show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr, | |
2540 | char *buf) | |
2541 | { | |
2542 | struct nct6775_data *data = nct6775_update_device(dev); | |
2543 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2544 | int index = sattr->index; | |
2545 | ||
2546 | return show_pwm_temp_sel_common(data, buf, | |
2547 | data->pwm_weight_temp_sel[index]); | |
2548 | } | |
2549 | ||
2550 | static ssize_t | |
2551 | store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr, | |
2552 | const char *buf, size_t count) | |
2553 | { | |
2554 | struct nct6775_data *data = nct6775_update_device(dev); | |
2555 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2556 | int nr = sattr->index; | |
2557 | unsigned long val; | |
2558 | int err, reg, src; | |
2559 | ||
2560 | err = kstrtoul(buf, 10, &val); | |
2561 | if (err < 0) | |
2562 | return err; | |
2563 | if (val > NUM_TEMP) | |
2564 | return -EINVAL; | |
2565 | if (val && (!(data->have_temp & (1 << (val - 1))) || | |
2566 | !data->temp_src[val - 1])) | |
2567 | return -EINVAL; | |
2568 | ||
2569 | mutex_lock(&data->update_lock); | |
2570 | if (val) { | |
2571 | src = data->temp_src[val - 1]; | |
2572 | data->pwm_weight_temp_sel[nr] = src; | |
2573 | reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]); | |
2574 | reg &= 0xe0; | |
2575 | reg |= (src | 0x80); | |
2576 | nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg); | |
2577 | } else { | |
2578 | data->pwm_weight_temp_sel[nr] = 0; | |
2579 | reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]); | |
2580 | reg &= 0x7f; | |
2581 | nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg); | |
2582 | } | |
2583 | mutex_unlock(&data->update_lock); | |
2584 | ||
2585 | return count; | |
2586 | } | |
2587 | ||
cdcaeceb GR |
2588 | static ssize_t |
2589 | show_target_temp(struct device *dev, struct device_attribute *attr, char *buf) | |
2590 | { | |
2591 | struct nct6775_data *data = nct6775_update_device(dev); | |
2592 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2593 | ||
2594 | return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000); | |
2595 | } | |
2596 | ||
2597 | static ssize_t | |
2598 | store_target_temp(struct device *dev, struct device_attribute *attr, | |
2599 | const char *buf, size_t count) | |
2600 | { | |
2601 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2602 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2603 | int nr = sattr->index; | |
2604 | unsigned long val; | |
2605 | int err; | |
2606 | ||
2607 | err = kstrtoul(buf, 10, &val); | |
2608 | if (err < 0) | |
2609 | return err; | |
2610 | ||
2611 | val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, | |
2612 | data->target_temp_mask); | |
2613 | ||
2614 | mutex_lock(&data->update_lock); | |
2615 | data->target_temp[nr] = val; | |
2616 | pwm_update_registers(data, nr); | |
2617 | mutex_unlock(&data->update_lock); | |
2618 | return count; | |
2619 | } | |
2620 | ||
2621 | static ssize_t | |
2622 | show_target_speed(struct device *dev, struct device_attribute *attr, char *buf) | |
2623 | { | |
2624 | struct nct6775_data *data = nct6775_update_device(dev); | |
2625 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2626 | int nr = sattr->index; | |
2627 | ||
2628 | return sprintf(buf, "%d\n", | |
2629 | fan_from_reg16(data->target_speed[nr], | |
2630 | data->fan_div[nr])); | |
2631 | } | |
2632 | ||
2633 | static ssize_t | |
2634 | store_target_speed(struct device *dev, struct device_attribute *attr, | |
2635 | const char *buf, size_t count) | |
2636 | { | |
2637 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2638 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2639 | int nr = sattr->index; | |
2640 | unsigned long val; | |
2641 | int err; | |
2642 | u16 speed; | |
2643 | ||
2644 | err = kstrtoul(buf, 10, &val); | |
2645 | if (err < 0) | |
2646 | return err; | |
2647 | ||
2648 | val = clamp_val(val, 0, 1350000U); | |
2649 | speed = fan_to_reg(val, data->fan_div[nr]); | |
2650 | ||
2651 | mutex_lock(&data->update_lock); | |
2652 | data->target_speed[nr] = speed; | |
2653 | pwm_update_registers(data, nr); | |
2654 | mutex_unlock(&data->update_lock); | |
2655 | return count; | |
2656 | } | |
2657 | ||
2658 | static ssize_t | |
2659 | show_temp_tolerance(struct device *dev, struct device_attribute *attr, | |
2660 | char *buf) | |
2661 | { | |
2662 | struct nct6775_data *data = nct6775_update_device(dev); | |
2663 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2664 | int nr = sattr->nr; | |
2665 | int index = sattr->index; | |
2666 | ||
2667 | return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000); | |
2668 | } | |
2669 | ||
2670 | static ssize_t | |
2671 | store_temp_tolerance(struct device *dev, struct device_attribute *attr, | |
2672 | const char *buf, size_t count) | |
2673 | { | |
2674 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2675 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2676 | int nr = sattr->nr; | |
2677 | int index = sattr->index; | |
2678 | unsigned long val; | |
2679 | int err; | |
2680 | ||
2681 | err = kstrtoul(buf, 10, &val); | |
2682 | if (err < 0) | |
2683 | return err; | |
2684 | ||
2685 | /* Limit tolerance as needed */ | |
2686 | val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask); | |
2687 | ||
2688 | mutex_lock(&data->update_lock); | |
2689 | data->temp_tolerance[index][nr] = val; | |
2690 | if (index) | |
2691 | pwm_update_registers(data, nr); | |
2692 | else | |
2693 | nct6775_write_value(data, | |
2694 | data->REG_CRITICAL_TEMP_TOLERANCE[nr], | |
2695 | val); | |
2696 | mutex_unlock(&data->update_lock); | |
2697 | return count; | |
2698 | } | |
2699 | ||
2700 | /* | |
2701 | * Fan speed tolerance is a tricky beast, since the associated register is | |
2702 | * a tick counter, but the value is reported and configured as rpm. | |
2703 | * Compute resulting low and high rpm values and report the difference. | |
2704 | */ | |
2705 | static ssize_t | |
2706 | show_speed_tolerance(struct device *dev, struct device_attribute *attr, | |
2707 | char *buf) | |
2708 | { | |
2709 | struct nct6775_data *data = nct6775_update_device(dev); | |
2710 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2711 | int nr = sattr->index; | |
2712 | int low = data->target_speed[nr] - data->target_speed_tolerance[nr]; | |
2713 | int high = data->target_speed[nr] + data->target_speed_tolerance[nr]; | |
2714 | int tolerance; | |
2715 | ||
2716 | if (low <= 0) | |
2717 | low = 1; | |
2718 | if (high > 0xffff) | |
2719 | high = 0xffff; | |
2720 | if (high < low) | |
2721 | high = low; | |
2722 | ||
2723 | tolerance = (fan_from_reg16(low, data->fan_div[nr]) | |
2724 | - fan_from_reg16(high, data->fan_div[nr])) / 2; | |
2725 | ||
2726 | return sprintf(buf, "%d\n", tolerance); | |
2727 | } | |
2728 | ||
2729 | static ssize_t | |
2730 | store_speed_tolerance(struct device *dev, struct device_attribute *attr, | |
2731 | const char *buf, size_t count) | |
2732 | { | |
2733 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2734 | struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr); | |
2735 | int nr = sattr->index; | |
2736 | unsigned long val; | |
2737 | int err; | |
2738 | int low, high; | |
2739 | ||
2740 | err = kstrtoul(buf, 10, &val); | |
2741 | if (err < 0) | |
2742 | return err; | |
2743 | ||
2744 | high = fan_from_reg16(data->target_speed[nr], | |
2745 | data->fan_div[nr]) + val; | |
2746 | low = fan_from_reg16(data->target_speed[nr], | |
2747 | data->fan_div[nr]) - val; | |
2748 | if (low <= 0) | |
2749 | low = 1; | |
2750 | if (high < low) | |
2751 | high = low; | |
2752 | ||
2753 | val = (fan_to_reg(low, data->fan_div[nr]) - | |
2754 | fan_to_reg(high, data->fan_div[nr])) / 2; | |
2755 | ||
2756 | /* Limit tolerance as needed */ | |
2757 | val = clamp_val(val, 0, data->speed_tolerance_limit); | |
2758 | ||
2759 | mutex_lock(&data->update_lock); | |
2760 | data->target_speed_tolerance[nr] = val; | |
2761 | pwm_update_registers(data, nr); | |
2762 | mutex_unlock(&data->update_lock); | |
2763 | return count; | |
2764 | } | |
2765 | ||
f73cf632 GR |
2766 | SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0); |
2767 | SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode, | |
2768 | store_pwm_mode, 0); | |
2769 | SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable, | |
2770 | store_pwm_enable, 0); | |
2771 | SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO, | |
2772 | show_pwm_temp_sel, store_pwm_temp_sel, 0); | |
2773 | SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO, | |
2774 | show_target_temp, store_target_temp, 0); | |
2775 | SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO, | |
2776 | show_target_speed, store_target_speed, 0); | |
2777 | SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO, | |
2778 | show_speed_tolerance, store_speed_tolerance, 0); | |
cdcaeceb GR |
2779 | |
2780 | /* Smart Fan registers */ | |
2781 | ||
bbd8decd GR |
2782 | static ssize_t |
2783 | show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf) | |
2784 | { | |
2785 | struct nct6775_data *data = nct6775_update_device(dev); | |
2786 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2787 | int nr = sattr->nr; | |
2788 | int index = sattr->index; | |
2789 | ||
2790 | return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000); | |
2791 | } | |
2792 | ||
2793 | static ssize_t | |
2794 | store_weight_temp(struct device *dev, struct device_attribute *attr, | |
2795 | const char *buf, size_t count) | |
2796 | { | |
2797 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2798 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2799 | int nr = sattr->nr; | |
2800 | int index = sattr->index; | |
2801 | unsigned long val; | |
2802 | int err; | |
2803 | ||
2804 | err = kstrtoul(buf, 10, &val); | |
2805 | if (err < 0) | |
2806 | return err; | |
2807 | ||
2808 | val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255); | |
2809 | ||
2810 | mutex_lock(&data->update_lock); | |
2811 | data->weight_temp[index][nr] = val; | |
2812 | nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val); | |
2813 | mutex_unlock(&data->update_lock); | |
2814 | return count; | |
2815 | } | |
2816 | ||
f73cf632 GR |
2817 | SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO, |
2818 | show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0); | |
2819 | SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step", | |
2820 | S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0); | |
2821 | SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol", | |
2822 | S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1); | |
2823 | SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base", | |
2824 | S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2); | |
2825 | SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step", | |
2826 | S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5); | |
2827 | SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base", | |
2828 | S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6); | |
bbd8decd | 2829 | |
cdcaeceb GR |
2830 | static ssize_t |
2831 | show_fan_time(struct device *dev, struct device_attribute *attr, char *buf) | |
2832 | { | |
2833 | struct nct6775_data *data = nct6775_update_device(dev); | |
2834 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2835 | int nr = sattr->nr; | |
2836 | int index = sattr->index; | |
2837 | ||
2838 | return sprintf(buf, "%d\n", | |
2839 | step_time_from_reg(data->fan_time[index][nr], | |
2840 | data->pwm_mode[nr])); | |
2841 | } | |
2842 | ||
2843 | static ssize_t | |
2844 | store_fan_time(struct device *dev, struct device_attribute *attr, | |
2845 | const char *buf, size_t count) | |
2846 | { | |
2847 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2848 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2849 | int nr = sattr->nr; | |
2850 | int index = sattr->index; | |
2851 | unsigned long val; | |
2852 | int err; | |
2853 | ||
2854 | err = kstrtoul(buf, 10, &val); | |
2855 | if (err < 0) | |
2856 | return err; | |
2857 | ||
2858 | val = step_time_to_reg(val, data->pwm_mode[nr]); | |
2859 | mutex_lock(&data->update_lock); | |
2860 | data->fan_time[index][nr] = val; | |
2861 | nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val); | |
2862 | mutex_unlock(&data->update_lock); | |
2863 | return count; | |
2864 | } | |
2865 | ||
cdcaeceb GR |
2866 | static ssize_t |
2867 | show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf) | |
2868 | { | |
2869 | struct nct6775_data *data = nct6775_update_device(dev); | |
2870 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2871 | ||
2872 | return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]); | |
2873 | } | |
2874 | ||
2875 | static ssize_t | |
2876 | store_auto_pwm(struct device *dev, struct device_attribute *attr, | |
2877 | const char *buf, size_t count) | |
2878 | { | |
2879 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2880 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2881 | int nr = sattr->nr; | |
2882 | int point = sattr->index; | |
2883 | unsigned long val; | |
2884 | int err; | |
2885 | u8 reg; | |
2886 | ||
2887 | err = kstrtoul(buf, 10, &val); | |
2888 | if (err < 0) | |
2889 | return err; | |
2890 | if (val > 255) | |
2891 | return -EINVAL; | |
2892 | ||
2893 | if (point == data->auto_pwm_num) { | |
2894 | if (data->kind != nct6775 && !val) | |
2895 | return -EINVAL; | |
2896 | if (data->kind != nct6779 && val) | |
2897 | val = 0xff; | |
2898 | } | |
2899 | ||
2900 | mutex_lock(&data->update_lock); | |
2901 | data->auto_pwm[nr][point] = val; | |
2902 | if (point < data->auto_pwm_num) { | |
2903 | nct6775_write_value(data, | |
2904 | NCT6775_AUTO_PWM(data, nr, point), | |
2905 | data->auto_pwm[nr][point]); | |
2906 | } else { | |
2907 | switch (data->kind) { | |
2908 | case nct6775: | |
2909 | /* disable if needed (pwm == 0) */ | |
2910 | reg = nct6775_read_value(data, | |
2911 | NCT6775_REG_CRITICAL_ENAB[nr]); | |
2912 | if (val) | |
2913 | reg |= 0x02; | |
2914 | else | |
2915 | reg &= ~0x02; | |
2916 | nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr], | |
2917 | reg); | |
2918 | break; | |
2919 | case nct6776: | |
2920 | break; /* always enabled, nothing to do */ | |
6c009501 | 2921 | case nct6106: |
cdcaeceb | 2922 | case nct6779: |
578ab5f0 | 2923 | case nct6791: |
8aefb93f | 2924 | case nct6792: |
cd1faefa | 2925 | case nct6793: |
6c009501 | 2926 | nct6775_write_value(data, data->REG_CRITICAL_PWM[nr], |
cdcaeceb GR |
2927 | val); |
2928 | reg = nct6775_read_value(data, | |
6c009501 | 2929 | data->REG_CRITICAL_PWM_ENABLE[nr]); |
cdcaeceb | 2930 | if (val == 255) |
6c009501 | 2931 | reg &= ~data->CRITICAL_PWM_ENABLE_MASK; |
cdcaeceb | 2932 | else |
6c009501 | 2933 | reg |= data->CRITICAL_PWM_ENABLE_MASK; |
cdcaeceb | 2934 | nct6775_write_value(data, |
6c009501 | 2935 | data->REG_CRITICAL_PWM_ENABLE[nr], |
cdcaeceb GR |
2936 | reg); |
2937 | break; | |
2938 | } | |
2939 | } | |
2940 | mutex_unlock(&data->update_lock); | |
2941 | return count; | |
2942 | } | |
2943 | ||
2944 | static ssize_t | |
2945 | show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf) | |
2946 | { | |
2947 | struct nct6775_data *data = nct6775_update_device(dev); | |
2948 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2949 | int nr = sattr->nr; | |
2950 | int point = sattr->index; | |
2951 | ||
2952 | /* | |
2953 | * We don't know for sure if the temperature is signed or unsigned. | |
2954 | * Assume it is unsigned. | |
2955 | */ | |
2956 | return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000); | |
2957 | } | |
2958 | ||
2959 | static ssize_t | |
2960 | store_auto_temp(struct device *dev, struct device_attribute *attr, | |
2961 | const char *buf, size_t count) | |
2962 | { | |
2963 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2964 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); | |
2965 | int nr = sattr->nr; | |
2966 | int point = sattr->index; | |
2967 | unsigned long val; | |
2968 | int err; | |
2969 | ||
2970 | err = kstrtoul(buf, 10, &val); | |
2971 | if (err) | |
2972 | return err; | |
2973 | if (val > 255000) | |
2974 | return -EINVAL; | |
2975 | ||
2976 | mutex_lock(&data->update_lock); | |
2977 | data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000); | |
2978 | if (point < data->auto_pwm_num) { | |
2979 | nct6775_write_value(data, | |
2980 | NCT6775_AUTO_TEMP(data, nr, point), | |
2981 | data->auto_temp[nr][point]); | |
2982 | } else { | |
2983 | nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr], | |
2984 | data->auto_temp[nr][point]); | |
2985 | } | |
2986 | mutex_unlock(&data->update_lock); | |
2987 | return count; | |
2988 | } | |
2989 | ||
f73cf632 GR |
2990 | static umode_t nct6775_pwm_is_visible(struct kobject *kobj, |
2991 | struct attribute *attr, int index) | |
2992 | { | |
2993 | struct device *dev = container_of(kobj, struct device, kobj); | |
2994 | struct nct6775_data *data = dev_get_drvdata(dev); | |
2995 | int pwm = index / 36; /* pwm index */ | |
2996 | int nr = index % 36; /* attribute index */ | |
2997 | ||
2998 | if (!(data->has_pwm & (1 << pwm))) | |
2999 | return 0; | |
3000 | ||
cc76dee1 GR |
3001 | if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */ |
3002 | if (!data->REG_WEIGHT_TEMP_SEL[pwm]) | |
3003 | return 0; | |
f73cf632 GR |
3004 | if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */ |
3005 | return 0; | |
3006 | if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */ | |
3007 | return 0; | |
3008 | if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */ | |
3009 | return 0; | |
3010 | ||
3011 | if (nr >= 22 && nr <= 35) { /* auto point */ | |
3012 | int api = (nr - 22) / 2; /* auto point index */ | |
3013 | ||
3014 | if (api > data->auto_pwm_num) | |
3015 | return 0; | |
3016 | } | |
3017 | return attr->mode; | |
3018 | } | |
3019 | ||
3020 | SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO, | |
3021 | show_fan_time, store_fan_time, 0, 0); | |
3022 | SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO, | |
3023 | show_fan_time, store_fan_time, 0, 1); | |
3024 | SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO, | |
3025 | show_fan_time, store_fan_time, 0, 2); | |
3026 | SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm, | |
3027 | store_pwm, 0, 1); | |
3028 | SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm, | |
3029 | store_pwm, 0, 2); | |
3030 | SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO, | |
3031 | show_temp_tolerance, store_temp_tolerance, 0, 0); | |
3032 | SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance", | |
3033 | S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance, | |
3034 | 0, 1); | |
3035 | ||
3036 | SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm, | |
3037 | 0, 3); | |
3038 | ||
3039 | SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm, | |
3040 | store_pwm, 0, 4); | |
3041 | ||
3042 | SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm", | |
3043 | S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0); | |
3044 | SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp", | |
3045 | S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0); | |
3046 | ||
3047 | SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm", | |
3048 | S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1); | |
3049 | SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp", | |
3050 | S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1); | |
3051 | ||
3052 | SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm", | |
3053 | S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2); | |
3054 | SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp", | |
3055 | S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2); | |
3056 | ||
3057 | SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm", | |
3058 | S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3); | |
3059 | SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp", | |
3060 | S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3); | |
3061 | ||
3062 | SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm", | |
3063 | S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4); | |
3064 | SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp", | |
3065 | S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4); | |
3066 | ||
3067 | SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm", | |
3068 | S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5); | |
3069 | SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp", | |
3070 | S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5); | |
3071 | ||
3072 | SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm", | |
3073 | S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6); | |
3074 | SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp", | |
3075 | S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6); | |
3076 | ||
cdcaeceb | 3077 | /* |
f73cf632 GR |
3078 | * nct6775_pwm_is_visible uses the index into the following array |
3079 | * to determine if attributes should be created or not. | |
3080 | * Any change in order or content must be matched. | |
cdcaeceb | 3081 | */ |
f73cf632 GR |
3082 | static struct sensor_device_template *nct6775_attributes_pwm_template[] = { |
3083 | &sensor_dev_template_pwm, | |
3084 | &sensor_dev_template_pwm_mode, | |
3085 | &sensor_dev_template_pwm_enable, | |
3086 | &sensor_dev_template_pwm_temp_sel, | |
3087 | &sensor_dev_template_pwm_temp_tolerance, | |
3088 | &sensor_dev_template_pwm_crit_temp_tolerance, | |
3089 | &sensor_dev_template_pwm_target_temp, | |
3090 | &sensor_dev_template_fan_target, | |
3091 | &sensor_dev_template_fan_tolerance, | |
3092 | &sensor_dev_template_pwm_stop_time, | |
3093 | &sensor_dev_template_pwm_step_up_time, | |
3094 | &sensor_dev_template_pwm_step_down_time, | |
3095 | &sensor_dev_template_pwm_start, | |
3096 | &sensor_dev_template_pwm_floor, | |
cc76dee1 | 3097 | &sensor_dev_template_pwm_weight_temp_sel, /* 14 */ |
f73cf632 GR |
3098 | &sensor_dev_template_pwm_weight_temp_step, |
3099 | &sensor_dev_template_pwm_weight_temp_step_tol, | |
3100 | &sensor_dev_template_pwm_weight_temp_step_base, | |
cc76dee1 | 3101 | &sensor_dev_template_pwm_weight_duty_step, /* 18 */ |
f73cf632 GR |
3102 | &sensor_dev_template_pwm_max, /* 19 */ |
3103 | &sensor_dev_template_pwm_step, /* 20 */ | |
3104 | &sensor_dev_template_pwm_weight_duty_base, /* 21 */ | |
3105 | &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */ | |
3106 | &sensor_dev_template_pwm_auto_point1_temp, | |
3107 | &sensor_dev_template_pwm_auto_point2_pwm, | |
3108 | &sensor_dev_template_pwm_auto_point2_temp, | |
3109 | &sensor_dev_template_pwm_auto_point3_pwm, | |
3110 | &sensor_dev_template_pwm_auto_point3_temp, | |
3111 | &sensor_dev_template_pwm_auto_point4_pwm, | |
3112 | &sensor_dev_template_pwm_auto_point4_temp, | |
3113 | &sensor_dev_template_pwm_auto_point5_pwm, | |
3114 | &sensor_dev_template_pwm_auto_point5_temp, | |
3115 | &sensor_dev_template_pwm_auto_point6_pwm, | |
3116 | &sensor_dev_template_pwm_auto_point6_temp, | |
3117 | &sensor_dev_template_pwm_auto_point7_pwm, | |
3118 | &sensor_dev_template_pwm_auto_point7_temp, /* 35 */ | |
3119 | ||
3120 | NULL | |
3121 | }; | |
3122 | ||
c60fdf85 | 3123 | static const struct sensor_template_group nct6775_pwm_template_group = { |
f73cf632 GR |
3124 | .templates = nct6775_attributes_pwm_template, |
3125 | .is_visible = nct6775_pwm_is_visible, | |
3126 | .base = 1, | |
cdcaeceb GR |
3127 | }; |
3128 | ||
9de2e2e8 GR |
3129 | static ssize_t |
3130 | show_vid(struct device *dev, struct device_attribute *attr, char *buf) | |
3131 | { | |
3132 | struct nct6775_data *data = dev_get_drvdata(dev); | |
9cd892bc | 3133 | |
9de2e2e8 GR |
3134 | return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm)); |
3135 | } | |
3136 | ||
3137 | static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL); | |
3138 | ||
a6bd5878 GR |
3139 | /* Case open detection */ |
3140 | ||
3141 | static ssize_t | |
3142 | clear_caseopen(struct device *dev, struct device_attribute *attr, | |
3143 | const char *buf, size_t count) | |
3144 | { | |
3145 | struct nct6775_data *data = dev_get_drvdata(dev); | |
a6bd5878 GR |
3146 | int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE; |
3147 | unsigned long val; | |
3148 | u8 reg; | |
3149 | int ret; | |
3150 | ||
3151 | if (kstrtoul(buf, 10, &val) || val != 0) | |
3152 | return -EINVAL; | |
3153 | ||
3154 | mutex_lock(&data->update_lock); | |
3155 | ||
3156 | /* | |
3157 | * Use CR registers to clear caseopen status. | |
3158 | * The CR registers are the same for all chips, and not all chips | |
3159 | * support clearing the caseopen status through "regular" registers. | |
3160 | */ | |
df612d5f | 3161 | ret = superio_enter(data->sioreg); |
a6bd5878 GR |
3162 | if (ret) { |
3163 | count = ret; | |
3164 | goto error; | |
3165 | } | |
3166 | ||
df612d5f GR |
3167 | superio_select(data->sioreg, NCT6775_LD_ACPI); |
3168 | reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]); | |
a6bd5878 | 3169 | reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr]; |
df612d5f | 3170 | superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg); |
a6bd5878 | 3171 | reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr]; |
df612d5f GR |
3172 | superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg); |
3173 | superio_exit(data->sioreg); | |
a6bd5878 GR |
3174 | |
3175 | data->valid = false; /* Force cache refresh */ | |
3176 | error: | |
3177 | mutex_unlock(&data->update_lock); | |
3178 | return count; | |
3179 | } | |
3180 | ||
f73cf632 GR |
3181 | static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm, |
3182 | clear_caseopen, INTRUSION_ALARM_BASE); | |
3183 | static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm, | |
3184 | clear_caseopen, INTRUSION_ALARM_BASE + 1); | |
30846993 GR |
3185 | static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep, |
3186 | store_beep, INTRUSION_ALARM_BASE); | |
3187 | static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep, | |
3188 | store_beep, INTRUSION_ALARM_BASE + 1); | |
3189 | static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep, | |
3190 | store_beep, BEEP_ENABLE_BASE); | |
9de2e2e8 | 3191 | |
f73cf632 GR |
3192 | static umode_t nct6775_other_is_visible(struct kobject *kobj, |
3193 | struct attribute *attr, int index) | |
9de2e2e8 | 3194 | { |
f73cf632 | 3195 | struct device *dev = container_of(kobj, struct device, kobj); |
9de2e2e8 GR |
3196 | struct nct6775_data *data = dev_get_drvdata(dev); |
3197 | ||
615fc8cb | 3198 | if (index == 0 && !data->have_vid) |
f73cf632 | 3199 | return 0; |
77eb5b37 | 3200 | |
615fc8cb GR |
3201 | if (index == 1 || index == 2) { |
3202 | if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0) | |
f73cf632 GR |
3203 | return 0; |
3204 | } | |
cdcaeceb | 3205 | |
615fc8cb GR |
3206 | if (index == 3 || index == 4) { |
3207 | if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0) | |
30846993 GR |
3208 | return 0; |
3209 | } | |
3210 | ||
f73cf632 GR |
3211 | return attr->mode; |
3212 | } | |
cdcaeceb | 3213 | |
f73cf632 GR |
3214 | /* |
3215 | * nct6775_other_is_visible uses the index into the following array | |
3216 | * to determine if attributes should be created or not. | |
3217 | * Any change in order or content must be matched. | |
3218 | */ | |
3219 | static struct attribute *nct6775_attributes_other[] = { | |
615fc8cb GR |
3220 | &dev_attr_cpu0_vid.attr, /* 0 */ |
3221 | &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */ | |
3222 | &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */ | |
3223 | &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */ | |
3224 | &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */ | |
3225 | &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */ | |
bbd8decd | 3226 | |
f73cf632 GR |
3227 | NULL |
3228 | }; | |
cdcaeceb | 3229 | |
f73cf632 GR |
3230 | static const struct attribute_group nct6775_group_other = { |
3231 | .attrs = nct6775_attributes_other, | |
3232 | .is_visible = nct6775_other_is_visible, | |
3233 | }; | |
9de2e2e8 | 3234 | |
9de2e2e8 GR |
3235 | static inline void nct6775_init_device(struct nct6775_data *data) |
3236 | { | |
aa136e5d GR |
3237 | int i; |
3238 | u8 tmp, diode; | |
9de2e2e8 GR |
3239 | |
3240 | /* Start monitoring if needed */ | |
3241 | if (data->REG_CONFIG) { | |
3242 | tmp = nct6775_read_value(data, data->REG_CONFIG); | |
3243 | if (!(tmp & 0x01)) | |
3244 | nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01); | |
3245 | } | |
3246 | ||
aa136e5d GR |
3247 | /* Enable temperature sensors if needed */ |
3248 | for (i = 0; i < NUM_TEMP; i++) { | |
3249 | if (!(data->have_temp & (1 << i))) | |
3250 | continue; | |
3251 | if (!data->reg_temp_config[i]) | |
3252 | continue; | |
3253 | tmp = nct6775_read_value(data, data->reg_temp_config[i]); | |
3254 | if (tmp & 0x01) | |
3255 | nct6775_write_value(data, data->reg_temp_config[i], | |
3256 | tmp & 0xfe); | |
3257 | } | |
3258 | ||
9de2e2e8 GR |
3259 | /* Enable VBAT monitoring if needed */ |
3260 | tmp = nct6775_read_value(data, data->REG_VBAT); | |
3261 | if (!(tmp & 0x01)) | |
3262 | nct6775_write_value(data, data->REG_VBAT, tmp | 0x01); | |
aa136e5d GR |
3263 | |
3264 | diode = nct6775_read_value(data, data->REG_DIODE); | |
3265 | ||
3266 | for (i = 0; i < data->temp_fixed_num; i++) { | |
3267 | if (!(data->have_temp_fixed & (1 << i))) | |
3268 | continue; | |
6c009501 GR |
3269 | if ((tmp & (data->DIODE_MASK << i))) /* diode */ |
3270 | data->temp_type[i] | |
3271 | = 3 - ((diode >> i) & data->DIODE_MASK); | |
aa136e5d GR |
3272 | else /* thermistor */ |
3273 | data->temp_type[i] = 4; | |
3274 | } | |
9de2e2e8 GR |
3275 | } |
3276 | ||
f73cf632 | 3277 | static void |
df612d5f | 3278 | nct6775_check_fan_inputs(struct nct6775_data *data) |
1c65dc36 | 3279 | { |
578ab5f0 DB |
3280 | bool fan3pin, fan4pin, fan4min, fan5pin, fan6pin; |
3281 | bool pwm3pin, pwm4pin, pwm5pin, pwm6pin; | |
df612d5f GR |
3282 | int sioreg = data->sioreg; |
3283 | int regval; | |
1c65dc36 | 3284 | |
d2a14ea5 GR |
3285 | /* Store SIO_REG_ENABLE for use during resume */ |
3286 | superio_select(sioreg, NCT6775_LD_HWM); | |
3287 | data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE); | |
3288 | ||
1c65dc36 GR |
3289 | /* fan4 and fan5 share some pins with the GPIO and serial flash */ |
3290 | if (data->kind == nct6775) { | |
df612d5f | 3291 | regval = superio_inb(sioreg, 0x2c); |
1c65dc36 GR |
3292 | |
3293 | fan3pin = regval & (1 << 6); | |
77eb5b37 | 3294 | pwm3pin = regval & (1 << 7); |
1c65dc36 GR |
3295 | |
3296 | /* On NCT6775, fan4 shares pins with the fdc interface */ | |
df612d5f | 3297 | fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80); |
578ab5f0 DB |
3298 | fan4min = false; |
3299 | fan5pin = false; | |
3300 | fan6pin = false; | |
3301 | pwm4pin = false; | |
3302 | pwm5pin = false; | |
3303 | pwm6pin = false; | |
1c65dc36 | 3304 | } else if (data->kind == nct6776) { |
df612d5f | 3305 | bool gpok = superio_inb(sioreg, 0x27) & 0x80; |
25cdd99d GR |
3306 | const char *board_vendor, *board_name; |
3307 | ||
3308 | board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR); | |
3309 | board_name = dmi_get_system_info(DMI_BOARD_NAME); | |
3310 | ||
3311 | if (board_name && board_vendor && | |
3312 | !strcmp(board_vendor, "ASRock")) { | |
3313 | /* | |
3314 | * Auxiliary fan monitoring is not enabled on ASRock | |
3315 | * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode. | |
3316 | * Observed with BIOS version 2.00. | |
3317 | */ | |
3318 | if (!strcmp(board_name, "Z77 Pro4-M")) { | |
3319 | if ((data->sio_reg_enable & 0xe0) != 0xe0) { | |
3320 | data->sio_reg_enable |= 0xe0; | |
3321 | superio_outb(sioreg, SIO_REG_ENABLE, | |
3322 | data->sio_reg_enable); | |
3323 | } | |
3324 | } | |
3325 | } | |
1c65dc36 | 3326 | |
d2a14ea5 | 3327 | if (data->sio_reg_enable & 0x80) |
1c65dc36 GR |
3328 | fan3pin = gpok; |
3329 | else | |
df612d5f | 3330 | fan3pin = !(superio_inb(sioreg, 0x24) & 0x40); |
1c65dc36 | 3331 | |
d2a14ea5 | 3332 | if (data->sio_reg_enable & 0x40) |
1c65dc36 GR |
3333 | fan4pin = gpok; |
3334 | else | |
df612d5f | 3335 | fan4pin = superio_inb(sioreg, 0x1C) & 0x01; |
1c65dc36 | 3336 | |
d2a14ea5 | 3337 | if (data->sio_reg_enable & 0x20) |
1c65dc36 GR |
3338 | fan5pin = gpok; |
3339 | else | |
df612d5f | 3340 | fan5pin = superio_inb(sioreg, 0x1C) & 0x02; |
1c65dc36 GR |
3341 | |
3342 | fan4min = fan4pin; | |
578ab5f0 | 3343 | fan6pin = false; |
77eb5b37 | 3344 | pwm3pin = fan3pin; |
578ab5f0 DB |
3345 | pwm4pin = false; |
3346 | pwm5pin = false; | |
3347 | pwm6pin = false; | |
6c009501 | 3348 | } else if (data->kind == nct6106) { |
df612d5f | 3349 | regval = superio_inb(sioreg, 0x24); |
6c009501 GR |
3350 | fan3pin = !(regval & 0x80); |
3351 | pwm3pin = regval & 0x08; | |
6c009501 GR |
3352 | |
3353 | fan4pin = false; | |
3354 | fan4min = false; | |
3355 | fan5pin = false; | |
578ab5f0 | 3356 | fan6pin = false; |
6c009501 GR |
3357 | pwm4pin = false; |
3358 | pwm5pin = false; | |
578ab5f0 | 3359 | pwm6pin = false; |
cd1faefa | 3360 | } else { /* NCT6779D, NCT6791D, NCT6792D, or NCT6793D */ |
df612d5f | 3361 | regval = superio_inb(sioreg, 0x1c); |
1c65dc36 GR |
3362 | |
3363 | fan3pin = !(regval & (1 << 5)); | |
3364 | fan4pin = !(regval & (1 << 6)); | |
3365 | fan5pin = !(regval & (1 << 7)); | |
3366 | ||
77eb5b37 GR |
3367 | pwm3pin = !(regval & (1 << 0)); |
3368 | pwm4pin = !(regval & (1 << 1)); | |
3369 | pwm5pin = !(regval & (1 << 2)); | |
3370 | ||
1c65dc36 | 3371 | fan4min = fan4pin; |
1c65dc36 | 3372 | |
cd1faefa GR |
3373 | if (data->kind == nct6791 || data->kind == nct6792 || |
3374 | data->kind == nct6793) { | |
df612d5f | 3375 | regval = superio_inb(sioreg, 0x2d); |
578ab5f0 DB |
3376 | fan6pin = (regval & (1 << 1)); |
3377 | pwm6pin = (regval & (1 << 0)); | |
3378 | } else { /* NCT6779D */ | |
3379 | fan6pin = false; | |
3380 | pwm6pin = false; | |
3381 | } | |
3382 | } | |
1c65dc36 | 3383 | |
578ab5f0 DB |
3384 | /* fan 1 and 2 (0x03) are always present */ |
3385 | data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) | | |
3386 | (fan5pin << 4) | (fan6pin << 5); | |
3387 | data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) | | |
3388 | (fan5pin << 4); | |
3389 | data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) | | |
3390 | (pwm5pin << 4) | (pwm6pin << 5); | |
1c65dc36 GR |
3391 | } |
3392 | ||
8e9285b0 GR |
3393 | static void add_temp_sensors(struct nct6775_data *data, const u16 *regp, |
3394 | int *available, int *mask) | |
3395 | { | |
3396 | int i; | |
3397 | u8 src; | |
3398 | ||
3399 | for (i = 0; i < data->pwm_num && *available; i++) { | |
3400 | int index; | |
3401 | ||
3402 | if (!regp[i]) | |
3403 | continue; | |
3404 | src = nct6775_read_value(data, regp[i]); | |
3405 | src &= 0x1f; | |
3406 | if (!src || (*mask & (1 << src))) | |
3407 | continue; | |
3408 | if (src >= data->temp_label_num || | |
3409 | !strlen(data->temp_label[src])) | |
3410 | continue; | |
3411 | ||
3412 | index = __ffs(*available); | |
3413 | nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src); | |
3414 | *available &= ~(1 << index); | |
3415 | *mask |= 1 << src; | |
3416 | } | |
3417 | } | |
3418 | ||
9de2e2e8 GR |
3419 | static int nct6775_probe(struct platform_device *pdev) |
3420 | { | |
3421 | struct device *dev = &pdev->dev; | |
a8b3a3a5 | 3422 | struct nct6775_sio_data *sio_data = dev_get_platdata(dev); |
9de2e2e8 GR |
3423 | struct nct6775_data *data; |
3424 | struct resource *res; | |
aa136e5d GR |
3425 | int i, s, err = 0; |
3426 | int src, mask, available; | |
3427 | const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config; | |
d1a284b7 | 3428 | const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit; |
b7a61353 | 3429 | const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL; |
d1a284b7 | 3430 | int num_reg_temp, num_reg_temp_mon; |
0fc1f8fc | 3431 | u8 cr2a; |
f73cf632 | 3432 | struct attribute_group *group; |
a150d95b | 3433 | struct device *hwmon_dev; |
55bdee69 | 3434 | int num_attr_groups = 0; |
9de2e2e8 GR |
3435 | |
3436 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
3437 | if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH, | |
3438 | DRVNAME)) | |
3439 | return -EBUSY; | |
3440 | ||
3441 | data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data), | |
3442 | GFP_KERNEL); | |
3443 | if (!data) | |
3444 | return -ENOMEM; | |
3445 | ||
3446 | data->kind = sio_data->kind; | |
df612d5f | 3447 | data->sioreg = sio_data->sioreg; |
9de2e2e8 | 3448 | data->addr = res->start; |
9de2e2e8 GR |
3449 | mutex_init(&data->update_lock); |
3450 | data->name = nct6775_device_names[data->kind]; | |
3451 | data->bank = 0xff; /* Force initial bank selection */ | |
3452 | platform_set_drvdata(pdev, data); | |
3453 | ||
3454 | switch (data->kind) { | |
6c009501 GR |
3455 | case nct6106: |
3456 | data->in_num = 9; | |
3457 | data->pwm_num = 3; | |
3458 | data->auto_pwm_num = 4; | |
3459 | data->temp_fixed_num = 3; | |
3460 | data->num_temp_alarms = 6; | |
30846993 | 3461 | data->num_temp_beeps = 6; |
6c009501 GR |
3462 | |
3463 | data->fan_from_reg = fan_from_reg13; | |
3464 | data->fan_from_reg_min = fan_from_reg13; | |
3465 | ||
3466 | data->temp_label = nct6776_temp_label; | |
3467 | data->temp_label_num = ARRAY_SIZE(nct6776_temp_label); | |
3468 | ||
3469 | data->REG_VBAT = NCT6106_REG_VBAT; | |
3470 | data->REG_DIODE = NCT6106_REG_DIODE; | |
3471 | data->DIODE_MASK = NCT6106_DIODE_MASK; | |
3472 | data->REG_VIN = NCT6106_REG_IN; | |
3473 | data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN; | |
3474 | data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX; | |
3475 | data->REG_TARGET = NCT6106_REG_TARGET; | |
3476 | data->REG_FAN = NCT6106_REG_FAN; | |
3477 | data->REG_FAN_MODE = NCT6106_REG_FAN_MODE; | |
3478 | data->REG_FAN_MIN = NCT6106_REG_FAN_MIN; | |
3479 | data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES; | |
3480 | data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT; | |
3481 | data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME; | |
3482 | data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME; | |
3483 | data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME; | |
3484 | data->REG_PWM[0] = NCT6106_REG_PWM; | |
3485 | data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT; | |
3486 | data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT; | |
3487 | data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP; | |
3488 | data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE; | |
3489 | data->REG_PWM_READ = NCT6106_REG_PWM_READ; | |
3490 | data->REG_PWM_MODE = NCT6106_REG_PWM_MODE; | |
3491 | data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK; | |
3492 | data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP; | |
3493 | data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM; | |
3494 | data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP; | |
3495 | data->REG_CRITICAL_TEMP_TOLERANCE | |
3496 | = NCT6106_REG_CRITICAL_TEMP_TOLERANCE; | |
3497 | data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE; | |
3498 | data->CRITICAL_PWM_ENABLE_MASK | |
3499 | = NCT6106_CRITICAL_PWM_ENABLE_MASK; | |
3500 | data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM; | |
3501 | data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET; | |
3502 | data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE; | |
3503 | data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL; | |
3504 | data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL; | |
3505 | data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP; | |
3506 | data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL; | |
3507 | data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE; | |
3508 | data->REG_ALARM = NCT6106_REG_ALARM; | |
3509 | data->ALARM_BITS = NCT6106_ALARM_BITS; | |
30846993 GR |
3510 | data->REG_BEEP = NCT6106_REG_BEEP; |
3511 | data->BEEP_BITS = NCT6106_BEEP_BITS; | |
6c009501 GR |
3512 | |
3513 | reg_temp = NCT6106_REG_TEMP; | |
d1a284b7 | 3514 | reg_temp_mon = NCT6106_REG_TEMP_MON; |
6c009501 | 3515 | num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP); |
d1a284b7 | 3516 | num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON); |
6c009501 GR |
3517 | reg_temp_over = NCT6106_REG_TEMP_OVER; |
3518 | reg_temp_hyst = NCT6106_REG_TEMP_HYST; | |
3519 | reg_temp_config = NCT6106_REG_TEMP_CONFIG; | |
3520 | reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE; | |
3521 | reg_temp_crit = NCT6106_REG_TEMP_CRIT; | |
b7a61353 GR |
3522 | reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L; |
3523 | reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H; | |
6c009501 GR |
3524 | |
3525 | break; | |
9de2e2e8 GR |
3526 | case nct6775: |
3527 | data->in_num = 9; | |
77eb5b37 | 3528 | data->pwm_num = 3; |
cdcaeceb | 3529 | data->auto_pwm_num = 6; |
1c65dc36 | 3530 | data->has_fan_div = true; |
aa136e5d | 3531 | data->temp_fixed_num = 3; |
b1d2bff6 | 3532 | data->num_temp_alarms = 3; |
30846993 | 3533 | data->num_temp_beeps = 3; |
9de2e2e8 GR |
3534 | |
3535 | data->ALARM_BITS = NCT6775_ALARM_BITS; | |
30846993 | 3536 | data->BEEP_BITS = NCT6775_BEEP_BITS; |
9de2e2e8 | 3537 | |
1c65dc36 GR |
3538 | data->fan_from_reg = fan_from_reg16; |
3539 | data->fan_from_reg_min = fan_from_reg8; | |
cdcaeceb GR |
3540 | data->target_temp_mask = 0x7f; |
3541 | data->tolerance_mask = 0x0f; | |
3542 | data->speed_tolerance_limit = 15; | |
1c65dc36 | 3543 | |
aa136e5d GR |
3544 | data->temp_label = nct6775_temp_label; |
3545 | data->temp_label_num = ARRAY_SIZE(nct6775_temp_label); | |
3546 | ||
9de2e2e8 GR |
3547 | data->REG_CONFIG = NCT6775_REG_CONFIG; |
3548 | data->REG_VBAT = NCT6775_REG_VBAT; | |
aa136e5d | 3549 | data->REG_DIODE = NCT6775_REG_DIODE; |
6c009501 | 3550 | data->DIODE_MASK = NCT6775_DIODE_MASK; |
9de2e2e8 GR |
3551 | data->REG_VIN = NCT6775_REG_IN; |
3552 | data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN; | |
3553 | data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX; | |
cdcaeceb | 3554 | data->REG_TARGET = NCT6775_REG_TARGET; |
1c65dc36 | 3555 | data->REG_FAN = NCT6775_REG_FAN; |
77eb5b37 | 3556 | data->REG_FAN_MODE = NCT6775_REG_FAN_MODE; |
1c65dc36 | 3557 | data->REG_FAN_MIN = NCT6775_REG_FAN_MIN; |
5c25d954 | 3558 | data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES; |
6c009501 | 3559 | data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT; |
cdcaeceb GR |
3560 | data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME; |
3561 | data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME; | |
3562 | data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME; | |
77eb5b37 | 3563 | data->REG_PWM[0] = NCT6775_REG_PWM; |
cdcaeceb GR |
3564 | data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT; |
3565 | data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT; | |
3566 | data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT; | |
3567 | data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT; | |
bbd8decd | 3568 | data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP; |
77eb5b37 GR |
3569 | data->REG_PWM_READ = NCT6775_REG_PWM_READ; |
3570 | data->REG_PWM_MODE = NCT6775_REG_PWM_MODE; | |
3571 | data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK; | |
cdcaeceb GR |
3572 | data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP; |
3573 | data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM; | |
3574 | data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP; | |
3575 | data->REG_CRITICAL_TEMP_TOLERANCE | |
3576 | = NCT6775_REG_CRITICAL_TEMP_TOLERANCE; | |
aa136e5d GR |
3577 | data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET; |
3578 | data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE; | |
cdcaeceb | 3579 | data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL; |
bbd8decd GR |
3580 | data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL; |
3581 | data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP; | |
3582 | data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL; | |
3583 | data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE; | |
9de2e2e8 | 3584 | data->REG_ALARM = NCT6775_REG_ALARM; |
30846993 | 3585 | data->REG_BEEP = NCT6775_REG_BEEP; |
aa136e5d GR |
3586 | |
3587 | reg_temp = NCT6775_REG_TEMP; | |
d1a284b7 | 3588 | reg_temp_mon = NCT6775_REG_TEMP_MON; |
aa136e5d | 3589 | num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP); |
d1a284b7 | 3590 | num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON); |
aa136e5d GR |
3591 | reg_temp_over = NCT6775_REG_TEMP_OVER; |
3592 | reg_temp_hyst = NCT6775_REG_TEMP_HYST; | |
3593 | reg_temp_config = NCT6775_REG_TEMP_CONFIG; | |
3594 | reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE; | |
3595 | reg_temp_crit = NCT6775_REG_TEMP_CRIT; | |
3596 | ||
9de2e2e8 GR |
3597 | break; |
3598 | case nct6776: | |
3599 | data->in_num = 9; | |
77eb5b37 | 3600 | data->pwm_num = 3; |
cdcaeceb | 3601 | data->auto_pwm_num = 4; |
1c65dc36 | 3602 | data->has_fan_div = false; |
aa136e5d | 3603 | data->temp_fixed_num = 3; |
b1d2bff6 | 3604 | data->num_temp_alarms = 3; |
30846993 | 3605 | data->num_temp_beeps = 6; |
9de2e2e8 GR |
3606 | |
3607 | data->ALARM_BITS = NCT6776_ALARM_BITS; | |
30846993 | 3608 | data->BEEP_BITS = NCT6776_BEEP_BITS; |
9de2e2e8 | 3609 | |
1c65dc36 GR |
3610 | data->fan_from_reg = fan_from_reg13; |
3611 | data->fan_from_reg_min = fan_from_reg13; | |
cdcaeceb GR |
3612 | data->target_temp_mask = 0xff; |
3613 | data->tolerance_mask = 0x07; | |
3614 | data->speed_tolerance_limit = 63; | |
1c65dc36 | 3615 | |
aa136e5d GR |
3616 | data->temp_label = nct6776_temp_label; |
3617 | data->temp_label_num = ARRAY_SIZE(nct6776_temp_label); | |
3618 | ||
9de2e2e8 GR |
3619 | data->REG_CONFIG = NCT6775_REG_CONFIG; |
3620 | data->REG_VBAT = NCT6775_REG_VBAT; | |
aa136e5d | 3621 | data->REG_DIODE = NCT6775_REG_DIODE; |
6c009501 | 3622 | data->DIODE_MASK = NCT6775_DIODE_MASK; |
9de2e2e8 GR |
3623 | data->REG_VIN = NCT6775_REG_IN; |
3624 | data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN; | |
3625 | data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX; | |
cdcaeceb | 3626 | data->REG_TARGET = NCT6775_REG_TARGET; |
1c65dc36 | 3627 | data->REG_FAN = NCT6775_REG_FAN; |
77eb5b37 | 3628 | data->REG_FAN_MODE = NCT6775_REG_FAN_MODE; |
1c65dc36 | 3629 | data->REG_FAN_MIN = NCT6776_REG_FAN_MIN; |
5c25d954 | 3630 | data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES; |
6c009501 | 3631 | data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT; |
cdcaeceb | 3632 | data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME; |
728d2940 GR |
3633 | data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME; |
3634 | data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME; | |
cdcaeceb | 3635 | data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H; |
77eb5b37 | 3636 | data->REG_PWM[0] = NCT6775_REG_PWM; |
cdcaeceb GR |
3637 | data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT; |
3638 | data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT; | |
bbd8decd GR |
3639 | data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP; |
3640 | data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE; | |
77eb5b37 GR |
3641 | data->REG_PWM_READ = NCT6775_REG_PWM_READ; |
3642 | data->REG_PWM_MODE = NCT6776_REG_PWM_MODE; | |
3643 | data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK; | |
cdcaeceb GR |
3644 | data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP; |
3645 | data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM; | |
3646 | data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP; | |
3647 | data->REG_CRITICAL_TEMP_TOLERANCE | |
3648 | = NCT6775_REG_CRITICAL_TEMP_TOLERANCE; | |
aa136e5d GR |
3649 | data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET; |
3650 | data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE; | |
cdcaeceb | 3651 | data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL; |
bbd8decd GR |
3652 | data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL; |
3653 | data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP; | |
3654 | data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL; | |
3655 | data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE; | |
9de2e2e8 | 3656 | data->REG_ALARM = NCT6775_REG_ALARM; |
30846993 | 3657 | data->REG_BEEP = NCT6776_REG_BEEP; |
aa136e5d GR |
3658 | |
3659 | reg_temp = NCT6775_REG_TEMP; | |
d1a284b7 | 3660 | reg_temp_mon = NCT6775_REG_TEMP_MON; |
aa136e5d | 3661 | num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP); |
d1a284b7 | 3662 | num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON); |
aa136e5d GR |
3663 | reg_temp_over = NCT6775_REG_TEMP_OVER; |
3664 | reg_temp_hyst = NCT6775_REG_TEMP_HYST; | |
3665 | reg_temp_config = NCT6776_REG_TEMP_CONFIG; | |
3666 | reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE; | |
3667 | reg_temp_crit = NCT6776_REG_TEMP_CRIT; | |
3668 | ||
9de2e2e8 GR |
3669 | break; |
3670 | case nct6779: | |
3671 | data->in_num = 15; | |
77eb5b37 | 3672 | data->pwm_num = 5; |
cdcaeceb | 3673 | data->auto_pwm_num = 4; |
1c65dc36 | 3674 | data->has_fan_div = false; |
aa136e5d | 3675 | data->temp_fixed_num = 6; |
b1d2bff6 | 3676 | data->num_temp_alarms = 2; |
30846993 | 3677 | data->num_temp_beeps = 2; |
9de2e2e8 GR |
3678 | |
3679 | data->ALARM_BITS = NCT6779_ALARM_BITS; | |
30846993 | 3680 | data->BEEP_BITS = NCT6779_BEEP_BITS; |
9de2e2e8 | 3681 | |
1c65dc36 GR |
3682 | data->fan_from_reg = fan_from_reg13; |
3683 | data->fan_from_reg_min = fan_from_reg13; | |
cdcaeceb GR |
3684 | data->target_temp_mask = 0xff; |
3685 | data->tolerance_mask = 0x07; | |
3686 | data->speed_tolerance_limit = 63; | |
1c65dc36 | 3687 | |
aa136e5d | 3688 | data->temp_label = nct6779_temp_label; |
9a38371a | 3689 | data->temp_label_num = NCT6779_NUM_LABELS; |
aa136e5d | 3690 | |
9de2e2e8 GR |
3691 | data->REG_CONFIG = NCT6775_REG_CONFIG; |
3692 | data->REG_VBAT = NCT6775_REG_VBAT; | |
aa136e5d | 3693 | data->REG_DIODE = NCT6775_REG_DIODE; |
6c009501 | 3694 | data->DIODE_MASK = NCT6775_DIODE_MASK; |
9de2e2e8 GR |
3695 | data->REG_VIN = NCT6779_REG_IN; |
3696 | data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN; | |
3697 | data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX; | |
cdcaeceb | 3698 | data->REG_TARGET = NCT6775_REG_TARGET; |
1c65dc36 | 3699 | data->REG_FAN = NCT6779_REG_FAN; |
77eb5b37 | 3700 | data->REG_FAN_MODE = NCT6775_REG_FAN_MODE; |
1c65dc36 | 3701 | data->REG_FAN_MIN = NCT6776_REG_FAN_MIN; |
5c25d954 | 3702 | data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES; |
6c009501 | 3703 | data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT; |
cdcaeceb | 3704 | data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME; |
728d2940 GR |
3705 | data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME; |
3706 | data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME; | |
cdcaeceb | 3707 | data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H; |
77eb5b37 | 3708 | data->REG_PWM[0] = NCT6775_REG_PWM; |
cdcaeceb GR |
3709 | data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT; |
3710 | data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT; | |
bbd8decd GR |
3711 | data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP; |
3712 | data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE; | |
77eb5b37 GR |
3713 | data->REG_PWM_READ = NCT6775_REG_PWM_READ; |
3714 | data->REG_PWM_MODE = NCT6776_REG_PWM_MODE; | |
3715 | data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK; | |
cdcaeceb GR |
3716 | data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP; |
3717 | data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM; | |
3718 | data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP; | |
3719 | data->REG_CRITICAL_TEMP_TOLERANCE | |
3720 | = NCT6775_REG_CRITICAL_TEMP_TOLERANCE; | |
6c009501 GR |
3721 | data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE; |
3722 | data->CRITICAL_PWM_ENABLE_MASK | |
3723 | = NCT6779_CRITICAL_PWM_ENABLE_MASK; | |
3724 | data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM; | |
aa136e5d GR |
3725 | data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET; |
3726 | data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE; | |
cdcaeceb | 3727 | data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL; |
bbd8decd GR |
3728 | data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL; |
3729 | data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP; | |
3730 | data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL; | |
3731 | data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE; | |
9de2e2e8 | 3732 | data->REG_ALARM = NCT6779_REG_ALARM; |
30846993 | 3733 | data->REG_BEEP = NCT6776_REG_BEEP; |
aa136e5d GR |
3734 | |
3735 | reg_temp = NCT6779_REG_TEMP; | |
d1a284b7 | 3736 | reg_temp_mon = NCT6779_REG_TEMP_MON; |
aa136e5d | 3737 | num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP); |
d1a284b7 | 3738 | num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON); |
aa136e5d GR |
3739 | reg_temp_over = NCT6779_REG_TEMP_OVER; |
3740 | reg_temp_hyst = NCT6779_REG_TEMP_HYST; | |
3741 | reg_temp_config = NCT6779_REG_TEMP_CONFIG; | |
3742 | reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE; | |
3743 | reg_temp_crit = NCT6779_REG_TEMP_CRIT; | |
3744 | ||
578ab5f0 DB |
3745 | break; |
3746 | case nct6791: | |
8aefb93f | 3747 | case nct6792: |
cd1faefa | 3748 | case nct6793: |
578ab5f0 DB |
3749 | data->in_num = 15; |
3750 | data->pwm_num = 6; | |
3751 | data->auto_pwm_num = 4; | |
3752 | data->has_fan_div = false; | |
3753 | data->temp_fixed_num = 6; | |
3754 | data->num_temp_alarms = 2; | |
3755 | data->num_temp_beeps = 2; | |
3756 | ||
3757 | data->ALARM_BITS = NCT6791_ALARM_BITS; | |
3758 | data->BEEP_BITS = NCT6779_BEEP_BITS; | |
3759 | ||
3760 | data->fan_from_reg = fan_from_reg13; | |
3761 | data->fan_from_reg_min = fan_from_reg13; | |
3762 | data->target_temp_mask = 0xff; | |
3763 | data->tolerance_mask = 0x07; | |
3764 | data->speed_tolerance_limit = 63; | |
3765 | ||
50224f4d GR |
3766 | switch (data->kind) { |
3767 | default: | |
3768 | case nct6791: | |
3769 | data->temp_label = nct6779_temp_label; | |
3770 | break; | |
3771 | case nct6792: | |
3772 | data->temp_label = nct6792_temp_label; | |
3773 | break; | |
3774 | case nct6793: | |
3775 | data->temp_label = nct6793_temp_label; | |
3776 | break; | |
3777 | } | |
9a38371a | 3778 | data->temp_label_num = NCT6791_NUM_LABELS; |
578ab5f0 DB |
3779 | |
3780 | data->REG_CONFIG = NCT6775_REG_CONFIG; | |
3781 | data->REG_VBAT = NCT6775_REG_VBAT; | |
3782 | data->REG_DIODE = NCT6775_REG_DIODE; | |
3783 | data->DIODE_MASK = NCT6775_DIODE_MASK; | |
3784 | data->REG_VIN = NCT6779_REG_IN; | |
3785 | data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN; | |
3786 | data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX; | |
3787 | data->REG_TARGET = NCT6775_REG_TARGET; | |
3788 | data->REG_FAN = NCT6779_REG_FAN; | |
3789 | data->REG_FAN_MODE = NCT6775_REG_FAN_MODE; | |
3790 | data->REG_FAN_MIN = NCT6776_REG_FAN_MIN; | |
3791 | data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES; | |
3792 | data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT; | |
3793 | data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME; | |
728d2940 GR |
3794 | data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME; |
3795 | data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME; | |
578ab5f0 DB |
3796 | data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H; |
3797 | data->REG_PWM[0] = NCT6775_REG_PWM; | |
3798 | data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT; | |
3799 | data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT; | |
cc76dee1 GR |
3800 | data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP; |
3801 | data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE; | |
578ab5f0 DB |
3802 | data->REG_PWM_READ = NCT6775_REG_PWM_READ; |
3803 | data->REG_PWM_MODE = NCT6776_REG_PWM_MODE; | |
3804 | data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK; | |
3805 | data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP; | |
3806 | data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM; | |
3807 | data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP; | |
3808 | data->REG_CRITICAL_TEMP_TOLERANCE | |
3809 | = NCT6775_REG_CRITICAL_TEMP_TOLERANCE; | |
3810 | data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE; | |
3811 | data->CRITICAL_PWM_ENABLE_MASK | |
3812 | = NCT6779_CRITICAL_PWM_ENABLE_MASK; | |
3813 | data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM; | |
3814 | data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET; | |
3815 | data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE; | |
3816 | data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL; | |
cc76dee1 GR |
3817 | data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL; |
3818 | data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP; | |
3819 | data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL; | |
3820 | data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE; | |
578ab5f0 | 3821 | data->REG_ALARM = NCT6791_REG_ALARM; |
8aefb93f GR |
3822 | if (data->kind == nct6791) |
3823 | data->REG_BEEP = NCT6776_REG_BEEP; | |
3824 | else | |
3825 | data->REG_BEEP = NCT6792_REG_BEEP; | |
578ab5f0 DB |
3826 | |
3827 | reg_temp = NCT6779_REG_TEMP; | |
3828 | num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP); | |
8aefb93f GR |
3829 | if (data->kind == nct6791) { |
3830 | reg_temp_mon = NCT6779_REG_TEMP_MON; | |
3831 | num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON); | |
3832 | } else { | |
3833 | reg_temp_mon = NCT6792_REG_TEMP_MON; | |
3834 | num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON); | |
3835 | } | |
578ab5f0 DB |
3836 | reg_temp_over = NCT6779_REG_TEMP_OVER; |
3837 | reg_temp_hyst = NCT6779_REG_TEMP_HYST; | |
3838 | reg_temp_config = NCT6779_REG_TEMP_CONFIG; | |
3839 | reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE; | |
3840 | reg_temp_crit = NCT6779_REG_TEMP_CRIT; | |
3841 | ||
9de2e2e8 GR |
3842 | break; |
3843 | default: | |
3844 | return -ENODEV; | |
3845 | } | |
3846 | data->have_in = (1 << data->in_num) - 1; | |
aa136e5d GR |
3847 | data->have_temp = 0; |
3848 | ||
3849 | /* | |
3850 | * On some boards, not all available temperature sources are monitored, | |
3851 | * even though some of the monitoring registers are unused. | |
3852 | * Get list of unused monitoring registers, then detect if any fan | |
3853 | * controls are configured to use unmonitored temperature sources. | |
3854 | * If so, assign the unmonitored temperature sources to available | |
3855 | * monitoring registers. | |
3856 | */ | |
3857 | mask = 0; | |
3858 | available = 0; | |
3859 | for (i = 0; i < num_reg_temp; i++) { | |
3860 | if (reg_temp[i] == 0) | |
3861 | continue; | |
3862 | ||
3863 | src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f; | |
3864 | if (!src || (mask & (1 << src))) | |
3865 | available |= 1 << i; | |
3866 | ||
3867 | mask |= 1 << src; | |
3868 | } | |
3869 | ||
8e9285b0 GR |
3870 | /* |
3871 | * Now find unmonitored temperature registers and enable monitoring | |
3872 | * if additional monitoring registers are available. | |
3873 | */ | |
3874 | add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask); | |
3875 | add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask); | |
3876 | ||
aa136e5d GR |
3877 | mask = 0; |
3878 | s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */ | |
3879 | for (i = 0; i < num_reg_temp; i++) { | |
3880 | if (reg_temp[i] == 0) | |
3881 | continue; | |
3882 | ||
3883 | src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f; | |
3884 | if (!src || (mask & (1 << src))) | |
3885 | continue; | |
3886 | ||
3887 | if (src >= data->temp_label_num || | |
3888 | !strlen(data->temp_label[src])) { | |
3889 | dev_info(dev, | |
3890 | "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n", | |
3891 | src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]); | |
3892 | continue; | |
3893 | } | |
3894 | ||
3895 | mask |= 1 << src; | |
3896 | ||
3897 | /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */ | |
3898 | if (src <= data->temp_fixed_num) { | |
3899 | data->have_temp |= 1 << (src - 1); | |
3900 | data->have_temp_fixed |= 1 << (src - 1); | |
3901 | data->reg_temp[0][src - 1] = reg_temp[i]; | |
3902 | data->reg_temp[1][src - 1] = reg_temp_over[i]; | |
3903 | data->reg_temp[2][src - 1] = reg_temp_hyst[i]; | |
b7a61353 GR |
3904 | if (reg_temp_crit_h && reg_temp_crit_h[i]) |
3905 | data->reg_temp[3][src - 1] = reg_temp_crit_h[i]; | |
3906 | else if (reg_temp_crit[src - 1]) | |
3907 | data->reg_temp[3][src - 1] | |
3908 | = reg_temp_crit[src - 1]; | |
3909 | if (reg_temp_crit_l && reg_temp_crit_l[i]) | |
3910 | data->reg_temp[4][src - 1] = reg_temp_crit_l[i]; | |
aa136e5d GR |
3911 | data->reg_temp_config[src - 1] = reg_temp_config[i]; |
3912 | data->temp_src[src - 1] = src; | |
3913 | continue; | |
3914 | } | |
3915 | ||
3916 | if (s >= NUM_TEMP) | |
3917 | continue; | |
3918 | ||
3919 | /* Use dynamic index for other sources */ | |
3920 | data->have_temp |= 1 << s; | |
3921 | data->reg_temp[0][s] = reg_temp[i]; | |
3922 | data->reg_temp[1][s] = reg_temp_over[i]; | |
3923 | data->reg_temp[2][s] = reg_temp_hyst[i]; | |
3924 | data->reg_temp_config[s] = reg_temp_config[i]; | |
b7a61353 GR |
3925 | if (reg_temp_crit_h && reg_temp_crit_h[i]) |
3926 | data->reg_temp[3][s] = reg_temp_crit_h[i]; | |
3927 | else if (reg_temp_crit[src - 1]) | |
aa136e5d | 3928 | data->reg_temp[3][s] = reg_temp_crit[src - 1]; |
b7a61353 GR |
3929 | if (reg_temp_crit_l && reg_temp_crit_l[i]) |
3930 | data->reg_temp[4][s] = reg_temp_crit_l[i]; | |
aa136e5d GR |
3931 | |
3932 | data->temp_src[s] = src; | |
3933 | s++; | |
3934 | } | |
3935 | ||
d1a284b7 GR |
3936 | /* |
3937 | * Repeat with temperatures used for fan control. | |
3938 | * This set of registers does not support limits. | |
3939 | */ | |
3940 | for (i = 0; i < num_reg_temp_mon; i++) { | |
3941 | if (reg_temp_mon[i] == 0) | |
3942 | continue; | |
3943 | ||
3944 | src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f; | |
7ce4190c | 3945 | if (!src) |
d1a284b7 GR |
3946 | continue; |
3947 | ||
3948 | if (src >= data->temp_label_num || | |
3949 | !strlen(data->temp_label[src])) { | |
3950 | dev_info(dev, | |
3951 | "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n", | |
3952 | src, i, data->REG_TEMP_SEL[i], | |
3953 | reg_temp_mon[i]); | |
3954 | continue; | |
3955 | } | |
3956 | ||
7ce4190c GR |
3957 | /* |
3958 | * For virtual temperature sources, the 'virtual' temperature | |
3959 | * for each fan reflects a different temperature, and there | |
3960 | * are no duplicates. | |
3961 | */ | |
3962 | if (src != TEMP_SOURCE_VIRTUAL) { | |
3963 | if (mask & (1 << src)) | |
3964 | continue; | |
3965 | mask |= 1 << src; | |
3966 | } | |
d1a284b7 GR |
3967 | |
3968 | /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */ | |
3969 | if (src <= data->temp_fixed_num) { | |
3970 | if (data->have_temp & (1 << (src - 1))) | |
3971 | continue; | |
3972 | data->have_temp |= 1 << (src - 1); | |
3973 | data->have_temp_fixed |= 1 << (src - 1); | |
3974 | data->reg_temp[0][src - 1] = reg_temp_mon[i]; | |
3975 | data->temp_src[src - 1] = src; | |
3976 | continue; | |
3977 | } | |
3978 | ||
3979 | if (s >= NUM_TEMP) | |
3980 | continue; | |
3981 | ||
3982 | /* Use dynamic index for other sources */ | |
3983 | data->have_temp |= 1 << s; | |
3984 | data->reg_temp[0][s] = reg_temp_mon[i]; | |
3985 | data->temp_src[s] = src; | |
3986 | s++; | |
3987 | } | |
3988 | ||
aa136e5d GR |
3989 | #ifdef USE_ALTERNATE |
3990 | /* | |
3991 | * Go through the list of alternate temp registers and enable | |
3992 | * if possible. | |
3993 | * The temperature is already monitored if the respective bit in <mask> | |
3994 | * is set. | |
3995 | */ | |
3996 | for (i = 0; i < data->temp_label_num - 1; i++) { | |
3997 | if (!reg_temp_alternate[i]) | |
3998 | continue; | |
3999 | if (mask & (1 << (i + 1))) | |
4000 | continue; | |
4001 | if (i < data->temp_fixed_num) { | |
4002 | if (data->have_temp & (1 << i)) | |
4003 | continue; | |
4004 | data->have_temp |= 1 << i; | |
4005 | data->have_temp_fixed |= 1 << i; | |
4006 | data->reg_temp[0][i] = reg_temp_alternate[i]; | |
169c05cd GR |
4007 | if (i < num_reg_temp) { |
4008 | data->reg_temp[1][i] = reg_temp_over[i]; | |
4009 | data->reg_temp[2][i] = reg_temp_hyst[i]; | |
4010 | } | |
aa136e5d GR |
4011 | data->temp_src[i] = i + 1; |
4012 | continue; | |
4013 | } | |
4014 | ||
4015 | if (s >= NUM_TEMP) /* Abort if no more space */ | |
4016 | break; | |
4017 | ||
4018 | data->have_temp |= 1 << s; | |
4019 | data->reg_temp[0][s] = reg_temp_alternate[i]; | |
4020 | data->temp_src[s] = i + 1; | |
4021 | s++; | |
4022 | } | |
4023 | #endif /* USE_ALTERNATE */ | |
4024 | ||
9de2e2e8 GR |
4025 | /* Initialize the chip */ |
4026 | nct6775_init_device(data); | |
4027 | ||
9de2e2e8 GR |
4028 | err = superio_enter(sio_data->sioreg); |
4029 | if (err) | |
4030 | return err; | |
4031 | ||
0fc1f8fc GR |
4032 | cr2a = superio_inb(sio_data->sioreg, 0x2a); |
4033 | switch (data->kind) { | |
4034 | case nct6775: | |
f73cf632 | 4035 | data->have_vid = (cr2a & 0x40); |
0fc1f8fc GR |
4036 | break; |
4037 | case nct6776: | |
f73cf632 | 4038 | data->have_vid = (cr2a & 0x60) == 0x40; |
0fc1f8fc | 4039 | break; |
6c009501 | 4040 | case nct6106: |
0fc1f8fc | 4041 | case nct6779: |
578ab5f0 | 4042 | case nct6791: |
8aefb93f | 4043 | case nct6792: |
cd1faefa | 4044 | case nct6793: |
0fc1f8fc GR |
4045 | break; |
4046 | } | |
4047 | ||
9de2e2e8 GR |
4048 | /* |
4049 | * Read VID value | |
4050 | * We can get the VID input values directly at logical device D 0xe3. | |
4051 | */ | |
f73cf632 | 4052 | if (data->have_vid) { |
0fc1f8fc GR |
4053 | superio_select(sio_data->sioreg, NCT6775_LD_VID); |
4054 | data->vid = superio_inb(sio_data->sioreg, 0xe3); | |
4055 | data->vrm = vid_which_vrm(); | |
4056 | } | |
47ece964 GR |
4057 | |
4058 | if (fan_debounce) { | |
4059 | u8 tmp; | |
4060 | ||
4061 | superio_select(sio_data->sioreg, NCT6775_LD_HWM); | |
4062 | tmp = superio_inb(sio_data->sioreg, | |
4063 | NCT6775_REG_CR_FAN_DEBOUNCE); | |
4064 | switch (data->kind) { | |
6c009501 GR |
4065 | case nct6106: |
4066 | tmp |= 0xe0; | |
4067 | break; | |
47ece964 GR |
4068 | case nct6775: |
4069 | tmp |= 0x1e; | |
4070 | break; | |
4071 | case nct6776: | |
4072 | case nct6779: | |
4073 | tmp |= 0x3e; | |
4074 | break; | |
578ab5f0 | 4075 | case nct6791: |
8aefb93f | 4076 | case nct6792: |
cd1faefa | 4077 | case nct6793: |
578ab5f0 DB |
4078 | tmp |= 0x7e; |
4079 | break; | |
47ece964 GR |
4080 | } |
4081 | superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE, | |
4082 | tmp); | |
4083 | dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n", | |
4084 | data->name); | |
4085 | } | |
4086 | ||
df612d5f | 4087 | nct6775_check_fan_inputs(data); |
9de2e2e8 | 4088 | |
f73cf632 | 4089 | superio_exit(sio_data->sioreg); |
1c65dc36 GR |
4090 | |
4091 | /* Read fan clock dividers immediately */ | |
4092 | nct6775_init_fan_common(dev, data); | |
4093 | ||
77eb5b37 | 4094 | /* Register sysfs hooks */ |
f73cf632 GR |
4095 | group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group, |
4096 | data->pwm_num); | |
615fc8cb GR |
4097 | if (IS_ERR(group)) |
4098 | return PTR_ERR(group); | |
4099 | ||
55bdee69 | 4100 | data->groups[num_attr_groups++] = group; |
9de2e2e8 | 4101 | |
f73cf632 GR |
4102 | group = nct6775_create_attr_group(dev, &nct6775_in_template_group, |
4103 | fls(data->have_in)); | |
615fc8cb GR |
4104 | if (IS_ERR(group)) |
4105 | return PTR_ERR(group); | |
4106 | ||
55bdee69 | 4107 | data->groups[num_attr_groups++] = group; |
1c65dc36 | 4108 | |
f73cf632 GR |
4109 | group = nct6775_create_attr_group(dev, &nct6775_fan_template_group, |
4110 | fls(data->has_fan)); | |
615fc8cb GR |
4111 | if (IS_ERR(group)) |
4112 | return PTR_ERR(group); | |
4113 | ||
55bdee69 | 4114 | data->groups[num_attr_groups++] = group; |
aa136e5d | 4115 | |
f73cf632 GR |
4116 | group = nct6775_create_attr_group(dev, &nct6775_temp_template_group, |
4117 | fls(data->have_temp)); | |
615fc8cb GR |
4118 | if (IS_ERR(group)) |
4119 | return PTR_ERR(group); | |
a6bd5878 | 4120 | |
55bdee69 AL |
4121 | data->groups[num_attr_groups++] = group; |
4122 | data->groups[num_attr_groups++] = &nct6775_group_other; | |
9de2e2e8 | 4123 | |
a150d95b GR |
4124 | hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name, |
4125 | data, data->groups); | |
9c09bd8d | 4126 | return PTR_ERR_OR_ZERO(hwmon_dev); |
9de2e2e8 GR |
4127 | } |
4128 | ||
f5776cc3 GR |
4129 | static void nct6791_enable_io_mapping(int sioaddr) |
4130 | { | |
4131 | int val; | |
4132 | ||
4133 | val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE); | |
4134 | if (val & 0x10) { | |
4135 | pr_info("Enabling hardware monitor logical device mappings.\n"); | |
4136 | superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE, | |
4137 | val & ~0x10); | |
4138 | } | |
4139 | } | |
4140 | ||
48e93182 | 4141 | static int __maybe_unused nct6775_suspend(struct device *dev) |
84d19d92 GR |
4142 | { |
4143 | struct nct6775_data *data = nct6775_update_device(dev); | |
84d19d92 GR |
4144 | |
4145 | mutex_lock(&data->update_lock); | |
4146 | data->vbat = nct6775_read_value(data, data->REG_VBAT); | |
df612d5f | 4147 | if (data->kind == nct6775) { |
84d19d92 GR |
4148 | data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1); |
4149 | data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2); | |
4150 | } | |
4151 | mutex_unlock(&data->update_lock); | |
4152 | ||
4153 | return 0; | |
4154 | } | |
4155 | ||
48e93182 | 4156 | static int __maybe_unused nct6775_resume(struct device *dev) |
84d19d92 GR |
4157 | { |
4158 | struct nct6775_data *data = dev_get_drvdata(dev); | |
d2a14ea5 | 4159 | int sioreg = data->sioreg; |
f5776cc3 | 4160 | int i, j, err = 0; |
d2a14ea5 | 4161 | u8 reg; |
84d19d92 GR |
4162 | |
4163 | mutex_lock(&data->update_lock); | |
4164 | data->bank = 0xff; /* Force initial bank selection */ | |
4165 | ||
d2a14ea5 GR |
4166 | err = superio_enter(sioreg); |
4167 | if (err) | |
4168 | goto abort; | |
f5776cc3 | 4169 | |
d2a14ea5 GR |
4170 | superio_select(sioreg, NCT6775_LD_HWM); |
4171 | reg = superio_inb(sioreg, SIO_REG_ENABLE); | |
4172 | if (reg != data->sio_reg_enable) | |
4173 | superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable); | |
4174 | ||
cd1faefa GR |
4175 | if (data->kind == nct6791 || data->kind == nct6792 || |
4176 | data->kind == nct6793) | |
d2a14ea5 GR |
4177 | nct6791_enable_io_mapping(sioreg); |
4178 | ||
4179 | superio_exit(sioreg); | |
f5776cc3 | 4180 | |
84d19d92 GR |
4181 | /* Restore limits */ |
4182 | for (i = 0; i < data->in_num; i++) { | |
4183 | if (!(data->have_in & (1 << i))) | |
4184 | continue; | |
4185 | ||
4186 | nct6775_write_value(data, data->REG_IN_MINMAX[0][i], | |
4187 | data->in[i][1]); | |
4188 | nct6775_write_value(data, data->REG_IN_MINMAX[1][i], | |
4189 | data->in[i][2]); | |
4190 | } | |
4191 | ||
c409fd43 | 4192 | for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) { |
84d19d92 GR |
4193 | if (!(data->has_fan_min & (1 << i))) |
4194 | continue; | |
4195 | ||
4196 | nct6775_write_value(data, data->REG_FAN_MIN[i], | |
4197 | data->fan_min[i]); | |
4198 | } | |
4199 | ||
4200 | for (i = 0; i < NUM_TEMP; i++) { | |
4201 | if (!(data->have_temp & (1 << i))) | |
4202 | continue; | |
4203 | ||
c409fd43 | 4204 | for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++) |
84d19d92 GR |
4205 | if (data->reg_temp[j][i]) |
4206 | nct6775_write_temp(data, data->reg_temp[j][i], | |
4207 | data->temp[j][i]); | |
4208 | } | |
4209 | ||
4210 | /* Restore other settings */ | |
4211 | nct6775_write_value(data, data->REG_VBAT, data->vbat); | |
df612d5f | 4212 | if (data->kind == nct6775) { |
84d19d92 GR |
4213 | nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1); |
4214 | nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2); | |
4215 | } | |
4216 | ||
f5776cc3 | 4217 | abort: |
84d19d92 GR |
4218 | /* Force re-reading all values */ |
4219 | data->valid = false; | |
4220 | mutex_unlock(&data->update_lock); | |
4221 | ||
f5776cc3 | 4222 | return err; |
84d19d92 GR |
4223 | } |
4224 | ||
48e93182 | 4225 | static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume); |
84d19d92 | 4226 | |
9de2e2e8 GR |
4227 | static struct platform_driver nct6775_driver = { |
4228 | .driver = { | |
9de2e2e8 | 4229 | .name = DRVNAME, |
48e93182 | 4230 | .pm = &nct6775_dev_pm_ops, |
9de2e2e8 GR |
4231 | }, |
4232 | .probe = nct6775_probe, | |
9de2e2e8 GR |
4233 | }; |
4234 | ||
4235 | /* nct6775_find() looks for a '627 in the Super-I/O config space */ | |
698a7c24 | 4236 | static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data) |
9de2e2e8 | 4237 | { |
9de2e2e8 | 4238 | u16 val; |
9de2e2e8 | 4239 | int err; |
698a7c24 | 4240 | int addr; |
9de2e2e8 GR |
4241 | |
4242 | err = superio_enter(sioaddr); | |
4243 | if (err) | |
4244 | return err; | |
4245 | ||
fc72af3a GR |
4246 | val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) | |
4247 | superio_inb(sioaddr, SIO_REG_DEVID + 1); | |
4248 | if (force_id && val != 0xffff) | |
9de2e2e8 | 4249 | val = force_id; |
fc72af3a | 4250 | |
9de2e2e8 | 4251 | switch (val & SIO_ID_MASK) { |
6c009501 GR |
4252 | case SIO_NCT6106_ID: |
4253 | sio_data->kind = nct6106; | |
4254 | break; | |
9de2e2e8 GR |
4255 | case SIO_NCT6775_ID: |
4256 | sio_data->kind = nct6775; | |
9de2e2e8 GR |
4257 | break; |
4258 | case SIO_NCT6776_ID: | |
4259 | sio_data->kind = nct6776; | |
9de2e2e8 GR |
4260 | break; |
4261 | case SIO_NCT6779_ID: | |
4262 | sio_data->kind = nct6779; | |
9de2e2e8 | 4263 | break; |
578ab5f0 DB |
4264 | case SIO_NCT6791_ID: |
4265 | sio_data->kind = nct6791; | |
4266 | break; | |
8aefb93f GR |
4267 | case SIO_NCT6792_ID: |
4268 | sio_data->kind = nct6792; | |
4269 | break; | |
cd1faefa GR |
4270 | case SIO_NCT6793_ID: |
4271 | sio_data->kind = nct6793; | |
4272 | break; | |
9de2e2e8 GR |
4273 | default: |
4274 | if (val != 0xffff) | |
4275 | pr_debug("unsupported chip ID: 0x%04x\n", val); | |
4276 | superio_exit(sioaddr); | |
4277 | return -ENODEV; | |
4278 | } | |
4279 | ||
4280 | /* We have a known chip, find the HWM I/O address */ | |
4281 | superio_select(sioaddr, NCT6775_LD_HWM); | |
4282 | val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8) | |
4283 | | superio_inb(sioaddr, SIO_REG_ADDR + 1); | |
698a7c24 GR |
4284 | addr = val & IOREGION_ALIGNMENT; |
4285 | if (addr == 0) { | |
9de2e2e8 GR |
4286 | pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n"); |
4287 | superio_exit(sioaddr); | |
4288 | return -ENODEV; | |
4289 | } | |
4290 | ||
4291 | /* Activate logical device if needed */ | |
4292 | val = superio_inb(sioaddr, SIO_REG_ENABLE); | |
4293 | if (!(val & 0x01)) { | |
4294 | pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n"); | |
4295 | superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01); | |
4296 | } | |
f5776cc3 | 4297 | |
cd1faefa GR |
4298 | if (sio_data->kind == nct6791 || sio_data->kind == nct6792 || |
4299 | sio_data->kind == nct6793) | |
f5776cc3 | 4300 | nct6791_enable_io_mapping(sioaddr); |
9de2e2e8 GR |
4301 | |
4302 | superio_exit(sioaddr); | |
698a7c24 GR |
4303 | pr_info("Found %s or compatible chip at %#x:%#x\n", |
4304 | nct6775_sio_names[sio_data->kind], sioaddr, addr); | |
9de2e2e8 GR |
4305 | sio_data->sioreg = sioaddr; |
4306 | ||
698a7c24 | 4307 | return addr; |
9de2e2e8 GR |
4308 | } |
4309 | ||
4310 | /* | |
4311 | * when Super-I/O functions move to a separate file, the Super-I/O | |
4312 | * bus will manage the lifetime of the device and this module will only keep | |
615fc8cb | 4313 | * track of the nct6775 driver. But since we use platform_device_alloc(), we |
9de2e2e8 GR |
4314 | * must keep track of the device |
4315 | */ | |
698a7c24 | 4316 | static struct platform_device *pdev[2]; |
9de2e2e8 GR |
4317 | |
4318 | static int __init sensors_nct6775_init(void) | |
4319 | { | |
698a7c24 GR |
4320 | int i, err; |
4321 | bool found = false; | |
4322 | int address; | |
9de2e2e8 GR |
4323 | struct resource res; |
4324 | struct nct6775_sio_data sio_data; | |
698a7c24 GR |
4325 | int sioaddr[2] = { 0x2e, 0x4e }; |
4326 | ||
4327 | err = platform_driver_register(&nct6775_driver); | |
4328 | if (err) | |
4329 | return err; | |
9de2e2e8 GR |
4330 | |
4331 | /* | |
4332 | * initialize sio_data->kind and sio_data->sioreg. | |
4333 | * | |
4334 | * when Super-I/O functions move to a separate file, the Super-I/O | |
4335 | * driver will probe 0x2e and 0x4e and auto-detect the presence of a | |
4336 | * nct6775 hardware monitor, and call probe() | |
4337 | */ | |
698a7c24 GR |
4338 | for (i = 0; i < ARRAY_SIZE(pdev); i++) { |
4339 | address = nct6775_find(sioaddr[i], &sio_data); | |
4340 | if (address <= 0) | |
4341 | continue; | |
9de2e2e8 | 4342 | |
698a7c24 | 4343 | found = true; |
9de2e2e8 | 4344 | |
698a7c24 GR |
4345 | pdev[i] = platform_device_alloc(DRVNAME, address); |
4346 | if (!pdev[i]) { | |
4347 | err = -ENOMEM; | |
9d311edd | 4348 | goto exit_device_unregister; |
698a7c24 | 4349 | } |
9de2e2e8 | 4350 | |
698a7c24 GR |
4351 | err = platform_device_add_data(pdev[i], &sio_data, |
4352 | sizeof(struct nct6775_sio_data)); | |
4353 | if (err) | |
4354 | goto exit_device_put; | |
4355 | ||
4356 | memset(&res, 0, sizeof(res)); | |
4357 | res.name = DRVNAME; | |
4358 | res.start = address + IOREGION_OFFSET; | |
4359 | res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1; | |
4360 | res.flags = IORESOURCE_IO; | |
4361 | ||
4362 | err = acpi_check_resource_conflict(&res); | |
4363 | if (err) { | |
4364 | platform_device_put(pdev[i]); | |
4365 | pdev[i] = NULL; | |
4366 | continue; | |
4367 | } | |
9de2e2e8 | 4368 | |
698a7c24 GR |
4369 | err = platform_device_add_resources(pdev[i], &res, 1); |
4370 | if (err) | |
4371 | goto exit_device_put; | |
9de2e2e8 | 4372 | |
698a7c24 GR |
4373 | /* platform_device_add calls probe() */ |
4374 | err = platform_device_add(pdev[i]); | |
4375 | if (err) | |
4376 | goto exit_device_put; | |
9de2e2e8 | 4377 | } |
698a7c24 GR |
4378 | if (!found) { |
4379 | err = -ENODEV; | |
4380 | goto exit_unregister; | |
9de2e2e8 GR |
4381 | } |
4382 | ||
4383 | return 0; | |
4384 | ||
4385 | exit_device_put: | |
9d311edd AL |
4386 | platform_device_put(pdev[i]); |
4387 | exit_device_unregister: | |
4388 | while (--i >= 0) { | |
698a7c24 | 4389 | if (pdev[i]) |
9d311edd | 4390 | platform_device_unregister(pdev[i]); |
698a7c24 | 4391 | } |
9de2e2e8 GR |
4392 | exit_unregister: |
4393 | platform_driver_unregister(&nct6775_driver); | |
9de2e2e8 GR |
4394 | return err; |
4395 | } | |
4396 | ||
4397 | static void __exit sensors_nct6775_exit(void) | |
4398 | { | |
698a7c24 GR |
4399 | int i; |
4400 | ||
4401 | for (i = 0; i < ARRAY_SIZE(pdev); i++) { | |
4402 | if (pdev[i]) | |
4403 | platform_device_unregister(pdev[i]); | |
4404 | } | |
9de2e2e8 GR |
4405 | platform_driver_unregister(&nct6775_driver); |
4406 | } | |
4407 | ||
4408 | MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>"); | |
cd1faefa | 4409 | MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips"); |
9de2e2e8 GR |
4410 | MODULE_LICENSE("GPL"); |
4411 | ||
4412 | module_init(sensors_nct6775_init); | |
4413 | module_exit(sensors_nct6775_exit); |