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16216333 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
29fa06c1 RM |
2 | /* |
3 | * k8temp.c - Linux kernel module for hardware monitoring | |
4 | * | |
7188cc66 | 5 | * Copyright (C) 2006 Rudolf Marek <r.marek@assembler.cz> |
29fa06c1 RM |
6 | * |
7 | * Inspired from the w83785 and amd756 drivers. | |
29fa06c1 RM |
8 | */ |
9 | ||
10 | #include <linux/module.h> | |
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11 | #include <linux/init.h> |
12 | #include <linux/slab.h> | |
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13 | #include <linux/pci.h> |
14 | #include <linux/hwmon.h> | |
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15 | #include <linux/err.h> |
16 | #include <linux/mutex.h> | |
bb9a35f2 | 17 | #include <asm/processor.h> |
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18 | |
19 | #define TEMP_FROM_REG(val) (((((val) >> 16) & 0xff) - 49) * 1000) | |
20 | #define REG_TEMP 0xe4 | |
21 | #define SEL_PLACE 0x40 | |
22 | #define SEL_CORE 0x04 | |
23 | ||
24 | struct k8temp_data { | |
29fa06c1 | 25 | struct mutex update_lock; |
29fa06c1 RM |
26 | |
27 | /* registers values */ | |
93092a64 | 28 | u8 sensorsp; /* sensor presence bits - SEL_CORE, SEL_PLACE */ |
a2e066bb | 29 | u8 swap_core_select; /* meaning of SEL_CORE is inverted */ |
76ff08da | 30 | u32 temp_offset; |
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31 | }; |
32 | ||
cd9bb056 | 33 | static const struct pci_device_id k8temp_ids[] = { |
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34 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) }, |
35 | { 0 }, | |
36 | }; | |
b17ebc94 JD |
37 | MODULE_DEVICE_TABLE(pci, k8temp_ids); |
38 | ||
6c931ae1 | 39 | static int is_rev_g_desktop(u8 model) |
a05e93f3 AH |
40 | { |
41 | u32 brandidx; | |
42 | ||
43 | if (model < 0x69) | |
44 | return 0; | |
45 | ||
46 | if (model == 0xc1 || model == 0x6c || model == 0x7c) | |
47 | return 0; | |
48 | ||
49 | /* | |
50 | * Differentiate between AM2 and ASB1. | |
51 | * See "Constructing the processor Name String" in "Revision | |
52 | * Guide for AMD NPT Family 0Fh Processors" (33610). | |
53 | */ | |
54 | brandidx = cpuid_ebx(0x80000001); | |
55 | brandidx = (brandidx >> 9) & 0x1f; | |
56 | ||
57 | /* Single core */ | |
58 | if ((model == 0x6f || model == 0x7f) && | |
59 | (brandidx == 0x7 || brandidx == 0x9 || brandidx == 0xc)) | |
60 | return 0; | |
61 | ||
62 | /* Dual core */ | |
63 | if (model == 0x6b && | |
64 | (brandidx == 0xb || brandidx == 0xc)) | |
65 | return 0; | |
66 | ||
67 | return 1; | |
68 | } | |
69 | ||
3b07a702 RK |
70 | static umode_t |
71 | k8temp_is_visible(const void *drvdata, enum hwmon_sensor_types type, | |
72 | u32 attr, int channel) | |
73 | { | |
74 | const struct k8temp_data *data = drvdata; | |
75 | ||
76 | if ((channel & 1) && !(data->sensorsp & SEL_PLACE)) | |
77 | return 0; | |
78 | ||
79 | if ((channel & 2) && !(data->sensorsp & SEL_CORE)) | |
80 | return 0; | |
81 | ||
82 | return 0444; | |
83 | } | |
84 | ||
85 | static int | |
86 | k8temp_read(struct device *dev, enum hwmon_sensor_types type, | |
87 | u32 attr, int channel, long *val) | |
88 | { | |
89 | struct k8temp_data *data = dev_get_drvdata(dev); | |
90 | struct pci_dev *pdev = to_pci_dev(dev->parent); | |
91 | int core, place; | |
92 | u32 temp; | |
93 | u8 tmp; | |
94 | ||
95 | core = (channel >> 1) & 1; | |
96 | place = channel & 1; | |
97 | ||
98 | core ^= data->swap_core_select; | |
99 | ||
100 | mutex_lock(&data->update_lock); | |
101 | pci_read_config_byte(pdev, REG_TEMP, &tmp); | |
102 | tmp &= ~(SEL_PLACE | SEL_CORE); | |
103 | if (core) | |
104 | tmp |= SEL_CORE; | |
105 | if (place) | |
106 | tmp |= SEL_PLACE; | |
107 | pci_write_config_byte(pdev, REG_TEMP, tmp); | |
108 | pci_read_config_dword(pdev, REG_TEMP, &temp); | |
109 | mutex_unlock(&data->update_lock); | |
110 | ||
111 | *val = TEMP_FROM_REG(temp) + data->temp_offset; | |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
116 | static const struct hwmon_ops k8temp_ops = { | |
117 | .is_visible = k8temp_is_visible, | |
118 | .read = k8temp_read, | |
119 | }; | |
120 | ||
55f44663 | 121 | static const struct hwmon_channel_info * const k8temp_info[] = { |
3b07a702 RK |
122 | HWMON_CHANNEL_INFO(temp, |
123 | HWMON_T_INPUT, HWMON_T_INPUT, HWMON_T_INPUT, HWMON_T_INPUT), | |
124 | NULL | |
125 | }; | |
126 | ||
127 | static const struct hwmon_chip_info k8temp_chip_info = { | |
128 | .ops = &k8temp_ops, | |
129 | .info = k8temp_info, | |
130 | }; | |
131 | ||
6c931ae1 | 132 | static int k8temp_probe(struct pci_dev *pdev, |
29fa06c1 RM |
133 | const struct pci_device_id *id) |
134 | { | |
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135 | u8 scfg; |
136 | u32 temp; | |
bb9a35f2 | 137 | u8 model, stepping; |
29fa06c1 | 138 | struct k8temp_data *data; |
3b07a702 | 139 | struct device *hwmon_dev; |
29fa06c1 | 140 | |
a0d44cbc GR |
141 | data = devm_kzalloc(&pdev->dev, sizeof(struct k8temp_data), GFP_KERNEL); |
142 | if (!data) | |
143 | return -ENOMEM; | |
29fa06c1 | 144 | |
bb9a35f2 | 145 | model = boot_cpu_data.x86_model; |
b399151c | 146 | stepping = boot_cpu_data.x86_stepping; |
bb9a35f2 | 147 | |
628b4504 | 148 | /* feature available since SH-C0, exclude older revisions */ |
a0d44cbc GR |
149 | if ((model == 4 && stepping == 0) || |
150 | (model == 5 && stepping <= 1)) | |
151 | return -ENODEV; | |
76ff08da | 152 | |
628b4504 AH |
153 | /* |
154 | * AMD NPT family 0fh, i.e. RevF and RevG: | |
155 | * meaning of SEL_CORE bit is inverted | |
156 | */ | |
157 | if (model >= 0x40) { | |
158 | data->swap_core_select = 1; | |
b55f3757 GR |
159 | dev_warn(&pdev->dev, |
160 | "Temperature readouts might be wrong - check erratum #141\n"); | |
bb9a35f2 AH |
161 | } |
162 | ||
628b4504 AH |
163 | /* |
164 | * RevG desktop CPUs (i.e. no socket S1G1 or ASB1 parts) need | |
165 | * additional offset, otherwise reported temperature is below | |
166 | * ambient temperature | |
167 | */ | |
168 | if (is_rev_g_desktop(model)) | |
169 | data->temp_offset = 21000; | |
170 | ||
29fa06c1 | 171 | pci_read_config_byte(pdev, REG_TEMP, &scfg); |
93092a64 | 172 | scfg &= ~(SEL_PLACE | SEL_CORE); /* Select sensor 0, core0 */ |
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173 | pci_write_config_byte(pdev, REG_TEMP, scfg); |
174 | pci_read_config_byte(pdev, REG_TEMP, &scfg); | |
175 | ||
176 | if (scfg & (SEL_PLACE | SEL_CORE)) { | |
177 | dev_err(&pdev->dev, "Configuration bit(s) stuck at 1!\n"); | |
a0d44cbc | 178 | return -ENODEV; |
29fa06c1 RM |
179 | } |
180 | ||
181 | scfg |= (SEL_PLACE | SEL_CORE); | |
182 | pci_write_config_byte(pdev, REG_TEMP, scfg); | |
183 | ||
184 | /* now we know if we can change core and/or sensor */ | |
185 | pci_read_config_byte(pdev, REG_TEMP, &data->sensorsp); | |
186 | ||
187 | if (data->sensorsp & SEL_PLACE) { | |
188 | scfg &= ~SEL_CORE; /* Select sensor 1, core0 */ | |
189 | pci_write_config_byte(pdev, REG_TEMP, scfg); | |
190 | pci_read_config_dword(pdev, REG_TEMP, &temp); | |
191 | scfg |= SEL_CORE; /* prepare for next selection */ | |
93092a64 | 192 | if (!((temp >> 16) & 0xff)) /* if temp is 0 -49C is unlikely */ |
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193 | data->sensorsp &= ~SEL_PLACE; |
194 | } | |
195 | ||
196 | if (data->sensorsp & SEL_CORE) { | |
197 | scfg &= ~SEL_PLACE; /* Select sensor 0, core1 */ | |
198 | pci_write_config_byte(pdev, REG_TEMP, scfg); | |
199 | pci_read_config_dword(pdev, REG_TEMP, &temp); | |
93092a64 | 200 | if (!((temp >> 16) & 0xff)) /* if temp is 0 -49C is unlikely */ |
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201 | data->sensorsp &= ~SEL_CORE; |
202 | } | |
203 | ||
29fa06c1 | 204 | mutex_init(&data->update_lock); |
29fa06c1 | 205 | |
3b07a702 RK |
206 | hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, |
207 | "k8temp", | |
208 | data, | |
209 | &k8temp_chip_info, | |
210 | NULL); | |
29fa06c1 | 211 | |
3b07a702 | 212 | return PTR_ERR_OR_ZERO(hwmon_dev); |
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213 | } |
214 | ||
215 | static struct pci_driver k8temp_driver = { | |
216 | .name = "k8temp", | |
217 | .id_table = k8temp_ids, | |
218 | .probe = k8temp_probe, | |
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219 | }; |
220 | ||
f71f5a55 | 221 | module_pci_driver(k8temp_driver); |
29fa06c1 | 222 | |
7188cc66 | 223 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); |
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224 | MODULE_DESCRIPTION("AMD K8 core temperature monitor"); |
225 | MODULE_LICENSE("GPL"); |