[linux-2.6-block.git] / drivers / hwmon / k10temp.c

/*
 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
 *
 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
 *
 *
 * This driver is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <asm/processor.h>

MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_LICENSE("GPL");

static bool force;
module_param(force, bool, 0444);
MODULE_PARM_DESC(force, "force loading on processors with erratum 319");

/* Provide lock for writing to NB_SMU_IND_ADDR */
static DEFINE_MUTEX(nb_smu_ind_mutex);

/* CPUID function 0x80000001, ebx */
#define CPUID_PKGTYPE_MASK	0xf0000000
#define CPUID_PKGTYPE_F		0x00000000
#define CPUID_PKGTYPE_AM2R2_AM3	0x10000000

/* DRAM controller (PCI function 2) */
#define REG_DCT0_CONFIG_HIGH		0x094
#define  DDR3_MODE			0x00000100

/* miscellaneous (PCI function 3) */
#define REG_HARDWARE_THERMAL_CONTROL	0x64
#define  HTC_ENABLE			0x00000001

#define REG_REPORTED_TEMPERATURE	0xa4

#define REG_NORTHBRIDGE_CAPABILITIES	0xe8
#define  NB_CAP_HTC			0x00000400

/*
 * For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
 * has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
 * Control]
 */
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET	0xd8200ca4
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F3	0x1573

static void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
				  int offset, u32 *val)
{
	mutex_lock(&nb_smu_ind_mutex);
	pci_bus_write_config_dword(pdev->bus, devfn,
				   0xb8, offset);
	pci_bus_read_config_dword(pdev->bus, devfn,
				  0xbc, val);
	mutex_unlock(&nb_smu_ind_mutex);
}

static ssize_t show_temp(struct device *dev,
			 struct device_attribute *attr, char *buf)
{
	u32 regval;
	struct pci_dev *pdev = to_pci_dev(dev);

	if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
		amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
				      F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
				      &regval);
	} else {
		pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
	}
	return sprintf(buf, "%u\n", (regval >> 21) * 125);
}

static ssize_t show_temp_max(struct device *dev,
			     struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "%d\n", 70 * 1000);
}

static ssize_t show_temp_crit(struct device *dev,
			      struct device_attribute *devattr, char *buf)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	int show_hyst = attr->index;
	u32 regval;
	int value;

	pci_read_config_dword(to_pci_dev(dev),
			      REG_HARDWARE_THERMAL_CONTROL, &regval);
	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	if (show_hyst)
		value -= ((regval >> 24) & 0xf) * 500;
	return sprintf(buf, "%d\n", value);
}

static ssize_t show_name(struct device *dev,
			 struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "k10temp\n");
}

static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL);
static DEVICE_ATTR(temp1_max, S_IRUGO, show_temp_max, NULL);
static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);

static bool has_erratum_319(struct pci_dev *pdev)
{
	u32 pkg_type, reg_dram_cfg;

	if (boot_cpu_data.x86 != 0x10)
		return false;

	/*
	 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
	 *              may be unreliable.
	 */
	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	if (pkg_type == CPUID_PKGTYPE_F)
		return true;
	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
		return false;

	/* DDR3 memory implies socket AM3, which is good */
	pci_bus_read_config_dword(pdev->bus,
				  PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
				  REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
	if (reg_dram_cfg & DDR3_MODE)
		return false;

	/*
	 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
	 * memory. We blacklist all the cores which do exist in socket AM2+
	 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	 * and AM3 formats, but that's the best we can do.
	 */
	return boot_cpu_data.x86_model < 4 ||
	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
}

static int k10temp_probe(struct pci_dev *pdev,
				   const struct pci_device_id *id)
{
	struct device *hwmon_dev;
	u32 reg_caps, reg_htc;
	int unreliable = has_erratum_319(pdev);
	int err;

	if (unreliable && !force) {
		dev_err(&pdev->dev,
			"unreliable CPU thermal sensor; monitoring disabled\n");
		err = -ENODEV;
		goto exit;
	}

	err = device_create_file(&pdev->dev, &dev_attr_temp1_input);
	if (err)
		goto exit;
	err = device_create_file(&pdev->dev, &dev_attr_temp1_max);
	if (err)
		goto exit_remove;

	pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES, &reg_caps);
	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, &reg_htc);
	if ((reg_caps & NB_CAP_HTC) && (reg_htc & HTC_ENABLE)) {
		err = device_create_file(&pdev->dev,
				&sensor_dev_attr_temp1_crit.dev_attr);
		if (err)
			goto exit_remove;
		err = device_create_file(&pdev->dev,
				&sensor_dev_attr_temp1_crit_hyst.dev_attr);
		if (err)
			goto exit_remove;
	}

	err = device_create_file(&pdev->dev, &dev_attr_name);
	if (err)
		goto exit_remove;

	hwmon_dev = hwmon_device_register(&pdev->dev);
	if (IS_ERR(hwmon_dev)) {
		err = PTR_ERR(hwmon_dev);
		goto exit_remove;
	}
	pci_set_drvdata(pdev, hwmon_dev);

	if (unreliable && force)
		dev_warn(&pdev->dev,
			 "unreliable CPU thermal sensor; check erratum 319\n");
	return 0;

exit_remove:
	device_remove_file(&pdev->dev, &dev_attr_name);
	device_remove_file(&pdev->dev, &dev_attr_temp1_input);
	device_remove_file(&pdev->dev, &dev_attr_temp1_max);
	device_remove_file(&pdev->dev,
			   &sensor_dev_attr_temp1_crit.dev_attr);
	device_remove_file(&pdev->dev,
			   &sensor_dev_attr_temp1_crit_hyst.dev_attr);
exit:
	return err;
}

static void k10temp_remove(struct pci_dev *pdev)
{
	hwmon_device_unregister(pci_get_drvdata(pdev));
	device_remove_file(&pdev->dev, &dev_attr_name);
	device_remove_file(&pdev->dev, &dev_attr_temp1_input);
	device_remove_file(&pdev->dev, &dev_attr_temp1_max);
	device_remove_file(&pdev->dev,
			   &sensor_dev_attr_temp1_crit.dev_attr);
	device_remove_file(&pdev->dev,
			   &sensor_dev_attr_temp1_crit_hyst.dev_attr);
}

static const struct pci_device_id k10temp_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);

static struct pci_driver k10temp_driver = {
	.name = "k10temp",
	.id_table = k10temp_id_table,
	.probe = k10temp_probe,
	.remove = k10temp_remove,
};

module_pci_driver(k10temp_driver);
Commit	Line	Data
3c57e89b	1	/*
30b146d1	2	* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
3c57e89b CL	3	*
	4	* Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
	5	*
	6	*
	7	* This driver is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This driver is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	14	* See the GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this driver; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/err.h>
	21	#include <linux/hwmon.h>
	22	#include <linux/hwmon-sysfs.h>
	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/pci.h>
	26	#include <asm/processor.h>
	27
9e581311	28	MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
3c57e89b CL	29	MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
	30	MODULE_LICENSE("GPL");
	31
	32	static bool force;
	33	module_param(force, bool, 0444);
	34	MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
	35
f89ce270 AG	36	/* Provide lock for writing to NB_SMU_IND_ADDR */
	37	static DEFINE_MUTEX(nb_smu_ind_mutex);
	38
c5114a1c CL	39	/* CPUID function 0x80000001, ebx */
	40	#define CPUID_PKGTYPE_MASK 0xf0000000
	41	#define CPUID_PKGTYPE_F 0x00000000
	42	#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
	43
	44	/* DRAM controller (PCI function 2) */
	45	#define REG_DCT0_CONFIG_HIGH 0x094
	46	#define DDR3_MODE 0x00000100
	47
	48	/* miscellaneous (PCI function 3) */
3c57e89b CL	49	#define REG_HARDWARE_THERMAL_CONTROL 0x64
	50	#define HTC_ENABLE 0x00000001
	51
	52	#define REG_REPORTED_TEMPERATURE 0xa4
	53
	54	#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
	55	#define NB_CAP_HTC 0x00000400
	56
f89ce270 AG	57	/*
	58	* For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
	59	* has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
	60	* Control]
	61	*/
	62	#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
	63	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F3 0x1573
	64
	65	static void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
	66	int offset, u32 *val)
	67	{
	68	mutex_lock(&nb_smu_ind_mutex);
	69	pci_bus_write_config_dword(pdev->bus, devfn,
	70	0xb8, offset);
	71	pci_bus_read_config_dword(pdev->bus, devfn,
	72	0xbc, val);
	73	mutex_unlock(&nb_smu_ind_mutex);
	74	}
	75
3c57e89b CL	76	static ssize_t show_temp(struct device *dev,
	77	struct device_attribute attr, char buf)
	78	{
	79	u32 regval;
f89ce270 AG	80	struct pci_dev *pdev = to_pci_dev(dev);
	81
	82	if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
	83	amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
	84	F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
	85	&regval);
	86	} else {
	87	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
	88	}
3c57e89b CL	89	return sprintf(buf, "%u\n", (regval >> 21) * 125);
	90	}
	91
	92	static ssize_t show_temp_max(struct device *dev,
	93	struct device_attribute attr, char buf)
	94	{
	95	return sprintf(buf, "%d\n", 70 * 1000);
	96	}
	97
	98	static ssize_t show_temp_crit(struct device *dev,
	99	struct device_attribute devattr, char buf)
	100	{
	101	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	102	int show_hyst = attr->index;
	103	u32 regval;
	104	int value;
	105
	106	pci_read_config_dword(to_pci_dev(dev),
	107	REG_HARDWARE_THERMAL_CONTROL, &regval);
	108	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	109	if (show_hyst)
	110	value -= ((regval >> 24) & 0xf) * 500;
	111	return sprintf(buf, "%d\n", value);
	112	}
	113
	114	static ssize_t show_name(struct device *dev,
	115	struct device_attribute attr, char buf)
	116	{
	117	return sprintf(buf, "k10temp\n");
	118	}
	119
	120	static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL);
	121	static DEVICE_ATTR(temp1_max, S_IRUGO, show_temp_max, NULL);
	122	static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
	123	static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
	124	static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
	125
6c931ae1	126	static bool has_erratum_319(struct pci_dev *pdev)
3c57e89b	127	{
c5114a1c CL	128	u32 pkg_type, reg_dram_cfg;
	129
	130	if (boot_cpu_data.x86 != 0x10)
	131	return false;
	132
3c57e89b	133	/*
c5114a1c CL	134	* Erratum 319: The thermal sensor of Socket F/AM2+ processors
c5114a1c CL	135	* may be unreliable.
3c57e89b	136	*/
c5114a1c CL	137	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	138	if (pkg_type == CPUID_PKGTYPE_F)
	139	return true;
	140	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
	141	return false;
	142
eefc2d9e	143	/* DDR3 memory implies socket AM3, which is good */
c5114a1c CL	144	pci_bus_read_config_dword(pdev->bus,
	145	PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
	146	REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
eefc2d9e JD	147	if (reg_dram_cfg & DDR3_MODE)
	148	return false;
	149
	150	/*
	151	* Unfortunately it is possible to run a socket AM3 CPU with DDR2
	152	* memory. We blacklist all the cores which do exist in socket AM2+
	153	* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	154	* and AM3 formats, but that's the best we can do.
	155	*/
	156	return boot_cpu_data.x86_model < 4 \|\|
	157	(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
3c57e89b CL	158	}
3c57e89b CL	159
6c931ae1	160	static int k10temp_probe(struct pci_dev *pdev,
3c57e89b CL	161	const struct pci_device_id *id)
	162	{
	163	struct device *hwmon_dev;
	164	u32 reg_caps, reg_htc;
c5114a1c	165	int unreliable = has_erratum_319(pdev);
3c57e89b CL	166	int err;
3c57e89b CL	167
c5114a1c	168	if (unreliable && !force) {
3c57e89b CL	169	dev_err(&pdev->dev,
	170	"unreliable CPU thermal sensor; monitoring disabled\n");
	171	err = -ENODEV;
	172	goto exit;
	173	}
	174
	175	err = device_create_file(&pdev->dev, &dev_attr_temp1_input);
	176	if (err)
	177	goto exit;
	178	err = device_create_file(&pdev->dev, &dev_attr_temp1_max);
	179	if (err)
	180	goto exit_remove;
	181
	182	pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES, &reg_caps);
	183	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, &reg_htc);
	184	if ((reg_caps & NB_CAP_HTC) && (reg_htc & HTC_ENABLE)) {
	185	err = device_create_file(&pdev->dev,
	186	&sensor_dev_attr_temp1_crit.dev_attr);
	187	if (err)
	188	goto exit_remove;
	189	err = device_create_file(&pdev->dev,
	190	&sensor_dev_attr_temp1_crit_hyst.dev_attr);
	191	if (err)
	192	goto exit_remove;
	193	}
	194
	195	err = device_create_file(&pdev->dev, &dev_attr_name);
	196	if (err)
	197	goto exit_remove;
	198
	199	hwmon_dev = hwmon_device_register(&pdev->dev);
	200	if (IS_ERR(hwmon_dev)) {
	201	err = PTR_ERR(hwmon_dev);
	202	goto exit_remove;
	203	}
95de3b25	204	pci_set_drvdata(pdev, hwmon_dev);
3c57e89b	205
c5114a1c	206	if (unreliable && force)
3c57e89b CL	207	dev_warn(&pdev->dev,
	208	"unreliable CPU thermal sensor; check erratum 319\n");
	209	return 0;
	210
	211	exit_remove:
	212	device_remove_file(&pdev->dev, &dev_attr_name);
	213	device_remove_file(&pdev->dev, &dev_attr_temp1_input);
	214	device_remove_file(&pdev->dev, &dev_attr_temp1_max);
	215	device_remove_file(&pdev->dev,
	216	&sensor_dev_attr_temp1_crit.dev_attr);
	217	device_remove_file(&pdev->dev,
	218	&sensor_dev_attr_temp1_crit_hyst.dev_attr);
	219	exit:
	220	return err;
	221	}
	222
281dfd0b	223	static void k10temp_remove(struct pci_dev *pdev)
3c57e89b	224	{
95de3b25	225	hwmon_device_unregister(pci_get_drvdata(pdev));
3c57e89b CL	226	device_remove_file(&pdev->dev, &dev_attr_name);
	227	device_remove_file(&pdev->dev, &dev_attr_temp1_input);
	228	device_remove_file(&pdev->dev, &dev_attr_temp1_max);
	229	device_remove_file(&pdev->dev,
	230	&sensor_dev_attr_temp1_crit.dev_attr);
	231	device_remove_file(&pdev->dev,
	232	&sensor_dev_attr_temp1_crit_hyst.dev_attr);
3c57e89b CL	233	}
3c57e89b CL	234
cd9bb056	235	static const struct pci_device_id k10temp_id_table[] = {
3c57e89b CL	236	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
3c57e89b CL	237	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
aa4790a6	238	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
9e581311	239	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	240	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
d303b1b5	241	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
f89ce270	242	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
30b146d1	243	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
ec015950	244	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
3c57e89b CL	245	{}
	246	};
	247	MODULE_DEVICE_TABLE(pci, k10temp_id_table);
	248
	249	static struct pci_driver k10temp_driver = {
	250	.name = "k10temp",
	251	.id_table = k10temp_id_table,
	252	.probe = k10temp_probe,
9e5e9b7a	253	.remove = k10temp_remove,
3c57e89b CL	254	};
3c57e89b CL	255
f71f5a55	256	module_pci_driver(k10temp_driver);