[linux-2.6-block.git] / drivers / hwmon / k10temp.c

/*
 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
 *
 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
 *
 *
 * This driver is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <asm/processor.h>

MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_LICENSE("GPL");

static bool force;
module_param(force, bool, 0444);
MODULE_PARM_DESC(force, "force loading on processors with erratum 319");

/* Provide lock for writing to NB_SMU_IND_ADDR */
static DEFINE_MUTEX(nb_smu_ind_mutex);

/* CPUID function 0x80000001, ebx */
#define CPUID_PKGTYPE_MASK	0xf0000000
#define CPUID_PKGTYPE_F		0x00000000
#define CPUID_PKGTYPE_AM2R2_AM3	0x10000000

/* DRAM controller (PCI function 2) */
#define REG_DCT0_CONFIG_HIGH		0x094
#define  DDR3_MODE			0x00000100

/* miscellaneous (PCI function 3) */
#define REG_HARDWARE_THERMAL_CONTROL	0x64
#define  HTC_ENABLE			0x00000001

#define REG_REPORTED_TEMPERATURE	0xa4

#define REG_NORTHBRIDGE_CAPABILITIES	0xe8
#define  NB_CAP_HTC			0x00000400

/*
 * For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
 * has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
 * Control]
 */
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET	0xd8200ca4
#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F3	0x1573

static void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
				  int offset, u32 *val)
{
	mutex_lock(&nb_smu_ind_mutex);
	pci_bus_write_config_dword(pdev->bus, devfn,
				   0xb8, offset);
	pci_bus_read_config_dword(pdev->bus, devfn,
				  0xbc, val);
	mutex_unlock(&nb_smu_ind_mutex);
}

static ssize_t show_temp(struct device *dev,
			 struct device_attribute *attr, char *buf)
{
	u32 regval;
	struct pci_dev *pdev = dev_get_drvdata(dev);

	if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
		amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
				      F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
				      &regval);
	} else {
		pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
	}
	return sprintf(buf, "%u\n", (regval >> 21) * 125);
}

static ssize_t show_temp_max(struct device *dev,
			     struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "%d\n", 70 * 1000);
}

static ssize_t show_temp_crit(struct device *dev,
			      struct device_attribute *devattr, char *buf)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	int show_hyst = attr->index;
	u32 regval;
	int value;

	pci_read_config_dword(dev_get_drvdata(dev),
			      REG_HARDWARE_THERMAL_CONTROL, &regval);
	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	if (show_hyst)
		value -= ((regval >> 24) & 0xf) * 500;
	return sprintf(buf, "%d\n", value);
}

static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL);
static DEVICE_ATTR(temp1_max, S_IRUGO, show_temp_max, NULL);
static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);

static umode_t k10temp_is_visible(struct kobject *kobj,
				  struct attribute *attr, int index)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct pci_dev *pdev = dev_get_drvdata(dev);

	if (index >= 2) {
		u32 reg_caps, reg_htc;

		pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
				      &reg_caps);
		pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
				      &reg_htc);
		if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE))
			return 0;
	}
	return attr->mode;
}

static struct attribute *k10temp_attrs[] = {
	&dev_attr_temp1_input.attr,
	&dev_attr_temp1_max.attr,
	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
	NULL
};

static const struct attribute_group k10temp_group = {
	.attrs = k10temp_attrs,
	.is_visible = k10temp_is_visible,
};
__ATTRIBUTE_GROUPS(k10temp);

static bool has_erratum_319(struct pci_dev *pdev)
{
	u32 pkg_type, reg_dram_cfg;

	if (boot_cpu_data.x86 != 0x10)
		return false;

	/*
	 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
	 *              may be unreliable.
	 */
	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	if (pkg_type == CPUID_PKGTYPE_F)
		return true;
	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
		return false;

	/* DDR3 memory implies socket AM3, which is good */
	pci_bus_read_config_dword(pdev->bus,
				  PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
				  REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
	if (reg_dram_cfg & DDR3_MODE)
		return false;

	/*
	 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
	 * memory. We blacklist all the cores which do exist in socket AM2+
	 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	 * and AM3 formats, but that's the best we can do.
	 */
	return boot_cpu_data.x86_model < 4 ||
	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
}

static int k10temp_probe(struct pci_dev *pdev,
				   const struct pci_device_id *id)
{
	int unreliable = has_erratum_319(pdev);
	struct device *dev = &pdev->dev;
	struct device *hwmon_dev;

	if (unreliable) {
		if (!force) {
			dev_err(dev,
				"unreliable CPU thermal sensor; monitoring disabled\n");
			return -ENODEV;
		}
		dev_warn(dev,
			 "unreliable CPU thermal sensor; check erratum 319\n");
	}

	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", pdev,
							   k10temp_groups);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static const struct pci_device_id k10temp_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);

static struct pci_driver k10temp_driver = {
	.name = "k10temp",
	.id_table = k10temp_id_table,
	.probe = k10temp_probe,
};

module_pci_driver(k10temp_driver);
Commit	Line	Data
3c57e89b	1	/*
30b146d1	2	* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
3c57e89b CL	3	*
	4	* Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
	5	*
	6	*
	7	* This driver is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This driver is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	14	* See the GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this driver; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/err.h>
	21	#include <linux/hwmon.h>
	22	#include <linux/hwmon-sysfs.h>
	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/pci.h>
	26	#include <asm/processor.h>
	27
9e581311	28	MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
3c57e89b CL	29	MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
	30	MODULE_LICENSE("GPL");
	31
	32	static bool force;
	33	module_param(force, bool, 0444);
	34	MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
	35
f89ce270 AG	36	/* Provide lock for writing to NB_SMU_IND_ADDR */
	37	static DEFINE_MUTEX(nb_smu_ind_mutex);
	38
c5114a1c CL	39	/* CPUID function 0x80000001, ebx */
	40	#define CPUID_PKGTYPE_MASK 0xf0000000
	41	#define CPUID_PKGTYPE_F 0x00000000
	42	#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
	43
	44	/* DRAM controller (PCI function 2) */
	45	#define REG_DCT0_CONFIG_HIGH 0x094
	46	#define DDR3_MODE 0x00000100
	47
	48	/* miscellaneous (PCI function 3) */
3c57e89b CL	49	#define REG_HARDWARE_THERMAL_CONTROL 0x64
	50	#define HTC_ENABLE 0x00000001
	51
	52	#define REG_REPORTED_TEMPERATURE 0xa4
	53
	54	#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
	55	#define NB_CAP_HTC 0x00000400
	56
f89ce270 AG	57	/*
	58	* For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
	59	* has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
	60	* Control]
	61	*/
	62	#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
	63	#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F3 0x1573
	64
	65	static void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
	66	int offset, u32 *val)
	67	{
	68	mutex_lock(&nb_smu_ind_mutex);
	69	pci_bus_write_config_dword(pdev->bus, devfn,
	70	0xb8, offset);
	71	pci_bus_read_config_dword(pdev->bus, devfn,
	72	0xbc, val);
	73	mutex_unlock(&nb_smu_ind_mutex);
	74	}
	75
3c57e89b CL	76	static ssize_t show_temp(struct device *dev,
	77	struct device_attribute attr, char buf)
	78	{
	79	u32 regval;
3e3e1022	80	struct pci_dev *pdev = dev_get_drvdata(dev);
f89ce270 AG	81
	82	if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
	83	amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
	84	F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
	85	&regval);
	86	} else {
	87	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
	88	}
3c57e89b CL	89	return sprintf(buf, "%u\n", (regval >> 21) * 125);
	90	}
	91
	92	static ssize_t show_temp_max(struct device *dev,
	93	struct device_attribute attr, char buf)
	94	{
	95	return sprintf(buf, "%d\n", 70 * 1000);
	96	}
	97
	98	static ssize_t show_temp_crit(struct device *dev,
	99	struct device_attribute devattr, char buf)
	100	{
	101	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	102	int show_hyst = attr->index;
	103	u32 regval;
	104	int value;
	105
3e3e1022	106	pci_read_config_dword(dev_get_drvdata(dev),
3c57e89b CL	107	REG_HARDWARE_THERMAL_CONTROL, &regval);
	108	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	109	if (show_hyst)
	110	value -= ((regval >> 24) & 0xf) * 500;
	111	return sprintf(buf, "%d\n", value);
	112	}
	113
3c57e89b CL	114	static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL);
	115	static DEVICE_ATTR(temp1_max, S_IRUGO, show_temp_max, NULL);
	116	static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
	117	static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
3e3e1022 GR	118
	119	static umode_t k10temp_is_visible(struct kobject *kobj,
	120	struct attribute *attr, int index)
	121	{
	122	struct device *dev = container_of(kobj, struct device, kobj);
	123	struct pci_dev *pdev = dev_get_drvdata(dev);
	124
	125	if (index >= 2) {
	126	u32 reg_caps, reg_htc;
	127
	128	pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
	129	&reg_caps);
	130	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
	131	&reg_htc);
	132	if (!(reg_caps & NB_CAP_HTC) \|\| !(reg_htc & HTC_ENABLE))
	133	return 0;
	134	}
	135	return attr->mode;
	136	}
	137
	138	static struct attribute *k10temp_attrs[] = {
	139	&dev_attr_temp1_input.attr,
	140	&dev_attr_temp1_max.attr,
	141	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	142	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
	143	NULL
	144	};
	145
	146	static const struct attribute_group k10temp_group = {
	147	.attrs = k10temp_attrs,
	148	.is_visible = k10temp_is_visible,
	149	};
	150	__ATTRIBUTE_GROUPS(k10temp);
3c57e89b	151
6c931ae1	152	static bool has_erratum_319(struct pci_dev *pdev)
3c57e89b	153	{
c5114a1c CL	154	u32 pkg_type, reg_dram_cfg;
	155
	156	if (boot_cpu_data.x86 != 0x10)
	157	return false;
	158
3c57e89b	159	/*
c5114a1c CL	160	* Erratum 319: The thermal sensor of Socket F/AM2+ processors
c5114a1c CL	161	* may be unreliable.
3c57e89b	162	*/
c5114a1c CL	163	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	164	if (pkg_type == CPUID_PKGTYPE_F)
	165	return true;
	166	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
	167	return false;
	168
eefc2d9e	169	/* DDR3 memory implies socket AM3, which is good */
c5114a1c CL	170	pci_bus_read_config_dword(pdev->bus,
	171	PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
	172	REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
eefc2d9e JD	173	if (reg_dram_cfg & DDR3_MODE)
	174	return false;
	175
	176	/*
	177	* Unfortunately it is possible to run a socket AM3 CPU with DDR2
	178	* memory. We blacklist all the cores which do exist in socket AM2+
	179	* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	180	* and AM3 formats, but that's the best we can do.
	181	*/
	182	return boot_cpu_data.x86_model < 4 \|\|
	183	(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
3c57e89b CL	184	}
3c57e89b CL	185
6c931ae1	186	static int k10temp_probe(struct pci_dev *pdev,
3c57e89b CL	187	const struct pci_device_id *id)
3c57e89b CL	188	{
c5114a1c	189	int unreliable = has_erratum_319(pdev);
3e3e1022 GR	190	struct device *dev = &pdev->dev;
3e3e1022 GR	191	struct device *hwmon_dev;
3c57e89b	192
3e3e1022 GR	193	if (unreliable) {
	194	if (!force) {
	195	dev_err(dev,
	196	"unreliable CPU thermal sensor; monitoring disabled\n");
	197	return -ENODEV;
	198	}
	199	dev_warn(dev,
3c57e89b	200	"unreliable CPU thermal sensor; check erratum 319\n");
3e3e1022	201	}
3c57e89b	202
3e3e1022 GR	203	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", pdev,
	204	k10temp_groups);
	205	return PTR_ERR_OR_ZERO(hwmon_dev);
3c57e89b CL	206	}
3c57e89b CL	207
cd9bb056	208	static const struct pci_device_id k10temp_id_table[] = {
3c57e89b CL	209	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
3c57e89b CL	210	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
aa4790a6	211	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
9e581311	212	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	213	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
d303b1b5	214	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
f89ce270	215	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
30b146d1	216	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
ec015950	217	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
3c57e89b CL	218	{}
	219	};
	220	MODULE_DEVICE_TABLE(pci, k10temp_id_table);
	221
	222	static struct pci_driver k10temp_driver = {
	223	.name = "k10temp",
	224	.id_table = k10temp_id_table,
	225	.probe = k10temp_probe,
3c57e89b CL	226	};
3c57e89b CL	227
f71f5a55	228	module_pci_driver(k10temp_driver);