[linux-2.6-block.git] / drivers / hwmon / k10temp.c

/*
 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
 *
 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
 *
 *
 * This driver is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <asm/amd_nb.h>
#include <asm/processor.h>

MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_LICENSE("GPL");

static bool force;
module_param(force, bool, 0444);
MODULE_PARM_DESC(force, "force loading on processors with erratum 319");

/* Provide lock for writing to NB_SMU_IND_ADDR */
static DEFINE_MUTEX(nb_smu_ind_mutex);

#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3	0x15b3
#endif

#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
#define PCI_DEVICE_ID_AMD_17H_DF_F3	0x1463
#endif

#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3	0x15eb
#endif

/* CPUID function 0x80000001, ebx */
#define CPUID_PKGTYPE_MASK	0xf0000000
#define CPUID_PKGTYPE_F		0x00000000
#define CPUID_PKGTYPE_AM2R2_AM3	0x10000000

/* DRAM controller (PCI function 2) */
#define REG_DCT0_CONFIG_HIGH		0x094
#define  DDR3_MODE			0x00000100

/* miscellaneous (PCI function 3) */
#define REG_HARDWARE_THERMAL_CONTROL	0x64
#define  HTC_ENABLE			0x00000001

#define REG_REPORTED_TEMPERATURE	0xa4

#define REG_NORTHBRIDGE_CAPABILITIES	0xe8
#define  NB_CAP_HTC			0x00000400

/*
 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
 * and REG_REPORTED_TEMPERATURE have been moved to
 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
 */
#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET	0xd8200c64
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET	0xd8200ca4

/* F17h M01h Access througn SMN */
#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET	0x00059800

struct k10temp_data {
	struct pci_dev *pdev;
	void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
	void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
	int temp_offset;
	u32 temp_adjust_mask;
	bool show_tdie;
};

struct tctl_offset {
	u8 model;
	char const *id;
	int offset;
};

static const struct tctl_offset tctl_offset_table[] = {
	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
	{ 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
	{ 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
	{ 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
	{ 0x17, "AMD Ryzen Threadripper 1950", 10000 },
	{ 0x17, "AMD Ryzen Threadripper 1920", 10000 },
	{ 0x17, "AMD Ryzen Threadripper 1910", 10000 },
};

static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
}

static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
}

static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
			      unsigned int base, int offset, u32 *val)
{
	mutex_lock(&nb_smu_ind_mutex);
	pci_bus_write_config_dword(pdev->bus, devfn,
				   base, offset);
	pci_bus_read_config_dword(pdev->bus, devfn,
				  base + 4, val);
	mutex_unlock(&nb_smu_ind_mutex);
}

static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
{
	amd_smn_read(amd_pci_dev_to_node_id(pdev),
		     F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static unsigned int get_raw_temp(struct k10temp_data *data)
{
	unsigned int temp;
	u32 regval;

	data->read_tempreg(data->pdev, &regval);
	temp = (regval >> 21) * 125;
	if (regval & data->temp_adjust_mask)
		temp -= 49000;
	return temp;
}

static ssize_t temp1_input_show(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	unsigned int temp = get_raw_temp(data);

	if (temp > data->temp_offset)
		temp -= data->temp_offset;
	else
		temp = 0;

	return sprintf(buf, "%u\n", temp);
}

static ssize_t temp2_input_show(struct device *dev,
				struct device_attribute *devattr, char *buf)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	unsigned int temp = get_raw_temp(data);

	return sprintf(buf, "%u\n", temp);
}

static ssize_t temp_label_show(struct device *dev,
			       struct device_attribute *devattr, char *buf)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);

	return sprintf(buf, "%s\n", attr->index ? "Tctl" : "Tdie");
}

static ssize_t temp1_max_show(struct device *dev,
			      struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "%d\n", 70 * 1000);
}

static ssize_t show_temp_crit(struct device *dev,
			      struct device_attribute *devattr, char *buf)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	struct k10temp_data *data = dev_get_drvdata(dev);
	int show_hyst = attr->index;
	u32 regval;
	int value;

	data->read_htcreg(data->pdev, &regval);
	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	if (show_hyst)
		value -= ((regval >> 24) & 0xf) * 500;
	return sprintf(buf, "%d\n", value);
}

static DEVICE_ATTR_RO(temp1_input);
static DEVICE_ATTR_RO(temp1_max);
static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);

static SENSOR_DEVICE_ATTR(temp1_label, 0444, temp_label_show, NULL, 0);
static DEVICE_ATTR_RO(temp2_input);
static SENSOR_DEVICE_ATTR(temp2_label, 0444, temp_label_show, NULL, 1);

static umode_t k10temp_is_visible(struct kobject *kobj,
				  struct attribute *attr, int index)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct k10temp_data *data = dev_get_drvdata(dev);
	struct pci_dev *pdev = data->pdev;
	u32 reg;

	switch (index) {
	case 0 ... 1:	/* temp1_input, temp1_max */
	default:
		break;
	case 2 ... 3:	/* temp1_crit, temp1_crit_hyst */
		if (!data->read_htcreg)
			return 0;

		pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
				      &reg);
		if (!(reg & NB_CAP_HTC))
			return 0;

		data->read_htcreg(data->pdev, &reg);
		if (!(reg & HTC_ENABLE))
			return 0;
		break;
	case 4 ... 6:	/* temp1_label, temp2_input, temp2_label */
		if (!data->show_tdie)
			return 0;
		break;
	}
	return attr->mode;
}

static struct attribute *k10temp_attrs[] = {
	&dev_attr_temp1_input.attr,
	&dev_attr_temp1_max.attr,
	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
	&sensor_dev_attr_temp1_label.dev_attr.attr,
	&dev_attr_temp2_input.attr,
	&sensor_dev_attr_temp2_label.dev_attr.attr,
	NULL
};

static const struct attribute_group k10temp_group = {
	.attrs = k10temp_attrs,
	.is_visible = k10temp_is_visible,
};
__ATTRIBUTE_GROUPS(k10temp);

static bool has_erratum_319(struct pci_dev *pdev)
{
	u32 pkg_type, reg_dram_cfg;

	if (boot_cpu_data.x86 != 0x10)
		return false;

	/*
	 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
	 *              may be unreliable.
	 */
	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	if (pkg_type == CPUID_PKGTYPE_F)
		return true;
	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
		return false;

	/* DDR3 memory implies socket AM3, which is good */
	pci_bus_read_config_dword(pdev->bus,
				  PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
				  REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
	if (reg_dram_cfg & DDR3_MODE)
		return false;

	/*
	 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
	 * memory. We blacklist all the cores which do exist in socket AM2+
	 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	 * and AM3 formats, but that's the best we can do.
	 */
	return boot_cpu_data.x86_model < 4 ||
	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
}

static int k10temp_probe(struct pci_dev *pdev,
				   const struct pci_device_id *id)
{
	int unreliable = has_erratum_319(pdev);
	struct device *dev = &pdev->dev;
	struct k10temp_data *data;
	struct device *hwmon_dev;
	int i;

	if (unreliable) {
		if (!force) {
			dev_err(dev,
				"unreliable CPU thermal sensor; monitoring disabled\n");
			return -ENODEV;
		}
		dev_warn(dev,
			 "unreliable CPU thermal sensor; check erratum 319\n");
	}

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->pdev = pdev;

	if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
					  boot_cpu_data.x86_model == 0x70)) {
		data->read_htcreg = read_htcreg_nb_f15;
		data->read_tempreg = read_tempreg_nb_f15;
	} else if (boot_cpu_data.x86 == 0x17) {
		data->temp_adjust_mask = 0x80000;
		data->read_tempreg = read_tempreg_nb_f17;
		data->show_tdie = true;
	} else {
		data->read_htcreg = read_htcreg_pci;
		data->read_tempreg = read_tempreg_pci;
	}

	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
		const struct tctl_offset *entry = &tctl_offset_table[i];

		if (boot_cpu_data.x86 == entry->model &&
		    strstr(boot_cpu_data.x86_model_id, entry->id)) {
			data->temp_offset = entry->offset;
			break;
		}
	}

	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
							   k10temp_groups);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static const struct pci_device_id k10temp_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
	{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);

static struct pci_driver k10temp_driver = {
	.name = "k10temp",
	.id_table = k10temp_id_table,
	.probe = k10temp_probe,
};

module_pci_driver(k10temp_driver);
Commit	Line	Data
3c57e89b	1	/*
30b146d1	2	* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
3c57e89b CL	3	*
	4	* Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
	5	*
	6	*
	7	* This driver is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This driver is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	14	* See the GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this driver; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/err.h>
	21	#include <linux/hwmon.h>
	22	#include <linux/hwmon-sysfs.h>
	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/pci.h>
3b031622	26	#include <asm/amd_nb.h>
3c57e89b CL	27	#include <asm/processor.h>
3c57e89b CL	28
9e581311	29	MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
3c57e89b CL	30	MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
	31	MODULE_LICENSE("GPL");
	32
	33	static bool force;
	34	module_param(force, bool, 0444);
	35	MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
	36
f89ce270 AG	37	/* Provide lock for writing to NB_SMU_IND_ADDR */
	38	static DEFINE_MUTEX(nb_smu_ind_mutex);
	39
ccaf63b4 GR	40	#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
	41	#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
	42	#endif
	43
9af0a9ae GR	44	#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
	45	#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
	46	#endif
	47
3b031622 GR	48	#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
3b031622 GR	49	#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
877d8948 GR	50	#endif
877d8948 GR	51
c5114a1c CL	52	/* CPUID function 0x80000001, ebx */
	53	#define CPUID_PKGTYPE_MASK 0xf0000000
	54	#define CPUID_PKGTYPE_F 0x00000000
	55	#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
	56
	57	/* DRAM controller (PCI function 2) */
	58	#define REG_DCT0_CONFIG_HIGH 0x094
	59	#define DDR3_MODE 0x00000100
	60
	61	/* miscellaneous (PCI function 3) */
3c57e89b CL	62	#define REG_HARDWARE_THERMAL_CONTROL 0x64
	63	#define HTC_ENABLE 0x00000001
	64
	65	#define REG_REPORTED_TEMPERATURE 0xa4
	66
	67	#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
	68	#define NB_CAP_HTC 0x00000400
	69
f89ce270	70	/*
40626a1b GR	71	* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
	72	* and REG_REPORTED_TEMPERATURE have been moved to
	73	* D0F0xBC_xD820_0C64 [Hardware Temperature Control]
	74	* D0F0xBC_xD820_0CA4 [Reported Temperature Control]
f89ce270	75	*/
40626a1b	76	#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
f89ce270	77	#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
f89ce270	78
9af0a9ae GR	79	/* F17h M01h Access througn SMN */
	80	#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
	81
68546abf GR	82	struct k10temp_data {
68546abf GR	83	struct pci_dev *pdev;
40626a1b	84	void (read_htcreg)(struct pci_dev pdev, u32 *regval);
68546abf	85	void (read_tempreg)(struct pci_dev pdev, u32 *regval);
1b50b776	86	int temp_offset;
1b597889	87	u32 temp_adjust_mask;
f934c059	88	bool show_tdie;
1b50b776 GR	89	};
	90
	91	struct tctl_offset {
	92	u8 model;
	93	char const *id;
	94	int offset;
	95	};
	96
	97	static const struct tctl_offset tctl_offset_table[] = {
ab5ee246	98	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
1b50b776 GR	99	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
1b50b776 GR	100	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
1b597889	101	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
1b50b776 GR	102	{ 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
1b50b776 GR	103	{ 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
6509614f	104	{ 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
1b50b776 GR	105	{ 0x17, "AMD Ryzen Threadripper 1950", 10000 },
	106	{ 0x17, "AMD Ryzen Threadripper 1920", 10000 },
	107	{ 0x17, "AMD Ryzen Threadripper 1910", 10000 },
68546abf GR	108	};
68546abf GR	109
40626a1b GR	110	static void read_htcreg_pci(struct pci_dev pdev, u32 regval)
	111	{
	112	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
	113	}
	114
68546abf GR	115	static void read_tempreg_pci(struct pci_dev pdev, u32 regval)
	116	{
	117	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
	118	}
	119
	120	static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
	121	unsigned int base, int offset, u32 *val)
f89ce270 AG	122	{
	123	mutex_lock(&nb_smu_ind_mutex);
	124	pci_bus_write_config_dword(pdev->bus, devfn,
68546abf	125	base, offset);
f89ce270	126	pci_bus_read_config_dword(pdev->bus, devfn,
68546abf	127	base + 4, val);
f89ce270 AG	128	mutex_unlock(&nb_smu_ind_mutex);
	129	}
	130
40626a1b GR	131	static void read_htcreg_nb_f15(struct pci_dev pdev, u32 regval)
	132	{
	133	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	134	F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
	135	}
	136
68546abf GR	137	static void read_tempreg_nb_f15(struct pci_dev pdev, u32 regval)
	138	{
	139	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	140	F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
	141	}
	142
9af0a9ae GR	143	static void read_tempreg_nb_f17(struct pci_dev pdev, u32 regval)
9af0a9ae GR	144	{
3b031622 GR	145	amd_smn_read(amd_pci_dev_to_node_id(pdev),
3b031622 GR	146	F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
9af0a9ae GR	147	}
9af0a9ae GR	148
fb8eefd3	149	static unsigned int get_raw_temp(struct k10temp_data *data)
3c57e89b	150	{
68546abf	151	unsigned int temp;
f934c059	152	u32 regval;
68546abf GR	153
	154	data->read_tempreg(data->pdev, &regval);
	155	temp = (regval >> 21) * 125;
1b597889 GR	156	if (regval & data->temp_adjust_mask)
1b597889 GR	157	temp -= 49000;
f934c059 GR	158	return temp;
	159	}
	160
	161	static ssize_t temp1_input_show(struct device *dev,
	162	struct device_attribute attr, char buf)
	163	{
	164	struct k10temp_data *data = dev_get_drvdata(dev);
	165	unsigned int temp = get_raw_temp(data);
	166
aef17ca1 GR	167	if (temp > data->temp_offset)
	168	temp -= data->temp_offset;
	169	else
	170	temp = 0;
68546abf GR	171
68546abf GR	172	return sprintf(buf, "%u\n", temp);
3c57e89b CL	173	}
3c57e89b CL	174
f934c059 GR	175	static ssize_t temp2_input_show(struct device *dev,
	176	struct device_attribute devattr, char buf)
	177	{
	178	struct k10temp_data *data = dev_get_drvdata(dev);
	179	unsigned int temp = get_raw_temp(data);
	180
	181	return sprintf(buf, "%u\n", temp);
	182	}
	183
	184	static ssize_t temp_label_show(struct device *dev,
	185	struct device_attribute devattr, char buf)
	186	{
	187	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	188
	189	return sprintf(buf, "%s\n", attr->index ? "Tctl" : "Tdie");
	190	}
	191
0c36d72e JL	192	static ssize_t temp1_max_show(struct device *dev,
0c36d72e JL	193	struct device_attribute attr, char buf)
3c57e89b CL	194	{
	195	return sprintf(buf, "%d\n", 70 * 1000);
	196	}
	197
	198	static ssize_t show_temp_crit(struct device *dev,
	199	struct device_attribute devattr, char buf)
	200	{
	201	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
68546abf	202	struct k10temp_data *data = dev_get_drvdata(dev);
3c57e89b CL	203	int show_hyst = attr->index;
	204	u32 regval;
	205	int value;
	206
40626a1b	207	data->read_htcreg(data->pdev, &regval);
3c57e89b CL	208	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	209	if (show_hyst)
	210	value -= ((regval >> 24) & 0xf) * 500;
	211	return sprintf(buf, "%d\n", value);
	212	}
	213
0c36d72e JL	214	static DEVICE_ATTR_RO(temp1_input);
0c36d72e JL	215	static DEVICE_ATTR_RO(temp1_max);
3c57e89b CL	216	static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
3c57e89b CL	217	static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
3e3e1022	218
f934c059 GR	219	static SENSOR_DEVICE_ATTR(temp1_label, 0444, temp_label_show, NULL, 0);
	220	static DEVICE_ATTR_RO(temp2_input);
	221	static SENSOR_DEVICE_ATTR(temp2_label, 0444, temp_label_show, NULL, 1);
	222
3e3e1022 GR	223	static umode_t k10temp_is_visible(struct kobject *kobj,
	224	struct attribute *attr, int index)
	225	{
	226	struct device *dev = container_of(kobj, struct device, kobj);
68546abf GR	227	struct k10temp_data *data = dev_get_drvdata(dev);
68546abf GR	228	struct pci_dev *pdev = data->pdev;
f934c059	229	u32 reg;
3e3e1022	230
f934c059 GR	231	switch (index) {
	232	case 0 ... 1: /* temp1_input, temp1_max */
	233	default:
	234	break;
	235	case 2 ... 3: /* temp1_crit, temp1_crit_hyst */
40626a1b GR	236	if (!data->read_htcreg)
40626a1b GR	237	return 0;
3e3e1022 GR	238
3e3e1022 GR	239	pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
40626a1b GR	240	&reg);
	241	if (!(reg & NB_CAP_HTC))
	242	return 0;
	243
	244	data->read_htcreg(data->pdev, &reg);
	245	if (!(reg & HTC_ENABLE))
3e3e1022	246	return 0;
f934c059 GR	247	break;
	248	case 4 ... 6: /* temp1_label, temp2_input, temp2_label */
	249	if (!data->show_tdie)
	250	return 0;
	251	break;
3e3e1022 GR	252	}
	253	return attr->mode;
	254	}
	255
	256	static struct attribute *k10temp_attrs[] = {
	257	&dev_attr_temp1_input.attr,
	258	&dev_attr_temp1_max.attr,
	259	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	260	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
f934c059 GR	261	&sensor_dev_attr_temp1_label.dev_attr.attr,
	262	&dev_attr_temp2_input.attr,
	263	&sensor_dev_attr_temp2_label.dev_attr.attr,
3e3e1022 GR	264	NULL
	265	};
	266
	267	static const struct attribute_group k10temp_group = {
	268	.attrs = k10temp_attrs,
	269	.is_visible = k10temp_is_visible,
	270	};
	271	__ATTRIBUTE_GROUPS(k10temp);
3c57e89b	272
6c931ae1	273	static bool has_erratum_319(struct pci_dev *pdev)
3c57e89b	274	{
c5114a1c CL	275	u32 pkg_type, reg_dram_cfg;
	276
	277	if (boot_cpu_data.x86 != 0x10)
	278	return false;
	279
3c57e89b	280	/*
c5114a1c CL	281	* Erratum 319: The thermal sensor of Socket F/AM2+ processors
c5114a1c CL	282	* may be unreliable.
3c57e89b	283	*/
c5114a1c CL	284	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	285	if (pkg_type == CPUID_PKGTYPE_F)
	286	return true;
	287	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
	288	return false;
	289
eefc2d9e	290	/* DDR3 memory implies socket AM3, which is good */
c5114a1c CL	291	pci_bus_read_config_dword(pdev->bus,
	292	PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
	293	REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
eefc2d9e JD	294	if (reg_dram_cfg & DDR3_MODE)
	295	return false;
	296
	297	/*
	298	* Unfortunately it is possible to run a socket AM3 CPU with DDR2
	299	* memory. We blacklist all the cores which do exist in socket AM2+
	300	* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	301	* and AM3 formats, but that's the best we can do.
	302	*/
	303	return boot_cpu_data.x86_model < 4 \|\|
b399151c	304	(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
3c57e89b CL	305	}
3c57e89b CL	306
6c931ae1	307	static int k10temp_probe(struct pci_dev *pdev,
3c57e89b CL	308	const struct pci_device_id *id)
3c57e89b CL	309	{
c5114a1c	310	int unreliable = has_erratum_319(pdev);
3e3e1022	311	struct device *dev = &pdev->dev;
68546abf	312	struct k10temp_data *data;
3e3e1022	313	struct device *hwmon_dev;
1b50b776	314	int i;
3c57e89b	315
3e3e1022 GR	316	if (unreliable) {
	317	if (!force) {
	318	dev_err(dev,
	319	"unreliable CPU thermal sensor; monitoring disabled\n");
	320	return -ENODEV;
	321	}
	322	dev_warn(dev,
3c57e89b	323	"unreliable CPU thermal sensor; check erratum 319\n");
3e3e1022	324	}
3c57e89b	325
68546abf GR	326	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	327	if (!data)
	328	return -ENOMEM;
	329
	330	data->pdev = pdev;
	331
	332	if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 \|\|
1b597889	333	boot_cpu_data.x86_model == 0x70)) {
40626a1b	334	data->read_htcreg = read_htcreg_nb_f15;
68546abf	335	data->read_tempreg = read_tempreg_nb_f15;
1b597889 GR	336	} else if (boot_cpu_data.x86 == 0x17) {
1b597889 GR	337	data->temp_adjust_mask = 0x80000;
9af0a9ae	338	data->read_tempreg = read_tempreg_nb_f17;
f934c059	339	data->show_tdie = true;
1b597889	340	} else {
40626a1b	341	data->read_htcreg = read_htcreg_pci;
68546abf	342	data->read_tempreg = read_tempreg_pci;
1b597889	343	}
68546abf	344
1b50b776 GR	345	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
	346	const struct tctl_offset *entry = &tctl_offset_table[i];
	347
	348	if (boot_cpu_data.x86 == entry->model &&
	349	strstr(boot_cpu_data.x86_model_id, entry->id)) {
	350	data->temp_offset = entry->offset;
	351	break;
	352	}
	353	}
	354
68546abf	355	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
3e3e1022 GR	356	k10temp_groups);
3e3e1022 GR	357	return PTR_ERR_OR_ZERO(hwmon_dev);
3c57e89b CL	358	}
3c57e89b CL	359
cd9bb056	360	static const struct pci_device_id k10temp_id_table[] = {
3c57e89b CL	361	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
3c57e89b CL	362	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
aa4790a6	363	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
9e581311	364	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	365	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
d303b1b5	366	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
f89ce270	367	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
ccaf63b4	368	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
30b146d1	369	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
ec015950	370	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
9af0a9ae	371	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
3b031622	372	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
3c57e89b CL	373	{}
	374	};
	375	MODULE_DEVICE_TABLE(pci, k10temp_id_table);
	376
	377	static struct pci_driver k10temp_driver = {
	378	.name = "k10temp",
	379	.id_table = k10temp_id_table,
	380	.probe = k10temp_probe,
3c57e89b CL	381	};
3c57e89b CL	382
f71f5a55	383	module_pci_driver(k10temp_driver);