Commit | Line | Data |
---|---|---|
4453d736 GR |
1 | /* |
2 | * jc42.c - driver for Jedec JC42.4 compliant temperature sensors | |
3 | * | |
4 | * Copyright (c) 2010 Ericsson AB. | |
5 | * | |
6 | * Derived from lm77.c by Andras BALI <drewie@freemail.hu>. | |
7 | * | |
8 | * JC42.4 compliant temperature sensors are typically used on memory modules. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/jiffies.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/hwmon.h> | |
31 | #include <linux/hwmon-sysfs.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/mutex.h> | |
34 | ||
35 | /* Addresses to scan */ | |
36 | static const unsigned short normal_i2c[] = { | |
37 | 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END }; | |
38 | ||
39 | /* JC42 registers. All registers are 16 bit. */ | |
40 | #define JC42_REG_CAP 0x00 | |
41 | #define JC42_REG_CONFIG 0x01 | |
42 | #define JC42_REG_TEMP_UPPER 0x02 | |
43 | #define JC42_REG_TEMP_LOWER 0x03 | |
44 | #define JC42_REG_TEMP_CRITICAL 0x04 | |
45 | #define JC42_REG_TEMP 0x05 | |
46 | #define JC42_REG_MANID 0x06 | |
47 | #define JC42_REG_DEVICEID 0x07 | |
48 | ||
49 | /* Status bits in temperature register */ | |
50 | #define JC42_ALARM_CRIT_BIT 15 | |
51 | #define JC42_ALARM_MAX_BIT 14 | |
52 | #define JC42_ALARM_MIN_BIT 13 | |
53 | ||
54 | /* Configuration register defines */ | |
55 | #define JC42_CFG_CRIT_ONLY (1 << 2) | |
2c6315da CL |
56 | #define JC42_CFG_TCRIT_LOCK (1 << 6) |
57 | #define JC42_CFG_EVENT_LOCK (1 << 7) | |
4453d736 GR |
58 | #define JC42_CFG_SHUTDOWN (1 << 8) |
59 | #define JC42_CFG_HYST_SHIFT 9 | |
2ccc8731 | 60 | #define JC42_CFG_HYST_MASK (0x03 << 9) |
4453d736 GR |
61 | |
62 | /* Capabilities */ | |
63 | #define JC42_CAP_RANGE (1 << 2) | |
64 | ||
65 | /* Manufacturer IDs */ | |
66 | #define ADT_MANID 0x11d4 /* Analog Devices */ | |
1bd612a2 | 67 | #define ATMEL_MANID 0x001f /* Atmel */ |
175c490c | 68 | #define ATMEL_MANID2 0x1114 /* Atmel */ |
4453d736 GR |
69 | #define MAX_MANID 0x004d /* Maxim */ |
70 | #define IDT_MANID 0x00b3 /* IDT */ | |
71 | #define MCP_MANID 0x0054 /* Microchip */ | |
72 | #define NXP_MANID 0x1131 /* NXP Semiconductors */ | |
73 | #define ONS_MANID 0x1b09 /* ON Semiconductor */ | |
74 | #define STM_MANID 0x104a /* ST Microelectronics */ | |
75 | ||
76 | /* Supported chips */ | |
77 | ||
78 | /* Analog Devices */ | |
79 | #define ADT7408_DEVID 0x0801 | |
80 | #define ADT7408_DEVID_MASK 0xffff | |
81 | ||
1bd612a2 GR |
82 | /* Atmel */ |
83 | #define AT30TS00_DEVID 0x8201 | |
84 | #define AT30TS00_DEVID_MASK 0xffff | |
85 | ||
175c490c GR |
86 | #define AT30TSE004_DEVID 0x2200 |
87 | #define AT30TSE004_DEVID_MASK 0xffff | |
88 | ||
4453d736 | 89 | /* IDT */ |
0ea2f1db GR |
90 | #define TSE2004_DEVID 0x2200 |
91 | #define TSE2004_DEVID_MASK 0xff00 | |
4453d736 | 92 | |
0ea2f1db GR |
93 | #define TS3000_DEVID 0x2900 /* Also matches TSE2002 */ |
94 | #define TS3000_DEVID_MASK 0xff00 | |
95 | ||
96 | #define TS3001_DEVID 0x3000 | |
97 | #define TS3001_DEVID_MASK 0xff00 | |
1bd612a2 | 98 | |
4453d736 GR |
99 | /* Maxim */ |
100 | #define MAX6604_DEVID 0x3e00 | |
101 | #define MAX6604_DEVID_MASK 0xffff | |
102 | ||
103 | /* Microchip */ | |
1bd612a2 GR |
104 | #define MCP9804_DEVID 0x0200 |
105 | #define MCP9804_DEVID_MASK 0xfffc | |
106 | ||
a31887dc AS |
107 | #define MCP9808_DEVID 0x0400 |
108 | #define MCP9808_DEVID_MASK 0xfffc | |
109 | ||
4453d736 GR |
110 | #define MCP98242_DEVID 0x2000 |
111 | #define MCP98242_DEVID_MASK 0xfffc | |
112 | ||
113 | #define MCP98243_DEVID 0x2100 | |
114 | #define MCP98243_DEVID_MASK 0xfffc | |
115 | ||
d4768280 GR |
116 | #define MCP98244_DEVID 0x2200 |
117 | #define MCP98244_DEVID_MASK 0xfffc | |
118 | ||
4453d736 GR |
119 | #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */ |
120 | #define MCP9843_DEVID_MASK 0xfffe | |
121 | ||
122 | /* NXP */ | |
123 | #define SE97_DEVID 0xa200 | |
124 | #define SE97_DEVID_MASK 0xfffc | |
125 | ||
126 | #define SE98_DEVID 0xa100 | |
127 | #define SE98_DEVID_MASK 0xfffc | |
128 | ||
129 | /* ON Semiconductor */ | |
130 | #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */ | |
131 | #define CAT6095_DEVID_MASK 0xffe0 | |
132 | ||
133 | /* ST Microelectronics */ | |
134 | #define STTS424_DEVID 0x0101 | |
135 | #define STTS424_DEVID_MASK 0xffff | |
136 | ||
137 | #define STTS424E_DEVID 0x0000 | |
138 | #define STTS424E_DEVID_MASK 0xfffe | |
139 | ||
4de86126 JD |
140 | #define STTS2002_DEVID 0x0300 |
141 | #define STTS2002_DEVID_MASK 0xffff | |
142 | ||
175c490c GR |
143 | #define STTS2004_DEVID 0x2201 |
144 | #define STTS2004_DEVID_MASK 0xffff | |
145 | ||
4de86126 JD |
146 | #define STTS3000_DEVID 0x0200 |
147 | #define STTS3000_DEVID_MASK 0xffff | |
148 | ||
4453d736 GR |
149 | static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 }; |
150 | ||
151 | struct jc42_chips { | |
152 | u16 manid; | |
153 | u16 devid; | |
154 | u16 devid_mask; | |
155 | }; | |
156 | ||
157 | static struct jc42_chips jc42_chips[] = { | |
158 | { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK }, | |
1bd612a2 | 159 | { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK }, |
175c490c | 160 | { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK }, |
0ea2f1db GR |
161 | { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, |
162 | { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK }, | |
163 | { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK }, | |
4453d736 | 164 | { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK }, |
1bd612a2 | 165 | { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK }, |
a31887dc | 166 | { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK }, |
4453d736 GR |
167 | { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK }, |
168 | { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK }, | |
d4768280 | 169 | { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK }, |
4453d736 GR |
170 | { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK }, |
171 | { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK }, | |
172 | { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK }, | |
173 | { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK }, | |
174 | { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK }, | |
175 | { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK }, | |
4de86126 | 176 | { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK }, |
175c490c | 177 | { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK }, |
4de86126 | 178 | { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK }, |
4453d736 GR |
179 | }; |
180 | ||
10192bc6 GR |
181 | enum temp_index { |
182 | t_input = 0, | |
183 | t_crit, | |
184 | t_min, | |
185 | t_max, | |
186 | t_num_temp | |
187 | }; | |
188 | ||
189 | static const u8 temp_regs[t_num_temp] = { | |
190 | [t_input] = JC42_REG_TEMP, | |
191 | [t_crit] = JC42_REG_TEMP_CRITICAL, | |
192 | [t_min] = JC42_REG_TEMP_LOWER, | |
193 | [t_max] = JC42_REG_TEMP_UPPER, | |
194 | }; | |
195 | ||
4453d736 GR |
196 | /* Each client has this additional data */ |
197 | struct jc42_data { | |
62f9a57c | 198 | struct i2c_client *client; |
4453d736 GR |
199 | struct mutex update_lock; /* protect register access */ |
200 | bool extended; /* true if extended range supported */ | |
201 | bool valid; | |
202 | unsigned long last_updated; /* In jiffies */ | |
203 | u16 orig_config; /* original configuration */ | |
204 | u16 config; /* current configuration */ | |
10192bc6 | 205 | u16 temp[t_num_temp];/* Temperatures */ |
4453d736 GR |
206 | }; |
207 | ||
4453d736 GR |
208 | #define JC42_TEMP_MIN_EXTENDED (-40000) |
209 | #define JC42_TEMP_MIN 0 | |
210 | #define JC42_TEMP_MAX 125000 | |
211 | ||
3a05633b | 212 | static u16 jc42_temp_to_reg(long temp, bool extended) |
4453d736 | 213 | { |
2a844c14 GR |
214 | int ntemp = clamp_val(temp, |
215 | extended ? JC42_TEMP_MIN_EXTENDED : | |
216 | JC42_TEMP_MIN, JC42_TEMP_MAX); | |
4453d736 GR |
217 | |
218 | /* convert from 0.001 to 0.0625 resolution */ | |
219 | return (ntemp * 2 / 125) & 0x1fff; | |
220 | } | |
221 | ||
222 | static int jc42_temp_from_reg(s16 reg) | |
223 | { | |
bca6a1ad | 224 | reg = sign_extend32(reg, 12); |
4453d736 GR |
225 | |
226 | /* convert from 0.0625 to 0.001 resolution */ | |
227 | return reg * 125 / 2; | |
228 | } | |
229 | ||
d397276b GR |
230 | static struct jc42_data *jc42_update_device(struct device *dev) |
231 | { | |
232 | struct jc42_data *data = dev_get_drvdata(dev); | |
233 | struct i2c_client *client = data->client; | |
234 | struct jc42_data *ret = data; | |
10192bc6 | 235 | int i, val; |
d397276b GR |
236 | |
237 | mutex_lock(&data->update_lock); | |
238 | ||
239 | if (time_after(jiffies, data->last_updated + HZ) || !data->valid) { | |
10192bc6 GR |
240 | for (i = 0; i < t_num_temp; i++) { |
241 | val = i2c_smbus_read_word_swapped(client, temp_regs[i]); | |
242 | if (val < 0) { | |
243 | ret = ERR_PTR(val); | |
244 | goto abort; | |
245 | } | |
246 | data->temp[i] = val; | |
d397276b | 247 | } |
d397276b GR |
248 | data->last_updated = jiffies; |
249 | data->valid = true; | |
250 | } | |
251 | abort: | |
252 | mutex_unlock(&data->update_lock); | |
253 | return ret; | |
254 | } | |
255 | ||
10192bc6 | 256 | /* sysfs functions */ |
4453d736 | 257 | |
10192bc6 GR |
258 | static ssize_t show_temp(struct device *dev, struct device_attribute *devattr, |
259 | char *buf) | |
4453d736 | 260 | { |
10192bc6 | 261 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
4453d736 | 262 | struct jc42_data *data = jc42_update_device(dev); |
4453d736 GR |
263 | if (IS_ERR(data)) |
264 | return PTR_ERR(data); | |
10192bc6 GR |
265 | return sprintf(buf, "%d\n", |
266 | jc42_temp_from_reg(data->temp[attr->index])); | |
4453d736 GR |
267 | } |
268 | ||
10192bc6 GR |
269 | static ssize_t show_temp_hyst(struct device *dev, |
270 | struct device_attribute *devattr, char *buf) | |
4453d736 | 271 | { |
10192bc6 | 272 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
4453d736 GR |
273 | struct jc42_data *data = jc42_update_device(dev); |
274 | int temp, hyst; | |
275 | ||
276 | if (IS_ERR(data)) | |
277 | return PTR_ERR(data); | |
278 | ||
10192bc6 | 279 | temp = jc42_temp_from_reg(data->temp[attr->index]); |
2ccc8731 JD |
280 | hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK) |
281 | >> JC42_CFG_HYST_SHIFT]; | |
4453d736 GR |
282 | return sprintf(buf, "%d\n", temp - hyst); |
283 | } | |
284 | ||
10192bc6 GR |
285 | static ssize_t set_temp(struct device *dev, struct device_attribute *devattr, |
286 | const char *buf, size_t count) | |
287 | { | |
288 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
289 | struct jc42_data *data = dev_get_drvdata(dev); | |
290 | int err, ret = count; | |
291 | int nr = attr->index; | |
292 | long val; | |
4453d736 | 293 | |
10192bc6 GR |
294 | if (kstrtol(buf, 10, &val) < 0) |
295 | return -EINVAL; | |
296 | mutex_lock(&data->update_lock); | |
297 | data->temp[nr] = jc42_temp_to_reg(val, data->extended); | |
298 | err = i2c_smbus_write_word_swapped(data->client, temp_regs[nr], | |
299 | data->temp[nr]); | |
300 | if (err < 0) | |
301 | ret = err; | |
302 | mutex_unlock(&data->update_lock); | |
303 | return ret; | |
304 | } | |
4453d736 | 305 | |
5d577dba GR |
306 | /* |
307 | * JC42.4 compliant chips only support four hysteresis values. | |
308 | * Pick best choice and go from there. | |
309 | */ | |
4453d736 GR |
310 | static ssize_t set_temp_crit_hyst(struct device *dev, |
311 | struct device_attribute *attr, | |
312 | const char *buf, size_t count) | |
313 | { | |
62f9a57c | 314 | struct jc42_data *data = dev_get_drvdata(dev); |
9130880a | 315 | long val; |
4453d736 GR |
316 | int diff, hyst; |
317 | int err; | |
318 | int ret = count; | |
319 | ||
9130880a | 320 | if (kstrtol(buf, 10, &val) < 0) |
4453d736 GR |
321 | return -EINVAL; |
322 | ||
9130880a JD |
323 | val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED : |
324 | JC42_TEMP_MIN) - 6000, JC42_TEMP_MAX); | |
10192bc6 | 325 | diff = jc42_temp_from_reg(data->temp[t_crit]) - val; |
e2c26f05 | 326 | |
4453d736 GR |
327 | hyst = 0; |
328 | if (diff > 0) { | |
329 | if (diff < 2250) | |
330 | hyst = 1; /* 1.5 degrees C */ | |
331 | else if (diff < 4500) | |
332 | hyst = 2; /* 3.0 degrees C */ | |
333 | else | |
334 | hyst = 3; /* 6.0 degrees C */ | |
335 | } | |
336 | ||
337 | mutex_lock(&data->update_lock); | |
2ccc8731 | 338 | data->config = (data->config & ~JC42_CFG_HYST_MASK) |
4453d736 | 339 | | (hyst << JC42_CFG_HYST_SHIFT); |
62f9a57c | 340 | err = i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, |
90f4102c | 341 | data->config); |
4453d736 GR |
342 | if (err < 0) |
343 | ret = err; | |
344 | mutex_unlock(&data->update_lock); | |
345 | return ret; | |
346 | } | |
347 | ||
348 | static ssize_t show_alarm(struct device *dev, | |
349 | struct device_attribute *attr, char *buf) | |
350 | { | |
351 | u16 bit = to_sensor_dev_attr(attr)->index; | |
352 | struct jc42_data *data = jc42_update_device(dev); | |
353 | u16 val; | |
354 | ||
355 | if (IS_ERR(data)) | |
356 | return PTR_ERR(data); | |
357 | ||
10192bc6 | 358 | val = data->temp[t_input]; |
4453d736 GR |
359 | if (bit != JC42_ALARM_CRIT_BIT && (data->config & JC42_CFG_CRIT_ONLY)) |
360 | val = 0; | |
361 | return sprintf(buf, "%u\n", (val >> bit) & 1); | |
362 | } | |
363 | ||
10192bc6 GR |
364 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, t_input); |
365 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, set_temp, t_crit); | |
366 | static SENSOR_DEVICE_ATTR(temp1_min, S_IRUGO, show_temp, set_temp, t_min); | |
367 | static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, set_temp, t_max); | |
4453d736 | 368 | |
10192bc6 GR |
369 | static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_hyst, |
370 | set_temp_crit_hyst, t_crit); | |
371 | static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IRUGO, show_temp_hyst, NULL, t_max); | |
4453d736 GR |
372 | |
373 | static SENSOR_DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL, | |
374 | JC42_ALARM_CRIT_BIT); | |
375 | static SENSOR_DEVICE_ATTR(temp1_min_alarm, S_IRUGO, show_alarm, NULL, | |
376 | JC42_ALARM_MIN_BIT); | |
377 | static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, show_alarm, NULL, | |
378 | JC42_ALARM_MAX_BIT); | |
379 | ||
380 | static struct attribute *jc42_attributes[] = { | |
10192bc6 GR |
381 | &sensor_dev_attr_temp1_input.dev_attr.attr, |
382 | &sensor_dev_attr_temp1_crit.dev_attr.attr, | |
383 | &sensor_dev_attr_temp1_min.dev_attr.attr, | |
384 | &sensor_dev_attr_temp1_max.dev_attr.attr, | |
385 | &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, | |
386 | &sensor_dev_attr_temp1_max_hyst.dev_attr.attr, | |
4453d736 GR |
387 | &sensor_dev_attr_temp1_crit_alarm.dev_attr.attr, |
388 | &sensor_dev_attr_temp1_min_alarm.dev_attr.attr, | |
389 | &sensor_dev_attr_temp1_max_alarm.dev_attr.attr, | |
390 | NULL | |
391 | }; | |
392 | ||
587a1f16 | 393 | static umode_t jc42_attribute_mode(struct kobject *kobj, |
2c6315da CL |
394 | struct attribute *attr, int index) |
395 | { | |
396 | struct device *dev = container_of(kobj, struct device, kobj); | |
62f9a57c | 397 | struct jc42_data *data = dev_get_drvdata(dev); |
2c6315da CL |
398 | unsigned int config = data->config; |
399 | bool readonly; | |
400 | ||
10192bc6 | 401 | if (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr) |
2c6315da | 402 | readonly = config & JC42_CFG_TCRIT_LOCK; |
10192bc6 GR |
403 | else if (attr == &sensor_dev_attr_temp1_min.dev_attr.attr || |
404 | attr == &sensor_dev_attr_temp1_max.dev_attr.attr) | |
2c6315da | 405 | readonly = config & JC42_CFG_EVENT_LOCK; |
10192bc6 | 406 | else if (attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr) |
2c6315da CL |
407 | readonly = config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK); |
408 | else | |
409 | readonly = true; | |
410 | ||
411 | return S_IRUGO | (readonly ? 0 : S_IWUSR); | |
412 | } | |
413 | ||
4453d736 GR |
414 | static const struct attribute_group jc42_group = { |
415 | .attrs = jc42_attributes, | |
2c6315da | 416 | .is_visible = jc42_attribute_mode, |
4453d736 | 417 | }; |
62f9a57c | 418 | __ATTRIBUTE_GROUPS(jc42); |
4453d736 GR |
419 | |
420 | /* Return 0 if detection is successful, -ENODEV otherwise */ | |
f15df57d | 421 | static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info) |
4453d736 | 422 | { |
f15df57d | 423 | struct i2c_adapter *adapter = client->adapter; |
4453d736 GR |
424 | int i, config, cap, manid, devid; |
425 | ||
426 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | | |
427 | I2C_FUNC_SMBUS_WORD_DATA)) | |
428 | return -ENODEV; | |
429 | ||
f15df57d GR |
430 | cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP); |
431 | config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); | |
432 | manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID); | |
433 | devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID); | |
4453d736 GR |
434 | |
435 | if (cap < 0 || config < 0 || manid < 0 || devid < 0) | |
436 | return -ENODEV; | |
437 | ||
438 | if ((cap & 0xff00) || (config & 0xf800)) | |
439 | return -ENODEV; | |
440 | ||
441 | for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) { | |
442 | struct jc42_chips *chip = &jc42_chips[i]; | |
443 | if (manid == chip->manid && | |
444 | (devid & chip->devid_mask) == chip->devid) { | |
445 | strlcpy(info->type, "jc42", I2C_NAME_SIZE); | |
446 | return 0; | |
447 | } | |
448 | } | |
449 | return -ENODEV; | |
450 | } | |
451 | ||
f15df57d | 452 | static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id) |
4453d736 | 453 | { |
f15df57d | 454 | struct device *dev = &client->dev; |
62f9a57c GR |
455 | struct device *hwmon_dev; |
456 | struct jc42_data *data; | |
457 | int config, cap; | |
4453d736 | 458 | |
f15df57d GR |
459 | data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL); |
460 | if (!data) | |
461 | return -ENOMEM; | |
4453d736 | 462 | |
62f9a57c | 463 | data->client = client; |
f15df57d | 464 | i2c_set_clientdata(client, data); |
4453d736 GR |
465 | mutex_init(&data->update_lock); |
466 | ||
f15df57d GR |
467 | cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP); |
468 | if (cap < 0) | |
469 | return cap; | |
470 | ||
4453d736 GR |
471 | data->extended = !!(cap & JC42_CAP_RANGE); |
472 | ||
f15df57d GR |
473 | config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); |
474 | if (config < 0) | |
475 | return config; | |
476 | ||
4453d736 GR |
477 | data->orig_config = config; |
478 | if (config & JC42_CFG_SHUTDOWN) { | |
479 | config &= ~JC42_CFG_SHUTDOWN; | |
f15df57d | 480 | i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config); |
4453d736 GR |
481 | } |
482 | data->config = config; | |
483 | ||
62f9a57c GR |
484 | hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name, |
485 | data, | |
486 | jc42_groups); | |
650a2c02 | 487 | return PTR_ERR_OR_ZERO(hwmon_dev); |
4453d736 GR |
488 | } |
489 | ||
490 | static int jc42_remove(struct i2c_client *client) | |
491 | { | |
492 | struct jc42_data *data = i2c_get_clientdata(client); | |
5953e276 JD |
493 | |
494 | /* Restore original configuration except hysteresis */ | |
495 | if ((data->config & ~JC42_CFG_HYST_MASK) != | |
496 | (data->orig_config & ~JC42_CFG_HYST_MASK)) { | |
497 | int config; | |
498 | ||
499 | config = (data->orig_config & ~JC42_CFG_HYST_MASK) | |
500 | | (data->config & JC42_CFG_HYST_MASK); | |
501 | i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config); | |
502 | } | |
4453d736 GR |
503 | return 0; |
504 | } | |
505 | ||
d397276b GR |
506 | #ifdef CONFIG_PM |
507 | ||
508 | static int jc42_suspend(struct device *dev) | |
4453d736 | 509 | { |
62f9a57c | 510 | struct jc42_data *data = dev_get_drvdata(dev); |
4453d736 | 511 | |
d397276b GR |
512 | data->config |= JC42_CFG_SHUTDOWN; |
513 | i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, | |
514 | data->config); | |
515 | return 0; | |
516 | } | |
4453d736 | 517 | |
d397276b GR |
518 | static int jc42_resume(struct device *dev) |
519 | { | |
520 | struct jc42_data *data = dev_get_drvdata(dev); | |
4453d736 | 521 | |
d397276b GR |
522 | data->config &= ~JC42_CFG_SHUTDOWN; |
523 | i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, | |
524 | data->config); | |
525 | return 0; | |
526 | } | |
4453d736 | 527 | |
d397276b GR |
528 | static const struct dev_pm_ops jc42_dev_pm_ops = { |
529 | .suspend = jc42_suspend, | |
530 | .resume = jc42_resume, | |
531 | }; | |
4453d736 | 532 | |
d397276b GR |
533 | #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops) |
534 | #else | |
535 | #define JC42_DEV_PM_OPS NULL | |
536 | #endif /* CONFIG_PM */ | |
4453d736 | 537 | |
d397276b GR |
538 | static const struct i2c_device_id jc42_id[] = { |
539 | { "jc42", 0 }, | |
540 | { } | |
541 | }; | |
542 | MODULE_DEVICE_TABLE(i2c, jc42_id); | |
543 | ||
544 | static struct i2c_driver jc42_driver = { | |
eacc48ce | 545 | .class = I2C_CLASS_SPD | I2C_CLASS_HWMON, |
d397276b GR |
546 | .driver = { |
547 | .name = "jc42", | |
548 | .pm = JC42_DEV_PM_OPS, | |
549 | }, | |
550 | .probe = jc42_probe, | |
551 | .remove = jc42_remove, | |
552 | .id_table = jc42_id, | |
553 | .detect = jc42_detect, | |
554 | .address_list = normal_i2c, | |
555 | }; | |
4453d736 | 556 | |
f0967eea | 557 | module_i2c_driver(jc42_driver); |
4453d736 | 558 | |
bb9a80e5 | 559 | MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>"); |
4453d736 GR |
560 | MODULE_DESCRIPTION("JC42 driver"); |
561 | MODULE_LICENSE("GPL"); |