[linux-block.git] / drivers / hwmon / jc42.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
 *
 * Copyright (c) 2010  Ericsson AB.
 *
 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
 *
 * JC42.4 compliant temperature sensors are typically used on memory modules.
 */

#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/of.h>

/* Addresses to scan */
static const unsigned short normal_i2c[] = {
	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };

/* JC42 registers. All registers are 16 bit. */
#define JC42_REG_CAP		0x00
#define JC42_REG_CONFIG		0x01
#define JC42_REG_TEMP_UPPER	0x02
#define JC42_REG_TEMP_LOWER	0x03
#define JC42_REG_TEMP_CRITICAL	0x04
#define JC42_REG_TEMP		0x05
#define JC42_REG_MANID		0x06
#define JC42_REG_DEVICEID	0x07
#define JC42_REG_SMBUS		0x22 /* NXP and Atmel, possibly others? */

/* Status bits in temperature register */
#define JC42_ALARM_CRIT_BIT	15
#define JC42_ALARM_MAX_BIT	14
#define JC42_ALARM_MIN_BIT	13

/* Configuration register defines */
#define JC42_CFG_CRIT_ONLY	(1 << 2)
#define JC42_CFG_TCRIT_LOCK	(1 << 6)
#define JC42_CFG_EVENT_LOCK	(1 << 7)
#define JC42_CFG_SHUTDOWN	(1 << 8)
#define JC42_CFG_HYST_SHIFT	9
#define JC42_CFG_HYST_MASK	(0x03 << 9)

/* Capabilities */
#define JC42_CAP_RANGE		(1 << 2)

/* Manufacturer IDs */
#define ADT_MANID		0x11d4  /* Analog Devices */
#define ATMEL_MANID		0x001f  /* Atmel */
#define ATMEL_MANID2		0x1114	/* Atmel */
#define MAX_MANID		0x004d  /* Maxim */
#define IDT_MANID		0x00b3  /* IDT */
#define MCP_MANID		0x0054  /* Microchip */
#define NXP_MANID		0x1131  /* NXP Semiconductors */
#define ONS_MANID		0x1b09  /* ON Semiconductor */
#define STM_MANID		0x104a  /* ST Microelectronics */
#define GT_MANID		0x1c68	/* Giantec */
#define GT_MANID2		0x132d	/* Giantec, 2nd mfg ID */

/* SMBUS register */
#define SMBUS_STMOUT		BIT(7)  /* SMBus time-out, active low */

/* Supported chips */

/* Analog Devices */
#define ADT7408_DEVID		0x0801
#define ADT7408_DEVID_MASK	0xffff

/* Atmel */
#define AT30TS00_DEVID		0x8201
#define AT30TS00_DEVID_MASK	0xffff

#define AT30TSE004_DEVID	0x2200
#define AT30TSE004_DEVID_MASK	0xffff

/* Giantec */
#define GT30TS00_DEVID		0x2200
#define GT30TS00_DEVID_MASK	0xff00

#define GT34TS02_DEVID		0x3300
#define GT34TS02_DEVID_MASK	0xff00

/* IDT */
#define TSE2004_DEVID		0x2200
#define TSE2004_DEVID_MASK	0xff00

#define TS3000_DEVID		0x2900  /* Also matches TSE2002 */
#define TS3000_DEVID_MASK	0xff00

#define TS3001_DEVID		0x3000
#define TS3001_DEVID_MASK	0xff00

/* Maxim */
#define MAX6604_DEVID		0x3e00
#define MAX6604_DEVID_MASK	0xffff

/* Microchip */
#define MCP9804_DEVID		0x0200
#define MCP9804_DEVID_MASK	0xfffc

#define MCP9808_DEVID		0x0400
#define MCP9808_DEVID_MASK	0xfffc

#define MCP98242_DEVID		0x2000
#define MCP98242_DEVID_MASK	0xfffc

#define MCP98243_DEVID		0x2100
#define MCP98243_DEVID_MASK	0xfffc

#define MCP98244_DEVID		0x2200
#define MCP98244_DEVID_MASK	0xfffc

#define MCP9843_DEVID		0x0000	/* Also matches mcp9805 */
#define MCP9843_DEVID_MASK	0xfffe

/* NXP */
#define SE97_DEVID		0xa200
#define SE97_DEVID_MASK		0xfffc

#define SE98_DEVID		0xa100
#define SE98_DEVID_MASK		0xfffc

/* ON Semiconductor */
#define CAT6095_DEVID		0x0800	/* Also matches CAT34TS02 */
#define CAT6095_DEVID_MASK	0xffe0

#define CAT34TS02C_DEVID	0x0a00
#define CAT34TS02C_DEVID_MASK	0xfff0

#define CAT34TS04_DEVID		0x2200
#define CAT34TS04_DEVID_MASK	0xfff0

#define N34TS04_DEVID		0x2230
#define N34TS04_DEVID_MASK	0xfff0

/* ST Microelectronics */
#define STTS424_DEVID		0x0101
#define STTS424_DEVID_MASK	0xffff

#define STTS424E_DEVID		0x0000
#define STTS424E_DEVID_MASK	0xfffe

#define STTS2002_DEVID		0x0300
#define STTS2002_DEVID_MASK	0xffff

#define STTS2004_DEVID		0x2201
#define STTS2004_DEVID_MASK	0xffff

#define STTS3000_DEVID		0x0200
#define STTS3000_DEVID_MASK	0xffff

static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };

struct jc42_chips {
	u16 manid;
	u16 devid;
	u16 devid_mask;
};

static struct jc42_chips jc42_chips[] = {
	{ ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
	{ ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
	{ ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
	{ GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
	{ GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
	{ IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
	{ IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
	{ IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
	{ MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
	{ MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
	{ MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
	{ MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
	{ MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
	{ MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
	{ MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
	{ NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
	{ ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
	{ ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
	{ ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
	{ ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
	{ NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
	{ STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
	{ STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
	{ STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
	{ STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
	{ STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
};

enum temp_index {
	t_input = 0,
	t_crit,
	t_min,
	t_max,
	t_num_temp
};

static const u8 temp_regs[t_num_temp] = {
	[t_input] = JC42_REG_TEMP,
	[t_crit] = JC42_REG_TEMP_CRITICAL,
	[t_min] = JC42_REG_TEMP_LOWER,
	[t_max] = JC42_REG_TEMP_UPPER,
};

/* Each client has this additional data */
struct jc42_data {
	struct i2c_client *client;
	struct mutex	update_lock;	/* protect register access */
	bool		extended;	/* true if extended range supported */
	bool		valid;
	unsigned long	last_updated;	/* In jiffies */
	u16		orig_config;	/* original configuration */
	u16		config;		/* current configuration */
	u16		temp[t_num_temp];/* Temperatures */
};

#define JC42_TEMP_MIN_EXTENDED	(-40000)
#define JC42_TEMP_MIN		0
#define JC42_TEMP_MAX		125000

static u16 jc42_temp_to_reg(long temp, bool extended)
{
	int ntemp = clamp_val(temp,
			      extended ? JC42_TEMP_MIN_EXTENDED :
			      JC42_TEMP_MIN, JC42_TEMP_MAX);

	/* convert from 0.001 to 0.0625 resolution */
	return (ntemp * 2 / 125) & 0x1fff;
}

static int jc42_temp_from_reg(s16 reg)
{
	reg = sign_extend32(reg, 12);

	/* convert from 0.0625 to 0.001 resolution */
	return reg * 125 / 2;
}

static struct jc42_data *jc42_update_device(struct device *dev)
{
	struct jc42_data *data = dev_get_drvdata(dev);
	struct i2c_client *client = data->client;
	struct jc42_data *ret = data;
	int i, val;

	mutex_lock(&data->update_lock);

	if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
		for (i = 0; i < t_num_temp; i++) {
			val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
			if (val < 0) {
				ret = ERR_PTR(val);
				goto abort;
			}
			data->temp[i] = val;
		}
		data->last_updated = jiffies;
		data->valid = true;
	}
abort:
	mutex_unlock(&data->update_lock);
	return ret;
}

static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
		     u32 attr, int channel, long *val)
{
	struct jc42_data *data = jc42_update_device(dev);
	int temp, hyst;

	if (IS_ERR(data))
		return PTR_ERR(data);

	switch (attr) {
	case hwmon_temp_input:
		*val = jc42_temp_from_reg(data->temp[t_input]);
		return 0;
	case hwmon_temp_min:
		*val = jc42_temp_from_reg(data->temp[t_min]);
		return 0;
	case hwmon_temp_max:
		*val = jc42_temp_from_reg(data->temp[t_max]);
		return 0;
	case hwmon_temp_crit:
		*val = jc42_temp_from_reg(data->temp[t_crit]);
		return 0;
	case hwmon_temp_max_hyst:
		temp = jc42_temp_from_reg(data->temp[t_max]);
		hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
						>> JC42_CFG_HYST_SHIFT];
		*val = temp - hyst;
		return 0;
	case hwmon_temp_crit_hyst:
		temp = jc42_temp_from_reg(data->temp[t_crit]);
		hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
						>> JC42_CFG_HYST_SHIFT];
		*val = temp - hyst;
		return 0;
	case hwmon_temp_min_alarm:
		*val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1;
		return 0;
	case hwmon_temp_max_alarm:
		*val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1;
		return 0;
	case hwmon_temp_crit_alarm:
		*val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1;
		return 0;
	default:
		return -EOPNOTSUPP;
	}
}

static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
		      u32 attr, int channel, long val)
{
	struct jc42_data *data = dev_get_drvdata(dev);
	struct i2c_client *client = data->client;
	int diff, hyst;
	int ret;

	mutex_lock(&data->update_lock);

	switch (attr) {
	case hwmon_temp_min:
		data->temp[t_min] = jc42_temp_to_reg(val, data->extended);
		ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min],
						   data->temp[t_min]);
		break;
	case hwmon_temp_max:
		data->temp[t_max] = jc42_temp_to_reg(val, data->extended);
		ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max],
						   data->temp[t_max]);
		break;
	case hwmon_temp_crit:
		data->temp[t_crit] = jc42_temp_to_reg(val, data->extended);
		ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit],
						   data->temp[t_crit]);
		break;
	case hwmon_temp_crit_hyst:
		/*
		 * JC42.4 compliant chips only support four hysteresis values.
		 * Pick best choice and go from there.
		 */
		val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
						     : JC42_TEMP_MIN) - 6000,
				JC42_TEMP_MAX);
		diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
		hyst = 0;
		if (diff > 0) {
			if (diff < 2250)
				hyst = 1;	/* 1.5 degrees C */
			else if (diff < 4500)
				hyst = 2;	/* 3.0 degrees C */
			else
				hyst = 3;	/* 6.0 degrees C */
		}
		data->config = (data->config & ~JC42_CFG_HYST_MASK) |
				(hyst << JC42_CFG_HYST_SHIFT);
		ret = i2c_smbus_write_word_swapped(data->client,
						   JC42_REG_CONFIG,
						   data->config);
		break;
	default:
		ret = -EOPNOTSUPP;
		break;
	}

	mutex_unlock(&data->update_lock);

	return ret;
}

static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
			       u32 attr, int channel)
{
	const struct jc42_data *data = _data;
	unsigned int config = data->config;
	umode_t mode = 0444;

	switch (attr) {
	case hwmon_temp_min:
	case hwmon_temp_max:
		if (!(config & JC42_CFG_EVENT_LOCK))
			mode |= 0200;
		break;
	case hwmon_temp_crit:
		if (!(config & JC42_CFG_TCRIT_LOCK))
			mode |= 0200;
		break;
	case hwmon_temp_crit_hyst:
		if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
			mode |= 0200;
		break;
	case hwmon_temp_input:
	case hwmon_temp_max_hyst:
	case hwmon_temp_min_alarm:
	case hwmon_temp_max_alarm:
	case hwmon_temp_crit_alarm:
		break;
	default:
		mode = 0;
		break;
	}
	return mode;
}

/* Return 0 if detection is successful, -ENODEV otherwise */
static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
{
	struct i2c_adapter *adapter = client->adapter;
	int i, config, cap, manid, devid;

	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
				     I2C_FUNC_SMBUS_WORD_DATA))
		return -ENODEV;

	cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
	config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
	manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
	devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);

	if (cap < 0 || config < 0 || manid < 0 || devid < 0)
		return -ENODEV;

	if ((cap & 0xff00) || (config & 0xf800))
		return -ENODEV;

	for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
		struct jc42_chips *chip = &jc42_chips[i];
		if (manid == chip->manid &&
		    (devid & chip->devid_mask) == chip->devid) {
			strlcpy(info->type, "jc42", I2C_NAME_SIZE);
			return 0;
		}
	}
	return -ENODEV;
}

static const struct hwmon_channel_info *jc42_info[] = {
	HWMON_CHANNEL_INFO(temp,
			   HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
			   HWMON_T_CRIT | HWMON_T_MAX_HYST |
			   HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
			   HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
	NULL
};

static const struct hwmon_ops jc42_hwmon_ops = {
	.is_visible = jc42_is_visible,
	.read = jc42_read,
	.write = jc42_write,
};

static const struct hwmon_chip_info jc42_chip_info = {
	.ops = &jc42_hwmon_ops,
	.info = jc42_info,
};

static int jc42_probe(struct i2c_client *client)
{
	struct device *dev = &client->dev;
	struct device *hwmon_dev;
	struct jc42_data *data;
	int config, cap;

	data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->client = client;
	i2c_set_clientdata(client, data);
	mutex_init(&data->update_lock);

	cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
	if (cap < 0)
		return cap;

	data->extended = !!(cap & JC42_CAP_RANGE);

	if (device_property_read_bool(dev, "smbus-timeout-disable")) {
		int smbus;

		/*
		 * Not all chips support this register, but from a
		 * quick read of various datasheets no chip appears
		 * incompatible with the below attempt to disable
		 * the timeout. And the whole thing is opt-in...
		 */
		smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS);
		if (smbus < 0)
			return smbus;
		i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS,
					     smbus | SMBUS_STMOUT);
	}

	config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
	if (config < 0)
		return config;

	data->orig_config = config;
	if (config & JC42_CFG_SHUTDOWN) {
		config &= ~JC42_CFG_SHUTDOWN;
		i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
	}
	data->config = config;

	hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
							 data, &jc42_chip_info,
							 NULL);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static int jc42_remove(struct i2c_client *client)
{
	struct jc42_data *data = i2c_get_clientdata(client);

	/* Restore original configuration except hysteresis */
	if ((data->config & ~JC42_CFG_HYST_MASK) !=
	    (data->orig_config & ~JC42_CFG_HYST_MASK)) {
		int config;

		config = (data->orig_config & ~JC42_CFG_HYST_MASK)
		  | (data->config & JC42_CFG_HYST_MASK);
		i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
	}
	return 0;
}

#ifdef CONFIG_PM

static int jc42_suspend(struct device *dev)
{
	struct jc42_data *data = dev_get_drvdata(dev);

	data->config |= JC42_CFG_SHUTDOWN;
	i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
				     data->config);
	return 0;
}

static int jc42_resume(struct device *dev)
{
	struct jc42_data *data = dev_get_drvdata(dev);

	data->config &= ~JC42_CFG_SHUTDOWN;
	i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
				     data->config);
	return 0;
}

static const struct dev_pm_ops jc42_dev_pm_ops = {
	.suspend = jc42_suspend,
	.resume = jc42_resume,
};

#define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
#else
#define JC42_DEV_PM_OPS NULL
#endif /* CONFIG_PM */

static const struct i2c_device_id jc42_id[] = {
	{ "jc42", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, jc42_id);

#ifdef CONFIG_OF
static const struct of_device_id jc42_of_ids[] = {
	{ .compatible = "jedec,jc-42.4-temp", },
	{ }
};
MODULE_DEVICE_TABLE(of, jc42_of_ids);
#endif

static struct i2c_driver jc42_driver = {
	.class		= I2C_CLASS_SPD | I2C_CLASS_HWMON,
	.driver = {
		.name	= "jc42",
		.pm = JC42_DEV_PM_OPS,
		.of_match_table = of_match_ptr(jc42_of_ids),
	},
	.probe_new	= jc42_probe,
	.remove		= jc42_remove,
	.id_table	= jc42_id,
	.detect		= jc42_detect,
	.address_list	= normal_i2c,
};

module_i2c_driver(jc42_driver);

MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
MODULE_DESCRIPTION("JC42 driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
74ba9207	1	// SPDX-License-Identifier: GPL-2.0-or-later
4453d736 GR	2	/*
	3	* jc42.c - driver for Jedec JC42.4 compliant temperature sensors
	4	*
	5	* Copyright (c) 2010 Ericsson AB.
	6	*
	7	* Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
	8	*
	9	* JC42.4 compliant temperature sensors are typically used on memory modules.
4453d736 GR	10	*/
4453d736 GR	11
68615eb0	12	#include <linux/bitops.h>
4453d736 GR	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/slab.h>
	16	#include <linux/jiffies.h>
	17	#include <linux/i2c.h>
	18	#include <linux/hwmon.h>
4453d736 GR	19	#include <linux/err.h>
4453d736 GR	20	#include <linux/mutex.h>
803decce	21	#include <linux/of.h>
4453d736 GR	22
	23	/* Addresses to scan */
	24	static const unsigned short normal_i2c[] = {
	25	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
	26
	27	/* JC42 registers. All registers are 16 bit. */
	28	#define JC42_REG_CAP 0x00
	29	#define JC42_REG_CONFIG 0x01
	30	#define JC42_REG_TEMP_UPPER 0x02
	31	#define JC42_REG_TEMP_LOWER 0x03
	32	#define JC42_REG_TEMP_CRITICAL 0x04
	33	#define JC42_REG_TEMP 0x05
	34	#define JC42_REG_MANID 0x06
	35	#define JC42_REG_DEVICEID 0x07
68615eb0	36	#define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
4453d736 GR	37
	38	/* Status bits in temperature register */
	39	#define JC42_ALARM_CRIT_BIT 15
	40	#define JC42_ALARM_MAX_BIT 14
	41	#define JC42_ALARM_MIN_BIT 13
	42
	43	/* Configuration register defines */
	44	#define JC42_CFG_CRIT_ONLY (1 << 2)
2c6315da CL	45	#define JC42_CFG_TCRIT_LOCK (1 << 6)
2c6315da CL	46	#define JC42_CFG_EVENT_LOCK (1 << 7)
4453d736 GR	47	#define JC42_CFG_SHUTDOWN (1 << 8)
4453d736 GR	48	#define JC42_CFG_HYST_SHIFT 9
2ccc8731	49	#define JC42_CFG_HYST_MASK (0x03 << 9)
4453d736 GR	50
	51	/* Capabilities */
	52	#define JC42_CAP_RANGE (1 << 2)
	53
	54	/* Manufacturer IDs */
	55	#define ADT_MANID 0x11d4 /* Analog Devices */
1bd612a2	56	#define ATMEL_MANID 0x001f /* Atmel */
175c490c	57	#define ATMEL_MANID2 0x1114 /* Atmel */
4453d736 GR	58	#define MAX_MANID 0x004d /* Maxim */
	59	#define IDT_MANID 0x00b3 /* IDT */
	60	#define MCP_MANID 0x0054 /* Microchip */
	61	#define NXP_MANID 0x1131 /* NXP Semiconductors */
	62	#define ONS_MANID 0x1b09 /* ON Semiconductor */
	63	#define STM_MANID 0x104a /* ST Microelectronics */
568003ce GR	64	#define GT_MANID 0x1c68 /* Giantec */
568003ce GR	65	#define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */
4453d736	66
68615eb0 PR	67	/* SMBUS register */
	68	#define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
	69
4453d736 GR	70	/* Supported chips */
	71
	72	/* Analog Devices */
	73	#define ADT7408_DEVID 0x0801
	74	#define ADT7408_DEVID_MASK 0xffff
	75
1bd612a2 GR	76	/* Atmel */
	77	#define AT30TS00_DEVID 0x8201
	78	#define AT30TS00_DEVID_MASK 0xffff
	79
175c490c GR	80	#define AT30TSE004_DEVID 0x2200
	81	#define AT30TSE004_DEVID_MASK 0xffff
	82
568003ce GR	83	/* Giantec */
	84	#define GT30TS00_DEVID 0x2200
	85	#define GT30TS00_DEVID_MASK 0xff00
	86
	87	#define GT34TS02_DEVID 0x3300
	88	#define GT34TS02_DEVID_MASK 0xff00
	89
4453d736	90	/* IDT */
0ea2f1db GR	91	#define TSE2004_DEVID 0x2200
0ea2f1db GR	92	#define TSE2004_DEVID_MASK 0xff00
4453d736	93
0ea2f1db GR	94	#define TS3000_DEVID 0x2900 /* Also matches TSE2002 */
	95	#define TS3000_DEVID_MASK 0xff00
	96
	97	#define TS3001_DEVID 0x3000
	98	#define TS3001_DEVID_MASK 0xff00
1bd612a2	99
4453d736 GR	100	/* Maxim */
	101	#define MAX6604_DEVID 0x3e00
	102	#define MAX6604_DEVID_MASK 0xffff
	103
	104	/* Microchip */
1bd612a2 GR	105	#define MCP9804_DEVID 0x0200
	106	#define MCP9804_DEVID_MASK 0xfffc
	107
a31887dc AS	108	#define MCP9808_DEVID 0x0400
	109	#define MCP9808_DEVID_MASK 0xfffc
	110
4453d736 GR	111	#define MCP98242_DEVID 0x2000
	112	#define MCP98242_DEVID_MASK 0xfffc
	113
	114	#define MCP98243_DEVID 0x2100
	115	#define MCP98243_DEVID_MASK 0xfffc
	116
d4768280 GR	117	#define MCP98244_DEVID 0x2200
	118	#define MCP98244_DEVID_MASK 0xfffc
	119
4453d736 GR	120	#define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */
	121	#define MCP9843_DEVID_MASK 0xfffe
	122
	123	/* NXP */
	124	#define SE97_DEVID 0xa200
	125	#define SE97_DEVID_MASK 0xfffc
	126
	127	#define SE98_DEVID 0xa100
	128	#define SE98_DEVID_MASK 0xfffc
	129
	130	/* ON Semiconductor */
	131	#define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */
	132	#define CAT6095_DEVID_MASK 0xffe0
	133
99b981b2 GR	134	#define CAT34TS02C_DEVID 0x0a00
	135	#define CAT34TS02C_DEVID_MASK 0xfff0
	136
568003ce GR	137	#define CAT34TS04_DEVID 0x2200
	138	#define CAT34TS04_DEVID_MASK 0xfff0
	139
bf4d8430 GR	140	#define N34TS04_DEVID 0x2230
	141	#define N34TS04_DEVID_MASK 0xfff0
	142
4453d736 GR	143	/* ST Microelectronics */
	144	#define STTS424_DEVID 0x0101
	145	#define STTS424_DEVID_MASK 0xffff
	146
	147	#define STTS424E_DEVID 0x0000
	148	#define STTS424E_DEVID_MASK 0xfffe
	149
4de86126 JD	150	#define STTS2002_DEVID 0x0300
	151	#define STTS2002_DEVID_MASK 0xffff
	152
175c490c GR	153	#define STTS2004_DEVID 0x2201
	154	#define STTS2004_DEVID_MASK 0xffff
	155
4de86126 JD	156	#define STTS3000_DEVID 0x0200
	157	#define STTS3000_DEVID_MASK 0xffff
	158
4453d736 GR	159	static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
	160
	161	struct jc42_chips {
	162	u16 manid;
	163	u16 devid;
	164	u16 devid_mask;
	165	};
	166
	167	static struct jc42_chips jc42_chips[] = {
	168	{ ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
1bd612a2	169	{ ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
175c490c	170	{ ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
568003ce GR	171	{ GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
568003ce GR	172	{ GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
0ea2f1db GR	173	{ IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
	174	{ IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
	175	{ IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
4453d736	176	{ MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
1bd612a2	177	{ MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
a31887dc	178	{ MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
4453d736 GR	179	{ MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
4453d736 GR	180	{ MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
d4768280	181	{ MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
4453d736 GR	182	{ MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
	183	{ NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
	184	{ ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
99b981b2	185	{ ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
568003ce	186	{ ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
bf4d8430	187	{ ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
4453d736 GR	188	{ NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
	189	{ STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
	190	{ STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
4de86126	191	{ STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
175c490c	192	{ STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
4de86126	193	{ STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
4453d736 GR	194	};
4453d736 GR	195
10192bc6 GR	196	enum temp_index {
	197	t_input = 0,
	198	t_crit,
	199	t_min,
	200	t_max,
	201	t_num_temp
	202	};
	203
	204	static const u8 temp_regs[t_num_temp] = {
	205	[t_input] = JC42_REG_TEMP,
	206	[t_crit] = JC42_REG_TEMP_CRITICAL,
	207	[t_min] = JC42_REG_TEMP_LOWER,
	208	[t_max] = JC42_REG_TEMP_UPPER,
	209	};
	210
4453d736 GR	211	/* Each client has this additional data */
4453d736 GR	212	struct jc42_data {
62f9a57c	213	struct i2c_client *client;
4453d736 GR	214	struct mutex update_lock; /* protect register access */
	215	bool extended; /* true if extended range supported */
	216	bool valid;
	217	unsigned long last_updated; /* In jiffies */
	218	u16 orig_config; /* original configuration */
	219	u16 config; /* current configuration */
10192bc6	220	u16 temp[t_num_temp];/* Temperatures */
4453d736 GR	221	};
4453d736 GR	222
4453d736 GR	223	#define JC42_TEMP_MIN_EXTENDED (-40000)
	224	#define JC42_TEMP_MIN 0
	225	#define JC42_TEMP_MAX 125000
	226
3a05633b	227	static u16 jc42_temp_to_reg(long temp, bool extended)
4453d736	228	{
2a844c14 GR	229	int ntemp = clamp_val(temp,
	230	extended ? JC42_TEMP_MIN_EXTENDED :
	231	JC42_TEMP_MIN, JC42_TEMP_MAX);
4453d736 GR	232
	233	/* convert from 0.001 to 0.0625 resolution */
	234	return (ntemp * 2 / 125) & 0x1fff;
	235	}
	236
	237	static int jc42_temp_from_reg(s16 reg)
	238	{
bca6a1ad	239	reg = sign_extend32(reg, 12);
4453d736 GR	240
	241	/* convert from 0.0625 to 0.001 resolution */
	242	return reg * 125 / 2;
	243	}
	244
d397276b GR	245	static struct jc42_data jc42_update_device(struct device dev)
	246	{
	247	struct jc42_data *data = dev_get_drvdata(dev);
	248	struct i2c_client *client = data->client;
	249	struct jc42_data *ret = data;
10192bc6	250	int i, val;
d397276b GR	251
	252	mutex_lock(&data->update_lock);
	253
	254	if (time_after(jiffies, data->last_updated + HZ) \|\| !data->valid) {
10192bc6 GR	255	for (i = 0; i < t_num_temp; i++) {
	256	val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
	257	if (val < 0) {
	258	ret = ERR_PTR(val);
	259	goto abort;
	260	}
	261	data->temp[i] = val;
d397276b	262	}
d397276b GR	263	data->last_updated = jiffies;
	264	data->valid = true;
	265	}
	266	abort:
	267	mutex_unlock(&data->update_lock);
	268	return ret;
	269	}
	270
fcc448cf GR	271	static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
fcc448cf GR	272	u32 attr, int channel, long *val)
4453d736 GR	273	{
	274	struct jc42_data *data = jc42_update_device(dev);
	275	int temp, hyst;
	276
	277	if (IS_ERR(data))
	278	return PTR_ERR(data);
	279
fcc448cf GR	280	switch (attr) {
	281	case hwmon_temp_input:
	282	*val = jc42_temp_from_reg(data->temp[t_input]);
	283	return 0;
	284	case hwmon_temp_min:
	285	*val = jc42_temp_from_reg(data->temp[t_min]);
	286	return 0;
	287	case hwmon_temp_max:
	288	*val = jc42_temp_from_reg(data->temp[t_max]);
	289	return 0;
	290	case hwmon_temp_crit:
	291	*val = jc42_temp_from_reg(data->temp[t_crit]);
	292	return 0;
	293	case hwmon_temp_max_hyst:
	294	temp = jc42_temp_from_reg(data->temp[t_max]);
	295	hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
	296	>> JC42_CFG_HYST_SHIFT];
	297	*val = temp - hyst;
	298	return 0;
	299	case hwmon_temp_crit_hyst:
	300	temp = jc42_temp_from_reg(data->temp[t_crit]);
	301	hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
	302	>> JC42_CFG_HYST_SHIFT];
	303	*val = temp - hyst;
	304	return 0;
	305	case hwmon_temp_min_alarm:
	306	*val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1;
	307	return 0;
	308	case hwmon_temp_max_alarm:
	309	*val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1;
	310	return 0;
	311	case hwmon_temp_crit_alarm:
	312	*val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1;
	313	return 0;
	314	default:
	315	return -EOPNOTSUPP;
	316	}
4453d736 GR	317	}
4453d736 GR	318
fcc448cf GR	319	static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
fcc448cf GR	320	u32 attr, int channel, long val)
10192bc6	321	{
10192bc6	322	struct jc42_data *data = dev_get_drvdata(dev);
fcc448cf GR	323	struct i2c_client *client = data->client;
	324	int diff, hyst;
	325	int ret;
4453d736	326
10192bc6	327	mutex_lock(&data->update_lock);
4453d736	328
fcc448cf GR	329	switch (attr) {
	330	case hwmon_temp_min:
	331	data->temp[t_min] = jc42_temp_to_reg(val, data->extended);
	332	ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min],
	333	data->temp[t_min]);
	334	break;
	335	case hwmon_temp_max:
	336	data->temp[t_max] = jc42_temp_to_reg(val, data->extended);
	337	ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max],
	338	data->temp[t_max]);
	339	break;
	340	case hwmon_temp_crit:
	341	data->temp[t_crit] = jc42_temp_to_reg(val, data->extended);
	342	ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit],
	343	data->temp[t_crit]);
	344	break;
	345	case hwmon_temp_crit_hyst:
	346	/*
	347	* JC42.4 compliant chips only support four hysteresis values.
	348	* Pick best choice and go from there.
	349	*/
	350	val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
	351	: JC42_TEMP_MIN) - 6000,
	352	JC42_TEMP_MAX);
	353	diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
	354	hyst = 0;
	355	if (diff > 0) {
	356	if (diff < 2250)
	357	hyst = 1; /* 1.5 degrees C */
	358	else if (diff < 4500)
	359	hyst = 2; /* 3.0 degrees C */
	360	else
	361	hyst = 3; /* 6.0 degrees C */
	362	}
	363	data->config = (data->config & ~JC42_CFG_HYST_MASK) \|
	364	(hyst << JC42_CFG_HYST_SHIFT);
	365	ret = i2c_smbus_write_word_swapped(data->client,
	366	JC42_REG_CONFIG,
	367	data->config);
	368	break;
	369	default:
	370	ret = -EOPNOTSUPP;
	371	break;
4453d736 GR	372	}
4453d736 GR	373
4453d736	374	mutex_unlock(&data->update_lock);
4453d736	375
fcc448cf	376	return ret;
4453d736 GR	377	}
4453d736 GR	378
fcc448cf GR	379	static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
fcc448cf GR	380	u32 attr, int channel)
2c6315da	381	{
fcc448cf	382	const struct jc42_data *data = _data;
2c6315da	383	unsigned int config = data->config;
4820d511	384	umode_t mode = 0444;
fcc448cf GR	385
	386	switch (attr) {
	387	case hwmon_temp_min:
	388	case hwmon_temp_max:
	389	if (!(config & JC42_CFG_EVENT_LOCK))
4820d511	390	mode \|= 0200;
fcc448cf GR	391	break;
	392	case hwmon_temp_crit:
	393	if (!(config & JC42_CFG_TCRIT_LOCK))
4820d511	394	mode \|= 0200;
fcc448cf GR	395	break;
	396	case hwmon_temp_crit_hyst:
	397	if (!(config & (JC42_CFG_EVENT_LOCK \| JC42_CFG_TCRIT_LOCK)))
4820d511	398	mode \|= 0200;
fcc448cf GR	399	break;
	400	case hwmon_temp_input:
	401	case hwmon_temp_max_hyst:
	402	case hwmon_temp_min_alarm:
	403	case hwmon_temp_max_alarm:
	404	case hwmon_temp_crit_alarm:
	405	break;
	406	default:
	407	mode = 0;
	408	break;
	409	}
	410	return mode;
2c6315da CL	411	}
2c6315da CL	412
4453d736	413	/* Return 0 if detection is successful, -ENODEV otherwise */
f15df57d	414	static int jc42_detect(struct i2c_client client, struct i2c_board_info info)
4453d736	415	{
f15df57d	416	struct i2c_adapter *adapter = client->adapter;
4453d736 GR	417	int i, config, cap, manid, devid;
	418
	419	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA \|
	420	I2C_FUNC_SMBUS_WORD_DATA))
	421	return -ENODEV;
	422
f15df57d GR	423	cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
	424	config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
	425	manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
	426	devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
4453d736 GR	427
	428	if (cap < 0 \|\| config < 0 \|\| manid < 0 \|\| devid < 0)
	429	return -ENODEV;
	430
	431	if ((cap & 0xff00) \|\| (config & 0xf800))
	432	return -ENODEV;
	433
	434	for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
	435	struct jc42_chips *chip = &jc42_chips[i];
	436	if (manid == chip->manid &&
	437	(devid & chip->devid_mask) == chip->devid) {
	438	strlcpy(info->type, "jc42", I2C_NAME_SIZE);
	439	return 0;
	440	}
	441	}
	442	return -ENODEV;
	443	}
	444
fcc448cf	445	static const struct hwmon_channel_info *jc42_info[] = {
1eade10f GR	446	HWMON_CHANNEL_INFO(temp,
	447	HWMON_T_INPUT \| HWMON_T_MIN \| HWMON_T_MAX \|
	448	HWMON_T_CRIT \| HWMON_T_MAX_HYST \|
	449	HWMON_T_CRIT_HYST \| HWMON_T_MIN_ALARM \|
	450	HWMON_T_MAX_ALARM \| HWMON_T_CRIT_ALARM),
fcc448cf GR	451	NULL
	452	};
	453
	454	static const struct hwmon_ops jc42_hwmon_ops = {
	455	.is_visible = jc42_is_visible,
	456	.read = jc42_read,
	457	.write = jc42_write,
	458	};
	459
	460	static const struct hwmon_chip_info jc42_chip_info = {
	461	.ops = &jc42_hwmon_ops,
	462	.info = jc42_info,
	463	};
	464
67487038	465	static int jc42_probe(struct i2c_client *client)
4453d736	466	{
f15df57d	467	struct device *dev = &client->dev;
62f9a57c GR	468	struct device *hwmon_dev;
	469	struct jc42_data *data;
	470	int config, cap;
4453d736	471
f15df57d GR	472	data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
	473	if (!data)
	474	return -ENOMEM;
4453d736	475
62f9a57c	476	data->client = client;
f15df57d	477	i2c_set_clientdata(client, data);
4453d736 GR	478	mutex_init(&data->update_lock);
4453d736 GR	479
f15df57d GR	480	cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
	481	if (cap < 0)
	482	return cap;
	483
4453d736 GR	484	data->extended = !!(cap & JC42_CAP_RANGE);
4453d736 GR	485
68615eb0 PR	486	if (device_property_read_bool(dev, "smbus-timeout-disable")) {
	487	int smbus;
	488
	489	/*
	490	* Not all chips support this register, but from a
	491	* quick read of various datasheets no chip appears
	492	* incompatible with the below attempt to disable
	493	* the timeout. And the whole thing is opt-in...
	494	*/
	495	smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS);
	496	if (smbus < 0)
	497	return smbus;
	498	i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS,
	499	smbus \| SMBUS_STMOUT);
	500	}
	501
f15df57d GR	502	config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
	503	if (config < 0)
	504	return config;
	505
4453d736 GR	506	data->orig_config = config;
	507	if (config & JC42_CFG_SHUTDOWN) {
	508	config &= ~JC42_CFG_SHUTDOWN;
f15df57d	509	i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
4453d736 GR	510	}
	511	data->config = config;
	512
c843b382	513	hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
fcc448cf GR	514	data, &jc42_chip_info,
fcc448cf GR	515	NULL);
650a2c02	516	return PTR_ERR_OR_ZERO(hwmon_dev);
4453d736 GR	517	}
	518
	519	static int jc42_remove(struct i2c_client *client)
	520	{
	521	struct jc42_data *data = i2c_get_clientdata(client);
5953e276 JD	522
	523	/* Restore original configuration except hysteresis */
	524	if ((data->config & ~JC42_CFG_HYST_MASK) !=
	525	(data->orig_config & ~JC42_CFG_HYST_MASK)) {
	526	int config;
	527
	528	config = (data->orig_config & ~JC42_CFG_HYST_MASK)
	529	\| (data->config & JC42_CFG_HYST_MASK);
	530	i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
	531	}
4453d736 GR	532	return 0;
	533	}
	534
d397276b GR	535	#ifdef CONFIG_PM
	536
	537	static int jc42_suspend(struct device *dev)
4453d736	538	{
62f9a57c	539	struct jc42_data *data = dev_get_drvdata(dev);
4453d736	540
d397276b GR	541	data->config \|= JC42_CFG_SHUTDOWN;
	542	i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
	543	data->config);
	544	return 0;
	545	}
4453d736	546
d397276b GR	547	static int jc42_resume(struct device *dev)
	548	{
	549	struct jc42_data *data = dev_get_drvdata(dev);
4453d736	550
d397276b GR	551	data->config &= ~JC42_CFG_SHUTDOWN;
	552	i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
	553	data->config);
	554	return 0;
	555	}
4453d736	556
d397276b GR	557	static const struct dev_pm_ops jc42_dev_pm_ops = {
	558	.suspend = jc42_suspend,
	559	.resume = jc42_resume,
	560	};
4453d736	561
d397276b GR	562	#define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
	563	#else
	564	#define JC42_DEV_PM_OPS NULL
	565	#endif /* CONFIG_PM */
4453d736	566
d397276b GR	567	static const struct i2c_device_id jc42_id[] = {
	568	{ "jc42", 0 },
	569	{ }
	570	};
	571	MODULE_DEVICE_TABLE(i2c, jc42_id);
	572
803decce GR	573	#ifdef CONFIG_OF
	574	static const struct of_device_id jc42_of_ids[] = {
	575	{ .compatible = "jedec,jc-42.4-temp", },
	576	{ }
	577	};
	578	MODULE_DEVICE_TABLE(of, jc42_of_ids);
	579	#endif
	580
d397276b	581	static struct i2c_driver jc42_driver = {
eacc48ce	582	.class = I2C_CLASS_SPD \| I2C_CLASS_HWMON,
d397276b GR	583	.driver = {
	584	.name = "jc42",
	585	.pm = JC42_DEV_PM_OPS,
803decce	586	.of_match_table = of_match_ptr(jc42_of_ids),
d397276b	587	},
67487038	588	.probe_new = jc42_probe,
d397276b GR	589	.remove = jc42_remove,
	590	.id_table = jc42_id,
	591	.detect = jc42_detect,
	592	.address_list = normal_i2c,
	593	};
4453d736	594
f0967eea	595	module_i2c_driver(jc42_driver);
4453d736	596
bb9a80e5	597	MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4453d736 GR	598	MODULE_DESCRIPTION("JC42 driver");
4453d736 GR	599	MODULE_LICENSE("GPL");