projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Linux 3.13
[linux-2.6-block.git] / drivers / hwmon / it87.c
CommitLineData
1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
13 * Supports: IT8705F Super I/O chip w/LPC interface
14 * IT8712F Super I/O chip w/LPC interface
15 * IT8716F Super I/O chip w/LPC interface
16 * IT8718F Super I/O chip w/LPC interface
17 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 18 * IT8721F Super I/O chip w/LPC interface
5f2dc798 19 * IT8726F Super I/O chip w/LPC interface
16b5dda2 20 * IT8728F Super I/O chip w/LPC interface
44c1bcd4 21 * IT8758E Super I/O chip w/LPC interface
b0636707
GR		 22 * IT8771E Super I/O chip w/LPC interface
23 * IT8772E Super I/O chip w/LPC interface
0531d98b
GR		 24 * IT8782F Super I/O chip w/LPC interface
25 * IT8783E/F Super I/O chip w/LPC interface
5f2dc798
JD		 26 * Sis950 A clone of the IT8705F
27 *
28 * Copyright (C) 2001 Chris Gauthron
29 * Copyright (C) 2005-2010 Jean Delvare <khali@linux-fr.org>
30 *
31 * This program is free software; you can redistribute it and/or modify
32 * it under the terms of the GNU General Public License as published by
33 * the Free Software Foundation; either version 2 of the License, or
34 * (at your option) any later version.
35 *
36 * This program is distributed in the hope that it will be useful,
37 * but WITHOUT ANY WARRANTY; without even the implied warranty of
38 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
39 * GNU General Public License for more details.
40 *
41 * You should have received a copy of the GNU General Public License
42 * along with this program; if not, write to the Free Software
43 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
44 */
1da177e4 45
a8ca1037
JP		 46#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
47
1da177e4
LT		 48#include <linux/module.h>
49#include <linux/init.h>
50#include <linux/slab.h>
51#include <linux/jiffies.h>
b74f3fdd 52#include <linux/platform_device.h>
943b0830 53#include <linux/hwmon.h>
303760b4
JD		 54#include <linux/hwmon-sysfs.h>
55#include <linux/hwmon-vid.h>
943b0830 56#include <linux/err.h>
9a61bf63 57#include <linux/mutex.h>
87808be4 58#include <linux/sysfs.h>
98dd22c3
JD		 59#include <linux/string.h>
60#include <linux/dmi.h>
b9acb64a 61#include <linux/acpi.h>
6055fae8 62#include <linux/io.h>
1da177e4 63
b74f3fdd 64#define DRVNAME "it87"
1da177e4 65
b0636707
GR		 66enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8771,
67 it8772, it8782, it8783 };
1da177e4 68
67b671bc
JD		 69static unsigned short force_id;
70module_param(force_id, ushort, 0);
71MODULE_PARM_DESC(force_id, "Override the detected device ID");
72
b74f3fdd 73static struct platform_device *pdev;
74
1da177e4
LT		 75#define REG 0x2e /* The register to read/write */
76#define DEV 0x07 /* Register: Logical device select */
77#define VAL 0x2f /* The value to read/write */
78#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 79
80/* The device with the IT8718F/IT8720F VID value in it */
81#define GPIO 0x07
82
1da177e4
LT		 83#define DEVID 0x20 /* Register: Device ID */
84#define DEVREV 0x22 /* Register: Device Revision */
85
5b0380c9 86static inline int superio_inb(int reg)
1da177e4
LT		 87{
88 outb(reg, REG);
89 return inb(VAL);
90}
91
5b0380c9 92static inline void superio_outb(int reg, int val)
436cad2a
JD		 93{
94 outb(reg, REG);
95 outb(val, VAL);
96}
97
1da177e4
LT		 98static int superio_inw(int reg)
99{
100 int val;
101 outb(reg++, REG);
102 val = inb(VAL) << 8;
103 outb(reg, REG);
104 val |= inb(VAL);
105 return val;
106}
107
5b0380c9 108static inline void superio_select(int ldn)
1da177e4
LT		 109{
110 outb(DEV, REG);
87673dd7 111 outb(ldn, VAL);
1da177e4
LT		 112}
113
5b0380c9 114static inline int superio_enter(void)
1da177e4 115{
5b0380c9
NG		 116 /*
117 * Try to reserve REG and REG + 1 for exclusive access.
118 */
119 if (!request_muxed_region(REG, 2, DRVNAME))
120 return -EBUSY;
121
1da177e4
LT		 122 outb(0x87, REG);
123 outb(0x01, REG);
124 outb(0x55, REG);
125 outb(0x55, REG);
5b0380c9 126 return 0;
1da177e4
LT		 127}
128
5b0380c9 129static inline void superio_exit(void)
1da177e4
LT		 130{
131 outb(0x02, REG);
132 outb(0x02, VAL);
5b0380c9 133 release_region(REG, 2);
1da177e4
LT		 134}
135
87673dd7 136/* Logical device 4 registers */
1da177e4
LT		 137#define IT8712F_DEVID 0x8712
138#define IT8705F_DEVID 0x8705
17d648bf 139#define IT8716F_DEVID 0x8716
87673dd7 140#define IT8718F_DEVID 0x8718
b4da93e4 141#define IT8720F_DEVID 0x8720
44c1bcd4 142#define IT8721F_DEVID 0x8721
08a8f6e9 143#define IT8726F_DEVID 0x8726
16b5dda2 144#define IT8728F_DEVID 0x8728
b0636707
GR		 145#define IT8771E_DEVID 0x8771
146#define IT8772E_DEVID 0x8772
0531d98b
GR		 147#define IT8782F_DEVID 0x8782
148#define IT8783E_DEVID 0x8783
1da177e4
LT		 149#define IT87_ACT_REG 0x30
150#define IT87_BASE_REG 0x60
151
87673dd7 152/* Logical device 7 registers (IT8712F and later) */
0531d98b 153#define IT87_SIO_GPIO1_REG 0x25
895ff267 154#define IT87_SIO_GPIO3_REG 0x27
591ec650 155#define IT87_SIO_GPIO5_REG 0x29
0531d98b 156#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 157#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 158#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 159#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 160#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 161
1da177e4 162/* Update battery voltage after every reading if true */
90ab5ee9 163static bool update_vbat;
1da177e4
LT		 164
165/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 166static bool fix_pwm_polarity;
1da177e4 167
1da177e4
LT		 168/* Many IT87 constants specified below */
169
170/* Length of ISA address segment */
171#define IT87_EXTENT 8
172
87b4b663
BH		 173/* Length of ISA address segment for Environmental Controller */
174#define IT87_EC_EXTENT 2
175
176/* Offset of EC registers from ISA base address */
177#define IT87_EC_OFFSET 5
178
179/* Where are the ISA address/data registers relative to the EC base address */
180#define IT87_ADDR_REG_OFFSET 0
181#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 182
183/*----- The IT87 registers -----*/
184
185#define IT87_REG_CONFIG 0x00
186
187#define IT87_REG_ALARM1 0x01
188#define IT87_REG_ALARM2 0x02
189#define IT87_REG_ALARM3 0x03
190
4a0d71cf
GR		 191/*
192 * The IT8718F and IT8720F have the VID value in a different register, in
193 * Super-I/O configuration space.
194 */
1da177e4 195#define IT87_REG_VID 0x0a
4a0d71cf
GR		 196/*
197 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
198 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
199 * mode.
200 */
1da177e4 201#define IT87_REG_FAN_DIV 0x0b
17d648bf 202#define IT87_REG_FAN_16BIT 0x0c
1da177e4
LT		 203
204/* Monitors: 9 voltage (0 to 7, battery), 3 temp (1 to 3), 3 fan (1 to 3) */
205
c7f1f716
JD		 206static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82 };
207static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86 };
208static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83 };
209static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 };
161d898a
GR		 210static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
211
1da177e4
LT		 212#define IT87_REG_FAN_MAIN_CTRL 0x13
213#define IT87_REG_FAN_CTL 0x14
214#define IT87_REG_PWM(nr) (0x15 + (nr))
6229cdb2 215#define IT87_REG_PWM_DUTY(nr) (0x63 + (nr) * 8)
1da177e4
LT		 216
217#define IT87_REG_VIN(nr) (0x20 + (nr))
218#define IT87_REG_TEMP(nr) (0x29 + (nr))
219
220#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
221#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
222#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
223#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
224
1da177e4
LT		 225#define IT87_REG_VIN_ENABLE 0x50
226#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 227#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 228#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 229
230#define IT87_REG_CHIPID 0x58
231
4f3f51bc
JD		 232#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
233#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
234
483db43e
GR		 235struct it87_devices {
236 const char *name;
237 u16 features;
19529784
GR		 238 u8 peci_mask;
239 u8 old_peci_mask;
483db43e
GR		 240};
241
242#define FEAT_12MV_ADC (1 << 0)
243#define FEAT_NEWER_AUTOPWM (1 << 1)
244#define FEAT_OLD_AUTOPWM (1 << 2)
245#define FEAT_16BIT_FANS (1 << 3)
246#define FEAT_TEMP_OFFSET (1 << 4)
5d8d2f2b 247#define FEAT_TEMP_PECI (1 << 5)
19529784 248#define FEAT_TEMP_OLD_PECI (1 << 6)
483db43e
GR		 249
250static const struct it87_devices it87_devices[] = {
251 [it87] = {
252 .name = "it87",
253 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
254 },
255 [it8712] = {
256 .name = "it8712",
257 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
258 },
259 [it8716] = {
260 .name = "it8716",
261 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET,
262 },
263 [it8718] = {
264 .name = "it8718",
19529784
GR		 265 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
266 | FEAT_TEMP_OLD_PECI,
267 .old_peci_mask = 0x4,
483db43e
GR		 268 },
269 [it8720] = {
270 .name = "it8720",
19529784
GR		 271 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
272 | FEAT_TEMP_OLD_PECI,
273 .old_peci_mask = 0x4,
483db43e
GR		 274 },
275 [it8721] = {
276 .name = "it8721",
277 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
19529784 278 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI,
5d8d2f2b 279 .peci_mask = 0x05,
19529784 280 .old_peci_mask = 0x02, /* Actually reports PCH */
483db43e
GR		 281 },
282 [it8728] = {
283 .name = "it8728",
284 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
5d8d2f2b
GR		 285 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
286 .peci_mask = 0x07,
483db43e 287 },
b0636707
GR		 288 [it8771] = {
289 .name = "it8771",
290 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
291 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
292 /* PECI: guesswork */
293 /* 12mV ADC (OHM) */
294 /* 16 bit fans (OHM) */
295 .peci_mask = 0x07,
296 },
297 [it8772] = {
298 .name = "it8772",
299 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
300 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
301 /* PECI (coreboot) */
302 /* 12mV ADC (HWSensors4, OHM) */
303 /* 16 bit fans (HWSensors4, OHM) */
304 .peci_mask = 0x07,
305 },
483db43e
GR		 306 [it8782] = {
307 .name = "it8782",
19529784
GR		 308 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
309 | FEAT_TEMP_OLD_PECI,
310 .old_peci_mask = 0x4,
483db43e
GR		 311 },
312 [it8783] = {
313 .name = "it8783",
19529784
GR		 314 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
315 | FEAT_TEMP_OLD_PECI,
316 .old_peci_mask = 0x4,
483db43e
GR		 317 },
318};
319
320#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
321#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
322#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
323#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
324#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b
GR		 325#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
326 ((data)->peci_mask & (1 << nr)))
19529784
GR		 327#define has_temp_old_peci(data, nr) \
328 (((data)->features & FEAT_TEMP_OLD_PECI) && \
329 ((data)->old_peci_mask & (1 << nr)))
1da177e4 330
b74f3fdd 331struct it87_sio_data {
332 enum chips type;
333 /* Values read from Super-I/O config space */
0475169c 334 u8 revision;
b74f3fdd 335 u8 vid_value;
d9b327c3 336 u8 beep_pin;
738e5e05 337 u8 internal; /* Internal sensors can be labeled */
591ec650 338 /* Features skipped based on config or DMI */
9172b5d1 339 u16 skip_in;
895ff267 340 u8 skip_vid;
591ec650 341 u8 skip_fan;
98dd22c3 342 u8 skip_pwm;
4573acbc 343 u8 skip_temp;
b74f3fdd 344};
345
4a0d71cf
GR		 346/*
347 * For each registered chip, we need to keep some data in memory.
348 * The structure is dynamically allocated.
349 */
1da177e4 350struct it87_data {
1beeffe4 351 struct device *hwmon_dev;
1da177e4 352 enum chips type;
483db43e 353 u16 features;
19529784
GR		 354 u8 peci_mask;
355 u8 old_peci_mask;
1da177e4 356
b74f3fdd 357 unsigned short addr;
358 const char *name;
9a61bf63 359 struct mutex update_lock;
1da177e4
LT		 360 char valid; /* !=0 if following fields are valid */
361 unsigned long last_updated; /* In jiffies */
362
44c1bcd4 363 u16 in_scaled; /* Internal voltage sensors are scaled */
929c6a56 364 u8 in[9][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 365 u8 has_fan; /* Bitfield, fans enabled */
e1169ba0 366 u16 fan[5][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 367 u8 has_temp; /* Bitfield, temp sensors enabled */
161d898a 368 s8 temp[3][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
19529784
GR		 369 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
370 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
1da177e4
LT		 371 u8 fan_div[3]; /* Register encoding, shifted right */
372 u8 vid; /* Register encoding, combined */
a7be58a1 373 u8 vrm;
1da177e4 374 u32 alarms; /* Register encoding, combined */
d9b327c3 375 u8 beeps; /* Register encoding */
1da177e4 376 u8 fan_main_ctrl; /* Register value */
f8d0c19a 377 u8 fan_ctl; /* Register value */
b99883dc 378
4a0d71cf
GR		 379 /*
380 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 381 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
382 * 7, and we want to preserve settings on mode changes, so we have
383 * to track all values separately.
384 * Starting with the IT8721F, the manual PWM duty cycles are stored
385 * in separate registers (8-bit values), so the separate tracking
386 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 387 * simple.
388 */
b99883dc 389 u8 pwm_ctrl[3]; /* Register value */
6229cdb2 390 u8 pwm_duty[3]; /* Manual PWM value set by user */
b99883dc 391 u8 pwm_temp_map[3]; /* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 392
393 /* Automatic fan speed control registers */
394 u8 auto_pwm[3][4]; /* [nr][3] is hard-coded */
395 s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 396};
0df6454d 397
0531d98b 398static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 399{
0531d98b
GR		 400 int lsb = has_12mv_adc(data) ? 12 : 16;
401 if (data->in_scaled & (1 << nr))
402 lsb <<= 1;
403 return lsb;
404}
44c1bcd4 405
0531d98b
GR		 406static u8 in_to_reg(const struct it87_data *data, int nr, long val)
407{
408 val = DIV_ROUND_CLOSEST(val, adc_lsb(data, nr));
2a844c14 409 return clamp_val(val, 0, 255);
44c1bcd4
JD		 410}
411
412static int in_from_reg(const struct it87_data *data, int nr, int val)
413{
0531d98b 414 return val * adc_lsb(data, nr);
44c1bcd4 415}
0df6454d
JD		 416
417static inline u8 FAN_TO_REG(long rpm, int div)
418{
419 if (rpm == 0)
420 return 255;
2a844c14
GR		 421 rpm = clamp_val(rpm, 1, 1000000);
422 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
0df6454d
JD		 423}
424
425static inline u16 FAN16_TO_REG(long rpm)
426{
427 if (rpm == 0)
428 return 0xffff;
2a844c14 429 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
0df6454d
JD		 430}
431
432#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
433 1350000 / ((val) * (div)))
434/* The divider is fixed to 2 in 16-bit mode */
435#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
436 1350000 / ((val) * 2))
437
2a844c14
GR		 438#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
439 ((val) + 500) / 1000), -128, 127))
0df6454d
JD		 440#define TEMP_FROM_REG(val) ((val) * 1000)
441
44c1bcd4
JD		 442static u8 pwm_to_reg(const struct it87_data *data, long val)
443{
16b5dda2 444 if (has_newer_autopwm(data))
44c1bcd4
JD		 445 return val;
446 else
447 return val >> 1;
448}
449
450static int pwm_from_reg(const struct it87_data *data, u8 reg)
451{
16b5dda2 452 if (has_newer_autopwm(data))
44c1bcd4
JD		 453 return reg;
454 else
455 return (reg & 0x7f) << 1;
456}
457
0df6454d
JD		 458
459static int DIV_TO_REG(int val)
460{
461 int answer = 0;
462 while (answer < 7 && (val >>= 1))
463 answer++;
464 return answer;
465}
466#define DIV_FROM_REG(val) (1 << (val))
467
468static const unsigned int pwm_freq[8] = {
469 48000000 / 128,
470 24000000 / 128,
471 12000000 / 128,
472 8000000 / 128,
473 6000000 / 128,
474 3000000 / 128,
475 1500000 / 128,
476 750000 / 128,
477};
1da177e4 478
b74f3fdd 479static int it87_probe(struct platform_device *pdev);
281dfd0b 480static int it87_remove(struct platform_device *pdev);
1da177e4 481
b74f3fdd 482static int it87_read_value(struct it87_data *data, u8 reg);
483static void it87_write_value(struct it87_data *data, u8 reg, u8 value);
1da177e4 484static struct it87_data *it87_update_device(struct device *dev);
b74f3fdd 485static int it87_check_pwm(struct device *dev);
486static void it87_init_device(struct platform_device *pdev);
1da177e4
LT		 487
488
b74f3fdd 489static struct platform_driver it87_driver = {
cdaf7934 490 .driver = {
87218842 491 .owner = THIS_MODULE,
b74f3fdd 492 .name = DRVNAME,
cdaf7934 493 },
b74f3fdd 494 .probe = it87_probe,
9e5e9b7a 495 .remove = it87_remove,
fde09509
JD		 496};
497
20ad93d4 498static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 499 char *buf)
1da177e4 500{
929c6a56
GR		 501 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
502 int nr = sattr->nr;
503 int index = sattr->index;
20ad93d4 504
1da177e4 505 struct it87_data *data = it87_update_device(dev);
929c6a56 506 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 507}
508
929c6a56
GR		 509static ssize_t set_in(struct device *dev, struct device_attribute *attr,
510 const char *buf, size_t count)
1da177e4 511{
929c6a56
GR		 512 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
513 int nr = sattr->nr;
514 int index = sattr->index;
20ad93d4 515
b74f3fdd 516 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 517 unsigned long val;
518
179c4fdb 519 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 520 return -EINVAL;
1da177e4 521
9a61bf63 522 mutex_lock(&data->update_lock);
929c6a56
GR		 523 data->in[nr][index] = in_to_reg(data, nr, val);
524 it87_write_value(data,
525 index == 1 ? IT87_REG_VIN_MIN(nr)
526 : IT87_REG_VIN_MAX(nr),
527 data->in[nr][index]);
9a61bf63 528 mutex_unlock(&data->update_lock);
1da177e4
LT		 529 return count;
530}
20ad93d4 531
929c6a56
GR		 532static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
533static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
534 0, 1);
535static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
536 0, 2);
f5f64501 537
929c6a56
GR		 538static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
539static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
540 1, 1);
541static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
542 1, 2);
1da177e4 543
929c6a56
GR		 544static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
545static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
546 2, 1);
547static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
548 2, 2);
1da177e4 549
929c6a56
GR		 550static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
551static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
552 3, 1);
553static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
554 3, 2);
555
556static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
557static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
558 4, 1);
559static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
560 4, 2);
561
562static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
563static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
564 5, 1);
565static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
566 5, 2);
567
568static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
569static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
570 6, 1);
571static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
572 6, 2);
573
574static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
575static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
576 7, 1);
577static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
578 7, 2);
579
580static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1da177e4
LT		 581
582/* 3 temperatures */
20ad93d4 583static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 584 char *buf)
1da177e4 585{
60ca385a
GR		 586 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
587 int nr = sattr->nr;
588 int index = sattr->index;
1da177e4 589 struct it87_data *data = it87_update_device(dev);
20ad93d4 590
60ca385a 591 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 592}
20ad93d4 593
60ca385a
GR		 594static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
595 const char *buf, size_t count)
1da177e4 596{
60ca385a
GR		 597 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
598 int nr = sattr->nr;
599 int index = sattr->index;
b74f3fdd 600 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 601 long val;
161d898a 602 u8 reg, regval;
f5f64501 603
179c4fdb 604 if (kstrtol(buf, 10, &val) < 0)
f5f64501 605 return -EINVAL;
1da177e4 606
9a61bf63 607 mutex_lock(&data->update_lock);
161d898a
GR		 608
609 switch (index) {
610 default:
611 case 1:
612 reg = IT87_REG_TEMP_LOW(nr);
613 break;
614 case 2:
615 reg = IT87_REG_TEMP_HIGH(nr);
616 break;
617 case 3:
618 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
619 if (!(regval & 0x80)) {
620 regval |= 0x80;
621 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
622 }
623 data->valid = 0;
624 reg = IT87_REG_TEMP_OFFSET[nr];
625 break;
626 }
627
60ca385a 628 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 629 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 630 mutex_unlock(&data->update_lock);
1da177e4
LT		 631 return count;
632}
1da177e4 633
60ca385a
GR		 634static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
635static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
636 0, 1);
637static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
638 0, 2);
161d898a
GR		 639static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
640 set_temp, 0, 3);
60ca385a
GR		 641static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
642static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
643 1, 1);
644static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
645 1, 2);
161d898a
GR		 646static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
647 set_temp, 1, 3);
60ca385a
GR		 648static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
649static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
650 2, 1);
651static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
652 2, 2);
161d898a
GR		 653static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
654 set_temp, 2, 3);
1da177e4 655
2cece01f
GR		 656static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
657 char *buf)
1da177e4 658{
20ad93d4
JD		 659 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
660 int nr = sensor_attr->index;
1da177e4 661 struct it87_data *data = it87_update_device(dev);
4a0d71cf 662 u8 reg = data->sensor; /* In case value is updated while used */
19529784 663 u8 extra = data->extra;
5f2dc798 664
19529784
GR		 665 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1))
666 || (has_temp_old_peci(data, nr) && (extra & 0x80)))
5d8d2f2b 667 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 668 if (reg & (1 << nr))
669 return sprintf(buf, "3\n"); /* thermal diode */
670 if (reg & (8 << nr))
4ed10779 671 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 672 return sprintf(buf, "0\n"); /* disabled */
673}
2cece01f
GR		 674
675static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
676 const char *buf, size_t count)
1da177e4 677{
20ad93d4
JD		 678 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
679 int nr = sensor_attr->index;
680
b74f3fdd 681 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 682 long val;
19529784 683 u8 reg, extra;
f5f64501 684
179c4fdb 685 if (kstrtol(buf, 10, &val) < 0)
f5f64501 686 return -EINVAL;
1da177e4 687
8acf07c5
JD		 688 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
689 reg &= ~(1 << nr);
690 reg &= ~(8 << nr);
5d8d2f2b
GR		 691 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
692 reg &= 0x3f;
19529784
GR		 693 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
694 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
695 extra &= 0x7f;
4ed10779 696 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 697 dev_warn(dev,
698 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 699 val = 4;
700 }
5d8d2f2b 701 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 702 if (val == 3)
8acf07c5 703 reg |= 1 << nr;
4ed10779 704 else if (val == 4)
8acf07c5 705 reg |= 8 << nr;
5d8d2f2b
GR		 706 else if (has_temp_peci(data, nr) && val == 6)
707 reg |= (nr + 1) << 6;
19529784
GR		 708 else if (has_temp_old_peci(data, nr) && val == 6)
709 extra |= 0x80;
8acf07c5 710 else if (val != 0)
1da177e4 711 return -EINVAL;
8acf07c5
JD		 712
713 mutex_lock(&data->update_lock);
714 data->sensor = reg;
19529784 715 data->extra = extra;
b74f3fdd 716 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
19529784
GR		 717 if (has_temp_old_peci(data, nr))
718 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2b3d1d87 719 data->valid = 0; /* Force cache refresh */
9a61bf63 720 mutex_unlock(&data->update_lock);
1da177e4
LT		 721 return count;
722}
1da177e4 723
2cece01f
GR		 724static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
725 set_temp_type, 0);
726static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
727 set_temp_type, 1);
728static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
729 set_temp_type, 2);
1da177e4
LT		 730
731/* 3 Fans */
b99883dc
JD		 732
733static int pwm_mode(const struct it87_data *data, int nr)
734{
735 int ctrl = data->fan_main_ctrl & (1 << nr);
736
737 if (ctrl == 0) /* Full speed */
738 return 0;
739 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
740 return 2;
741 else /* Manual mode */
742 return 1;
743}
744
20ad93d4 745static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 746 char *buf)
1da177e4 747{
e1169ba0
GR		 748 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
749 int nr = sattr->nr;
750 int index = sattr->index;
751 int speed;
1da177e4 752 struct it87_data *data = it87_update_device(dev);
20ad93d4 753
e1169ba0
GR		 754 speed = has_16bit_fans(data) ?
755 FAN16_FROM_REG(data->fan[nr][index]) :
756 FAN_FROM_REG(data->fan[nr][index],
757 DIV_FROM_REG(data->fan_div[nr]));
758 return sprintf(buf, "%d\n", speed);
1da177e4 759}
e1169ba0 760
20ad93d4
JD		 761static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
762 char *buf)
1da177e4 763{
20ad93d4
JD		 764 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
765 int nr = sensor_attr->index;
766
1da177e4
LT		 767 struct it87_data *data = it87_update_device(dev);
768 return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr]));
769}
5f2dc798
JD		 770static ssize_t show_pwm_enable(struct device *dev,
771 struct device_attribute *attr, char *buf)
1da177e4 772{
20ad93d4
JD		 773 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
774 int nr = sensor_attr->index;
775
1da177e4 776 struct it87_data *data = it87_update_device(dev);
b99883dc 777 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 778}
20ad93d4
JD		 779static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
780 char *buf)
1da177e4 781{
20ad93d4
JD		 782 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
783 int nr = sensor_attr->index;
784
1da177e4 785 struct it87_data *data = it87_update_device(dev);
44c1bcd4
JD		 786 return sprintf(buf, "%d\n",
787 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 788}
f8d0c19a
JD		 789static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
790 char *buf)
791{
792 struct it87_data *data = it87_update_device(dev);
793 int index = (data->fan_ctl >> 4) & 0x07;
794
795 return sprintf(buf, "%u\n", pwm_freq[index]);
796}
e1169ba0
GR		 797
798static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
799 const char *buf, size_t count)
1da177e4 800{
e1169ba0
GR		 801 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
802 int nr = sattr->nr;
803 int index = sattr->index;
20ad93d4 804
b74f3fdd 805 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 806 long val;
7f999aa7 807 u8 reg;
1da177e4 808
179c4fdb 809 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 810 return -EINVAL;
811
9a61bf63 812 mutex_lock(&data->update_lock);
e1169ba0
GR		 813
814 if (has_16bit_fans(data)) {
815 data->fan[nr][index] = FAN16_TO_REG(val);
816 it87_write_value(data, IT87_REG_FAN_MIN[nr],
817 data->fan[nr][index] & 0xff);
818 it87_write_value(data, IT87_REG_FANX_MIN[nr],
819 data->fan[nr][index] >> 8);
820 } else {
821 reg = it87_read_value(data, IT87_REG_FAN_DIV);
822 switch (nr) {
823 case 0:
824 data->fan_div[nr] = reg & 0x07;
825 break;
826 case 1:
827 data->fan_div[nr] = (reg >> 3) & 0x07;
828 break;
829 case 2:
830 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
831 break;
832 }
833 data->fan[nr][index] =
834 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
835 it87_write_value(data, IT87_REG_FAN_MIN[nr],
836 data->fan[nr][index]);
07eab46d
JD		 837 }
838
9a61bf63 839 mutex_unlock(&data->update_lock);
1da177e4
LT		 840 return count;
841}
e1169ba0 842
20ad93d4
JD		 843static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
844 const char *buf, size_t count)
1da177e4 845{
20ad93d4
JD		 846 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
847 int nr = sensor_attr->index;
848
b74f3fdd 849 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 850 unsigned long val;
8ab4ec3e 851 int min;
1da177e4
LT		 852 u8 old;
853
179c4fdb 854 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 855 return -EINVAL;
856
9a61bf63 857 mutex_lock(&data->update_lock);
b74f3fdd 858 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 859
8ab4ec3e 860 /* Save fan min limit */
e1169ba0 861 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 862
863 switch (nr) {
864 case 0:
865 case 1:
866 data->fan_div[nr] = DIV_TO_REG(val);
867 break;
868 case 2:
869 if (val < 8)
870 data->fan_div[nr] = 1;
871 else
872 data->fan_div[nr] = 3;
873 }
874 val = old & 0x80;
875 val |= (data->fan_div[0] & 0x07);
876 val |= (data->fan_div[1] & 0x07) << 3;
877 if (data->fan_div[2] == 3)
878 val |= 0x1 << 6;
b74f3fdd 879 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 880
8ab4ec3e 881 /* Restore fan min limit */
e1169ba0
GR		 882 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
883 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 884
9a61bf63 885 mutex_unlock(&data->update_lock);
1da177e4
LT		 886 return count;
887}
cccfc9c4
JD		 888
889/* Returns 0 if OK, -EINVAL otherwise */
890static int check_trip_points(struct device *dev, int nr)
891{
892 const struct it87_data *data = dev_get_drvdata(dev);
893 int i, err = 0;
894
895 if (has_old_autopwm(data)) {
896 for (i = 0; i < 3; i++) {
897 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
898 err = -EINVAL;
899 }
900 for (i = 0; i < 2; i++) {
901 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
902 err = -EINVAL;
903 }
904 }
905
906 if (err) {
1d9bcf6a
GR		 907 dev_err(dev,
908 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 909 dev_err(dev, "Adjust the trip points and try again\n");
910 }
911 return err;
912}
913
20ad93d4
JD		 914static ssize_t set_pwm_enable(struct device *dev,
915 struct device_attribute *attr, const char *buf, size_t count)
1da177e4 916{
20ad93d4
JD		 917 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
918 int nr = sensor_attr->index;
919
b74f3fdd 920 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 921 long val;
1da177e4 922
179c4fdb 923 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 924 return -EINVAL;
925
cccfc9c4
JD		 926 /* Check trip points before switching to automatic mode */
927 if (val == 2) {
928 if (check_trip_points(dev, nr) < 0)
929 return -EINVAL;
930 }
931
9a61bf63 932 mutex_lock(&data->update_lock);
1da177e4
LT		 933
934 if (val == 0) {
935 int tmp;
936 /* make sure the fan is on when in on/off mode */
b74f3fdd 937 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
938 it87_write_value(data, IT87_REG_FAN_CTL, tmp | (1 << nr));
1da177e4
LT		 939 /* set on/off mode */
940 data->fan_main_ctrl &= ~(1 << nr);
5f2dc798
JD		 941 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
942 data->fan_main_ctrl);
b99883dc
JD		 943 } else {
944 if (val == 1) /* Manual mode */
16b5dda2 945 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 946 data->pwm_temp_map[nr] :
947 data->pwm_duty[nr];
b99883dc
JD		 948 else /* Automatic mode */
949 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
950 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
1da177e4
LT		 951 /* set SmartGuardian mode */
952 data->fan_main_ctrl |= (1 << nr);
5f2dc798
JD		 953 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
954 data->fan_main_ctrl);
1da177e4
LT		 955 }
956
9a61bf63 957 mutex_unlock(&data->update_lock);
1da177e4
LT		 958 return count;
959}
20ad93d4
JD		 960static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
961 const char *buf, size_t count)
1da177e4 962{
20ad93d4
JD		 963 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
964 int nr = sensor_attr->index;
965
b74f3fdd 966 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 967 long val;
1da177e4 968
179c4fdb 969 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 970 return -EINVAL;
971
9a61bf63 972 mutex_lock(&data->update_lock);
16b5dda2 973 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 974 /*
975 * If we are in automatic mode, the PWM duty cycle register
976 * is read-only so we can't write the value.
977 */
6229cdb2
JD		 978 if (data->pwm_ctrl[nr] & 0x80) {
979 mutex_unlock(&data->update_lock);
980 return -EBUSY;
981 }
982 data->pwm_duty[nr] = pwm_to_reg(data, val);
983 it87_write_value(data, IT87_REG_PWM_DUTY(nr),
984 data->pwm_duty[nr]);
985 } else {
986 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 987 /*
988 * If we are in manual mode, write the duty cycle immediately;
989 * otherwise, just store it for later use.
990 */
6229cdb2
JD		 991 if (!(data->pwm_ctrl[nr] & 0x80)) {
992 data->pwm_ctrl[nr] = data->pwm_duty[nr];
993 it87_write_value(data, IT87_REG_PWM(nr),
994 data->pwm_ctrl[nr]);
995 }
b99883dc 996 }
9a61bf63 997 mutex_unlock(&data->update_lock);
1da177e4
LT		 998 return count;
999}
f8d0c19a
JD		 1000static ssize_t set_pwm_freq(struct device *dev,
1001 struct device_attribute *attr, const char *buf, size_t count)
1002{
b74f3fdd 1003 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1004 unsigned long val;
f8d0c19a
JD		 1005 int i;
1006
179c4fdb 1007 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 1008 return -EINVAL;
1009
f8d0c19a
JD		 1010 /* Search for the nearest available frequency */
1011 for (i = 0; i < 7; i++) {
1012 if (val > (pwm_freq[i] + pwm_freq[i+1]) / 2)
1013 break;
1014 }
1015
1016 mutex_lock(&data->update_lock);
b74f3fdd 1017 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
f8d0c19a 1018 data->fan_ctl |= i << 4;
b74f3fdd 1019 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
f8d0c19a
JD		 1020 mutex_unlock(&data->update_lock);
1021
1022 return count;
1023}
94ac7ee6
JD		 1024static ssize_t show_pwm_temp_map(struct device *dev,
1025 struct device_attribute *attr, char *buf)
1026{
1027 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1028 int nr = sensor_attr->index;
1029
1030 struct it87_data *data = it87_update_device(dev);
1031 int map;
1032
1033 if (data->pwm_temp_map[nr] < 3)
1034 map = 1 << data->pwm_temp_map[nr];
1035 else
1036 map = 0; /* Should never happen */
1037 return sprintf(buf, "%d\n", map);
1038}
1039static ssize_t set_pwm_temp_map(struct device *dev,
1040 struct device_attribute *attr, const char *buf, size_t count)
1041{
1042 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1043 int nr = sensor_attr->index;
1044
1045 struct it87_data *data = dev_get_drvdata(dev);
1046 long val;
1047 u8 reg;
1048
4a0d71cf
GR		 1049 /*
1050 * This check can go away if we ever support automatic fan speed
1051 * control on newer chips.
1052 */
4f3f51bc
JD		 1053 if (!has_old_autopwm(data)) {
1054 dev_notice(dev, "Mapping change disabled for safety reasons\n");
1055 return -EINVAL;
1056 }
1057
179c4fdb 1058 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1059 return -EINVAL;
1060
1061 switch (val) {
1062 case (1 << 0):
1063 reg = 0x00;
1064 break;
1065 case (1 << 1):
1066 reg = 0x01;
1067 break;
1068 case (1 << 2):
1069 reg = 0x02;
1070 break;
1071 default:
1072 return -EINVAL;
1073 }
1074
1075 mutex_lock(&data->update_lock);
1076 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1077 /*
1078 * If we are in automatic mode, write the temp mapping immediately;
1079 * otherwise, just store it for later use.
1080 */
94ac7ee6
JD		 1081 if (data->pwm_ctrl[nr] & 0x80) {
1082 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
1083 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
1084 }
1085 mutex_unlock(&data->update_lock);
1086 return count;
1087}
1da177e4 1088
4f3f51bc
JD		 1089static ssize_t show_auto_pwm(struct device *dev,
1090 struct device_attribute *attr, char *buf)
1091{
1092 struct it87_data *data = it87_update_device(dev);
1093 struct sensor_device_attribute_2 *sensor_attr =
1094 to_sensor_dev_attr_2(attr);
1095 int nr = sensor_attr->nr;
1096 int point = sensor_attr->index;
1097
44c1bcd4
JD		 1098 return sprintf(buf, "%d\n",
1099 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1100}
1101
1102static ssize_t set_auto_pwm(struct device *dev,
1103 struct device_attribute *attr, const char *buf, size_t count)
1104{
1105 struct it87_data *data = dev_get_drvdata(dev);
1106 struct sensor_device_attribute_2 *sensor_attr =
1107 to_sensor_dev_attr_2(attr);
1108 int nr = sensor_attr->nr;
1109 int point = sensor_attr->index;
1110 long val;
1111
179c4fdb 1112 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1113 return -EINVAL;
1114
1115 mutex_lock(&data->update_lock);
44c1bcd4 1116 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
4f3f51bc
JD		 1117 it87_write_value(data, IT87_REG_AUTO_PWM(nr, point),
1118 data->auto_pwm[nr][point]);
1119 mutex_unlock(&data->update_lock);
1120 return count;
1121}
1122
1123static ssize_t show_auto_temp(struct device *dev,
1124 struct device_attribute *attr, char *buf)
1125{
1126 struct it87_data *data = it87_update_device(dev);
1127 struct sensor_device_attribute_2 *sensor_attr =
1128 to_sensor_dev_attr_2(attr);
1129 int nr = sensor_attr->nr;
1130 int point = sensor_attr->index;
1131
1132 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point]));
1133}
1134
1135static ssize_t set_auto_temp(struct device *dev,
1136 struct device_attribute *attr, const char *buf, size_t count)
1137{
1138 struct it87_data *data = dev_get_drvdata(dev);
1139 struct sensor_device_attribute_2 *sensor_attr =
1140 to_sensor_dev_attr_2(attr);
1141 int nr = sensor_attr->nr;
1142 int point = sensor_attr->index;
1143 long val;
1144
179c4fdb 1145 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1146 return -EINVAL;
1147
1148 mutex_lock(&data->update_lock);
1149 data->auto_temp[nr][point] = TEMP_TO_REG(val);
1150 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point),
1151 data->auto_temp[nr][point]);
1152 mutex_unlock(&data->update_lock);
1153 return count;
1154}
1155
e1169ba0
GR		 1156static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1157static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1158 0, 1);
1159static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1160 set_fan_div, 0);
1161
1162static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1163static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1164 1, 1);
1165static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1166 set_fan_div, 1);
1167
1168static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1169static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1170 2, 1);
1171static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1172 set_fan_div, 2);
1173
1174static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1175static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1176 3, 1);
1da177e4 1177
e1169ba0
GR		 1178static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1179static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1180 4, 1);
1da177e4 1181
c4458db3
GR		 1182static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1183 show_pwm_enable, set_pwm_enable, 0);
1184static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1185static DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, set_pwm_freq);
1186static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO | S_IWUSR,
1187 show_pwm_temp_map, set_pwm_temp_map, 0);
1188static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1189 show_auto_pwm, set_auto_pwm, 0, 0);
1190static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1191 show_auto_pwm, set_auto_pwm, 0, 1);
1192static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1193 show_auto_pwm, set_auto_pwm, 0, 2);
1194static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1195 show_auto_pwm, NULL, 0, 3);
1196static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1197 show_auto_temp, set_auto_temp, 0, 1);
1198static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1199 show_auto_temp, set_auto_temp, 0, 0);
1200static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1201 show_auto_temp, set_auto_temp, 0, 2);
1202static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1203 show_auto_temp, set_auto_temp, 0, 3);
1204static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1205 show_auto_temp, set_auto_temp, 0, 4);
1206
1207static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1208 show_pwm_enable, set_pwm_enable, 1);
1209static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1210static DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, NULL);
1211static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO | S_IWUSR,
1212 show_pwm_temp_map, set_pwm_temp_map, 1);
1213static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1214 show_auto_pwm, set_auto_pwm, 1, 0);
1215static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1216 show_auto_pwm, set_auto_pwm, 1, 1);
1217static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1218 show_auto_pwm, set_auto_pwm, 1, 2);
1219static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1220 show_auto_pwm, NULL, 1, 3);
1221static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1222 show_auto_temp, set_auto_temp, 1, 1);
1223static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1224 show_auto_temp, set_auto_temp, 1, 0);
1225static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1226 show_auto_temp, set_auto_temp, 1, 2);
1227static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1228 show_auto_temp, set_auto_temp, 1, 3);
1229static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1230 show_auto_temp, set_auto_temp, 1, 4);
1231
1232static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1233 show_pwm_enable, set_pwm_enable, 2);
1234static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1235static DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL);
1236static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO | S_IWUSR,
1237 show_pwm_temp_map, set_pwm_temp_map, 2);
1238static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1239 show_auto_pwm, set_auto_pwm, 2, 0);
1240static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1241 show_auto_pwm, set_auto_pwm, 2, 1);
1242static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1243 show_auto_pwm, set_auto_pwm, 2, 2);
1244static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1245 show_auto_pwm, NULL, 2, 3);
1246static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1247 show_auto_temp, set_auto_temp, 2, 1);
1248static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1249 show_auto_temp, set_auto_temp, 2, 0);
1250static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1251 show_auto_temp, set_auto_temp, 2, 2);
1252static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1253 show_auto_temp, set_auto_temp, 2, 3);
1254static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1255 show_auto_temp, set_auto_temp, 2, 4);
1da177e4
LT		 1256
1257/* Alarms */
5f2dc798
JD		 1258static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
1259 char *buf)
1da177e4
LT		 1260{
1261 struct it87_data *data = it87_update_device(dev);
68188ba7 1262 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1263}
1d66c64c 1264static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1265
0124dd78
JD		 1266static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1267 char *buf)
1268{
1269 int bitnr = to_sensor_dev_attr(attr)->index;
1270 struct it87_data *data = it87_update_device(dev);
1271 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1272}
3d30f9e6
JD		 1273
1274static ssize_t clear_intrusion(struct device *dev, struct device_attribute
1275 *attr, const char *buf, size_t count)
1276{
1277 struct it87_data *data = dev_get_drvdata(dev);
1278 long val;
1279 int config;
1280
179c4fdb 1281 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1282 return -EINVAL;
1283
1284 mutex_lock(&data->update_lock);
1285 config = it87_read_value(data, IT87_REG_CONFIG);
1286 if (config < 0) {
1287 count = config;
1288 } else {
1289 config |= 1 << 5;
1290 it87_write_value(data, IT87_REG_CONFIG, config);
1291 /* Invalidate cache to force re-read */
1292 data->valid = 0;
1293 }
1294 mutex_unlock(&data->update_lock);
1295
1296 return count;
1297}
1298
0124dd78
JD		 1299static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1300static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1301static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1302static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1303static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1304static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1305static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1306static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1307static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1308static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1309static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1310static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1311static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1312static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1313static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1314static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1315static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1316 show_alarm, clear_intrusion, 4);
0124dd78 1317
d9b327c3
JD		 1318static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1319 char *buf)
1320{
1321 int bitnr = to_sensor_dev_attr(attr)->index;
1322 struct it87_data *data = it87_update_device(dev);
1323 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1324}
1325static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1326 const char *buf, size_t count)
1327{
1328 int bitnr = to_sensor_dev_attr(attr)->index;
1329 struct it87_data *data = dev_get_drvdata(dev);
1330 long val;
1331
179c4fdb 1332 if (kstrtol(buf, 10, &val) < 0
d9b327c3
JD		 1333 || (val != 0 && val != 1))
1334 return -EINVAL;
1335
1336 mutex_lock(&data->update_lock);
1337 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1338 if (val)
1339 data->beeps |= (1 << bitnr);
1340 else
1341 data->beeps &= ~(1 << bitnr);
1342 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1343 mutex_unlock(&data->update_lock);
1344 return count;
1345}
1346
1347static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1348 show_beep, set_beep, 1);
1349static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1350static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1351static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1352static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1353static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1354static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1355static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1356/* fanX_beep writability is set later */
1357static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1358static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1359static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1360static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1361static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1362static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1363 show_beep, set_beep, 2);
1364static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1365static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1366
5f2dc798
JD		 1367static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
1368 char *buf)
1da177e4 1369{
90d6619a 1370 struct it87_data *data = dev_get_drvdata(dev);
a7be58a1 1371 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1372}
5f2dc798
JD		 1373static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
1374 const char *buf, size_t count)
1da177e4 1375{
b74f3fdd 1376 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1377 unsigned long val;
1378
179c4fdb 1379 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1380 return -EINVAL;
1da177e4 1381
1da177e4
LT		 1382 data->vrm = val;
1383
1384 return count;
1385}
1386static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1387
5f2dc798
JD		 1388static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
1389 char *buf)
1da177e4
LT		 1390{
1391 struct it87_data *data = it87_update_device(dev);
1392 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
1393}
1394static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1395
738e5e05
JD		 1396static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1397 char *buf)
1398{
3c4c4971 1399 static const char * const labels[] = {
738e5e05
JD		 1400 "+5V",
1401 "5VSB",
1402 "Vbat",
1403 };
3c4c4971 1404 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1405 "+3.3V",
1406 "3VSB",
1407 "Vbat",
1408 };
1409 struct it87_data *data = dev_get_drvdata(dev);
738e5e05
JD		 1410 int nr = to_sensor_dev_attr(attr)->index;
1411
16b5dda2
JD		 1412 return sprintf(buf, "%s\n", has_12mv_adc(data) ? labels_it8721[nr]
1413 : labels[nr]);
738e5e05
JD		 1414}
1415static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1416static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1417static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
1418
b74f3fdd 1419static ssize_t show_name(struct device *dev, struct device_attribute
1420 *devattr, char *buf)
1421{
1422 struct it87_data *data = dev_get_drvdata(dev);
1423 return sprintf(buf, "%s\n", data->name);
1424}
1425static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1426
9172b5d1
GR		 1427static struct attribute *it87_attributes_in[9][5] = {
1428{
87808be4 1429 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1430 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1431 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1432 &sensor_dev_attr_in0_alarm.dev_attr.attr,
9172b5d1
GR		 1433 NULL
1434}, {
1435 &sensor_dev_attr_in1_input.dev_attr.attr,
1436 &sensor_dev_attr_in1_min.dev_attr.attr,
1437 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1438 &sensor_dev_attr_in1_alarm.dev_attr.attr,
9172b5d1
GR		 1439 NULL
1440}, {
1441 &sensor_dev_attr_in2_input.dev_attr.attr,
1442 &sensor_dev_attr_in2_min.dev_attr.attr,
1443 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1444 &sensor_dev_attr_in2_alarm.dev_attr.attr,
9172b5d1
GR		 1445 NULL
1446}, {
1447 &sensor_dev_attr_in3_input.dev_attr.attr,
1448 &sensor_dev_attr_in3_min.dev_attr.attr,
1449 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1450 &sensor_dev_attr_in3_alarm.dev_attr.attr,
9172b5d1
GR		 1451 NULL
1452}, {
1453 &sensor_dev_attr_in4_input.dev_attr.attr,
1454 &sensor_dev_attr_in4_min.dev_attr.attr,
1455 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1456 &sensor_dev_attr_in4_alarm.dev_attr.attr,
9172b5d1
GR		 1457 NULL
1458}, {
1459 &sensor_dev_attr_in5_input.dev_attr.attr,
1460 &sensor_dev_attr_in5_min.dev_attr.attr,
1461 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1462 &sensor_dev_attr_in5_alarm.dev_attr.attr,
9172b5d1
GR		 1463 NULL
1464}, {
1465 &sensor_dev_attr_in6_input.dev_attr.attr,
1466 &sensor_dev_attr_in6_min.dev_attr.attr,
1467 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1468 &sensor_dev_attr_in6_alarm.dev_attr.attr,
9172b5d1
GR		 1469 NULL
1470}, {
1471 &sensor_dev_attr_in7_input.dev_attr.attr,
1472 &sensor_dev_attr_in7_min.dev_attr.attr,
1473 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1474 &sensor_dev_attr_in7_alarm.dev_attr.attr,
9172b5d1
GR		 1475 NULL
1476}, {
1477 &sensor_dev_attr_in8_input.dev_attr.attr,
1478 NULL
1479} };
87808be4 1480
9172b5d1
GR		 1481static const struct attribute_group it87_group_in[9] = {
1482 { .attrs = it87_attributes_in[0] },
1483 { .attrs = it87_attributes_in[1] },
1484 { .attrs = it87_attributes_in[2] },
1485 { .attrs = it87_attributes_in[3] },
1486 { .attrs = it87_attributes_in[4] },
1487 { .attrs = it87_attributes_in[5] },
1488 { .attrs = it87_attributes_in[6] },
1489 { .attrs = it87_attributes_in[7] },
1490 { .attrs = it87_attributes_in[8] },
1491};
1492
4573acbc
GR		 1493static struct attribute *it87_attributes_temp[3][6] = {
1494{
87808be4 1495 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 1496 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 1497 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 1498 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 1499 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
4573acbc
GR		 1500 NULL
1501} , {
1502 &sensor_dev_attr_temp2_input.dev_attr.attr,
1503 &sensor_dev_attr_temp2_max.dev_attr.attr,
1504 &sensor_dev_attr_temp2_min.dev_attr.attr,
1505 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 1506 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
4573acbc
GR		 1507 NULL
1508} , {
1509 &sensor_dev_attr_temp3_input.dev_attr.attr,
1510 &sensor_dev_attr_temp3_max.dev_attr.attr,
1511 &sensor_dev_attr_temp3_min.dev_attr.attr,
1512 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 1513 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
4573acbc
GR		 1514 NULL
1515} };
1516
1517static const struct attribute_group it87_group_temp[3] = {
1518 { .attrs = it87_attributes_temp[0] },
1519 { .attrs = it87_attributes_temp[1] },
1520 { .attrs = it87_attributes_temp[2] },
1521};
87808be4 1522
161d898a
GR		 1523static struct attribute *it87_attributes_temp_offset[] = {
1524 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1525 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1526 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1527};
1528
4573acbc 1529static struct attribute *it87_attributes[] = {
87808be4 1530 &dev_attr_alarms.attr,
3d30f9e6 1531 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
b74f3fdd 1532 &dev_attr_name.attr,
87808be4
JD		 1533 NULL
1534};
1535
1536static const struct attribute_group it87_group = {
1537 .attrs = it87_attributes,
1538};
1539
9172b5d1 1540static struct attribute *it87_attributes_in_beep[] = {
d9b327c3
JD		 1541 &sensor_dev_attr_in0_beep.dev_attr.attr,
1542 &sensor_dev_attr_in1_beep.dev_attr.attr,
1543 &sensor_dev_attr_in2_beep.dev_attr.attr,
1544 &sensor_dev_attr_in3_beep.dev_attr.attr,
1545 &sensor_dev_attr_in4_beep.dev_attr.attr,
1546 &sensor_dev_attr_in5_beep.dev_attr.attr,
1547 &sensor_dev_attr_in6_beep.dev_attr.attr,
1548 &sensor_dev_attr_in7_beep.dev_attr.attr,
9172b5d1
GR		 1549 NULL
1550};
d9b327c3 1551
4573acbc 1552static struct attribute *it87_attributes_temp_beep[] = {
d9b327c3
JD		 1553 &sensor_dev_attr_temp1_beep.dev_attr.attr,
1554 &sensor_dev_attr_temp2_beep.dev_attr.attr,
1555 &sensor_dev_attr_temp3_beep.dev_attr.attr,
d9b327c3
JD		 1556};
1557
e1169ba0
GR		 1558static struct attribute *it87_attributes_fan[5][3+1] = { {
1559 &sensor_dev_attr_fan1_input.dev_attr.attr,
1560 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0
JD		 1561 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1562 NULL
1563}, {
e1169ba0
GR		 1564 &sensor_dev_attr_fan2_input.dev_attr.attr,
1565 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0
JD		 1566 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1567 NULL
1568}, {
e1169ba0
GR		 1569 &sensor_dev_attr_fan3_input.dev_attr.attr,
1570 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0
JD		 1571 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1572 NULL
1573}, {
e1169ba0
GR		 1574 &sensor_dev_attr_fan4_input.dev_attr.attr,
1575 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0
JD		 1576 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1577 NULL
1578}, {
e1169ba0
GR		 1579 &sensor_dev_attr_fan5_input.dev_attr.attr,
1580 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0
JD		 1581 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1582 NULL
1583} };
1584
e1169ba0
GR		 1585static const struct attribute_group it87_group_fan[5] = {
1586 { .attrs = it87_attributes_fan[0] },
1587 { .attrs = it87_attributes_fan[1] },
1588 { .attrs = it87_attributes_fan[2] },
1589 { .attrs = it87_attributes_fan[3] },
1590 { .attrs = it87_attributes_fan[4] },
723a0aa0 1591};
87808be4 1592
e1169ba0 1593static const struct attribute *it87_attributes_fan_div[] = {
87808be4 1594 &sensor_dev_attr_fan1_div.dev_attr.attr,
87808be4 1595 &sensor_dev_attr_fan2_div.dev_attr.attr,
87808be4 1596 &sensor_dev_attr_fan3_div.dev_attr.attr,
723a0aa0
JD		 1597};
1598
723a0aa0 1599static struct attribute *it87_attributes_pwm[3][4+1] = { {
87808be4 1600 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 1601 &sensor_dev_attr_pwm1.dev_attr.attr,
d5b0b5d6 1602 &dev_attr_pwm1_freq.attr,
94ac7ee6 1603 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1604 NULL
1605}, {
1606 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1607 &sensor_dev_attr_pwm2.dev_attr.attr,
1608 &dev_attr_pwm2_freq.attr,
94ac7ee6 1609 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1610 NULL
1611}, {
1612 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1613 &sensor_dev_attr_pwm3.dev_attr.attr,
1614 &dev_attr_pwm3_freq.attr,
94ac7ee6 1615 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1616 NULL
1617} };
87808be4 1618
723a0aa0
JD		 1619static const struct attribute_group it87_group_pwm[3] = {
1620 { .attrs = it87_attributes_pwm[0] },
1621 { .attrs = it87_attributes_pwm[1] },
1622 { .attrs = it87_attributes_pwm[2] },
1623};
1624
4f3f51bc
JD		 1625static struct attribute *it87_attributes_autopwm[3][9+1] = { {
1626 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1627 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1628 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
1629 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
1630 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
1631 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
1632 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
1633 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
1634 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
1635 NULL
1636}, {
1637 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1638 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1639 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
1640 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
1641 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
1642 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
1643 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
1644 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
1645 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
1646 NULL
1647}, {
1648 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1649 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1650 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
1651 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
1652 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
1653 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
1654 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
1655 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
1656 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
1657 NULL
1658} };
1659
1660static const struct attribute_group it87_group_autopwm[3] = {
1661 { .attrs = it87_attributes_autopwm[0] },
1662 { .attrs = it87_attributes_autopwm[1] },
1663 { .attrs = it87_attributes_autopwm[2] },
1664};
1665
d9b327c3
JD		 1666static struct attribute *it87_attributes_fan_beep[] = {
1667 &sensor_dev_attr_fan1_beep.dev_attr.attr,
1668 &sensor_dev_attr_fan2_beep.dev_attr.attr,
1669 &sensor_dev_attr_fan3_beep.dev_attr.attr,
1670 &sensor_dev_attr_fan4_beep.dev_attr.attr,
1671 &sensor_dev_attr_fan5_beep.dev_attr.attr,
1672};
1673
6a8d7acf 1674static struct attribute *it87_attributes_vid[] = {
87808be4
JD		 1675 &dev_attr_vrm.attr,
1676 &dev_attr_cpu0_vid.attr,
1677 NULL
1678};
1679
6a8d7acf
JD		 1680static const struct attribute_group it87_group_vid = {
1681 .attrs = it87_attributes_vid,
87808be4 1682};
1da177e4 1683
738e5e05
JD		 1684static struct attribute *it87_attributes_label[] = {
1685 &sensor_dev_attr_in3_label.dev_attr.attr,
1686 &sensor_dev_attr_in7_label.dev_attr.attr,
1687 &sensor_dev_attr_in8_label.dev_attr.attr,
1688 NULL
1689};
1690
1691static const struct attribute_group it87_group_label = {
fa8b6975 1692 .attrs = it87_attributes_label,
738e5e05
JD		 1693};
1694
2d8672c5 1695/* SuperIO detection - will change isa_address if a chip is found */
b74f3fdd 1696static int __init it87_find(unsigned short *address,
1697 struct it87_sio_data *sio_data)
1da177e4 1698{
5b0380c9 1699 int err;
b74f3fdd 1700 u16 chip_type;
98dd22c3 1701 const char *board_vendor, *board_name;
1da177e4 1702
5b0380c9
NG		 1703 err = superio_enter();
1704 if (err)
1705 return err;
1706
1707 err = -ENODEV;
67b671bc 1708 chip_type = force_id ? force_id : superio_inw(DEVID);
b74f3fdd 1709
1710 switch (chip_type) {
1711 case IT8705F_DEVID:
1712 sio_data->type = it87;
1713 break;
1714 case IT8712F_DEVID:
1715 sio_data->type = it8712;
1716 break;
1717 case IT8716F_DEVID:
1718 case IT8726F_DEVID:
1719 sio_data->type = it8716;
1720 break;
1721 case IT8718F_DEVID:
1722 sio_data->type = it8718;
1723 break;
b4da93e4
JMS		 1724 case IT8720F_DEVID:
1725 sio_data->type = it8720;
1726 break;
44c1bcd4
JD		 1727 case IT8721F_DEVID:
1728 sio_data->type = it8721;
1729 break;
16b5dda2
JD		 1730 case IT8728F_DEVID:
1731 sio_data->type = it8728;
1732 break;
b0636707
GR		 1733 case IT8771E_DEVID:
1734 sio_data->type = it8771;
1735 break;
1736 case IT8772E_DEVID:
1737 sio_data->type = it8772;
1738 break;
0531d98b
GR		 1739 case IT8782F_DEVID:
1740 sio_data->type = it8782;
1741 break;
1742 case IT8783E_DEVID:
1743 sio_data->type = it8783;
1744 break;
b74f3fdd 1745 case 0xffff: /* No device at all */
1746 goto exit;
1747 default:
a8ca1037 1748 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 1749 goto exit;
1750 }
1da177e4 1751
87673dd7 1752 superio_select(PME);
1da177e4 1753 if (!(superio_inb(IT87_ACT_REG) & 0x01)) {
a8ca1037 1754 pr_info("Device not activated, skipping\n");
1da177e4
LT		 1755 goto exit;
1756 }
1757
1758 *address = superio_inw(IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1759 if (*address == 0) {
a8ca1037 1760 pr_info("Base address not set, skipping\n");
1da177e4
LT		 1761 goto exit;
1762 }
1763
1764 err = 0;
0475169c 1765 sio_data->revision = superio_inb(DEVREV) & 0x0f;
a8ca1037 1766 pr_info("Found IT%04xF chip at 0x%x, revision %d\n",
0475169c 1767 chip_type, *address, sio_data->revision);
1da177e4 1768
738e5e05
JD		 1769 /* in8 (Vbat) is always internal */
1770 sio_data->internal = (1 << 2);
1771
87673dd7 1772 /* Read GPIO config and VID value from LDN 7 (GPIO) */
895ff267
JD		 1773 if (sio_data->type == it87) {
1774 /* The IT8705F doesn't have VID pins at all */
1775 sio_data->skip_vid = 1;
d9b327c3
JD		 1776
1777 /* The IT8705F has a different LD number for GPIO */
1778 superio_select(5);
1779 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b 1780 } else if (sio_data->type == it8783) {
088ce2ac 1781 int reg25, reg27, reg2a, reg2c, regef;
0531d98b
GR		 1782
1783 sio_data->skip_vid = 1; /* No VID */
1784
1785 superio_select(GPIO);
1786
1787 reg25 = superio_inb(IT87_SIO_GPIO1_REG);
1788 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
088ce2ac
GR		 1789 reg2a = superio_inb(IT87_SIO_PINX1_REG);
1790 reg2c = superio_inb(IT87_SIO_PINX2_REG);
1791 regef = superio_inb(IT87_SIO_SPI_REG);
0531d98b 1792
0531d98b 1793 /* Check if fan3 is there or not */
088ce2ac 1794 if ((reg27 & (1 << 0)) || !(reg2c & (1 << 2)))
0531d98b
GR		 1795 sio_data->skip_fan |= (1 << 2);
1796 if ((reg25 & (1 << 4))
088ce2ac 1797 || (!(reg2a & (1 << 1)) && (regef & (1 << 0))))
0531d98b
GR		 1798 sio_data->skip_pwm |= (1 << 2);
1799
1800 /* Check if fan2 is there or not */
1801 if (reg27 & (1 << 7))
1802 sio_data->skip_fan |= (1 << 1);
1803 if (reg27 & (1 << 3))
1804 sio_data->skip_pwm |= (1 << 1);
1805
1806 /* VIN5 */
088ce2ac 1807 if ((reg27 & (1 << 0)) || (reg2c & (1 << 2)))
9172b5d1 1808 sio_data->skip_in |= (1 << 5); /* No VIN5 */
0531d98b
GR		 1809
1810 /* VIN6 */
9172b5d1
GR		 1811 if (reg27 & (1 << 1))
1812 sio_data->skip_in |= (1 << 6); /* No VIN6 */
0531d98b
GR		 1813
1814 /*
1815 * VIN7
1816 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
1817 */
9172b5d1
GR		 1818 if (reg27 & (1 << 2)) {
1819 /*
1820 * The data sheet is a bit unclear regarding the
1821 * internal voltage divider for VCCH5V. It says
1822 * "This bit enables and switches VIN7 (pin 91) to the
1823 * internal voltage divider for VCCH5V".
1824 * This is different to other chips, where the internal
1825 * voltage divider would connect VIN7 to an internal
1826 * voltage source. Maybe that is the case here as well.
1827 *
1828 * Since we don't know for sure, re-route it if that is
1829 * not the case, and ask the user to report if the
1830 * resulting voltage is sane.
1831 */
088ce2ac
GR		 1832 if (!(reg2c & (1 << 1))) {
1833 reg2c |= (1 << 1);
1834 superio_outb(IT87_SIO_PINX2_REG, reg2c);
9172b5d1
GR		 1835 pr_notice("Routing internal VCCH5V to in7.\n");
1836 }
1837 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
1838 pr_notice("Please report if it displays a reasonable voltage.\n");
1839 }
0531d98b 1840
088ce2ac 1841 if (reg2c & (1 << 0))
0531d98b 1842 sio_data->internal |= (1 << 0);
088ce2ac 1843 if (reg2c & (1 << 1))
0531d98b
GR		 1844 sio_data->internal |= (1 << 1);
1845
1846 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
1847
895ff267 1848 } else {
87673dd7 1849 int reg;
9172b5d1 1850 bool uart6;
87673dd7
JD		 1851
1852 superio_select(GPIO);
44c1bcd4 1853
895ff267 1854 reg = superio_inb(IT87_SIO_GPIO3_REG);
0531d98b 1855 if (sio_data->type == it8721 || sio_data->type == it8728 ||
b0636707 1856 sio_data->type == it8771 || sio_data->type == it8772 ||
0531d98b 1857 sio_data->type == it8782) {
16b5dda2 1858 /*
0531d98b 1859 * IT8721F/IT8758E, and IT8782F don't have VID pins
b0636707 1860 * at all, not sure about the IT8728F and compatibles.
16b5dda2 1861 */
895ff267 1862 sio_data->skip_vid = 1;
44c1bcd4
JD		 1863 } else {
1864 /* We need at least 4 VID pins */
1865 if (reg & 0x0f) {
a8ca1037 1866 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 1867 sio_data->skip_vid = 1;
1868 }
895ff267
JD		 1869 }
1870
591ec650
JD		 1871 /* Check if fan3 is there or not */
1872 if (reg & (1 << 6))
1873 sio_data->skip_pwm |= (1 << 2);
1874 if (reg & (1 << 7))
1875 sio_data->skip_fan |= (1 << 2);
1876
1877 /* Check if fan2 is there or not */
1878 reg = superio_inb(IT87_SIO_GPIO5_REG);
1879 if (reg & (1 << 1))
1880 sio_data->skip_pwm |= (1 << 1);
1881 if (reg & (1 << 2))
1882 sio_data->skip_fan |= (1 << 1);
1883
895ff267
JD		 1884 if ((sio_data->type == it8718 || sio_data->type == it8720)
1885 && !(sio_data->skip_vid))
b74f3fdd 1886 sio_data->vid_value = superio_inb(IT87_SIO_VID_REG);
87673dd7
JD		 1887
1888 reg = superio_inb(IT87_SIO_PINX2_REG);
9172b5d1
GR		 1889
1890 uart6 = sio_data->type == it8782 && (reg & (1 << 2));
1891
436cad2a
JD		 1892 /*
1893 * The IT8720F has no VIN7 pin, so VCCH should always be
1894 * routed internally to VIN7 with an internal divider.
1895 * Curiously, there still is a configuration bit to control
1896 * this, which means it can be set incorrectly. And even
1897 * more curiously, many boards out there are improperly
1898 * configured, even though the IT8720F datasheet claims
1899 * that the internal routing of VCCH to VIN7 is the default
1900 * setting. So we force the internal routing in this case.
0531d98b
GR		 1901 *
1902 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 1903 * If UART6 is enabled, re-route VIN7 to the internal divider
1904 * if that is not already the case.
436cad2a 1905 */
9172b5d1 1906 if ((sio_data->type == it8720 || uart6) && !(reg & (1 << 1))) {
436cad2a
JD		 1907 reg |= (1 << 1);
1908 superio_outb(IT87_SIO_PINX2_REG, reg);
a8ca1037 1909 pr_notice("Routing internal VCCH to in7\n");
436cad2a 1910 }
87673dd7 1911 if (reg & (1 << 0))
738e5e05 1912 sio_data->internal |= (1 << 0);
16b5dda2 1913 if ((reg & (1 << 1)) || sio_data->type == it8721 ||
b0636707
GR		 1914 sio_data->type == it8728 ||
1915 sio_data->type == it8771 ||
1916 sio_data->type == it8772)
738e5e05 1917 sio_data->internal |= (1 << 1);
d9b327c3 1918
9172b5d1
GR		 1919 /*
1920 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
1921 * While VIN7 can be routed to the internal voltage divider,
1922 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 1923 *
1924 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
1925 * is the temperature source. Since we can not read the
1926 * temperature source here, skip_temp is preliminary.
9172b5d1 1927 */
4573acbc 1928 if (uart6) {
9172b5d1 1929 sio_data->skip_in |= (1 << 5) | (1 << 6);
4573acbc
GR		 1930 sio_data->skip_temp |= (1 << 2);
1931 }
9172b5d1 1932
d9b327c3 1933 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 1934 }
d9b327c3 1935 if (sio_data->beep_pin)
a8ca1037 1936 pr_info("Beeping is supported\n");
87673dd7 1937
98dd22c3
JD		 1938 /* Disable specific features based on DMI strings */
1939 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
1940 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1941 if (board_vendor && board_name) {
1942 if (strcmp(board_vendor, "nVIDIA") == 0
1943 && strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 1944 /*
1945 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
1946 * connected to a fan, but to something else. One user
1947 * has reported instant system power-off when changing
1948 * the PWM2 duty cycle, so we disable it.
1949 * I use the board name string as the trigger in case
1950 * the same board is ever used in other systems.
1951 */
a8ca1037 1952 pr_info("Disabling pwm2 due to hardware constraints\n");
98dd22c3
JD		 1953 sio_data->skip_pwm = (1 << 1);
1954 }
1955 }
1956
1da177e4
LT		 1957exit:
1958 superio_exit();
1959 return err;
1960}
1961
723a0aa0
JD		 1962static void it87_remove_files(struct device *dev)
1963{
1964 struct it87_data *data = platform_get_drvdata(pdev);
a8b3a3a5 1965 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0
JD		 1966 int i;
1967
1968 sysfs_remove_group(&dev->kobj, &it87_group);
9172b5d1
GR		 1969 for (i = 0; i < 9; i++) {
1970 if (sio_data->skip_in & (1 << i))
1971 continue;
1972 sysfs_remove_group(&dev->kobj, &it87_group_in[i]);
1973 if (it87_attributes_in_beep[i])
1974 sysfs_remove_file(&dev->kobj,
1975 it87_attributes_in_beep[i]);
1976 }
4573acbc
GR		 1977 for (i = 0; i < 3; i++) {
1978 if (!(data->has_temp & (1 << i)))
1979 continue;
1980 sysfs_remove_group(&dev->kobj, &it87_group_temp[i]);
161d898a
GR		 1981 if (has_temp_offset(data))
1982 sysfs_remove_file(&dev->kobj,
1983 it87_attributes_temp_offset[i]);
4573acbc
GR		 1984 if (sio_data->beep_pin)
1985 sysfs_remove_file(&dev->kobj,
1986 it87_attributes_temp_beep[i]);
1987 }
723a0aa0
JD		 1988 for (i = 0; i < 5; i++) {
1989 if (!(data->has_fan & (1 << i)))
1990 continue;
e1169ba0 1991 sysfs_remove_group(&dev->kobj, &it87_group_fan[i]);
d9b327c3
JD		 1992 if (sio_data->beep_pin)
1993 sysfs_remove_file(&dev->kobj,
1994 it87_attributes_fan_beep[i]);
e1169ba0
GR		 1995 if (i < 3 && !has_16bit_fans(data))
1996 sysfs_remove_file(&dev->kobj,
1997 it87_attributes_fan_div[i]);
723a0aa0
JD		 1998 }
1999 for (i = 0; i < 3; i++) {
2000 if (sio_data->skip_pwm & (1 << 0))
2001 continue;
2002 sysfs_remove_group(&dev->kobj, &it87_group_pwm[i]);
4f3f51bc
JD		 2003 if (has_old_autopwm(data))
2004 sysfs_remove_group(&dev->kobj,
2005 &it87_group_autopwm[i]);
723a0aa0 2006 }
6a8d7acf
JD		 2007 if (!sio_data->skip_vid)
2008 sysfs_remove_group(&dev->kobj, &it87_group_vid);
738e5e05 2009 sysfs_remove_group(&dev->kobj, &it87_group_label);
723a0aa0
JD		 2010}
2011
6c931ae1 2012static int it87_probe(struct platform_device *pdev)
1da177e4 2013{
1da177e4 2014 struct it87_data *data;
b74f3fdd 2015 struct resource *res;
2016 struct device *dev = &pdev->dev;
a8b3a3a5 2017 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0 2018 int err = 0, i;
1da177e4 2019 int enable_pwm_interface;
d9b327c3 2020 int fan_beep_need_rw;
b74f3fdd 2021
2022 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
62a1d05f
GR		 2023 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2024 DRVNAME)) {
b74f3fdd 2025 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2026 (unsigned long)res->start,
87b4b663 2027 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
62a1d05f 2028 return -EBUSY;
8e9afcbb 2029 }
1da177e4 2030
62a1d05f
GR		 2031 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2032 if (!data)
2033 return -ENOMEM;
1da177e4 2034
b74f3fdd 2035 data->addr = res->start;
2036 data->type = sio_data->type;
483db43e 2037 data->features = it87_devices[sio_data->type].features;
5d8d2f2b 2038 data->peci_mask = it87_devices[sio_data->type].peci_mask;
19529784 2039 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
483db43e
GR		 2040 data->name = it87_devices[sio_data->type].name;
2041 /*
2042 * IT8705F Datasheet 0.4.1, 3h == Version G.
2043 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2044 * These are the first revisions with 16-bit tachometer support.
2045 */
2046 switch (data->type) {
2047 case it87:
2048 if (sio_data->revision >= 0x03) {
2049 data->features &= ~FEAT_OLD_AUTOPWM;
2050 data->features |= FEAT_16BIT_FANS;
2051 }
2052 break;
2053 case it8712:
2054 if (sio_data->revision >= 0x08) {
2055 data->features &= ~FEAT_OLD_AUTOPWM;
2056 data->features |= FEAT_16BIT_FANS;
2057 }
2058 break;
2059 default:
2060 break;
2061 }
1da177e4
LT		 2062
2063 /* Now, we do the remaining detection. */
b74f3fdd 2064 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80)
62a1d05f
GR		 2065 || it87_read_value(data, IT87_REG_CHIPID) != 0x90)
2066 return -ENODEV;
1da177e4 2067
b74f3fdd 2068 platform_set_drvdata(pdev, data);
1da177e4 2069
9a61bf63 2070 mutex_init(&data->update_lock);
1da177e4 2071
1da177e4 2072 /* Check PWM configuration */
b74f3fdd 2073 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2074
44c1bcd4 2075 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2076 if (has_12mv_adc(data)) {
44c1bcd4
JD		 2077 if (sio_data->internal & (1 << 0))
2078 data->in_scaled |= (1 << 3); /* in3 is AVCC */
2079 if (sio_data->internal & (1 << 1))
2080 data->in_scaled |= (1 << 7); /* in7 is VSB */
2081 if (sio_data->internal & (1 << 2))
2082 data->in_scaled |= (1 << 8); /* in8 is Vbat */
0531d98b
GR		 2083 } else if (sio_data->type == it8782 || sio_data->type == it8783) {
2084 if (sio_data->internal & (1 << 0))
2085 data->in_scaled |= (1 << 3); /* in3 is VCC5V */
2086 if (sio_data->internal & (1 << 1))
2087 data->in_scaled |= (1 << 7); /* in7 is VCCH5V */
44c1bcd4
JD		 2088 }
2089
4573acbc
GR		 2090 data->has_temp = 0x07;
2091 if (sio_data->skip_temp & (1 << 2)) {
2092 if (sio_data->type == it8782
2093 && !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
2094 data->has_temp &= ~(1 << 2);
2095 }
2096
1da177e4 2097 /* Initialize the IT87 chip */
b74f3fdd 2098 it87_init_device(pdev);
1da177e4
LT		 2099
2100 /* Register sysfs hooks */
5f2dc798
JD		 2101 err = sysfs_create_group(&dev->kobj, &it87_group);
2102 if (err)
62a1d05f 2103 return err;
17d648bf 2104
9172b5d1
GR		 2105 for (i = 0; i < 9; i++) {
2106 if (sio_data->skip_in & (1 << i))
2107 continue;
2108 err = sysfs_create_group(&dev->kobj, &it87_group_in[i]);
2109 if (err)
62a1d05f 2110 goto error;
9172b5d1
GR		 2111 if (sio_data->beep_pin && it87_attributes_in_beep[i]) {
2112 err = sysfs_create_file(&dev->kobj,
2113 it87_attributes_in_beep[i]);
2114 if (err)
62a1d05f 2115 goto error;
9172b5d1
GR		 2116 }
2117 }
2118
4573acbc
GR		 2119 for (i = 0; i < 3; i++) {
2120 if (!(data->has_temp & (1 << i)))
2121 continue;
2122 err = sysfs_create_group(&dev->kobj, &it87_group_temp[i]);
d9b327c3 2123 if (err)
62a1d05f 2124 goto error;
161d898a
GR		 2125 if (has_temp_offset(data)) {
2126 err = sysfs_create_file(&dev->kobj,
2127 it87_attributes_temp_offset[i]);
2128 if (err)
2129 goto error;
2130 }
4573acbc
GR		 2131 if (sio_data->beep_pin) {
2132 err = sysfs_create_file(&dev->kobj,
2133 it87_attributes_temp_beep[i]);
2134 if (err)
2135 goto error;
2136 }
d9b327c3
JD		 2137 }
2138
9060f8bd 2139 /* Do not create fan files for disabled fans */
d9b327c3 2140 fan_beep_need_rw = 1;
723a0aa0
JD		 2141 for (i = 0; i < 5; i++) {
2142 if (!(data->has_fan & (1 << i)))
2143 continue;
e1169ba0 2144 err = sysfs_create_group(&dev->kobj, &it87_group_fan[i]);
723a0aa0 2145 if (err)
62a1d05f 2146 goto error;
d9b327c3 2147
e1169ba0
GR		 2148 if (i < 3 && !has_16bit_fans(data)) {
2149 err = sysfs_create_file(&dev->kobj,
2150 it87_attributes_fan_div[i]);
2151 if (err)
2152 goto error;
2153 }
2154
d9b327c3
JD		 2155 if (sio_data->beep_pin) {
2156 err = sysfs_create_file(&dev->kobj,
2157 it87_attributes_fan_beep[i]);
2158 if (err)
62a1d05f 2159 goto error;
d9b327c3
JD		 2160 if (!fan_beep_need_rw)
2161 continue;
2162
4a0d71cf
GR		 2163 /*
2164 * As we have a single beep enable bit for all fans,
d9b327c3 2165 * only the first enabled fan has a writable attribute
4a0d71cf
GR		 2166 * for it.
2167 */
d9b327c3
JD		 2168 if (sysfs_chmod_file(&dev->kobj,
2169 it87_attributes_fan_beep[i],
2170 S_IRUGO | S_IWUSR))
2171 dev_dbg(dev, "chmod +w fan%d_beep failed\n",
2172 i + 1);
2173 fan_beep_need_rw = 0;
2174 }
17d648bf
JD		 2175 }
2176
1da177e4 2177 if (enable_pwm_interface) {
723a0aa0
JD		 2178 for (i = 0; i < 3; i++) {
2179 if (sio_data->skip_pwm & (1 << i))
2180 continue;
2181 err = sysfs_create_group(&dev->kobj,
2182 &it87_group_pwm[i]);
2183 if (err)
62a1d05f 2184 goto error;
4f3f51bc
JD		 2185
2186 if (!has_old_autopwm(data))
2187 continue;
2188 err = sysfs_create_group(&dev->kobj,
2189 &it87_group_autopwm[i]);
2190 if (err)
62a1d05f 2191 goto error;
98dd22c3 2192 }
1da177e4
LT		 2193 }
2194
895ff267 2195 if (!sio_data->skip_vid) {
303760b4 2196 data->vrm = vid_which_vrm();
87673dd7 2197 /* VID reading from Super-I/O config space if available */
b74f3fdd 2198 data->vid = sio_data->vid_value;
6a8d7acf
JD		 2199 err = sysfs_create_group(&dev->kobj, &it87_group_vid);
2200 if (err)
62a1d05f 2201 goto error;
87808be4
JD		 2202 }
2203
738e5e05
JD		 2204 /* Export labels for internal sensors */
2205 for (i = 0; i < 3; i++) {
2206 if (!(sio_data->internal & (1 << i)))
2207 continue;
2208 err = sysfs_create_file(&dev->kobj,
2209 it87_attributes_label[i]);
2210 if (err)
62a1d05f 2211 goto error;
738e5e05
JD		 2212 }
2213
1beeffe4
TJ		 2214 data->hwmon_dev = hwmon_device_register(dev);
2215 if (IS_ERR(data->hwmon_dev)) {
2216 err = PTR_ERR(data->hwmon_dev);
62a1d05f 2217 goto error;
1da177e4
LT		 2218 }
2219
2220 return 0;
2221
62a1d05f 2222error:
723a0aa0 2223 it87_remove_files(dev);
1da177e4
LT		 2224 return err;
2225}
2226
281dfd0b 2227static int it87_remove(struct platform_device *pdev)
1da177e4 2228{
b74f3fdd 2229 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2230
1beeffe4 2231 hwmon_device_unregister(data->hwmon_dev);
723a0aa0 2232 it87_remove_files(&pdev->dev);
943b0830 2233
1da177e4
LT		 2234 return 0;
2235}
2236
4a0d71cf
GR		 2237/*
2238 * Must be called with data->update_lock held, except during initialization.
2239 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2240 * would slow down the IT87 access and should not be necessary.
2241 */
b74f3fdd 2242static int it87_read_value(struct it87_data *data, u8 reg)
1da177e4 2243{
b74f3fdd 2244 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2245 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2246}
2247
4a0d71cf
GR		 2248/*
2249 * Must be called with data->update_lock held, except during initialization.
2250 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2251 * would slow down the IT87 access and should not be necessary.
2252 */
b74f3fdd 2253static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
1da177e4 2254{
b74f3fdd 2255 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2256 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2257}
2258
2259/* Return 1 if and only if the PWM interface is safe to use */
6c931ae1 2260static int it87_check_pwm(struct device *dev)
1da177e4 2261{
b74f3fdd 2262 struct it87_data *data = dev_get_drvdata(dev);
4a0d71cf
GR		 2263 /*
2264 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
1da177e4 2265 * and polarity set to active low is sign that this is the case so we
4a0d71cf
GR		 2266 * disable pwm control to protect the user.
2267 */
b74f3fdd 2268 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1da177e4
LT		 2269 if ((tmp & 0x87) == 0) {
2270 if (fix_pwm_polarity) {
4a0d71cf
GR		 2271 /*
2272 * The user asks us to attempt a chip reconfiguration.
1da177e4 2273 * This means switching to active high polarity and
4a0d71cf
GR		 2274 * inverting all fan speed values.
2275 */
1da177e4
LT		 2276 int i;
2277 u8 pwm[3];
2278
2279 for (i = 0; i < 3; i++)
b74f3fdd 2280 pwm[i] = it87_read_value(data,
1da177e4
LT		 2281 IT87_REG_PWM(i));
2282
4a0d71cf
GR		 2283 /*
2284 * If any fan is in automatic pwm mode, the polarity
1da177e4
LT		 2285 * might be correct, as suspicious as it seems, so we
2286 * better don't change anything (but still disable the
4a0d71cf
GR		 2287 * PWM interface).
2288 */
1da177e4 2289 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
1d9bcf6a
GR		 2290 dev_info(dev,
2291 "Reconfiguring PWM to active high polarity\n");
b74f3fdd 2292 it87_write_value(data, IT87_REG_FAN_CTL,
1da177e4
LT		 2293 tmp | 0x87);
2294 for (i = 0; i < 3; i++)
b74f3fdd 2295 it87_write_value(data,
1da177e4
LT		 2296 IT87_REG_PWM(i),
2297 0x7f & ~pwm[i]);
2298 return 1;
2299 }
2300
1d9bcf6a
GR		 2301 dev_info(dev,
2302 "PWM configuration is too broken to be fixed\n");
1da177e4
LT		 2303 }
2304
1d9bcf6a
GR		 2305 dev_info(dev,
2306 "Detected broken BIOS defaults, disabling PWM interface\n");
1da177e4
LT		 2307 return 0;
2308 } else if (fix_pwm_polarity) {
1d9bcf6a
GR		 2309 dev_info(dev,
2310 "PWM configuration looks sane, won't touch\n");
1da177e4
LT		 2311 }
2312
2313 return 1;
2314}
2315
2316/* Called when we have found a new IT87. */
6c931ae1 2317static void it87_init_device(struct platform_device *pdev)
1da177e4 2318{
a8b3a3a5 2319 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
b74f3fdd 2320 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2321 int tmp, i;
591ec650 2322 u8 mask;
1da177e4 2323
4a0d71cf
GR		 2324 /*
2325 * For each PWM channel:
b99883dc
JD		 2326 * - If it is in automatic mode, setting to manual mode should set
2327 * the fan to full speed by default.
2328 * - If it is in manual mode, we need a mapping to temperature
2329 * channels to use when later setting to automatic mode later.
2330 * Use a 1:1 mapping by default (we are clueless.)
2331 * In both cases, the value can (and should) be changed by the user
6229cdb2
JD		 2332 * prior to switching to a different mode.
2333 * Note that this is no longer needed for the IT8721F and later, as
2334 * these have separate registers for the temperature mapping and the
4a0d71cf
GR		 2335 * manual duty cycle.
2336 */
1da177e4 2337 for (i = 0; i < 3; i++) {
b99883dc
JD		 2338 data->pwm_temp_map[i] = i;
2339 data->pwm_duty[i] = 0x7f; /* Full speed */
4f3f51bc 2340 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
1da177e4
LT		 2341 }
2342
4a0d71cf
GR		 2343 /*
2344 * Some chips seem to have default value 0xff for all limit
c5df9b7a
JD		 2345 * registers. For low voltage limits it makes no sense and triggers
2346 * alarms, so change to 0 instead. For high temperature limits, it
2347 * means -1 degree C, which surprisingly doesn't trigger an alarm,
4a0d71cf
GR		 2348 * but is still confusing, so change to 127 degrees C.
2349 */
c5df9b7a 2350 for (i = 0; i < 8; i++) {
b74f3fdd 2351 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
c5df9b7a 2352 if (tmp == 0xff)
b74f3fdd 2353 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
c5df9b7a
JD		 2354 }
2355 for (i = 0; i < 3; i++) {
b74f3fdd 2356 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
c5df9b7a 2357 if (tmp == 0xff)
b74f3fdd 2358 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
c5df9b7a
JD		 2359 }
2360
4a0d71cf
GR		 2361 /*
2362 * Temperature channels are not forcibly enabled, as they can be
a00afb97
JD		 2363 * set to two different sensor types and we can't guess which one
2364 * is correct for a given system. These channels can be enabled at
4a0d71cf
GR		 2365 * run-time through the temp{1-3}_type sysfs accessors if needed.
2366 */
1da177e4
LT		 2367
2368 /* Check if voltage monitors are reset manually or by some reason */
b74f3fdd 2369 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
1da177e4
LT		 2370 if ((tmp & 0xff) == 0) {
2371 /* Enable all voltage monitors */
b74f3fdd 2372 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
1da177e4
LT		 2373 }
2374
2375 /* Check if tachometers are reset manually or by some reason */
591ec650 2376 mask = 0x70 & ~(sio_data->skip_fan << 4);
b74f3fdd 2377 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
591ec650 2378 if ((data->fan_main_ctrl & mask) == 0) {
1da177e4 2379 /* Enable all fan tachometers */
591ec650 2380 data->fan_main_ctrl |= mask;
5f2dc798
JD		 2381 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2382 data->fan_main_ctrl);
1da177e4 2383 }
9060f8bd 2384 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
1da177e4 2385
17d648bf 2386 /* Set tachometers to 16-bit mode if needed */
0475169c 2387 if (has_16bit_fans(data)) {
b74f3fdd 2388 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
9060f8bd 2389 if (~tmp & 0x07 & data->has_fan) {
b74f3fdd 2390 dev_dbg(&pdev->dev,
17d648bf 2391 "Setting fan1-3 to 16-bit mode\n");
b74f3fdd 2392 it87_write_value(data, IT87_REG_FAN_16BIT,
17d648bf
JD		 2393 tmp | 0x07);
2394 }
0531d98b
GR		 2395 /* IT8705F, IT8782F, and IT8783E/F only support three fans. */
2396 if (data->type != it87 && data->type != it8782 &&
2397 data->type != it8783) {
816d8c6a
AP		 2398 if (tmp & (1 << 4))
2399 data->has_fan |= (1 << 3); /* fan4 enabled */
2400 if (tmp & (1 << 5))
2401 data->has_fan |= (1 << 4); /* fan5 enabled */
2402 }
17d648bf
JD		 2403 }
2404
591ec650
JD		 2405 /* Fan input pins may be used for alternative functions */
2406 data->has_fan &= ~sio_data->skip_fan;
2407
1da177e4 2408 /* Start monitoring */
b74f3fdd 2409 it87_write_value(data, IT87_REG_CONFIG,
41002f8d 2410 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
1da177e4
LT		 2411 | (update_vbat ? 0x41 : 0x01));
2412}
2413
b99883dc
JD		 2414static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
2415{
2416 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM(nr));
16b5dda2 2417 if (has_newer_autopwm(data)) {
b99883dc 2418 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
6229cdb2
JD		 2419 data->pwm_duty[nr] = it87_read_value(data,
2420 IT87_REG_PWM_DUTY(nr));
2421 } else {
2422 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
2423 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
2424 else /* Manual mode */
2425 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
2426 }
4f3f51bc
JD		 2427
2428 if (has_old_autopwm(data)) {
2429 int i;
2430
2431 for (i = 0; i < 5 ; i++)
2432 data->auto_temp[nr][i] = it87_read_value(data,
2433 IT87_REG_AUTO_TEMP(nr, i));
2434 for (i = 0; i < 3 ; i++)
2435 data->auto_pwm[nr][i] = it87_read_value(data,
2436 IT87_REG_AUTO_PWM(nr, i));
2437 }
b99883dc
JD		 2438}
2439
1da177e4
LT		 2440static struct it87_data *it87_update_device(struct device *dev)
2441{
b74f3fdd 2442 struct it87_data *data = dev_get_drvdata(dev);
1da177e4
LT		 2443 int i;
2444
9a61bf63 2445 mutex_lock(&data->update_lock);
1da177e4
LT		 2446
2447 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
2448 || !data->valid) {
1da177e4 2449 if (update_vbat) {
4a0d71cf
GR		 2450 /*
2451 * Cleared after each update, so reenable. Value
2452 * returned by this read will be previous value
2453 */
b74f3fdd 2454 it87_write_value(data, IT87_REG_CONFIG,
5f2dc798 2455 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1da177e4
LT		 2456 }
2457 for (i = 0; i <= 7; i++) {
929c6a56 2458 data->in[i][0] =
5f2dc798 2459 it87_read_value(data, IT87_REG_VIN(i));
929c6a56 2460 data->in[i][1] =
5f2dc798 2461 it87_read_value(data, IT87_REG_VIN_MIN(i));
929c6a56 2462 data->in[i][2] =
5f2dc798 2463 it87_read_value(data, IT87_REG_VIN_MAX(i));
1da177e4 2464 }
3543a53f 2465 /* in8 (battery) has no limit registers */
929c6a56 2466 data->in[8][0] = it87_read_value(data, IT87_REG_VIN(8));
1da177e4 2467
c7f1f716 2468 for (i = 0; i < 5; i++) {
9060f8bd
JD		 2469 /* Skip disabled fans */
2470 if (!(data->has_fan & (1 << i)))
2471 continue;
2472
e1169ba0 2473 data->fan[i][1] =
5f2dc798 2474 it87_read_value(data, IT87_REG_FAN_MIN[i]);
e1169ba0 2475 data->fan[i][0] = it87_read_value(data,
c7f1f716 2476 IT87_REG_FAN[i]);
17d648bf 2477 /* Add high byte if in 16-bit mode */
0475169c 2478 if (has_16bit_fans(data)) {
e1169ba0 2479 data->fan[i][0] |= it87_read_value(data,
c7f1f716 2480 IT87_REG_FANX[i]) << 8;
e1169ba0 2481 data->fan[i][1] |= it87_read_value(data,
c7f1f716 2482 IT87_REG_FANX_MIN[i]) << 8;
17d648bf 2483 }
1da177e4
LT		 2484 }
2485 for (i = 0; i < 3; i++) {
4573acbc
GR		 2486 if (!(data->has_temp & (1 << i)))
2487 continue;
60ca385a 2488 data->temp[i][0] =
5f2dc798 2489 it87_read_value(data, IT87_REG_TEMP(i));
60ca385a 2490 data->temp[i][1] =
5f2dc798 2491 it87_read_value(data, IT87_REG_TEMP_LOW(i));
60ca385a
GR		 2492 data->temp[i][2] =
2493 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
161d898a
GR		 2494 if (has_temp_offset(data))
2495 data->temp[i][3] =
2496 it87_read_value(data,
2497 IT87_REG_TEMP_OFFSET[i]);
1da177e4
LT		 2498 }
2499
17d648bf 2500 /* Newer chips don't have clock dividers */
0475169c 2501 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
b74f3fdd 2502 i = it87_read_value(data, IT87_REG_FAN_DIV);
17d648bf
JD		 2503 data->fan_div[0] = i & 0x07;
2504 data->fan_div[1] = (i >> 3) & 0x07;
2505 data->fan_div[2] = (i & 0x40) ? 3 : 1;
2506 }
1da177e4
LT		 2507
2508 data->alarms =
b74f3fdd 2509 it87_read_value(data, IT87_REG_ALARM1) |
2510 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
2511 (it87_read_value(data, IT87_REG_ALARM3) << 16);
d9b327c3 2512 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
b99883dc 2513
b74f3fdd 2514 data->fan_main_ctrl = it87_read_value(data,
2515 IT87_REG_FAN_MAIN_CTRL);
2516 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
b99883dc
JD		 2517 for (i = 0; i < 3; i++)
2518 it87_update_pwm_ctrl(data, i);
b74f3fdd 2519
2520 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
19529784 2521 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
4a0d71cf
GR		 2522 /*
2523 * The IT8705F does not have VID capability.
2524 * The IT8718F and later don't use IT87_REG_VID for the
2525 * same purpose.
2526 */
17d648bf 2527 if (data->type == it8712 || data->type == it8716) {
b74f3fdd 2528 data->vid = it87_read_value(data, IT87_REG_VID);
4a0d71cf
GR		 2529 /*
2530 * The older IT8712F revisions had only 5 VID pins,
2531 * but we assume it is always safe to read 6 bits.
2532 */
17d648bf 2533 data->vid &= 0x3f;
1da177e4
LT		 2534 }
2535 data->last_updated = jiffies;
2536 data->valid = 1;
2537 }
2538
9a61bf63 2539 mutex_unlock(&data->update_lock);
1da177e4
LT		 2540
2541 return data;
2542}
2543
b74f3fdd 2544static int __init it87_device_add(unsigned short address,
2545 const struct it87_sio_data *sio_data)
2546{
2547 struct resource res = {
87b4b663
BH		 2548 .start = address + IT87_EC_OFFSET,
2549 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 2550 .name = DRVNAME,
2551 .flags = IORESOURCE_IO,
2552 };
2553 int err;
2554
b9acb64a
JD		 2555 err = acpi_check_resource_conflict(&res);
2556 if (err)
2557 goto exit;
2558
b74f3fdd 2559 pdev = platform_device_alloc(DRVNAME, address);
2560 if (!pdev) {
2561 err = -ENOMEM;
a8ca1037 2562 pr_err("Device allocation failed\n");
b74f3fdd 2563 goto exit;
2564 }
2565
2566 err = platform_device_add_resources(pdev, &res, 1);
2567 if (err) {
a8ca1037 2568 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 2569 goto exit_device_put;
2570 }
2571
2572 err = platform_device_add_data(pdev, sio_data,
2573 sizeof(struct it87_sio_data));
2574 if (err) {
a8ca1037 2575 pr_err("Platform data allocation failed\n");
b74f3fdd 2576 goto exit_device_put;
2577 }
2578
2579 err = platform_device_add(pdev);
2580 if (err) {
a8ca1037 2581 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 2582 goto exit_device_put;
2583 }
2584
2585 return 0;
2586
2587exit_device_put:
2588 platform_device_put(pdev);
2589exit:
2590 return err;
2591}
2592
1da177e4
LT		 2593static int __init sm_it87_init(void)
2594{
b74f3fdd 2595 int err;
5f2dc798 2596 unsigned short isa_address = 0;
b74f3fdd 2597 struct it87_sio_data sio_data;
2598
98dd22c3 2599 memset(&sio_data, 0, sizeof(struct it87_sio_data));
b74f3fdd 2600 err = it87_find(&isa_address, &sio_data);
2601 if (err)
2602 return err;
2603 err = platform_driver_register(&it87_driver);
2604 if (err)
2605 return err;
fde09509 2606
b74f3fdd 2607 err = it87_device_add(isa_address, &sio_data);
5f2dc798 2608 if (err) {
b74f3fdd 2609 platform_driver_unregister(&it87_driver);
2610 return err;
2611 }
2612
2613 return 0;
1da177e4
LT		 2614}
2615
2616static void __exit sm_it87_exit(void)
2617{
b74f3fdd 2618 platform_device_unregister(pdev);
2619 platform_driver_unregister(&it87_driver);
1da177e4
LT		 2620}
2621
2622
1d9bcf6a 2623MODULE_AUTHOR("Chris Gauthron, Jean Delvare <khali@linux-fr.org>");
44c1bcd4 2624MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 2625module_param(update_vbat, bool, 0);
2626MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
2627module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 2628MODULE_PARM_DESC(fix_pwm_polarity,
2629 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 2630MODULE_LICENSE("GPL");
2631
2632module_init(sm_it87_init);
2633module_exit(sm_it87_exit);
Linux 6.x block layer and io_uring tree(s)