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hwmon: (it87) Introduce feature flag to reflect internal in7 sensor
[linux-2.6-block.git] / drivers / hwmon / it87.c
CommitLineData
1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
c145d5c6 13 * Supports: IT8603E Super I/O chip w/LPC interface
574e9bd8 14 * IT8623E Super I/O chip w/LPC interface
c145d5c6 15 * IT8705F Super I/O chip w/LPC interface
5f2dc798
JD		 16 * IT8712F Super I/O chip w/LPC interface
17 * IT8716F Super I/O chip w/LPC interface
18 * IT8718F Super I/O chip w/LPC interface
19 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 20 * IT8721F Super I/O chip w/LPC interface
5f2dc798 21 * IT8726F Super I/O chip w/LPC interface
16b5dda2 22 * IT8728F Super I/O chip w/LPC interface
44c1bcd4 23 * IT8758E Super I/O chip w/LPC interface
b0636707
GR		 24 * IT8771E Super I/O chip w/LPC interface
25 * IT8772E Super I/O chip w/LPC interface
7bc32d29 26 * IT8781F Super I/O chip w/LPC interface
0531d98b
GR		 27 * IT8782F Super I/O chip w/LPC interface
28 * IT8783E/F Super I/O chip w/LPC interface
a0c1424a 29 * IT8786E Super I/O chip w/LPC interface
5f2dc798
JD		 30 * Sis950 A clone of the IT8705F
31 *
32 * Copyright (C) 2001 Chris Gauthron
7c81c60f 33 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
5f2dc798
JD		 34 *
35 * This program is free software; you can redistribute it and/or modify
36 * it under the terms of the GNU General Public License as published by
37 * the Free Software Foundation; either version 2 of the License, or
38 * (at your option) any later version.
39 *
40 * This program is distributed in the hope that it will be useful,
41 * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 * GNU General Public License for more details.
44 *
45 * You should have received a copy of the GNU General Public License
46 * along with this program; if not, write to the Free Software
47 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
48 */
1da177e4 49
a8ca1037
JP		 50#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51
1da177e4
LT		 52#include <linux/module.h>
53#include <linux/init.h>
54#include <linux/slab.h>
55#include <linux/jiffies.h>
b74f3fdd 56#include <linux/platform_device.h>
943b0830 57#include <linux/hwmon.h>
303760b4
JD		 58#include <linux/hwmon-sysfs.h>
59#include <linux/hwmon-vid.h>
943b0830 60#include <linux/err.h>
9a61bf63 61#include <linux/mutex.h>
87808be4 62#include <linux/sysfs.h>
98dd22c3
JD		 63#include <linux/string.h>
64#include <linux/dmi.h>
b9acb64a 65#include <linux/acpi.h>
6055fae8 66#include <linux/io.h>
1da177e4 67
b74f3fdd 68#define DRVNAME "it87"
1da177e4 69
b0636707 70enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8771,
a0c1424a 71 it8772, it8781, it8782, it8783, it8786, it8603 };
1da177e4 72
67b671bc
JD		 73static unsigned short force_id;
74module_param(force_id, ushort, 0);
75MODULE_PARM_DESC(force_id, "Override the detected device ID");
76
b74f3fdd 77static struct platform_device *pdev;
78
1da177e4
LT		 79#define REG 0x2e /* The register to read/write */
80#define DEV 0x07 /* Register: Logical device select */
81#define VAL 0x2f /* The value to read/write */
82#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 83
84/* The device with the IT8718F/IT8720F VID value in it */
85#define GPIO 0x07
86
1da177e4
LT		 87#define DEVID 0x20 /* Register: Device ID */
88#define DEVREV 0x22 /* Register: Device Revision */
89
5b0380c9 90static inline int superio_inb(int reg)
1da177e4
LT		 91{
92 outb(reg, REG);
93 return inb(VAL);
94}
95
5b0380c9 96static inline void superio_outb(int reg, int val)
436cad2a
JD		 97{
98 outb(reg, REG);
99 outb(val, VAL);
100}
101
1da177e4
LT		 102static int superio_inw(int reg)
103{
104 int val;
105 outb(reg++, REG);
106 val = inb(VAL) << 8;
107 outb(reg, REG);
108 val |= inb(VAL);
109 return val;
110}
111
5b0380c9 112static inline void superio_select(int ldn)
1da177e4
LT		 113{
114 outb(DEV, REG);
87673dd7 115 outb(ldn, VAL);
1da177e4
LT		 116}
117
5b0380c9 118static inline int superio_enter(void)
1da177e4 119{
5b0380c9
NG		 120 /*
121 * Try to reserve REG and REG + 1 for exclusive access.
122 */
123 if (!request_muxed_region(REG, 2, DRVNAME))
124 return -EBUSY;
125
1da177e4
LT		 126 outb(0x87, REG);
127 outb(0x01, REG);
128 outb(0x55, REG);
129 outb(0x55, REG);
5b0380c9 130 return 0;
1da177e4
LT		 131}
132
5b0380c9 133static inline void superio_exit(void)
1da177e4
LT		 134{
135 outb(0x02, REG);
136 outb(0x02, VAL);
5b0380c9 137 release_region(REG, 2);
1da177e4
LT		 138}
139
87673dd7 140/* Logical device 4 registers */
1da177e4
LT		 141#define IT8712F_DEVID 0x8712
142#define IT8705F_DEVID 0x8705
17d648bf 143#define IT8716F_DEVID 0x8716
87673dd7 144#define IT8718F_DEVID 0x8718
b4da93e4 145#define IT8720F_DEVID 0x8720
44c1bcd4 146#define IT8721F_DEVID 0x8721
08a8f6e9 147#define IT8726F_DEVID 0x8726
16b5dda2 148#define IT8728F_DEVID 0x8728
b0636707
GR		 149#define IT8771E_DEVID 0x8771
150#define IT8772E_DEVID 0x8772
7bc32d29 151#define IT8781F_DEVID 0x8781
0531d98b
GR		 152#define IT8782F_DEVID 0x8782
153#define IT8783E_DEVID 0x8783
a0c1424a 154#define IT8786E_DEVID 0x8786
7183ae8c 155#define IT8603E_DEVID 0x8603
574e9bd8 156#define IT8623E_DEVID 0x8623
1da177e4
LT		 157#define IT87_ACT_REG 0x30
158#define IT87_BASE_REG 0x60
159
87673dd7 160/* Logical device 7 registers (IT8712F and later) */
0531d98b 161#define IT87_SIO_GPIO1_REG 0x25
895ff267 162#define IT87_SIO_GPIO3_REG 0x27
591ec650 163#define IT87_SIO_GPIO5_REG 0x29
0531d98b 164#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 165#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 166#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 167#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 168#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 169
1da177e4 170/* Update battery voltage after every reading if true */
90ab5ee9 171static bool update_vbat;
1da177e4
LT		 172
173/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 174static bool fix_pwm_polarity;
1da177e4 175
1da177e4
LT		 176/* Many IT87 constants specified below */
177
178/* Length of ISA address segment */
179#define IT87_EXTENT 8
180
87b4b663
BH		 181/* Length of ISA address segment for Environmental Controller */
182#define IT87_EC_EXTENT 2
183
184/* Offset of EC registers from ISA base address */
185#define IT87_EC_OFFSET 5
186
187/* Where are the ISA address/data registers relative to the EC base address */
188#define IT87_ADDR_REG_OFFSET 0
189#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 190
191/*----- The IT87 registers -----*/
192
193#define IT87_REG_CONFIG 0x00
194
195#define IT87_REG_ALARM1 0x01
196#define IT87_REG_ALARM2 0x02
197#define IT87_REG_ALARM3 0x03
198
4a0d71cf
GR		 199/*
200 * The IT8718F and IT8720F have the VID value in a different register, in
201 * Super-I/O configuration space.
202 */
1da177e4 203#define IT87_REG_VID 0x0a
4a0d71cf
GR		 204/*
205 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
206 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
207 * mode.
208 */
1da177e4 209#define IT87_REG_FAN_DIV 0x0b
17d648bf 210#define IT87_REG_FAN_16BIT 0x0c
1da177e4
LT		 211
212/* Monitors: 9 voltage (0 to 7, battery), 3 temp (1 to 3), 3 fan (1 to 3) */
213
c7f1f716
JD		 214static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82 };
215static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86 };
216static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83 };
217static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 };
161d898a
GR		 218static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
219
1da177e4
LT		 220#define IT87_REG_FAN_MAIN_CTRL 0x13
221#define IT87_REG_FAN_CTL 0x14
222#define IT87_REG_PWM(nr) (0x15 + (nr))
6229cdb2 223#define IT87_REG_PWM_DUTY(nr) (0x63 + (nr) * 8)
1da177e4
LT		 224
225#define IT87_REG_VIN(nr) (0x20 + (nr))
226#define IT87_REG_TEMP(nr) (0x29 + (nr))
227
228#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
229#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
230#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
231#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
232
1da177e4
LT		 233#define IT87_REG_VIN_ENABLE 0x50
234#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 235#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 236#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 237
238#define IT87_REG_CHIPID 0x58
239
4f3f51bc
JD		 240#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
241#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
242
483db43e
GR		 243struct it87_devices {
244 const char *name;
faf392fb 245 const char * const suffix;
483db43e 246 u16 features;
19529784
GR		 247 u8 peci_mask;
248 u8 old_peci_mask;
483db43e
GR		 249};
250
251#define FEAT_12MV_ADC (1 << 0)
252#define FEAT_NEWER_AUTOPWM (1 << 1)
253#define FEAT_OLD_AUTOPWM (1 << 2)
254#define FEAT_16BIT_FANS (1 << 3)
255#define FEAT_TEMP_OFFSET (1 << 4)
5d8d2f2b 256#define FEAT_TEMP_PECI (1 << 5)
19529784 257#define FEAT_TEMP_OLD_PECI (1 << 6)
9faf28ca
GR		 258#define FEAT_FAN16_CONFIG (1 << 7) /* Need to enable 16-bit fans */
259#define FEAT_FIVE_FANS (1 << 8) /* Supports five fans */
32dd7c40 260#define FEAT_VID (1 << 9) /* Set if chip supports VID */
7f5726c3 261#define FEAT_IN7_INTERNAL (1 << 10) /* Set if in7 is internal */
483db43e
GR		 262
263static const struct it87_devices it87_devices[] = {
264 [it87] = {
265 .name = "it87",
faf392fb 266 .suffix = "F",
483db43e
GR		 267 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
268 },
269 [it8712] = {
270 .name = "it8712",
faf392fb 271 .suffix = "F",
32dd7c40
GR		 272 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
273 /* may need to overwrite */
483db43e
GR		 274 },
275 [it8716] = {
276 .name = "it8716",
faf392fb 277 .suffix = "F",
32dd7c40 278 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
9faf28ca 279 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
483db43e
GR		 280 },
281 [it8718] = {
282 .name = "it8718",
faf392fb 283 .suffix = "F",
32dd7c40 284 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
9faf28ca 285 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
19529784 286 .old_peci_mask = 0x4,
483db43e
GR		 287 },
288 [it8720] = {
289 .name = "it8720",
faf392fb 290 .suffix = "F",
32dd7c40 291 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
9faf28ca 292 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
19529784 293 .old_peci_mask = 0x4,
483db43e
GR		 294 },
295 [it8721] = {
296 .name = "it8721",
faf392fb 297 .suffix = "F",
483db43e 298 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
9faf28ca 299 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
7f5726c3 300 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL,
5d8d2f2b 301 .peci_mask = 0x05,
19529784 302 .old_peci_mask = 0x02, /* Actually reports PCH */
483db43e
GR		 303 },
304 [it8728] = {
305 .name = "it8728",
faf392fb 306 .suffix = "F",
483db43e 307 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
7f5726c3
GR		 308 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
309 | FEAT_IN7_INTERNAL,
5d8d2f2b 310 .peci_mask = 0x07,
483db43e 311 },
b0636707
GR		 312 [it8771] = {
313 .name = "it8771",
faf392fb 314 .suffix = "E",
b0636707 315 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
7f5726c3 316 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL,
9faf28ca
GR		 317 /* PECI: guesswork */
318 /* 12mV ADC (OHM) */
319 /* 16 bit fans (OHM) */
320 /* three fans, always 16 bit (guesswork) */
b0636707
GR		 321 .peci_mask = 0x07,
322 },
323 [it8772] = {
324 .name = "it8772",
faf392fb 325 .suffix = "E",
b0636707 326 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
7f5726c3 327 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL,
9faf28ca
GR		 328 /* PECI (coreboot) */
329 /* 12mV ADC (HWSensors4, OHM) */
330 /* 16 bit fans (HWSensors4, OHM) */
331 /* three fans, always 16 bit (datasheet) */
b0636707
GR		 332 .peci_mask = 0x07,
333 },
7bc32d29
GR		 334 [it8781] = {
335 .name = "it8781",
faf392fb 336 .suffix = "F",
7bc32d29 337 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
9faf28ca 338 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG,
7bc32d29
GR		 339 .old_peci_mask = 0x4,
340 },
483db43e
GR		 341 [it8782] = {
342 .name = "it8782",
faf392fb 343 .suffix = "F",
19529784 344 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
9faf28ca 345 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG,
19529784 346 .old_peci_mask = 0x4,
483db43e
GR		 347 },
348 [it8783] = {
349 .name = "it8783",
faf392fb 350 .suffix = "E/F",
19529784 351 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
9faf28ca 352 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG,
19529784 353 .old_peci_mask = 0x4,
483db43e 354 },
a0c1424a
TL		 355 [it8786] = {
356 .name = "it8786",
faf392fb 357 .suffix = "E",
a0c1424a 358 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
7f5726c3 359 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL,
a0c1424a
TL		 360 .peci_mask = 0x07,
361 },
c145d5c6
RM		 362 [it8603] = {
363 .name = "it8603",
faf392fb 364 .suffix = "E",
c145d5c6 365 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
7f5726c3 366 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL,
c145d5c6
RM		 367 .peci_mask = 0x07,
368 },
483db43e
GR		 369};
370
371#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
372#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
373#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
374#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
375#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b
GR		 376#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
377 ((data)->peci_mask & (1 << nr)))
19529784
GR		 378#define has_temp_old_peci(data, nr) \
379 (((data)->features & FEAT_TEMP_OLD_PECI) && \
380 ((data)->old_peci_mask & (1 << nr)))
9faf28ca
GR		 381#define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
382#define has_five_fans(data) ((data)->features & FEAT_FIVE_FANS)
32dd7c40 383#define has_vid(data) ((data)->features & FEAT_VID)
7f5726c3 384#define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
1da177e4 385
b74f3fdd 386struct it87_sio_data {
387 enum chips type;
388 /* Values read from Super-I/O config space */
0475169c 389 u8 revision;
b74f3fdd 390 u8 vid_value;
d9b327c3 391 u8 beep_pin;
738e5e05 392 u8 internal; /* Internal sensors can be labeled */
591ec650 393 /* Features skipped based on config or DMI */
9172b5d1 394 u16 skip_in;
895ff267 395 u8 skip_vid;
591ec650 396 u8 skip_fan;
98dd22c3 397 u8 skip_pwm;
4573acbc 398 u8 skip_temp;
b74f3fdd 399};
400
4a0d71cf
GR		 401/*
402 * For each registered chip, we need to keep some data in memory.
403 * The structure is dynamically allocated.
404 */
1da177e4 405struct it87_data {
1beeffe4 406 struct device *hwmon_dev;
1da177e4 407 enum chips type;
483db43e 408 u16 features;
19529784
GR		 409 u8 peci_mask;
410 u8 old_peci_mask;
1da177e4 411
b74f3fdd 412 unsigned short addr;
413 const char *name;
9a61bf63 414 struct mutex update_lock;
1da177e4
LT		 415 char valid; /* !=0 if following fields are valid */
416 unsigned long last_updated; /* In jiffies */
417
44c1bcd4 418 u16 in_scaled; /* Internal voltage sensors are scaled */
c145d5c6 419 u8 in[10][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 420 u8 has_fan; /* Bitfield, fans enabled */
e1169ba0 421 u16 fan[5][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 422 u8 has_temp; /* Bitfield, temp sensors enabled */
161d898a 423 s8 temp[3][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
19529784
GR		 424 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
425 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
1da177e4
LT		 426 u8 fan_div[3]; /* Register encoding, shifted right */
427 u8 vid; /* Register encoding, combined */
a7be58a1 428 u8 vrm;
1da177e4 429 u32 alarms; /* Register encoding, combined */
d9b327c3 430 u8 beeps; /* Register encoding */
1da177e4 431 u8 fan_main_ctrl; /* Register value */
f8d0c19a 432 u8 fan_ctl; /* Register value */
b99883dc 433
4a0d71cf
GR		 434 /*
435 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 436 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
437 * 7, and we want to preserve settings on mode changes, so we have
438 * to track all values separately.
439 * Starting with the IT8721F, the manual PWM duty cycles are stored
440 * in separate registers (8-bit values), so the separate tracking
441 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 442 * simple.
443 */
b99883dc 444 u8 pwm_ctrl[3]; /* Register value */
6229cdb2 445 u8 pwm_duty[3]; /* Manual PWM value set by user */
b99883dc 446 u8 pwm_temp_map[3]; /* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 447
448 /* Automatic fan speed control registers */
449 u8 auto_pwm[3][4]; /* [nr][3] is hard-coded */
450 s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 451};
0df6454d 452
0531d98b 453static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 454{
0531d98b
GR		 455 int lsb = has_12mv_adc(data) ? 12 : 16;
456 if (data->in_scaled & (1 << nr))
457 lsb <<= 1;
458 return lsb;
459}
44c1bcd4 460
0531d98b
GR		 461static u8 in_to_reg(const struct it87_data *data, int nr, long val)
462{
463 val = DIV_ROUND_CLOSEST(val, adc_lsb(data, nr));
2a844c14 464 return clamp_val(val, 0, 255);
44c1bcd4
JD		 465}
466
467static int in_from_reg(const struct it87_data *data, int nr, int val)
468{
0531d98b 469 return val * adc_lsb(data, nr);
44c1bcd4 470}
0df6454d
JD		 471
472static inline u8 FAN_TO_REG(long rpm, int div)
473{
474 if (rpm == 0)
475 return 255;
2a844c14
GR		 476 rpm = clamp_val(rpm, 1, 1000000);
477 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
0df6454d
JD		 478}
479
480static inline u16 FAN16_TO_REG(long rpm)
481{
482 if (rpm == 0)
483 return 0xffff;
2a844c14 484 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
0df6454d
JD		 485}
486
487#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
488 1350000 / ((val) * (div)))
489/* The divider is fixed to 2 in 16-bit mode */
490#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
491 1350000 / ((val) * 2))
492
2a844c14
GR		 493#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
494 ((val) + 500) / 1000), -128, 127))
0df6454d
JD		 495#define TEMP_FROM_REG(val) ((val) * 1000)
496
44c1bcd4
JD		 497static u8 pwm_to_reg(const struct it87_data *data, long val)
498{
16b5dda2 499 if (has_newer_autopwm(data))
44c1bcd4
JD		 500 return val;
501 else
502 return val >> 1;
503}
504
505static int pwm_from_reg(const struct it87_data *data, u8 reg)
506{
16b5dda2 507 if (has_newer_autopwm(data))
44c1bcd4
JD		 508 return reg;
509 else
510 return (reg & 0x7f) << 1;
511}
512
0df6454d
JD		 513
514static int DIV_TO_REG(int val)
515{
516 int answer = 0;
517 while (answer < 7 && (val >>= 1))
518 answer++;
519 return answer;
520}
521#define DIV_FROM_REG(val) (1 << (val))
522
f56c9c0a
GR		 523/*
524 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
525 * depending on the chip type, to calculate the actual PWM frequency.
526 *
527 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
528 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
529 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
530 * sometimes just one. It is unknown if this is a datasheet error or real,
531 * so this is ignored for now.
532 */
0df6454d 533static const unsigned int pwm_freq[8] = {
f56c9c0a
GR		 534 48000000,
535 24000000,
536 12000000,
537 8000000,
538 6000000,
539 3000000,
540 1500000,
541 750000,
0df6454d 542};
1da177e4 543
b74f3fdd 544static int it87_probe(struct platform_device *pdev);
281dfd0b 545static int it87_remove(struct platform_device *pdev);
1da177e4 546
b74f3fdd 547static int it87_read_value(struct it87_data *data, u8 reg);
548static void it87_write_value(struct it87_data *data, u8 reg, u8 value);
1da177e4 549static struct it87_data *it87_update_device(struct device *dev);
b74f3fdd 550static int it87_check_pwm(struct device *dev);
551static void it87_init_device(struct platform_device *pdev);
1da177e4
LT		 552
553
b74f3fdd 554static struct platform_driver it87_driver = {
cdaf7934 555 .driver = {
b74f3fdd 556 .name = DRVNAME,
cdaf7934 557 },
b74f3fdd 558 .probe = it87_probe,
9e5e9b7a 559 .remove = it87_remove,
fde09509
JD		 560};
561
20ad93d4 562static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 563 char *buf)
1da177e4 564{
929c6a56
GR		 565 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
566 int nr = sattr->nr;
567 int index = sattr->index;
20ad93d4 568
1da177e4 569 struct it87_data *data = it87_update_device(dev);
929c6a56 570 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 571}
572
929c6a56
GR		 573static ssize_t set_in(struct device *dev, struct device_attribute *attr,
574 const char *buf, size_t count)
1da177e4 575{
929c6a56
GR		 576 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
577 int nr = sattr->nr;
578 int index = sattr->index;
20ad93d4 579
b74f3fdd 580 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 581 unsigned long val;
582
179c4fdb 583 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 584 return -EINVAL;
1da177e4 585
9a61bf63 586 mutex_lock(&data->update_lock);
929c6a56
GR		 587 data->in[nr][index] = in_to_reg(data, nr, val);
588 it87_write_value(data,
589 index == 1 ? IT87_REG_VIN_MIN(nr)
590 : IT87_REG_VIN_MAX(nr),
591 data->in[nr][index]);
9a61bf63 592 mutex_unlock(&data->update_lock);
1da177e4
LT		 593 return count;
594}
20ad93d4 595
929c6a56
GR		 596static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
597static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
598 0, 1);
599static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
600 0, 2);
f5f64501 601
929c6a56
GR		 602static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
603static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
604 1, 1);
605static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
606 1, 2);
1da177e4 607
929c6a56
GR		 608static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
609static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
610 2, 1);
611static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
612 2, 2);
1da177e4 613
929c6a56
GR		 614static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
615static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
616 3, 1);
617static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
618 3, 2);
619
620static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
621static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
622 4, 1);
623static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
624 4, 2);
625
626static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
627static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
628 5, 1);
629static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
630 5, 2);
631
632static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
633static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
634 6, 1);
635static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
636 6, 2);
637
638static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
639static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
640 7, 1);
641static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
642 7, 2);
643
644static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
c145d5c6 645static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1da177e4
LT		 646
647/* 3 temperatures */
20ad93d4 648static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 649 char *buf)
1da177e4 650{
60ca385a
GR		 651 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
652 int nr = sattr->nr;
653 int index = sattr->index;
1da177e4 654 struct it87_data *data = it87_update_device(dev);
20ad93d4 655
60ca385a 656 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 657}
20ad93d4 658
60ca385a
GR		 659static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
660 const char *buf, size_t count)
1da177e4 661{
60ca385a
GR		 662 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
663 int nr = sattr->nr;
664 int index = sattr->index;
b74f3fdd 665 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 666 long val;
161d898a 667 u8 reg, regval;
f5f64501 668
179c4fdb 669 if (kstrtol(buf, 10, &val) < 0)
f5f64501 670 return -EINVAL;
1da177e4 671
9a61bf63 672 mutex_lock(&data->update_lock);
161d898a
GR		 673
674 switch (index) {
675 default:
676 case 1:
677 reg = IT87_REG_TEMP_LOW(nr);
678 break;
679 case 2:
680 reg = IT87_REG_TEMP_HIGH(nr);
681 break;
682 case 3:
683 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
684 if (!(regval & 0x80)) {
685 regval |= 0x80;
686 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
687 }
688 data->valid = 0;
689 reg = IT87_REG_TEMP_OFFSET[nr];
690 break;
691 }
692
60ca385a 693 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 694 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 695 mutex_unlock(&data->update_lock);
1da177e4
LT		 696 return count;
697}
1da177e4 698
60ca385a
GR		 699static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
700static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
701 0, 1);
702static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
703 0, 2);
161d898a
GR		 704static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
705 set_temp, 0, 3);
60ca385a
GR		 706static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
707static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
708 1, 1);
709static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
710 1, 2);
161d898a
GR		 711static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
712 set_temp, 1, 3);
60ca385a
GR		 713static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
714static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
715 2, 1);
716static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
717 2, 2);
161d898a
GR		 718static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
719 set_temp, 2, 3);
1da177e4 720
2cece01f
GR		 721static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
722 char *buf)
1da177e4 723{
20ad93d4
JD		 724 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
725 int nr = sensor_attr->index;
1da177e4 726 struct it87_data *data = it87_update_device(dev);
4a0d71cf 727 u8 reg = data->sensor; /* In case value is updated while used */
19529784 728 u8 extra = data->extra;
5f2dc798 729
19529784
GR		 730 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1))
731 || (has_temp_old_peci(data, nr) && (extra & 0x80)))
5d8d2f2b 732 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 733 if (reg & (1 << nr))
734 return sprintf(buf, "3\n"); /* thermal diode */
735 if (reg & (8 << nr))
4ed10779 736 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 737 return sprintf(buf, "0\n"); /* disabled */
738}
2cece01f
GR		 739
740static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
741 const char *buf, size_t count)
1da177e4 742{
20ad93d4
JD		 743 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
744 int nr = sensor_attr->index;
745
b74f3fdd 746 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 747 long val;
19529784 748 u8 reg, extra;
f5f64501 749
179c4fdb 750 if (kstrtol(buf, 10, &val) < 0)
f5f64501 751 return -EINVAL;
1da177e4 752
8acf07c5
JD		 753 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
754 reg &= ~(1 << nr);
755 reg &= ~(8 << nr);
5d8d2f2b
GR		 756 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
757 reg &= 0x3f;
19529784
GR		 758 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
759 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
760 extra &= 0x7f;
4ed10779 761 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 762 dev_warn(dev,
763 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 764 val = 4;
765 }
5d8d2f2b 766 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 767 if (val == 3)
8acf07c5 768 reg |= 1 << nr;
4ed10779 769 else if (val == 4)
8acf07c5 770 reg |= 8 << nr;
5d8d2f2b
GR		 771 else if (has_temp_peci(data, nr) && val == 6)
772 reg |= (nr + 1) << 6;
19529784
GR		 773 else if (has_temp_old_peci(data, nr) && val == 6)
774 extra |= 0x80;
8acf07c5 775 else if (val != 0)
1da177e4 776 return -EINVAL;
8acf07c5
JD		 777
778 mutex_lock(&data->update_lock);
779 data->sensor = reg;
19529784 780 data->extra = extra;
b74f3fdd 781 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
19529784
GR		 782 if (has_temp_old_peci(data, nr))
783 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2b3d1d87 784 data->valid = 0; /* Force cache refresh */
9a61bf63 785 mutex_unlock(&data->update_lock);
1da177e4
LT		 786 return count;
787}
1da177e4 788
2cece01f
GR		 789static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
790 set_temp_type, 0);
791static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
792 set_temp_type, 1);
793static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
794 set_temp_type, 2);
1da177e4
LT		 795
796/* 3 Fans */
b99883dc
JD		 797
798static int pwm_mode(const struct it87_data *data, int nr)
799{
800 int ctrl = data->fan_main_ctrl & (1 << nr);
801
c145d5c6 802 if (ctrl == 0 && data->type != it8603) /* Full speed */
b99883dc
JD		 803 return 0;
804 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
805 return 2;
806 else /* Manual mode */
807 return 1;
808}
809
20ad93d4 810static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 811 char *buf)
1da177e4 812{
e1169ba0
GR		 813 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
814 int nr = sattr->nr;
815 int index = sattr->index;
816 int speed;
1da177e4 817 struct it87_data *data = it87_update_device(dev);
20ad93d4 818
e1169ba0
GR		 819 speed = has_16bit_fans(data) ?
820 FAN16_FROM_REG(data->fan[nr][index]) :
821 FAN_FROM_REG(data->fan[nr][index],
822 DIV_FROM_REG(data->fan_div[nr]));
823 return sprintf(buf, "%d\n", speed);
1da177e4 824}
e1169ba0 825
20ad93d4
JD		 826static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
827 char *buf)
1da177e4 828{
20ad93d4
JD		 829 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
830 int nr = sensor_attr->index;
831
1da177e4
LT		 832 struct it87_data *data = it87_update_device(dev);
833 return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr]));
834}
5f2dc798
JD		 835static ssize_t show_pwm_enable(struct device *dev,
836 struct device_attribute *attr, char *buf)
1da177e4 837{
20ad93d4
JD		 838 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
839 int nr = sensor_attr->index;
840
1da177e4 841 struct it87_data *data = it87_update_device(dev);
b99883dc 842 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 843}
20ad93d4
JD		 844static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
845 char *buf)
1da177e4 846{
20ad93d4
JD		 847 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
848 int nr = sensor_attr->index;
849
1da177e4 850 struct it87_data *data = it87_update_device(dev);
44c1bcd4
JD		 851 return sprintf(buf, "%d\n",
852 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 853}
f8d0c19a
JD		 854static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
855 char *buf)
856{
857 struct it87_data *data = it87_update_device(dev);
858 int index = (data->fan_ctl >> 4) & 0x07;
f56c9c0a 859 unsigned int freq;
f8d0c19a 860
f56c9c0a
GR		 861 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
862
863 return sprintf(buf, "%u\n", freq);
f8d0c19a 864}
e1169ba0
GR		 865
866static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
867 const char *buf, size_t count)
1da177e4 868{
e1169ba0
GR		 869 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
870 int nr = sattr->nr;
871 int index = sattr->index;
20ad93d4 872
b74f3fdd 873 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 874 long val;
7f999aa7 875 u8 reg;
1da177e4 876
179c4fdb 877 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 878 return -EINVAL;
879
9a61bf63 880 mutex_lock(&data->update_lock);
e1169ba0
GR		 881
882 if (has_16bit_fans(data)) {
883 data->fan[nr][index] = FAN16_TO_REG(val);
884 it87_write_value(data, IT87_REG_FAN_MIN[nr],
885 data->fan[nr][index] & 0xff);
886 it87_write_value(data, IT87_REG_FANX_MIN[nr],
887 data->fan[nr][index] >> 8);
888 } else {
889 reg = it87_read_value(data, IT87_REG_FAN_DIV);
890 switch (nr) {
891 case 0:
892 data->fan_div[nr] = reg & 0x07;
893 break;
894 case 1:
895 data->fan_div[nr] = (reg >> 3) & 0x07;
896 break;
897 case 2:
898 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
899 break;
900 }
901 data->fan[nr][index] =
902 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
903 it87_write_value(data, IT87_REG_FAN_MIN[nr],
904 data->fan[nr][index]);
07eab46d
JD		 905 }
906
9a61bf63 907 mutex_unlock(&data->update_lock);
1da177e4
LT		 908 return count;
909}
e1169ba0 910
20ad93d4
JD		 911static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
912 const char *buf, size_t count)
1da177e4 913{
20ad93d4
JD		 914 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
915 int nr = sensor_attr->index;
916
b74f3fdd 917 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 918 unsigned long val;
8ab4ec3e 919 int min;
1da177e4
LT		 920 u8 old;
921
179c4fdb 922 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 923 return -EINVAL;
924
9a61bf63 925 mutex_lock(&data->update_lock);
b74f3fdd 926 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 927
8ab4ec3e 928 /* Save fan min limit */
e1169ba0 929 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 930
931 switch (nr) {
932 case 0:
933 case 1:
934 data->fan_div[nr] = DIV_TO_REG(val);
935 break;
936 case 2:
937 if (val < 8)
938 data->fan_div[nr] = 1;
939 else
940 data->fan_div[nr] = 3;
941 }
942 val = old & 0x80;
943 val |= (data->fan_div[0] & 0x07);
944 val |= (data->fan_div[1] & 0x07) << 3;
945 if (data->fan_div[2] == 3)
946 val |= 0x1 << 6;
b74f3fdd 947 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 948
8ab4ec3e 949 /* Restore fan min limit */
e1169ba0
GR		 950 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
951 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 952
9a61bf63 953 mutex_unlock(&data->update_lock);
1da177e4
LT		 954 return count;
955}
cccfc9c4
JD		 956
957/* Returns 0 if OK, -EINVAL otherwise */
958static int check_trip_points(struct device *dev, int nr)
959{
960 const struct it87_data *data = dev_get_drvdata(dev);
961 int i, err = 0;
962
963 if (has_old_autopwm(data)) {
964 for (i = 0; i < 3; i++) {
965 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
966 err = -EINVAL;
967 }
968 for (i = 0; i < 2; i++) {
969 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
970 err = -EINVAL;
971 }
972 }
973
974 if (err) {
1d9bcf6a
GR		 975 dev_err(dev,
976 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 977 dev_err(dev, "Adjust the trip points and try again\n");
978 }
979 return err;
980}
981
20ad93d4
JD		 982static ssize_t set_pwm_enable(struct device *dev,
983 struct device_attribute *attr, const char *buf, size_t count)
1da177e4 984{
20ad93d4
JD		 985 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
986 int nr = sensor_attr->index;
987
b74f3fdd 988 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 989 long val;
1da177e4 990
179c4fdb 991 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 992 return -EINVAL;
993
cccfc9c4
JD		 994 /* Check trip points before switching to automatic mode */
995 if (val == 2) {
996 if (check_trip_points(dev, nr) < 0)
997 return -EINVAL;
998 }
999
c145d5c6
RM		 1000 /* IT8603E does not have on/off mode */
1001 if (val == 0 && data->type == it8603)
1002 return -EINVAL;
1003
9a61bf63 1004 mutex_lock(&data->update_lock);
1da177e4
LT		 1005
1006 if (val == 0) {
1007 int tmp;
1008 /* make sure the fan is on when in on/off mode */
b74f3fdd 1009 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1010 it87_write_value(data, IT87_REG_FAN_CTL, tmp | (1 << nr));
1da177e4
LT		 1011 /* set on/off mode */
1012 data->fan_main_ctrl &= ~(1 << nr);
5f2dc798
JD		 1013 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1014 data->fan_main_ctrl);
b99883dc
JD		 1015 } else {
1016 if (val == 1) /* Manual mode */
16b5dda2 1017 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 1018 data->pwm_temp_map[nr] :
1019 data->pwm_duty[nr];
b99883dc
JD		 1020 else /* Automatic mode */
1021 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
1022 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
c145d5c6
RM		 1023
1024 if (data->type != it8603) {
1025 /* set SmartGuardian mode */
1026 data->fan_main_ctrl |= (1 << nr);
1027 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1028 data->fan_main_ctrl);
1029 }
1da177e4
LT		 1030 }
1031
9a61bf63 1032 mutex_unlock(&data->update_lock);
1da177e4
LT		 1033 return count;
1034}
20ad93d4
JD		 1035static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1036 const char *buf, size_t count)
1da177e4 1037{
20ad93d4
JD		 1038 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1039 int nr = sensor_attr->index;
1040
b74f3fdd 1041 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1042 long val;
1da177e4 1043
179c4fdb 1044 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 1045 return -EINVAL;
1046
9a61bf63 1047 mutex_lock(&data->update_lock);
16b5dda2 1048 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 1049 /*
1050 * If we are in automatic mode, the PWM duty cycle register
1051 * is read-only so we can't write the value.
1052 */
6229cdb2
JD		 1053 if (data->pwm_ctrl[nr] & 0x80) {
1054 mutex_unlock(&data->update_lock);
1055 return -EBUSY;
1056 }
1057 data->pwm_duty[nr] = pwm_to_reg(data, val);
1058 it87_write_value(data, IT87_REG_PWM_DUTY(nr),
1059 data->pwm_duty[nr]);
1060 } else {
1061 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 1062 /*
1063 * If we are in manual mode, write the duty cycle immediately;
1064 * otherwise, just store it for later use.
1065 */
6229cdb2
JD		 1066 if (!(data->pwm_ctrl[nr] & 0x80)) {
1067 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1068 it87_write_value(data, IT87_REG_PWM(nr),
1069 data->pwm_ctrl[nr]);
1070 }
b99883dc 1071 }
9a61bf63 1072 mutex_unlock(&data->update_lock);
1da177e4
LT		 1073 return count;
1074}
f8d0c19a
JD		 1075static ssize_t set_pwm_freq(struct device *dev,
1076 struct device_attribute *attr, const char *buf, size_t count)
1077{
b74f3fdd 1078 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1079 unsigned long val;
f8d0c19a
JD		 1080 int i;
1081
179c4fdb 1082 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1083 return -EINVAL;
f56c9c0a
GR		 1084
1085 val = clamp_val(val, 0, 1000000);
1086 val *= has_newer_autopwm(data) ? 256 : 128;
f5f64501 1087
f8d0c19a
JD		 1088 /* Search for the nearest available frequency */
1089 for (i = 0; i < 7; i++) {
1090 if (val > (pwm_freq[i] + pwm_freq[i+1]) / 2)
1091 break;
1092 }
1093
1094 mutex_lock(&data->update_lock);
b74f3fdd 1095 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
f8d0c19a 1096 data->fan_ctl |= i << 4;
b74f3fdd 1097 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
f8d0c19a
JD		 1098 mutex_unlock(&data->update_lock);
1099
1100 return count;
1101}
94ac7ee6
JD		 1102static ssize_t show_pwm_temp_map(struct device *dev,
1103 struct device_attribute *attr, char *buf)
1104{
1105 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1106 int nr = sensor_attr->index;
1107
1108 struct it87_data *data = it87_update_device(dev);
1109 int map;
1110
1111 if (data->pwm_temp_map[nr] < 3)
1112 map = 1 << data->pwm_temp_map[nr];
1113 else
1114 map = 0; /* Should never happen */
1115 return sprintf(buf, "%d\n", map);
1116}
1117static ssize_t set_pwm_temp_map(struct device *dev,
1118 struct device_attribute *attr, const char *buf, size_t count)
1119{
1120 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1121 int nr = sensor_attr->index;
1122
1123 struct it87_data *data = dev_get_drvdata(dev);
1124 long val;
1125 u8 reg;
1126
4a0d71cf
GR		 1127 /*
1128 * This check can go away if we ever support automatic fan speed
1129 * control on newer chips.
1130 */
4f3f51bc
JD		 1131 if (!has_old_autopwm(data)) {
1132 dev_notice(dev, "Mapping change disabled for safety reasons\n");
1133 return -EINVAL;
1134 }
1135
179c4fdb 1136 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1137 return -EINVAL;
1138
1139 switch (val) {
1140 case (1 << 0):
1141 reg = 0x00;
1142 break;
1143 case (1 << 1):
1144 reg = 0x01;
1145 break;
1146 case (1 << 2):
1147 reg = 0x02;
1148 break;
1149 default:
1150 return -EINVAL;
1151 }
1152
1153 mutex_lock(&data->update_lock);
1154 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1155 /*
1156 * If we are in automatic mode, write the temp mapping immediately;
1157 * otherwise, just store it for later use.
1158 */
94ac7ee6
JD		 1159 if (data->pwm_ctrl[nr] & 0x80) {
1160 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
1161 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
1162 }
1163 mutex_unlock(&data->update_lock);
1164 return count;
1165}
1da177e4 1166
4f3f51bc
JD		 1167static ssize_t show_auto_pwm(struct device *dev,
1168 struct device_attribute *attr, char *buf)
1169{
1170 struct it87_data *data = it87_update_device(dev);
1171 struct sensor_device_attribute_2 *sensor_attr =
1172 to_sensor_dev_attr_2(attr);
1173 int nr = sensor_attr->nr;
1174 int point = sensor_attr->index;
1175
44c1bcd4
JD		 1176 return sprintf(buf, "%d\n",
1177 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1178}
1179
1180static ssize_t set_auto_pwm(struct device *dev,
1181 struct device_attribute *attr, const char *buf, size_t count)
1182{
1183 struct it87_data *data = dev_get_drvdata(dev);
1184 struct sensor_device_attribute_2 *sensor_attr =
1185 to_sensor_dev_attr_2(attr);
1186 int nr = sensor_attr->nr;
1187 int point = sensor_attr->index;
1188 long val;
1189
179c4fdb 1190 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1191 return -EINVAL;
1192
1193 mutex_lock(&data->update_lock);
44c1bcd4 1194 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
4f3f51bc
JD		 1195 it87_write_value(data, IT87_REG_AUTO_PWM(nr, point),
1196 data->auto_pwm[nr][point]);
1197 mutex_unlock(&data->update_lock);
1198 return count;
1199}
1200
1201static ssize_t show_auto_temp(struct device *dev,
1202 struct device_attribute *attr, char *buf)
1203{
1204 struct it87_data *data = it87_update_device(dev);
1205 struct sensor_device_attribute_2 *sensor_attr =
1206 to_sensor_dev_attr_2(attr);
1207 int nr = sensor_attr->nr;
1208 int point = sensor_attr->index;
1209
1210 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point]));
1211}
1212
1213static ssize_t set_auto_temp(struct device *dev,
1214 struct device_attribute *attr, const char *buf, size_t count)
1215{
1216 struct it87_data *data = dev_get_drvdata(dev);
1217 struct sensor_device_attribute_2 *sensor_attr =
1218 to_sensor_dev_attr_2(attr);
1219 int nr = sensor_attr->nr;
1220 int point = sensor_attr->index;
1221 long val;
1222
179c4fdb 1223 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1224 return -EINVAL;
1225
1226 mutex_lock(&data->update_lock);
1227 data->auto_temp[nr][point] = TEMP_TO_REG(val);
1228 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point),
1229 data->auto_temp[nr][point]);
1230 mutex_unlock(&data->update_lock);
1231 return count;
1232}
1233
e1169ba0
GR		 1234static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1235static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1236 0, 1);
1237static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1238 set_fan_div, 0);
1239
1240static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1241static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1242 1, 1);
1243static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1244 set_fan_div, 1);
1245
1246static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1247static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1248 2, 1);
1249static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1250 set_fan_div, 2);
1251
1252static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1253static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1254 3, 1);
1da177e4 1255
e1169ba0
GR		 1256static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1257static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1258 4, 1);
1da177e4 1259
c4458db3
GR		 1260static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1261 show_pwm_enable, set_pwm_enable, 0);
1262static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1263static DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, set_pwm_freq);
1264static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO | S_IWUSR,
1265 show_pwm_temp_map, set_pwm_temp_map, 0);
1266static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1267 show_auto_pwm, set_auto_pwm, 0, 0);
1268static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1269 show_auto_pwm, set_auto_pwm, 0, 1);
1270static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1271 show_auto_pwm, set_auto_pwm, 0, 2);
1272static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1273 show_auto_pwm, NULL, 0, 3);
1274static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1275 show_auto_temp, set_auto_temp, 0, 1);
1276static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1277 show_auto_temp, set_auto_temp, 0, 0);
1278static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1279 show_auto_temp, set_auto_temp, 0, 2);
1280static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1281 show_auto_temp, set_auto_temp, 0, 3);
1282static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1283 show_auto_temp, set_auto_temp, 0, 4);
1284
1285static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1286 show_pwm_enable, set_pwm_enable, 1);
1287static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1288static DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, NULL);
1289static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO | S_IWUSR,
1290 show_pwm_temp_map, set_pwm_temp_map, 1);
1291static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1292 show_auto_pwm, set_auto_pwm, 1, 0);
1293static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1294 show_auto_pwm, set_auto_pwm, 1, 1);
1295static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1296 show_auto_pwm, set_auto_pwm, 1, 2);
1297static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1298 show_auto_pwm, NULL, 1, 3);
1299static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1300 show_auto_temp, set_auto_temp, 1, 1);
1301static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1302 show_auto_temp, set_auto_temp, 1, 0);
1303static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1304 show_auto_temp, set_auto_temp, 1, 2);
1305static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1306 show_auto_temp, set_auto_temp, 1, 3);
1307static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1308 show_auto_temp, set_auto_temp, 1, 4);
1309
1310static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1311 show_pwm_enable, set_pwm_enable, 2);
1312static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1313static DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL);
1314static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO | S_IWUSR,
1315 show_pwm_temp_map, set_pwm_temp_map, 2);
1316static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1317 show_auto_pwm, set_auto_pwm, 2, 0);
1318static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1319 show_auto_pwm, set_auto_pwm, 2, 1);
1320static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1321 show_auto_pwm, set_auto_pwm, 2, 2);
1322static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1323 show_auto_pwm, NULL, 2, 3);
1324static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1325 show_auto_temp, set_auto_temp, 2, 1);
1326static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1327 show_auto_temp, set_auto_temp, 2, 0);
1328static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1329 show_auto_temp, set_auto_temp, 2, 2);
1330static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1331 show_auto_temp, set_auto_temp, 2, 3);
1332static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1333 show_auto_temp, set_auto_temp, 2, 4);
1da177e4
LT		 1334
1335/* Alarms */
5f2dc798
JD		 1336static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
1337 char *buf)
1da177e4
LT		 1338{
1339 struct it87_data *data = it87_update_device(dev);
68188ba7 1340 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1341}
1d66c64c 1342static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1343
0124dd78
JD		 1344static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1345 char *buf)
1346{
1347 int bitnr = to_sensor_dev_attr(attr)->index;
1348 struct it87_data *data = it87_update_device(dev);
1349 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1350}
3d30f9e6
JD		 1351
1352static ssize_t clear_intrusion(struct device *dev, struct device_attribute
1353 *attr, const char *buf, size_t count)
1354{
1355 struct it87_data *data = dev_get_drvdata(dev);
1356 long val;
1357 int config;
1358
179c4fdb 1359 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1360 return -EINVAL;
1361
1362 mutex_lock(&data->update_lock);
1363 config = it87_read_value(data, IT87_REG_CONFIG);
1364 if (config < 0) {
1365 count = config;
1366 } else {
1367 config |= 1 << 5;
1368 it87_write_value(data, IT87_REG_CONFIG, config);
1369 /* Invalidate cache to force re-read */
1370 data->valid = 0;
1371 }
1372 mutex_unlock(&data->update_lock);
1373
1374 return count;
1375}
1376
0124dd78
JD		 1377static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1378static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1379static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1380static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1381static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1382static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1383static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1384static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1385static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1386static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1387static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1388static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1389static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1390static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1391static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1392static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1393static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1394 show_alarm, clear_intrusion, 4);
0124dd78 1395
d9b327c3
JD		 1396static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1397 char *buf)
1398{
1399 int bitnr = to_sensor_dev_attr(attr)->index;
1400 struct it87_data *data = it87_update_device(dev);
1401 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1402}
1403static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1404 const char *buf, size_t count)
1405{
1406 int bitnr = to_sensor_dev_attr(attr)->index;
1407 struct it87_data *data = dev_get_drvdata(dev);
1408 long val;
1409
179c4fdb 1410 if (kstrtol(buf, 10, &val) < 0
d9b327c3
JD		 1411 || (val != 0 && val != 1))
1412 return -EINVAL;
1413
1414 mutex_lock(&data->update_lock);
1415 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1416 if (val)
1417 data->beeps |= (1 << bitnr);
1418 else
1419 data->beeps &= ~(1 << bitnr);
1420 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1421 mutex_unlock(&data->update_lock);
1422 return count;
1423}
1424
1425static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1426 show_beep, set_beep, 1);
1427static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1428static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1429static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1430static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1431static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1432static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1433static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1434/* fanX_beep writability is set later */
1435static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1436static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1437static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1438static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1439static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1440static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1441 show_beep, set_beep, 2);
1442static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1443static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1444
5f2dc798
JD		 1445static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
1446 char *buf)
1da177e4 1447{
90d6619a 1448 struct it87_data *data = dev_get_drvdata(dev);
a7be58a1 1449 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1450}
5f2dc798
JD		 1451static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
1452 const char *buf, size_t count)
1da177e4 1453{
b74f3fdd 1454 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1455 unsigned long val;
1456
179c4fdb 1457 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1458 return -EINVAL;
1da177e4 1459
1da177e4
LT		 1460 data->vrm = val;
1461
1462 return count;
1463}
1464static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1465
5f2dc798
JD		 1466static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
1467 char *buf)
1da177e4
LT		 1468{
1469 struct it87_data *data = it87_update_device(dev);
1470 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
1471}
1472static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1473
738e5e05
JD		 1474static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1475 char *buf)
1476{
3c4c4971 1477 static const char * const labels[] = {
738e5e05
JD		 1478 "+5V",
1479 "5VSB",
1480 "Vbat",
1481 };
3c4c4971 1482 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1483 "+3.3V",
1484 "3VSB",
1485 "Vbat",
1486 };
1487 struct it87_data *data = dev_get_drvdata(dev);
738e5e05
JD		 1488 int nr = to_sensor_dev_attr(attr)->index;
1489
16b5dda2
JD		 1490 return sprintf(buf, "%s\n", has_12mv_adc(data) ? labels_it8721[nr]
1491 : labels[nr]);
738e5e05
JD		 1492}
1493static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1494static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1495static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
7183ae8c 1496/* special AVCC3 IT8603E in9 */
c145d5c6 1497static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
738e5e05 1498
b74f3fdd 1499static ssize_t show_name(struct device *dev, struct device_attribute
1500 *devattr, char *buf)
1501{
1502 struct it87_data *data = dev_get_drvdata(dev);
1503 return sprintf(buf, "%s\n", data->name);
1504}
1505static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1506
c145d5c6 1507static struct attribute *it87_attributes_in[10][5] = {
9172b5d1 1508{
87808be4 1509 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1510 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1511 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1512 &sensor_dev_attr_in0_alarm.dev_attr.attr,
9172b5d1
GR		 1513 NULL
1514}, {
1515 &sensor_dev_attr_in1_input.dev_attr.attr,
1516 &sensor_dev_attr_in1_min.dev_attr.attr,
1517 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1518 &sensor_dev_attr_in1_alarm.dev_attr.attr,
9172b5d1
GR		 1519 NULL
1520}, {
1521 &sensor_dev_attr_in2_input.dev_attr.attr,
1522 &sensor_dev_attr_in2_min.dev_attr.attr,
1523 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1524 &sensor_dev_attr_in2_alarm.dev_attr.attr,
9172b5d1
GR		 1525 NULL
1526}, {
1527 &sensor_dev_attr_in3_input.dev_attr.attr,
1528 &sensor_dev_attr_in3_min.dev_attr.attr,
1529 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1530 &sensor_dev_attr_in3_alarm.dev_attr.attr,
9172b5d1
GR		 1531 NULL
1532}, {
1533 &sensor_dev_attr_in4_input.dev_attr.attr,
1534 &sensor_dev_attr_in4_min.dev_attr.attr,
1535 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1536 &sensor_dev_attr_in4_alarm.dev_attr.attr,
9172b5d1
GR		 1537 NULL
1538}, {
1539 &sensor_dev_attr_in5_input.dev_attr.attr,
1540 &sensor_dev_attr_in5_min.dev_attr.attr,
1541 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1542 &sensor_dev_attr_in5_alarm.dev_attr.attr,
9172b5d1
GR		 1543 NULL
1544}, {
1545 &sensor_dev_attr_in6_input.dev_attr.attr,
1546 &sensor_dev_attr_in6_min.dev_attr.attr,
1547 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1548 &sensor_dev_attr_in6_alarm.dev_attr.attr,
9172b5d1
GR		 1549 NULL
1550}, {
1551 &sensor_dev_attr_in7_input.dev_attr.attr,
1552 &sensor_dev_attr_in7_min.dev_attr.attr,
1553 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1554 &sensor_dev_attr_in7_alarm.dev_attr.attr,
9172b5d1
GR		 1555 NULL
1556}, {
1557 &sensor_dev_attr_in8_input.dev_attr.attr,
1558 NULL
c145d5c6
RM		 1559}, {
1560 &sensor_dev_attr_in9_input.dev_attr.attr,
1561 NULL
9172b5d1 1562} };
87808be4 1563
c145d5c6 1564static const struct attribute_group it87_group_in[10] = {
9172b5d1
GR		 1565 { .attrs = it87_attributes_in[0] },
1566 { .attrs = it87_attributes_in[1] },
1567 { .attrs = it87_attributes_in[2] },
1568 { .attrs = it87_attributes_in[3] },
1569 { .attrs = it87_attributes_in[4] },
1570 { .attrs = it87_attributes_in[5] },
1571 { .attrs = it87_attributes_in[6] },
1572 { .attrs = it87_attributes_in[7] },
1573 { .attrs = it87_attributes_in[8] },
c145d5c6 1574 { .attrs = it87_attributes_in[9] },
9172b5d1
GR		 1575};
1576
4573acbc
GR		 1577static struct attribute *it87_attributes_temp[3][6] = {
1578{
87808be4 1579 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 1580 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 1581 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 1582 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 1583 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
4573acbc
GR		 1584 NULL
1585} , {
1586 &sensor_dev_attr_temp2_input.dev_attr.attr,
1587 &sensor_dev_attr_temp2_max.dev_attr.attr,
1588 &sensor_dev_attr_temp2_min.dev_attr.attr,
1589 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 1590 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
4573acbc
GR		 1591 NULL
1592} , {
1593 &sensor_dev_attr_temp3_input.dev_attr.attr,
1594 &sensor_dev_attr_temp3_max.dev_attr.attr,
1595 &sensor_dev_attr_temp3_min.dev_attr.attr,
1596 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 1597 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
4573acbc
GR		 1598 NULL
1599} };
1600
1601static const struct attribute_group it87_group_temp[3] = {
1602 { .attrs = it87_attributes_temp[0] },
1603 { .attrs = it87_attributes_temp[1] },
1604 { .attrs = it87_attributes_temp[2] },
1605};
87808be4 1606
161d898a
GR		 1607static struct attribute *it87_attributes_temp_offset[] = {
1608 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1609 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1610 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1611};
1612
4573acbc 1613static struct attribute *it87_attributes[] = {
87808be4 1614 &dev_attr_alarms.attr,
3d30f9e6 1615 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
b74f3fdd 1616 &dev_attr_name.attr,
87808be4
JD		 1617 NULL
1618};
1619
1620static const struct attribute_group it87_group = {
1621 .attrs = it87_attributes,
1622};
1623
9172b5d1 1624static struct attribute *it87_attributes_in_beep[] = {
d9b327c3
JD		 1625 &sensor_dev_attr_in0_beep.dev_attr.attr,
1626 &sensor_dev_attr_in1_beep.dev_attr.attr,
1627 &sensor_dev_attr_in2_beep.dev_attr.attr,
1628 &sensor_dev_attr_in3_beep.dev_attr.attr,
1629 &sensor_dev_attr_in4_beep.dev_attr.attr,
1630 &sensor_dev_attr_in5_beep.dev_attr.attr,
1631 &sensor_dev_attr_in6_beep.dev_attr.attr,
1632 &sensor_dev_attr_in7_beep.dev_attr.attr,
c145d5c6
RM		 1633 NULL,
1634 NULL,
9172b5d1 1635};
d9b327c3 1636
4573acbc 1637static struct attribute *it87_attributes_temp_beep[] = {
d9b327c3
JD		 1638 &sensor_dev_attr_temp1_beep.dev_attr.attr,
1639 &sensor_dev_attr_temp2_beep.dev_attr.attr,
1640 &sensor_dev_attr_temp3_beep.dev_attr.attr,
d9b327c3
JD		 1641};
1642
e1169ba0
GR		 1643static struct attribute *it87_attributes_fan[5][3+1] = { {
1644 &sensor_dev_attr_fan1_input.dev_attr.attr,
1645 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0
JD		 1646 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1647 NULL
1648}, {
e1169ba0
GR		 1649 &sensor_dev_attr_fan2_input.dev_attr.attr,
1650 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0
JD		 1651 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1652 NULL
1653}, {
e1169ba0
GR		 1654 &sensor_dev_attr_fan3_input.dev_attr.attr,
1655 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0
JD		 1656 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1657 NULL
1658}, {
e1169ba0
GR		 1659 &sensor_dev_attr_fan4_input.dev_attr.attr,
1660 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0
JD		 1661 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1662 NULL
1663}, {
e1169ba0
GR		 1664 &sensor_dev_attr_fan5_input.dev_attr.attr,
1665 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0
JD		 1666 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1667 NULL
1668} };
1669
e1169ba0
GR		 1670static const struct attribute_group it87_group_fan[5] = {
1671 { .attrs = it87_attributes_fan[0] },
1672 { .attrs = it87_attributes_fan[1] },
1673 { .attrs = it87_attributes_fan[2] },
1674 { .attrs = it87_attributes_fan[3] },
1675 { .attrs = it87_attributes_fan[4] },
723a0aa0 1676};
87808be4 1677
e1169ba0 1678static const struct attribute *it87_attributes_fan_div[] = {
87808be4 1679 &sensor_dev_attr_fan1_div.dev_attr.attr,
87808be4 1680 &sensor_dev_attr_fan2_div.dev_attr.attr,
87808be4 1681 &sensor_dev_attr_fan3_div.dev_attr.attr,
723a0aa0
JD		 1682};
1683
723a0aa0 1684static struct attribute *it87_attributes_pwm[3][4+1] = { {
87808be4 1685 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 1686 &sensor_dev_attr_pwm1.dev_attr.attr,
d5b0b5d6 1687 &dev_attr_pwm1_freq.attr,
94ac7ee6 1688 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1689 NULL
1690}, {
1691 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1692 &sensor_dev_attr_pwm2.dev_attr.attr,
1693 &dev_attr_pwm2_freq.attr,
94ac7ee6 1694 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1695 NULL
1696}, {
1697 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1698 &sensor_dev_attr_pwm3.dev_attr.attr,
1699 &dev_attr_pwm3_freq.attr,
94ac7ee6 1700 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1701 NULL
1702} };
87808be4 1703
723a0aa0
JD		 1704static const struct attribute_group it87_group_pwm[3] = {
1705 { .attrs = it87_attributes_pwm[0] },
1706 { .attrs = it87_attributes_pwm[1] },
1707 { .attrs = it87_attributes_pwm[2] },
1708};
1709
4f3f51bc
JD		 1710static struct attribute *it87_attributes_autopwm[3][9+1] = { {
1711 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1712 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1713 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
1714 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
1715 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
1716 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
1717 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
1718 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
1719 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
1720 NULL
1721}, {
1722 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1723 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1724 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
1725 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
1726 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
1727 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
1728 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
1729 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
1730 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
1731 NULL
1732}, {
1733 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1734 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1735 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
1736 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
1737 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
1738 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
1739 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
1740 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
1741 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
1742 NULL
1743} };
1744
1745static const struct attribute_group it87_group_autopwm[3] = {
1746 { .attrs = it87_attributes_autopwm[0] },
1747 { .attrs = it87_attributes_autopwm[1] },
1748 { .attrs = it87_attributes_autopwm[2] },
1749};
1750
d9b327c3
JD		 1751static struct attribute *it87_attributes_fan_beep[] = {
1752 &sensor_dev_attr_fan1_beep.dev_attr.attr,
1753 &sensor_dev_attr_fan2_beep.dev_attr.attr,
1754 &sensor_dev_attr_fan3_beep.dev_attr.attr,
1755 &sensor_dev_attr_fan4_beep.dev_attr.attr,
1756 &sensor_dev_attr_fan5_beep.dev_attr.attr,
1757};
1758
6a8d7acf 1759static struct attribute *it87_attributes_vid[] = {
87808be4
JD		 1760 &dev_attr_vrm.attr,
1761 &dev_attr_cpu0_vid.attr,
1762 NULL
1763};
1764
6a8d7acf
JD		 1765static const struct attribute_group it87_group_vid = {
1766 .attrs = it87_attributes_vid,
87808be4 1767};
1da177e4 1768
738e5e05
JD		 1769static struct attribute *it87_attributes_label[] = {
1770 &sensor_dev_attr_in3_label.dev_attr.attr,
1771 &sensor_dev_attr_in7_label.dev_attr.attr,
1772 &sensor_dev_attr_in8_label.dev_attr.attr,
c145d5c6 1773 &sensor_dev_attr_in9_label.dev_attr.attr,
738e5e05
JD		 1774 NULL
1775};
1776
1777static const struct attribute_group it87_group_label = {
fa8b6975 1778 .attrs = it87_attributes_label,
738e5e05
JD		 1779};
1780
2d8672c5 1781/* SuperIO detection - will change isa_address if a chip is found */
b74f3fdd 1782static int __init it87_find(unsigned short *address,
1783 struct it87_sio_data *sio_data)
1da177e4 1784{
5b0380c9 1785 int err;
b74f3fdd 1786 u16 chip_type;
98dd22c3 1787 const char *board_vendor, *board_name;
1da177e4 1788
5b0380c9
NG		 1789 err = superio_enter();
1790 if (err)
1791 return err;
1792
1793 err = -ENODEV;
67b671bc 1794 chip_type = force_id ? force_id : superio_inw(DEVID);
b74f3fdd 1795
1796 switch (chip_type) {
1797 case IT8705F_DEVID:
1798 sio_data->type = it87;
1799 break;
1800 case IT8712F_DEVID:
1801 sio_data->type = it8712;
1802 break;
1803 case IT8716F_DEVID:
1804 case IT8726F_DEVID:
1805 sio_data->type = it8716;
1806 break;
1807 case IT8718F_DEVID:
1808 sio_data->type = it8718;
1809 break;
b4da93e4
JMS		 1810 case IT8720F_DEVID:
1811 sio_data->type = it8720;
1812 break;
44c1bcd4
JD		 1813 case IT8721F_DEVID:
1814 sio_data->type = it8721;
1815 break;
16b5dda2
JD		 1816 case IT8728F_DEVID:
1817 sio_data->type = it8728;
1818 break;
b0636707
GR		 1819 case IT8771E_DEVID:
1820 sio_data->type = it8771;
1821 break;
1822 case IT8772E_DEVID:
1823 sio_data->type = it8772;
1824 break;
7bc32d29
GR		 1825 case IT8781F_DEVID:
1826 sio_data->type = it8781;
1827 break;
0531d98b
GR		 1828 case IT8782F_DEVID:
1829 sio_data->type = it8782;
1830 break;
1831 case IT8783E_DEVID:
1832 sio_data->type = it8783;
1833 break;
a0c1424a
TL		 1834 case IT8786E_DEVID:
1835 sio_data->type = it8786;
1836 break;
7183ae8c 1837 case IT8603E_DEVID:
574e9bd8 1838 case IT8623E_DEVID:
c145d5c6
RM		 1839 sio_data->type = it8603;
1840 break;
b74f3fdd 1841 case 0xffff: /* No device at all */
1842 goto exit;
1843 default:
a8ca1037 1844 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 1845 goto exit;
1846 }
1da177e4 1847
87673dd7 1848 superio_select(PME);
1da177e4 1849 if (!(superio_inb(IT87_ACT_REG) & 0x01)) {
a8ca1037 1850 pr_info("Device not activated, skipping\n");
1da177e4
LT		 1851 goto exit;
1852 }
1853
1854 *address = superio_inw(IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1855 if (*address == 0) {
a8ca1037 1856 pr_info("Base address not set, skipping\n");
1da177e4
LT		 1857 goto exit;
1858 }
1859
1860 err = 0;
0475169c 1861 sio_data->revision = superio_inb(DEVREV) & 0x0f;
faf392fb
GR		 1862 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
1863 it87_devices[sio_data->type].suffix,
a0c1424a 1864 *address, sio_data->revision);
1da177e4 1865
7f5726c3
GR		 1866 /* in7 (VSB or VCCH5V) is always internal on some chips */
1867 if (it87_devices[sio_data->type].features & FEAT_IN7_INTERNAL)
1868 sio_data->internal |= (1 << 1);
1869
738e5e05 1870 /* in8 (Vbat) is always internal */
7f5726c3
GR		 1871 sio_data->internal |= (1 << 2);
1872
c145d5c6
RM		 1873 /* Only the IT8603E has in9 */
1874 if (sio_data->type != it8603)
1875 sio_data->skip_in |= (1 << 9);
738e5e05 1876
32dd7c40 1877 if (!(it87_devices[sio_data->type].features & FEAT_VID))
895ff267 1878 sio_data->skip_vid = 1;
d9b327c3 1879
32dd7c40
GR		 1880 /* Read GPIO config and VID value from LDN 7 (GPIO) */
1881 if (sio_data->type == it87) {
d9b327c3
JD		 1882 /* The IT8705F has a different LD number for GPIO */
1883 superio_select(5);
1884 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b 1885 } else if (sio_data->type == it8783) {
088ce2ac 1886 int reg25, reg27, reg2a, reg2c, regef;
0531d98b 1887
0531d98b
GR		 1888 superio_select(GPIO);
1889
1890 reg25 = superio_inb(IT87_SIO_GPIO1_REG);
1891 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
088ce2ac
GR		 1892 reg2a = superio_inb(IT87_SIO_PINX1_REG);
1893 reg2c = superio_inb(IT87_SIO_PINX2_REG);
1894 regef = superio_inb(IT87_SIO_SPI_REG);
0531d98b 1895
0531d98b 1896 /* Check if fan3 is there or not */
088ce2ac 1897 if ((reg27 & (1 << 0)) || !(reg2c & (1 << 2)))
0531d98b
GR		 1898 sio_data->skip_fan |= (1 << 2);
1899 if ((reg25 & (1 << 4))
088ce2ac 1900 || (!(reg2a & (1 << 1)) && (regef & (1 << 0))))
0531d98b
GR		 1901 sio_data->skip_pwm |= (1 << 2);
1902
1903 /* Check if fan2 is there or not */
1904 if (reg27 & (1 << 7))
1905 sio_data->skip_fan |= (1 << 1);
1906 if (reg27 & (1 << 3))
1907 sio_data->skip_pwm |= (1 << 1);
1908
1909 /* VIN5 */
088ce2ac 1910 if ((reg27 & (1 << 0)) || (reg2c & (1 << 2)))
9172b5d1 1911 sio_data->skip_in |= (1 << 5); /* No VIN5 */
0531d98b
GR		 1912
1913 /* VIN6 */
9172b5d1
GR		 1914 if (reg27 & (1 << 1))
1915 sio_data->skip_in |= (1 << 6); /* No VIN6 */
0531d98b
GR		 1916
1917 /*
1918 * VIN7
1919 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
1920 */
9172b5d1
GR		 1921 if (reg27 & (1 << 2)) {
1922 /*
1923 * The data sheet is a bit unclear regarding the
1924 * internal voltage divider for VCCH5V. It says
1925 * "This bit enables and switches VIN7 (pin 91) to the
1926 * internal voltage divider for VCCH5V".
1927 * This is different to other chips, where the internal
1928 * voltage divider would connect VIN7 to an internal
1929 * voltage source. Maybe that is the case here as well.
1930 *
1931 * Since we don't know for sure, re-route it if that is
1932 * not the case, and ask the user to report if the
1933 * resulting voltage is sane.
1934 */
088ce2ac
GR		 1935 if (!(reg2c & (1 << 1))) {
1936 reg2c |= (1 << 1);
1937 superio_outb(IT87_SIO_PINX2_REG, reg2c);
9172b5d1
GR		 1938 pr_notice("Routing internal VCCH5V to in7.\n");
1939 }
1940 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
1941 pr_notice("Please report if it displays a reasonable voltage.\n");
1942 }
0531d98b 1943
088ce2ac 1944 if (reg2c & (1 << 0))
0531d98b 1945 sio_data->internal |= (1 << 0);
088ce2ac 1946 if (reg2c & (1 << 1))
0531d98b
GR		 1947 sio_data->internal |= (1 << 1);
1948
1949 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
c145d5c6
RM		 1950 } else if (sio_data->type == it8603) {
1951 int reg27, reg29;
1952
c145d5c6 1953 superio_select(GPIO);
0531d98b 1954
c145d5c6
RM		 1955 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
1956
1957 /* Check if fan3 is there or not */
1958 if (reg27 & (1 << 6))
1959 sio_data->skip_pwm |= (1 << 2);
1960 if (reg27 & (1 << 7))
1961 sio_data->skip_fan |= (1 << 2);
1962
1963 /* Check if fan2 is there or not */
1964 reg29 = superio_inb(IT87_SIO_GPIO5_REG);
1965 if (reg29 & (1 << 1))
1966 sio_data->skip_pwm |= (1 << 1);
1967 if (reg29 & (1 << 2))
1968 sio_data->skip_fan |= (1 << 1);
1969
1970 sio_data->skip_in |= (1 << 5); /* No VIN5 */
1971 sio_data->skip_in |= (1 << 6); /* No VIN6 */
1972
c145d5c6
RM		 1973 sio_data->internal |= (1 << 3); /* in9 is AVCC */
1974
1975 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
895ff267 1976 } else {
87673dd7 1977 int reg;
9172b5d1 1978 bool uart6;
87673dd7
JD		 1979
1980 superio_select(GPIO);
44c1bcd4 1981
895ff267 1982 reg = superio_inb(IT87_SIO_GPIO3_REG);
32dd7c40 1983 if (!sio_data->skip_vid) {
44c1bcd4
JD		 1984 /* We need at least 4 VID pins */
1985 if (reg & 0x0f) {
a8ca1037 1986 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 1987 sio_data->skip_vid = 1;
1988 }
895ff267
JD		 1989 }
1990
591ec650
JD		 1991 /* Check if fan3 is there or not */
1992 if (reg & (1 << 6))
1993 sio_data->skip_pwm |= (1 << 2);
1994 if (reg & (1 << 7))
1995 sio_data->skip_fan |= (1 << 2);
1996
1997 /* Check if fan2 is there or not */
1998 reg = superio_inb(IT87_SIO_GPIO5_REG);
1999 if (reg & (1 << 1))
2000 sio_data->skip_pwm |= (1 << 1);
2001 if (reg & (1 << 2))
2002 sio_data->skip_fan |= (1 << 1);
2003
895ff267
JD		 2004 if ((sio_data->type == it8718 || sio_data->type == it8720)
2005 && !(sio_data->skip_vid))
b74f3fdd 2006 sio_data->vid_value = superio_inb(IT87_SIO_VID_REG);
87673dd7
JD		 2007
2008 reg = superio_inb(IT87_SIO_PINX2_REG);
9172b5d1
GR		 2009
2010 uart6 = sio_data->type == it8782 && (reg & (1 << 2));
2011
436cad2a
JD		 2012 /*
2013 * The IT8720F has no VIN7 pin, so VCCH should always be
2014 * routed internally to VIN7 with an internal divider.
2015 * Curiously, there still is a configuration bit to control
2016 * this, which means it can be set incorrectly. And even
2017 * more curiously, many boards out there are improperly
2018 * configured, even though the IT8720F datasheet claims
2019 * that the internal routing of VCCH to VIN7 is the default
2020 * setting. So we force the internal routing in this case.
0531d98b
GR		 2021 *
2022 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 2023 * If UART6 is enabled, re-route VIN7 to the internal divider
2024 * if that is not already the case.
436cad2a 2025 */
9172b5d1 2026 if ((sio_data->type == it8720 || uart6) && !(reg & (1 << 1))) {
436cad2a
JD		 2027 reg |= (1 << 1);
2028 superio_outb(IT87_SIO_PINX2_REG, reg);
a8ca1037 2029 pr_notice("Routing internal VCCH to in7\n");
436cad2a 2030 }
87673dd7 2031 if (reg & (1 << 0))
738e5e05 2032 sio_data->internal |= (1 << 0);
7f5726c3 2033 if (reg & (1 << 1))
738e5e05 2034 sio_data->internal |= (1 << 1);
d9b327c3 2035
9172b5d1
GR		 2036 /*
2037 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2038 * While VIN7 can be routed to the internal voltage divider,
2039 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 2040 *
2041 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2042 * is the temperature source. Since we can not read the
2043 * temperature source here, skip_temp is preliminary.
9172b5d1 2044 */
4573acbc 2045 if (uart6) {
9172b5d1 2046 sio_data->skip_in |= (1 << 5) | (1 << 6);
4573acbc
GR		 2047 sio_data->skip_temp |= (1 << 2);
2048 }
9172b5d1 2049
d9b327c3 2050 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 2051 }
d9b327c3 2052 if (sio_data->beep_pin)
a8ca1037 2053 pr_info("Beeping is supported\n");
87673dd7 2054
98dd22c3
JD		 2055 /* Disable specific features based on DMI strings */
2056 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2057 board_name = dmi_get_system_info(DMI_BOARD_NAME);
2058 if (board_vendor && board_name) {
2059 if (strcmp(board_vendor, "nVIDIA") == 0
2060 && strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 2061 /*
2062 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2063 * connected to a fan, but to something else. One user
2064 * has reported instant system power-off when changing
2065 * the PWM2 duty cycle, so we disable it.
2066 * I use the board name string as the trigger in case
2067 * the same board is ever used in other systems.
2068 */
a8ca1037 2069 pr_info("Disabling pwm2 due to hardware constraints\n");
98dd22c3
JD		 2070 sio_data->skip_pwm = (1 << 1);
2071 }
2072 }
2073
1da177e4
LT		 2074exit:
2075 superio_exit();
2076 return err;
2077}
2078
723a0aa0
JD		 2079static void it87_remove_files(struct device *dev)
2080{
2081 struct it87_data *data = platform_get_drvdata(pdev);
a8b3a3a5 2082 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0
JD		 2083 int i;
2084
2085 sysfs_remove_group(&dev->kobj, &it87_group);
c145d5c6 2086 for (i = 0; i < 10; i++) {
9172b5d1
GR		 2087 if (sio_data->skip_in & (1 << i))
2088 continue;
2089 sysfs_remove_group(&dev->kobj, &it87_group_in[i]);
2090 if (it87_attributes_in_beep[i])
2091 sysfs_remove_file(&dev->kobj,
2092 it87_attributes_in_beep[i]);
2093 }
4573acbc
GR		 2094 for (i = 0; i < 3; i++) {
2095 if (!(data->has_temp & (1 << i)))
2096 continue;
2097 sysfs_remove_group(&dev->kobj, &it87_group_temp[i]);
161d898a
GR		 2098 if (has_temp_offset(data))
2099 sysfs_remove_file(&dev->kobj,
2100 it87_attributes_temp_offset[i]);
4573acbc
GR		 2101 if (sio_data->beep_pin)
2102 sysfs_remove_file(&dev->kobj,
2103 it87_attributes_temp_beep[i]);
2104 }
723a0aa0
JD		 2105 for (i = 0; i < 5; i++) {
2106 if (!(data->has_fan & (1 << i)))
2107 continue;
e1169ba0 2108 sysfs_remove_group(&dev->kobj, &it87_group_fan[i]);
d9b327c3
JD		 2109 if (sio_data->beep_pin)
2110 sysfs_remove_file(&dev->kobj,
2111 it87_attributes_fan_beep[i]);
e1169ba0
GR		 2112 if (i < 3 && !has_16bit_fans(data))
2113 sysfs_remove_file(&dev->kobj,
2114 it87_attributes_fan_div[i]);
723a0aa0
JD		 2115 }
2116 for (i = 0; i < 3; i++) {
1696d1de 2117 if (sio_data->skip_pwm & (1 << i))
723a0aa0
JD		 2118 continue;
2119 sysfs_remove_group(&dev->kobj, &it87_group_pwm[i]);
4f3f51bc
JD		 2120 if (has_old_autopwm(data))
2121 sysfs_remove_group(&dev->kobj,
2122 &it87_group_autopwm[i]);
723a0aa0 2123 }
6a8d7acf
JD		 2124 if (!sio_data->skip_vid)
2125 sysfs_remove_group(&dev->kobj, &it87_group_vid);
738e5e05 2126 sysfs_remove_group(&dev->kobj, &it87_group_label);
723a0aa0
JD		 2127}
2128
6c931ae1 2129static int it87_probe(struct platform_device *pdev)
1da177e4 2130{
1da177e4 2131 struct it87_data *data;
b74f3fdd 2132 struct resource *res;
2133 struct device *dev = &pdev->dev;
a8b3a3a5 2134 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0 2135 int err = 0, i;
1da177e4 2136 int enable_pwm_interface;
d9b327c3 2137 int fan_beep_need_rw;
b74f3fdd 2138
2139 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
62a1d05f
GR		 2140 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2141 DRVNAME)) {
b74f3fdd 2142 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2143 (unsigned long)res->start,
87b4b663 2144 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
62a1d05f 2145 return -EBUSY;
8e9afcbb 2146 }
1da177e4 2147
62a1d05f
GR		 2148 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2149 if (!data)
2150 return -ENOMEM;
1da177e4 2151
b74f3fdd 2152 data->addr = res->start;
2153 data->type = sio_data->type;
483db43e 2154 data->features = it87_devices[sio_data->type].features;
5d8d2f2b 2155 data->peci_mask = it87_devices[sio_data->type].peci_mask;
19529784 2156 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
483db43e
GR		 2157 data->name = it87_devices[sio_data->type].name;
2158 /*
2159 * IT8705F Datasheet 0.4.1, 3h == Version G.
2160 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2161 * These are the first revisions with 16-bit tachometer support.
2162 */
2163 switch (data->type) {
2164 case it87:
2165 if (sio_data->revision >= 0x03) {
2166 data->features &= ~FEAT_OLD_AUTOPWM;
9faf28ca 2167 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
483db43e
GR		 2168 }
2169 break;
2170 case it8712:
2171 if (sio_data->revision >= 0x08) {
2172 data->features &= ~FEAT_OLD_AUTOPWM;
9faf28ca
GR		 2173 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
2174 FEAT_FIVE_FANS;
483db43e
GR		 2175 }
2176 break;
2177 default:
2178 break;
2179 }
1da177e4
LT		 2180
2181 /* Now, we do the remaining detection. */
b74f3fdd 2182 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80)
62a1d05f
GR		 2183 || it87_read_value(data, IT87_REG_CHIPID) != 0x90)
2184 return -ENODEV;
1da177e4 2185
b74f3fdd 2186 platform_set_drvdata(pdev, data);
1da177e4 2187
9a61bf63 2188 mutex_init(&data->update_lock);
1da177e4 2189
1da177e4 2190 /* Check PWM configuration */
b74f3fdd 2191 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2192
44c1bcd4 2193 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2194 if (has_12mv_adc(data)) {
44c1bcd4
JD		 2195 if (sio_data->internal & (1 << 0))
2196 data->in_scaled |= (1 << 3); /* in3 is AVCC */
2197 if (sio_data->internal & (1 << 1))
2198 data->in_scaled |= (1 << 7); /* in7 is VSB */
2199 if (sio_data->internal & (1 << 2))
2200 data->in_scaled |= (1 << 8); /* in8 is Vbat */
c145d5c6
RM		 2201 if (sio_data->internal & (1 << 3))
2202 data->in_scaled |= (1 << 9); /* in9 is AVCC */
7bc32d29
GR		 2203 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
2204 sio_data->type == it8783) {
0531d98b
GR		 2205 if (sio_data->internal & (1 << 0))
2206 data->in_scaled |= (1 << 3); /* in3 is VCC5V */
2207 if (sio_data->internal & (1 << 1))
2208 data->in_scaled |= (1 << 7); /* in7 is VCCH5V */
44c1bcd4
JD		 2209 }
2210
4573acbc
GR		 2211 data->has_temp = 0x07;
2212 if (sio_data->skip_temp & (1 << 2)) {
2213 if (sio_data->type == it8782
2214 && !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
2215 data->has_temp &= ~(1 << 2);
2216 }
2217
1da177e4 2218 /* Initialize the IT87 chip */
b74f3fdd 2219 it87_init_device(pdev);
1da177e4
LT		 2220
2221 /* Register sysfs hooks */
5f2dc798
JD		 2222 err = sysfs_create_group(&dev->kobj, &it87_group);
2223 if (err)
62a1d05f 2224 return err;
17d648bf 2225
c145d5c6 2226 for (i = 0; i < 10; i++) {
9172b5d1
GR		 2227 if (sio_data->skip_in & (1 << i))
2228 continue;
2229 err = sysfs_create_group(&dev->kobj, &it87_group_in[i]);
2230 if (err)
62a1d05f 2231 goto error;
9172b5d1
GR		 2232 if (sio_data->beep_pin && it87_attributes_in_beep[i]) {
2233 err = sysfs_create_file(&dev->kobj,
2234 it87_attributes_in_beep[i]);
2235 if (err)
62a1d05f 2236 goto error;
9172b5d1
GR		 2237 }
2238 }
2239
4573acbc
GR		 2240 for (i = 0; i < 3; i++) {
2241 if (!(data->has_temp & (1 << i)))
2242 continue;
2243 err = sysfs_create_group(&dev->kobj, &it87_group_temp[i]);
d9b327c3 2244 if (err)
62a1d05f 2245 goto error;
161d898a
GR		 2246 if (has_temp_offset(data)) {
2247 err = sysfs_create_file(&dev->kobj,
2248 it87_attributes_temp_offset[i]);
2249 if (err)
2250 goto error;
2251 }
4573acbc
GR		 2252 if (sio_data->beep_pin) {
2253 err = sysfs_create_file(&dev->kobj,
2254 it87_attributes_temp_beep[i]);
2255 if (err)
2256 goto error;
2257 }
d9b327c3
JD		 2258 }
2259
9060f8bd 2260 /* Do not create fan files for disabled fans */
d9b327c3 2261 fan_beep_need_rw = 1;
723a0aa0
JD		 2262 for (i = 0; i < 5; i++) {
2263 if (!(data->has_fan & (1 << i)))
2264 continue;
e1169ba0 2265 err = sysfs_create_group(&dev->kobj, &it87_group_fan[i]);
723a0aa0 2266 if (err)
62a1d05f 2267 goto error;
d9b327c3 2268
e1169ba0
GR		 2269 if (i < 3 && !has_16bit_fans(data)) {
2270 err = sysfs_create_file(&dev->kobj,
2271 it87_attributes_fan_div[i]);
2272 if (err)
2273 goto error;
2274 }
2275
d9b327c3
JD		 2276 if (sio_data->beep_pin) {
2277 err = sysfs_create_file(&dev->kobj,
2278 it87_attributes_fan_beep[i]);
2279 if (err)
62a1d05f 2280 goto error;
d9b327c3
JD		 2281 if (!fan_beep_need_rw)
2282 continue;
2283
4a0d71cf
GR		 2284 /*
2285 * As we have a single beep enable bit for all fans,
d9b327c3 2286 * only the first enabled fan has a writable attribute
4a0d71cf
GR		 2287 * for it.
2288 */
d9b327c3
JD		 2289 if (sysfs_chmod_file(&dev->kobj,
2290 it87_attributes_fan_beep[i],
2291 S_IRUGO | S_IWUSR))
2292 dev_dbg(dev, "chmod +w fan%d_beep failed\n",
2293 i + 1);
2294 fan_beep_need_rw = 0;
2295 }
17d648bf
JD		 2296 }
2297
1da177e4 2298 if (enable_pwm_interface) {
723a0aa0
JD		 2299 for (i = 0; i < 3; i++) {
2300 if (sio_data->skip_pwm & (1 << i))
2301 continue;
2302 err = sysfs_create_group(&dev->kobj,
2303 &it87_group_pwm[i]);
2304 if (err)
62a1d05f 2305 goto error;
4f3f51bc
JD		 2306
2307 if (!has_old_autopwm(data))
2308 continue;
2309 err = sysfs_create_group(&dev->kobj,
2310 &it87_group_autopwm[i]);
2311 if (err)
62a1d05f 2312 goto error;
98dd22c3 2313 }
1da177e4
LT		 2314 }
2315
895ff267 2316 if (!sio_data->skip_vid) {
303760b4 2317 data->vrm = vid_which_vrm();
87673dd7 2318 /* VID reading from Super-I/O config space if available */
b74f3fdd 2319 data->vid = sio_data->vid_value;
6a8d7acf
JD		 2320 err = sysfs_create_group(&dev->kobj, &it87_group_vid);
2321 if (err)
62a1d05f 2322 goto error;
87808be4
JD		 2323 }
2324
738e5e05 2325 /* Export labels for internal sensors */
c145d5c6 2326 for (i = 0; i < 4; i++) {
738e5e05
JD		 2327 if (!(sio_data->internal & (1 << i)))
2328 continue;
2329 err = sysfs_create_file(&dev->kobj,
2330 it87_attributes_label[i]);
2331 if (err)
62a1d05f 2332 goto error;
738e5e05
JD		 2333 }
2334
1beeffe4
TJ		 2335 data->hwmon_dev = hwmon_device_register(dev);
2336 if (IS_ERR(data->hwmon_dev)) {
2337 err = PTR_ERR(data->hwmon_dev);
62a1d05f 2338 goto error;
1da177e4
LT		 2339 }
2340
2341 return 0;
2342
62a1d05f 2343error:
723a0aa0 2344 it87_remove_files(dev);
1da177e4
LT		 2345 return err;
2346}
2347
281dfd0b 2348static int it87_remove(struct platform_device *pdev)
1da177e4 2349{
b74f3fdd 2350 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2351
1beeffe4 2352 hwmon_device_unregister(data->hwmon_dev);
723a0aa0 2353 it87_remove_files(&pdev->dev);
943b0830 2354
1da177e4
LT		 2355 return 0;
2356}
2357
4a0d71cf
GR		 2358/*
2359 * Must be called with data->update_lock held, except during initialization.
2360 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2361 * would slow down the IT87 access and should not be necessary.
2362 */
b74f3fdd 2363static int it87_read_value(struct it87_data *data, u8 reg)
1da177e4 2364{
b74f3fdd 2365 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2366 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2367}
2368
4a0d71cf
GR		 2369/*
2370 * Must be called with data->update_lock held, except during initialization.
2371 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2372 * would slow down the IT87 access and should not be necessary.
2373 */
b74f3fdd 2374static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
1da177e4 2375{
b74f3fdd 2376 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2377 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2378}
2379
2380/* Return 1 if and only if the PWM interface is safe to use */
6c931ae1 2381static int it87_check_pwm(struct device *dev)
1da177e4 2382{
b74f3fdd 2383 struct it87_data *data = dev_get_drvdata(dev);
4a0d71cf
GR		 2384 /*
2385 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
1da177e4 2386 * and polarity set to active low is sign that this is the case so we
4a0d71cf
GR		 2387 * disable pwm control to protect the user.
2388 */
b74f3fdd 2389 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1da177e4
LT		 2390 if ((tmp & 0x87) == 0) {
2391 if (fix_pwm_polarity) {
4a0d71cf
GR		 2392 /*
2393 * The user asks us to attempt a chip reconfiguration.
1da177e4 2394 * This means switching to active high polarity and
4a0d71cf
GR		 2395 * inverting all fan speed values.
2396 */
1da177e4
LT		 2397 int i;
2398 u8 pwm[3];
2399
2400 for (i = 0; i < 3; i++)
b74f3fdd 2401 pwm[i] = it87_read_value(data,
1da177e4
LT		 2402 IT87_REG_PWM(i));
2403
4a0d71cf
GR		 2404 /*
2405 * If any fan is in automatic pwm mode, the polarity
1da177e4
LT		 2406 * might be correct, as suspicious as it seems, so we
2407 * better don't change anything (but still disable the
4a0d71cf
GR		 2408 * PWM interface).
2409 */
1da177e4 2410 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
1d9bcf6a
GR		 2411 dev_info(dev,
2412 "Reconfiguring PWM to active high polarity\n");
b74f3fdd 2413 it87_write_value(data, IT87_REG_FAN_CTL,
1da177e4
LT		 2414 tmp | 0x87);
2415 for (i = 0; i < 3; i++)
b74f3fdd 2416 it87_write_value(data,
1da177e4
LT		 2417 IT87_REG_PWM(i),
2418 0x7f & ~pwm[i]);
2419 return 1;
2420 }
2421
1d9bcf6a
GR		 2422 dev_info(dev,
2423 "PWM configuration is too broken to be fixed\n");
1da177e4
LT		 2424 }
2425
1d9bcf6a
GR		 2426 dev_info(dev,
2427 "Detected broken BIOS defaults, disabling PWM interface\n");
1da177e4
LT		 2428 return 0;
2429 } else if (fix_pwm_polarity) {
1d9bcf6a
GR		 2430 dev_info(dev,
2431 "PWM configuration looks sane, won't touch\n");
1da177e4
LT		 2432 }
2433
2434 return 1;
2435}
2436
2437/* Called when we have found a new IT87. */
6c931ae1 2438static void it87_init_device(struct platform_device *pdev)
1da177e4 2439{
a8b3a3a5 2440 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
b74f3fdd 2441 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2442 int tmp, i;
591ec650 2443 u8 mask;
1da177e4 2444
4a0d71cf
GR		 2445 /*
2446 * For each PWM channel:
b99883dc
JD		 2447 * - If it is in automatic mode, setting to manual mode should set
2448 * the fan to full speed by default.
2449 * - If it is in manual mode, we need a mapping to temperature
2450 * channels to use when later setting to automatic mode later.
2451 * Use a 1:1 mapping by default (we are clueless.)
2452 * In both cases, the value can (and should) be changed by the user
6229cdb2
JD		 2453 * prior to switching to a different mode.
2454 * Note that this is no longer needed for the IT8721F and later, as
2455 * these have separate registers for the temperature mapping and the
4a0d71cf
GR		 2456 * manual duty cycle.
2457 */
1da177e4 2458 for (i = 0; i < 3; i++) {
b99883dc
JD		 2459 data->pwm_temp_map[i] = i;
2460 data->pwm_duty[i] = 0x7f; /* Full speed */
4f3f51bc 2461 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
1da177e4
LT		 2462 }
2463
4a0d71cf
GR		 2464 /*
2465 * Some chips seem to have default value 0xff for all limit
c5df9b7a
JD		 2466 * registers. For low voltage limits it makes no sense and triggers
2467 * alarms, so change to 0 instead. For high temperature limits, it
2468 * means -1 degree C, which surprisingly doesn't trigger an alarm,
4a0d71cf
GR		 2469 * but is still confusing, so change to 127 degrees C.
2470 */
c5df9b7a 2471 for (i = 0; i < 8; i++) {
b74f3fdd 2472 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
c5df9b7a 2473 if (tmp == 0xff)
b74f3fdd 2474 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
c5df9b7a
JD		 2475 }
2476 for (i = 0; i < 3; i++) {
b74f3fdd 2477 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
c5df9b7a 2478 if (tmp == 0xff)
b74f3fdd 2479 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
c5df9b7a
JD		 2480 }
2481
4a0d71cf
GR		 2482 /*
2483 * Temperature channels are not forcibly enabled, as they can be
a00afb97
JD		 2484 * set to two different sensor types and we can't guess which one
2485 * is correct for a given system. These channels can be enabled at
4a0d71cf
GR		 2486 * run-time through the temp{1-3}_type sysfs accessors if needed.
2487 */
1da177e4
LT		 2488
2489 /* Check if voltage monitors are reset manually or by some reason */
b74f3fdd 2490 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
1da177e4
LT		 2491 if ((tmp & 0xff) == 0) {
2492 /* Enable all voltage monitors */
b74f3fdd 2493 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
1da177e4
LT		 2494 }
2495
2496 /* Check if tachometers are reset manually or by some reason */
591ec650 2497 mask = 0x70 & ~(sio_data->skip_fan << 4);
b74f3fdd 2498 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
591ec650 2499 if ((data->fan_main_ctrl & mask) == 0) {
1da177e4 2500 /* Enable all fan tachometers */
591ec650 2501 data->fan_main_ctrl |= mask;
5f2dc798
JD		 2502 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2503 data->fan_main_ctrl);
1da177e4 2504 }
9060f8bd 2505 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
1da177e4 2506
9faf28ca
GR		 2507 /* Set tachometers to 16-bit mode if needed */
2508 if (has_fan16_config(data)) {
b74f3fdd 2509 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
9060f8bd 2510 if (~tmp & 0x07 & data->has_fan) {
b74f3fdd 2511 dev_dbg(&pdev->dev,
17d648bf 2512 "Setting fan1-3 to 16-bit mode\n");
b74f3fdd 2513 it87_write_value(data, IT87_REG_FAN_16BIT,
17d648bf
JD		 2514 tmp | 0x07);
2515 }
9faf28ca
GR		 2516 }
2517
2518 /* Check for additional fans */
2519 if (has_five_fans(data)) {
2520 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2521 if (tmp & (1 << 4))
2522 data->has_fan |= (1 << 3); /* fan4 enabled */
2523 if (tmp & (1 << 5))
2524 data->has_fan |= (1 << 4); /* fan5 enabled */
17d648bf
JD		 2525 }
2526
591ec650
JD		 2527 /* Fan input pins may be used for alternative functions */
2528 data->has_fan &= ~sio_data->skip_fan;
2529
1da177e4 2530 /* Start monitoring */
b74f3fdd 2531 it87_write_value(data, IT87_REG_CONFIG,
41002f8d 2532 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
1da177e4
LT		 2533 | (update_vbat ? 0x41 : 0x01));
2534}
2535
b99883dc
JD		 2536static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
2537{
2538 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM(nr));
16b5dda2 2539 if (has_newer_autopwm(data)) {
b99883dc 2540 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
6229cdb2
JD		 2541 data->pwm_duty[nr] = it87_read_value(data,
2542 IT87_REG_PWM_DUTY(nr));
2543 } else {
2544 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
2545 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
2546 else /* Manual mode */
2547 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
2548 }
4f3f51bc
JD		 2549
2550 if (has_old_autopwm(data)) {
2551 int i;
2552
2553 for (i = 0; i < 5 ; i++)
2554 data->auto_temp[nr][i] = it87_read_value(data,
2555 IT87_REG_AUTO_TEMP(nr, i));
2556 for (i = 0; i < 3 ; i++)
2557 data->auto_pwm[nr][i] = it87_read_value(data,
2558 IT87_REG_AUTO_PWM(nr, i));
2559 }
b99883dc
JD		 2560}
2561
1da177e4
LT		 2562static struct it87_data *it87_update_device(struct device *dev)
2563{
b74f3fdd 2564 struct it87_data *data = dev_get_drvdata(dev);
1da177e4
LT		 2565 int i;
2566
9a61bf63 2567 mutex_lock(&data->update_lock);
1da177e4
LT		 2568
2569 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
2570 || !data->valid) {
1da177e4 2571 if (update_vbat) {
4a0d71cf
GR		 2572 /*
2573 * Cleared after each update, so reenable. Value
2574 * returned by this read will be previous value
2575 */
b74f3fdd 2576 it87_write_value(data, IT87_REG_CONFIG,
5f2dc798 2577 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1da177e4
LT		 2578 }
2579 for (i = 0; i <= 7; i++) {
929c6a56 2580 data->in[i][0] =
5f2dc798 2581 it87_read_value(data, IT87_REG_VIN(i));
929c6a56 2582 data->in[i][1] =
5f2dc798 2583 it87_read_value(data, IT87_REG_VIN_MIN(i));
929c6a56 2584 data->in[i][2] =
5f2dc798 2585 it87_read_value(data, IT87_REG_VIN_MAX(i));
1da177e4 2586 }
3543a53f 2587 /* in8 (battery) has no limit registers */
929c6a56 2588 data->in[8][0] = it87_read_value(data, IT87_REG_VIN(8));
c145d5c6
RM		 2589 if (data->type == it8603)
2590 data->in[9][0] = it87_read_value(data, 0x2f);
1da177e4 2591
c7f1f716 2592 for (i = 0; i < 5; i++) {
9060f8bd
JD		 2593 /* Skip disabled fans */
2594 if (!(data->has_fan & (1 << i)))
2595 continue;
2596
e1169ba0 2597 data->fan[i][1] =
5f2dc798 2598 it87_read_value(data, IT87_REG_FAN_MIN[i]);
e1169ba0 2599 data->fan[i][0] = it87_read_value(data,
c7f1f716 2600 IT87_REG_FAN[i]);
17d648bf 2601 /* Add high byte if in 16-bit mode */
0475169c 2602 if (has_16bit_fans(data)) {
e1169ba0 2603 data->fan[i][0] |= it87_read_value(data,
c7f1f716 2604 IT87_REG_FANX[i]) << 8;
e1169ba0 2605 data->fan[i][1] |= it87_read_value(data,
c7f1f716 2606 IT87_REG_FANX_MIN[i]) << 8;
17d648bf 2607 }
1da177e4
LT		 2608 }
2609 for (i = 0; i < 3; i++) {
4573acbc
GR		 2610 if (!(data->has_temp & (1 << i)))
2611 continue;
60ca385a 2612 data->temp[i][0] =
5f2dc798 2613 it87_read_value(data, IT87_REG_TEMP(i));
60ca385a 2614 data->temp[i][1] =
5f2dc798 2615 it87_read_value(data, IT87_REG_TEMP_LOW(i));
60ca385a
GR		 2616 data->temp[i][2] =
2617 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
161d898a
GR		 2618 if (has_temp_offset(data))
2619 data->temp[i][3] =
2620 it87_read_value(data,
2621 IT87_REG_TEMP_OFFSET[i]);
1da177e4
LT		 2622 }
2623
17d648bf 2624 /* Newer chips don't have clock dividers */
0475169c 2625 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
b74f3fdd 2626 i = it87_read_value(data, IT87_REG_FAN_DIV);
17d648bf
JD		 2627 data->fan_div[0] = i & 0x07;
2628 data->fan_div[1] = (i >> 3) & 0x07;
2629 data->fan_div[2] = (i & 0x40) ? 3 : 1;
2630 }
1da177e4
LT		 2631
2632 data->alarms =
b74f3fdd 2633 it87_read_value(data, IT87_REG_ALARM1) |
2634 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
2635 (it87_read_value(data, IT87_REG_ALARM3) << 16);
d9b327c3 2636 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
b99883dc 2637
b74f3fdd 2638 data->fan_main_ctrl = it87_read_value(data,
2639 IT87_REG_FAN_MAIN_CTRL);
2640 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
b99883dc
JD		 2641 for (i = 0; i < 3; i++)
2642 it87_update_pwm_ctrl(data, i);
b74f3fdd 2643
2644 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
19529784 2645 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
4a0d71cf
GR		 2646 /*
2647 * The IT8705F does not have VID capability.
2648 * The IT8718F and later don't use IT87_REG_VID for the
2649 * same purpose.
2650 */
17d648bf 2651 if (data->type == it8712 || data->type == it8716) {
b74f3fdd 2652 data->vid = it87_read_value(data, IT87_REG_VID);
4a0d71cf
GR		 2653 /*
2654 * The older IT8712F revisions had only 5 VID pins,
2655 * but we assume it is always safe to read 6 bits.
2656 */
17d648bf 2657 data->vid &= 0x3f;
1da177e4
LT		 2658 }
2659 data->last_updated = jiffies;
2660 data->valid = 1;
2661 }
2662
9a61bf63 2663 mutex_unlock(&data->update_lock);
1da177e4
LT		 2664
2665 return data;
2666}
2667
b74f3fdd 2668static int __init it87_device_add(unsigned short address,
2669 const struct it87_sio_data *sio_data)
2670{
2671 struct resource res = {
87b4b663
BH		 2672 .start = address + IT87_EC_OFFSET,
2673 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 2674 .name = DRVNAME,
2675 .flags = IORESOURCE_IO,
2676 };
2677 int err;
2678
b9acb64a
JD		 2679 err = acpi_check_resource_conflict(&res);
2680 if (err)
2681 goto exit;
2682
b74f3fdd 2683 pdev = platform_device_alloc(DRVNAME, address);
2684 if (!pdev) {
2685 err = -ENOMEM;
a8ca1037 2686 pr_err("Device allocation failed\n");
b74f3fdd 2687 goto exit;
2688 }
2689
2690 err = platform_device_add_resources(pdev, &res, 1);
2691 if (err) {
a8ca1037 2692 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 2693 goto exit_device_put;
2694 }
2695
2696 err = platform_device_add_data(pdev, sio_data,
2697 sizeof(struct it87_sio_data));
2698 if (err) {
a8ca1037 2699 pr_err("Platform data allocation failed\n");
b74f3fdd 2700 goto exit_device_put;
2701 }
2702
2703 err = platform_device_add(pdev);
2704 if (err) {
a8ca1037 2705 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 2706 goto exit_device_put;
2707 }
2708
2709 return 0;
2710
2711exit_device_put:
2712 platform_device_put(pdev);
2713exit:
2714 return err;
2715}
2716
1da177e4
LT		 2717static int __init sm_it87_init(void)
2718{
b74f3fdd 2719 int err;
5f2dc798 2720 unsigned short isa_address = 0;
b74f3fdd 2721 struct it87_sio_data sio_data;
2722
98dd22c3 2723 memset(&sio_data, 0, sizeof(struct it87_sio_data));
b74f3fdd 2724 err = it87_find(&isa_address, &sio_data);
2725 if (err)
2726 return err;
2727 err = platform_driver_register(&it87_driver);
2728 if (err)
2729 return err;
fde09509 2730
b74f3fdd 2731 err = it87_device_add(isa_address, &sio_data);
5f2dc798 2732 if (err) {
b74f3fdd 2733 platform_driver_unregister(&it87_driver);
2734 return err;
2735 }
2736
2737 return 0;
1da177e4
LT		 2738}
2739
2740static void __exit sm_it87_exit(void)
2741{
b74f3fdd 2742 platform_device_unregister(pdev);
2743 platform_driver_unregister(&it87_driver);
1da177e4
LT		 2744}
2745
2746
7c81c60f 2747MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
44c1bcd4 2748MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 2749module_param(update_vbat, bool, 0);
2750MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
2751module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 2752MODULE_PARM_DESC(fix_pwm_polarity,
2753 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 2754MODULE_LICENSE("GPL");
2755
2756module_init(sm_it87_init);
2757module_exit(sm_it87_exit);
Linux 6.x block layer and io_uring tree(s)