Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 | 2 | /* |
5f2dc798 JD |
3 | * it87.c - Part of lm_sensors, Linux kernel modules for hardware |
4 | * monitoring. | |
5 | * | |
6 | * The IT8705F is an LPC-based Super I/O part that contains UARTs, a | |
7 | * parallel port, an IR port, a MIDI port, a floppy controller, etc., in | |
8 | * addition to an Environment Controller (Enhanced Hardware Monitor and | |
9 | * Fan Controller) | |
10 | * | |
11 | * This driver supports only the Environment Controller in the IT8705F and | |
12 | * similar parts. The other devices are supported by different drivers. | |
13 | * | |
c145d5c6 | 14 | * Supports: IT8603E Super I/O chip w/LPC interface |
3ba9d977 | 15 | * IT8620E Super I/O chip w/LPC interface |
8af1abae | 16 | * IT8622E Super I/O chip w/LPC interface |
574e9bd8 | 17 | * IT8623E Super I/O chip w/LPC interface |
71a9c232 | 18 | * IT8628E Super I/O chip w/LPC interface |
c145d5c6 | 19 | * IT8705F Super I/O chip w/LPC interface |
5f2dc798 JD |
20 | * IT8712F Super I/O chip w/LPC interface |
21 | * IT8716F Super I/O chip w/LPC interface | |
22 | * IT8718F Super I/O chip w/LPC interface | |
23 | * IT8720F Super I/O chip w/LPC interface | |
44c1bcd4 | 24 | * IT8721F Super I/O chip w/LPC interface |
5f2dc798 | 25 | * IT8726F Super I/O chip w/LPC interface |
16b5dda2 | 26 | * IT8728F Super I/O chip w/LPC interface |
ead80803 | 27 | * IT8732F Super I/O chip w/LPC interface |
44c1bcd4 | 28 | * IT8758E Super I/O chip w/LPC interface |
b0636707 GR |
29 | * IT8771E Super I/O chip w/LPC interface |
30 | * IT8772E Super I/O chip w/LPC interface | |
7bc32d29 | 31 | * IT8781F Super I/O chip w/LPC interface |
0531d98b GR |
32 | * IT8782F Super I/O chip w/LPC interface |
33 | * IT8783E/F Super I/O chip w/LPC interface | |
a0c1424a | 34 | * IT8786E Super I/O chip w/LPC interface |
4ee07157 | 35 | * IT8790E Super I/O chip w/LPC interface |
e531ffc0 | 36 | * IT8792E Super I/O chip w/LPC interface |
d44cb4cd | 37 | * IT87952E Super I/O chip w/LPC interface |
5f2dc798 JD |
38 | * Sis950 A clone of the IT8705F |
39 | * | |
40 | * Copyright (C) 2001 Chris Gauthron | |
7c81c60f | 41 | * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de> |
5f2dc798 | 42 | */ |
1da177e4 | 43 | |
a8ca1037 JP |
44 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
45 | ||
48b2ae7f | 46 | #include <linux/bitops.h> |
1da177e4 LT |
47 | #include <linux/module.h> |
48 | #include <linux/init.h> | |
49 | #include <linux/slab.h> | |
50 | #include <linux/jiffies.h> | |
b74f3fdd | 51 | #include <linux/platform_device.h> |
943b0830 | 52 | #include <linux/hwmon.h> |
303760b4 JD |
53 | #include <linux/hwmon-sysfs.h> |
54 | #include <linux/hwmon-vid.h> | |
943b0830 | 55 | #include <linux/err.h> |
9a61bf63 | 56 | #include <linux/mutex.h> |
87808be4 | 57 | #include <linux/sysfs.h> |
98dd22c3 JD |
58 | #include <linux/string.h> |
59 | #include <linux/dmi.h> | |
b9acb64a | 60 | #include <linux/acpi.h> |
6055fae8 | 61 | #include <linux/io.h> |
1da177e4 | 62 | |
b74f3fdd | 63 | #define DRVNAME "it87" |
1da177e4 | 64 | |
ead80803 | 65 | enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, |
e531ffc0 | 66 | it8771, it8772, it8781, it8782, it8783, it8786, it8790, |
d44cb4cd | 67 | it8792, it8603, it8620, it8622, it8628, it87952 }; |
1da177e4 | 68 | |
e84bd953 | 69 | static struct platform_device *it87_pdev[2]; |
b74f3fdd | 70 | |
3c2e3512 | 71 | #define REG_2E 0x2e /* The register to read/write */ |
e84bd953 | 72 | #define REG_4E 0x4e /* Secondary register to read/write */ |
3c2e3512 | 73 | |
1da177e4 | 74 | #define DEV 0x07 /* Register: Logical device select */ |
1da177e4 | 75 | #define PME 0x04 /* The device with the fan registers in it */ |
b4da93e4 JMS |
76 | |
77 | /* The device with the IT8718F/IT8720F VID value in it */ | |
78 | #define GPIO 0x07 | |
79 | ||
1da177e4 LT |
80 | #define DEVID 0x20 /* Register: Device ID */ |
81 | #define DEVREV 0x22 /* Register: Device Revision */ | |
82 | ||
d47e377c FC |
83 | static inline void __superio_enter(int ioreg) |
84 | { | |
85 | outb(0x87, ioreg); | |
86 | outb(0x01, ioreg); | |
87 | outb(0x55, ioreg); | |
88 | outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg); | |
89 | } | |
90 | ||
3c2e3512 | 91 | static inline int superio_inb(int ioreg, int reg) |
1da177e4 | 92 | { |
3c2e3512 GR |
93 | outb(reg, ioreg); |
94 | return inb(ioreg + 1); | |
1da177e4 LT |
95 | } |
96 | ||
3c2e3512 | 97 | static inline void superio_outb(int ioreg, int reg, int val) |
436cad2a | 98 | { |
3c2e3512 GR |
99 | outb(reg, ioreg); |
100 | outb(val, ioreg + 1); | |
436cad2a JD |
101 | } |
102 | ||
3c2e3512 | 103 | static int superio_inw(int ioreg, int reg) |
1da177e4 LT |
104 | { |
105 | int val; | |
c962024e | 106 | |
3c2e3512 GR |
107 | outb(reg++, ioreg); |
108 | val = inb(ioreg + 1) << 8; | |
109 | outb(reg, ioreg); | |
110 | val |= inb(ioreg + 1); | |
1da177e4 LT |
111 | return val; |
112 | } | |
113 | ||
3c2e3512 | 114 | static inline void superio_select(int ioreg, int ldn) |
1da177e4 | 115 | { |
3c2e3512 GR |
116 | outb(DEV, ioreg); |
117 | outb(ldn, ioreg + 1); | |
1da177e4 LT |
118 | } |
119 | ||
3c2e3512 | 120 | static inline int superio_enter(int ioreg) |
1da177e4 | 121 | { |
5b0380c9 | 122 | /* |
3c2e3512 | 123 | * Try to reserve ioreg and ioreg + 1 for exclusive access. |
5b0380c9 | 124 | */ |
3c2e3512 | 125 | if (!request_muxed_region(ioreg, 2, DRVNAME)) |
5b0380c9 NG |
126 | return -EBUSY; |
127 | ||
d47e377c | 128 | __superio_enter(ioreg); |
5b0380c9 | 129 | return 0; |
1da177e4 LT |
130 | } |
131 | ||
4119693b | 132 | static inline void superio_exit(int ioreg, bool noexit) |
1da177e4 | 133 | { |
4119693b FC |
134 | if (!noexit) { |
135 | outb(0x02, ioreg); | |
136 | outb(0x02, ioreg + 1); | |
137 | } | |
3c2e3512 | 138 | release_region(ioreg, 2); |
1da177e4 LT |
139 | } |
140 | ||
87673dd7 | 141 | /* Logical device 4 registers */ |
1da177e4 LT |
142 | #define IT8712F_DEVID 0x8712 |
143 | #define IT8705F_DEVID 0x8705 | |
17d648bf | 144 | #define IT8716F_DEVID 0x8716 |
87673dd7 | 145 | #define IT8718F_DEVID 0x8718 |
b4da93e4 | 146 | #define IT8720F_DEVID 0x8720 |
44c1bcd4 | 147 | #define IT8721F_DEVID 0x8721 |
08a8f6e9 | 148 | #define IT8726F_DEVID 0x8726 |
16b5dda2 | 149 | #define IT8728F_DEVID 0x8728 |
ead80803 | 150 | #define IT8732F_DEVID 0x8732 |
e531ffc0 | 151 | #define IT8792E_DEVID 0x8733 |
b0636707 GR |
152 | #define IT8771E_DEVID 0x8771 |
153 | #define IT8772E_DEVID 0x8772 | |
7bc32d29 | 154 | #define IT8781F_DEVID 0x8781 |
0531d98b GR |
155 | #define IT8782F_DEVID 0x8782 |
156 | #define IT8783E_DEVID 0x8783 | |
a0c1424a | 157 | #define IT8786E_DEVID 0x8786 |
4ee07157 | 158 | #define IT8790E_DEVID 0x8790 |
7183ae8c | 159 | #define IT8603E_DEVID 0x8603 |
3ba9d977 | 160 | #define IT8620E_DEVID 0x8620 |
8af1abae | 161 | #define IT8622E_DEVID 0x8622 |
574e9bd8 | 162 | #define IT8623E_DEVID 0x8623 |
71a9c232 | 163 | #define IT8628E_DEVID 0x8628 |
d44cb4cd | 164 | #define IT87952E_DEVID 0x8695 |
1da177e4 LT |
165 | #define IT87_ACT_REG 0x30 |
166 | #define IT87_BASE_REG 0x60 | |
167 | ||
87673dd7 | 168 | /* Logical device 7 registers (IT8712F and later) */ |
0531d98b | 169 | #define IT87_SIO_GPIO1_REG 0x25 |
3ba9d977 | 170 | #define IT87_SIO_GPIO2_REG 0x26 |
895ff267 | 171 | #define IT87_SIO_GPIO3_REG 0x27 |
36c4d98a | 172 | #define IT87_SIO_GPIO4_REG 0x28 |
591ec650 | 173 | #define IT87_SIO_GPIO5_REG 0x29 |
0531d98b | 174 | #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */ |
87673dd7 | 175 | #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */ |
0531d98b | 176 | #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */ |
87673dd7 | 177 | #define IT87_SIO_VID_REG 0xfc /* VID value */ |
d9b327c3 | 178 | #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */ |
87673dd7 | 179 | |
2a64e9d4 FC |
180 | /* Force chip IDs to specified values. Should only be used for testing */ |
181 | static unsigned short force_id[2]; | |
182 | static unsigned int force_id_cnt; | |
b361a1cf FC |
183 | |
184 | /* ACPI resource conflicts are ignored if this parameter is set to 1 */ | |
185 | static bool ignore_resource_conflict; | |
186 | ||
1da177e4 | 187 | /* Update battery voltage after every reading if true */ |
90ab5ee9 | 188 | static bool update_vbat; |
1da177e4 LT |
189 | |
190 | /* Not all BIOSes properly configure the PWM registers */ | |
90ab5ee9 | 191 | static bool fix_pwm_polarity; |
1da177e4 | 192 | |
1da177e4 LT |
193 | /* Many IT87 constants specified below */ |
194 | ||
195 | /* Length of ISA address segment */ | |
196 | #define IT87_EXTENT 8 | |
197 | ||
87b4b663 BH |
198 | /* Length of ISA address segment for Environmental Controller */ |
199 | #define IT87_EC_EXTENT 2 | |
200 | ||
201 | /* Offset of EC registers from ISA base address */ | |
202 | #define IT87_EC_OFFSET 5 | |
203 | ||
204 | /* Where are the ISA address/data registers relative to the EC base address */ | |
205 | #define IT87_ADDR_REG_OFFSET 0 | |
206 | #define IT87_DATA_REG_OFFSET 1 | |
1da177e4 LT |
207 | |
208 | /*----- The IT87 registers -----*/ | |
209 | ||
210 | #define IT87_REG_CONFIG 0x00 | |
211 | ||
212 | #define IT87_REG_ALARM1 0x01 | |
213 | #define IT87_REG_ALARM2 0x02 | |
214 | #define IT87_REG_ALARM3 0x03 | |
215 | ||
4a0d71cf GR |
216 | /* |
217 | * The IT8718F and IT8720F have the VID value in a different register, in | |
218 | * Super-I/O configuration space. | |
219 | */ | |
1da177e4 | 220 | #define IT87_REG_VID 0x0a |
4a0d71cf GR |
221 | /* |
222 | * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b | |
223 | * for fan divisors. Later IT8712F revisions must use 16-bit tachometer | |
224 | * mode. | |
225 | */ | |
1da177e4 | 226 | #define IT87_REG_FAN_DIV 0x0b |
17d648bf | 227 | #define IT87_REG_FAN_16BIT 0x0c |
1da177e4 | 228 | |
f838aa26 GR |
229 | /* |
230 | * Monitors: | |
231 | * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12) | |
232 | * - up to 6 temp (1 to 6) | |
233 | * - up to 6 fan (1 to 6) | |
234 | */ | |
1da177e4 | 235 | |
fa3f70d6 GR |
236 | static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c }; |
237 | static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e }; | |
238 | static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d }; | |
239 | static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f }; | |
240 | static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 }; | |
161d898a | 241 | |
1da177e4 LT |
242 | #define IT87_REG_FAN_MAIN_CTRL 0x13 |
243 | #define IT87_REG_FAN_CTL 0x14 | |
36c4d98a GR |
244 | static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf }; |
245 | static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab }; | |
1da177e4 | 246 | |
559313c4 | 247 | static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, |
f838aa26 | 248 | 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e }; |
1da177e4 | 249 | |
559313c4 | 250 | #define IT87_REG_TEMP(nr) (0x29 + (nr)) |
73055405 | 251 | |
1da177e4 LT |
252 | #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2) |
253 | #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2) | |
254 | #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2) | |
255 | #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2) | |
256 | ||
1da177e4 LT |
257 | #define IT87_REG_VIN_ENABLE 0x50 |
258 | #define IT87_REG_TEMP_ENABLE 0x51 | |
4573acbc | 259 | #define IT87_REG_TEMP_EXTRA 0x55 |
d9b327c3 | 260 | #define IT87_REG_BEEP_ENABLE 0x5c |
1da177e4 LT |
261 | |
262 | #define IT87_REG_CHIPID 0x58 | |
263 | ||
2cbb9c37 GR |
264 | static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 }; |
265 | ||
266 | #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i)) | |
267 | #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i)) | |
4f3f51bc | 268 | |
cc18da79 GR |
269 | #define IT87_REG_TEMP456_ENABLE 0x77 |
270 | ||
2310048d GR |
271 | #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN) |
272 | #define NUM_VIN_LIMIT 8 | |
273 | #define NUM_TEMP 6 | |
274 | #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) | |
275 | #define NUM_TEMP_LIMIT 3 | |
276 | #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) | |
277 | #define NUM_FAN_DIV 3 | |
278 | #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) | |
279 | #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM) | |
280 | ||
483db43e GR |
281 | struct it87_devices { |
282 | const char *name; | |
1f21531d | 283 | const char * const model; |
cc18da79 | 284 | u32 features; |
19529784 GR |
285 | u8 peci_mask; |
286 | u8 old_peci_mask; | |
483db43e GR |
287 | }; |
288 | ||
48b2ae7f GR |
289 | #define FEAT_12MV_ADC BIT(0) |
290 | #define FEAT_NEWER_AUTOPWM BIT(1) | |
291 | #define FEAT_OLD_AUTOPWM BIT(2) | |
292 | #define FEAT_16BIT_FANS BIT(3) | |
293 | #define FEAT_TEMP_OFFSET BIT(4) | |
294 | #define FEAT_TEMP_PECI BIT(5) | |
295 | #define FEAT_TEMP_OLD_PECI BIT(6) | |
296 | #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ | |
297 | #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */ | |
298 | #define FEAT_VID BIT(9) /* Set if chip supports VID */ | |
299 | #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */ | |
300 | #define FEAT_SIX_FANS BIT(11) /* Supports six fans */ | |
301 | #define FEAT_10_9MV_ADC BIT(12) | |
302 | #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */ | |
638c1c07 GR |
303 | #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */ |
304 | #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */ | |
305 | #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */ | |
306 | #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */ | |
307 | #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */ | |
4119693b FC |
308 | /* |
309 | * Disabling configuration mode on some chips can result in system | |
310 | * hang-ups and access failures to the Super-IO chip at the | |
311 | * second SIO address. Never exit configuration mode on these | |
312 | * chips to avoid the problem. | |
313 | */ | |
314 | #define FEAT_CONF_NOEXIT BIT(19) /* Chip should not exit conf mode */ | |
483db43e GR |
315 | |
316 | static const struct it87_devices it87_devices[] = { | |
317 | [it87] = { | |
318 | .name = "it87", | |
1f21531d | 319 | .model = "IT87F", |
483db43e GR |
320 | .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */ |
321 | }, | |
322 | [it8712] = { | |
323 | .name = "it8712", | |
1f21531d | 324 | .model = "IT8712F", |
32dd7c40 GR |
325 | .features = FEAT_OLD_AUTOPWM | FEAT_VID, |
326 | /* may need to overwrite */ | |
483db43e GR |
327 | }, |
328 | [it8716] = { | |
329 | .name = "it8716", | |
1f21531d | 330 | .model = "IT8716F", |
32dd7c40 | 331 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID |
60878bcf | 332 | | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2, |
483db43e GR |
333 | }, |
334 | [it8718] = { | |
335 | .name = "it8718", | |
1f21531d | 336 | .model = "IT8718F", |
32dd7c40 | 337 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID |
60878bcf GR |
338 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS |
339 | | FEAT_PWM_FREQ2, | |
19529784 | 340 | .old_peci_mask = 0x4, |
483db43e GR |
341 | }, |
342 | [it8720] = { | |
343 | .name = "it8720", | |
1f21531d | 344 | .model = "IT8720F", |
32dd7c40 | 345 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID |
60878bcf GR |
346 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS |
347 | | FEAT_PWM_FREQ2, | |
19529784 | 348 | .old_peci_mask = 0x4, |
483db43e GR |
349 | }, |
350 | [it8721] = { | |
351 | .name = "it8721", | |
1f21531d | 352 | .model = "IT8721F", |
483db43e | 353 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
9faf28ca | 354 | | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI |
60878bcf GR |
355 | | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL |
356 | | FEAT_PWM_FREQ2, | |
5d8d2f2b | 357 | .peci_mask = 0x05, |
19529784 | 358 | .old_peci_mask = 0x02, /* Actually reports PCH */ |
483db43e GR |
359 | }, |
360 | [it8728] = { | |
361 | .name = "it8728", | |
1f21531d | 362 | .model = "IT8728F", |
483db43e | 363 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
7f5726c3 | 364 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS |
60878bcf | 365 | | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2, |
5d8d2f2b | 366 | .peci_mask = 0x07, |
483db43e | 367 | }, |
ead80803 JM |
368 | [it8732] = { |
369 | .name = "it8732", | |
1f21531d | 370 | .model = "IT8732F", |
ead80803 JM |
371 | .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS |
372 | | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | |
373 | | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL, | |
374 | .peci_mask = 0x07, | |
375 | .old_peci_mask = 0x02, /* Actually reports PCH */ | |
376 | }, | |
b0636707 GR |
377 | [it8771] = { |
378 | .name = "it8771", | |
1f21531d | 379 | .model = "IT8771E", |
b0636707 | 380 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf GR |
381 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
382 | | FEAT_PWM_FREQ2, | |
9faf28ca GR |
383 | /* PECI: guesswork */ |
384 | /* 12mV ADC (OHM) */ | |
385 | /* 16 bit fans (OHM) */ | |
386 | /* three fans, always 16 bit (guesswork) */ | |
b0636707 GR |
387 | .peci_mask = 0x07, |
388 | }, | |
389 | [it8772] = { | |
390 | .name = "it8772", | |
1f21531d | 391 | .model = "IT8772E", |
b0636707 | 392 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf GR |
393 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
394 | | FEAT_PWM_FREQ2, | |
9faf28ca GR |
395 | /* PECI (coreboot) */ |
396 | /* 12mV ADC (HWSensors4, OHM) */ | |
397 | /* 16 bit fans (HWSensors4, OHM) */ | |
398 | /* three fans, always 16 bit (datasheet) */ | |
b0636707 GR |
399 | .peci_mask = 0x07, |
400 | }, | |
7bc32d29 GR |
401 | [it8781] = { |
402 | .name = "it8781", | |
1f21531d | 403 | .model = "IT8781F", |
7bc32d29 | 404 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET |
60878bcf | 405 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, |
7bc32d29 GR |
406 | .old_peci_mask = 0x4, |
407 | }, | |
483db43e GR |
408 | [it8782] = { |
409 | .name = "it8782", | |
1f21531d | 410 | .model = "IT8782F", |
19529784 | 411 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET |
60878bcf | 412 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, |
19529784 | 413 | .old_peci_mask = 0x4, |
483db43e GR |
414 | }, |
415 | [it8783] = { | |
416 | .name = "it8783", | |
1f21531d | 417 | .model = "IT8783E/F", |
19529784 | 418 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET |
60878bcf | 419 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, |
19529784 | 420 | .old_peci_mask = 0x4, |
483db43e | 421 | }, |
a0c1424a TL |
422 | [it8786] = { |
423 | .name = "it8786", | |
1f21531d | 424 | .model = "IT8786E", |
a0c1424a | 425 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf GR |
426 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
427 | | FEAT_PWM_FREQ2, | |
a0c1424a TL |
428 | .peci_mask = 0x07, |
429 | }, | |
4ee07157 GR |
430 | [it8790] = { |
431 | .name = "it8790", | |
1f21531d | 432 | .model = "IT8790E", |
4ee07157 | 433 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf | 434 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
e1147378 | 435 | | FEAT_PWM_FREQ2 | FEAT_CONF_NOEXIT, |
4ee07157 GR |
436 | .peci_mask = 0x07, |
437 | }, | |
e531ffc0 GR |
438 | [it8792] = { |
439 | .name = "it8792", | |
1f21531d | 440 | .model = "IT8792E/IT8795E", |
e531ffc0 GR |
441 | .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS |
442 | | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | |
e1147378 | 443 | | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_CONF_NOEXIT, |
e531ffc0 GR |
444 | .peci_mask = 0x07, |
445 | .old_peci_mask = 0x02, /* Actually reports PCH */ | |
446 | }, | |
c145d5c6 RM |
447 | [it8603] = { |
448 | .name = "it8603", | |
1f21531d | 449 | .model = "IT8603E", |
c145d5c6 | 450 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
73055405 | 451 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
60878bcf | 452 | | FEAT_AVCC3 | FEAT_PWM_FREQ2, |
c145d5c6 RM |
453 | .peci_mask = 0x07, |
454 | }, | |
3ba9d977 GR |
455 | [it8620] = { |
456 | .name = "it8620", | |
1f21531d | 457 | .model = "IT8620E", |
3ba9d977 | 458 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
fa3f70d6 | 459 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS |
cc18da79 | 460 | | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 |
a9eebd4f | 461 | | FEAT_SIX_TEMP | FEAT_VIN3_5V, |
3ba9d977 GR |
462 | .peci_mask = 0x07, |
463 | }, | |
8af1abae GR |
464 | [it8622] = { |
465 | .name = "it8622", | |
1f21531d | 466 | .model = "IT8622E", |
8af1abae GR |
467 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
468 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS | |
638c1c07 GR |
469 | | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 |
470 | | FEAT_AVCC3 | FEAT_VIN3_5V, | |
8af1abae GR |
471 | .peci_mask = 0x07, |
472 | }, | |
71a9c232 GR |
473 | [it8628] = { |
474 | .name = "it8628", | |
1f21531d | 475 | .model = "IT8628E", |
71a9c232 GR |
476 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
477 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS | |
478 | | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | |
a9eebd4f | 479 | | FEAT_SIX_TEMP | FEAT_VIN3_5V, |
71a9c232 GR |
480 | .peci_mask = 0x07, |
481 | }, | |
d44cb4cd FC |
482 | [it87952] = { |
483 | .name = "it87952", | |
484 | .model = "IT87952E", | |
485 | .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS | |
486 | | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | |
487 | | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_CONF_NOEXIT, | |
488 | .peci_mask = 0x07, | |
489 | .old_peci_mask = 0x02, /* Actually reports PCH */ | |
490 | }, | |
483db43e GR |
491 | }; |
492 | ||
493 | #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) | |
494 | #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) | |
ead80803 | 495 | #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) |
483db43e GR |
496 | #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) |
497 | #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) | |
498 | #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) | |
5d8d2f2b | 499 | #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ |
48b2ae7f | 500 | ((data)->peci_mask & BIT(nr))) |
19529784 GR |
501 | #define has_temp_old_peci(data, nr) \ |
502 | (((data)->features & FEAT_TEMP_OLD_PECI) && \ | |
48b2ae7f | 503 | ((data)->old_peci_mask & BIT(nr))) |
9faf28ca | 504 | #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG) |
fa3f70d6 GR |
505 | #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \ |
506 | FEAT_SIX_FANS)) | |
32dd7c40 | 507 | #define has_vid(data) ((data)->features & FEAT_VID) |
7f5726c3 | 508 | #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL) |
fa3f70d6 | 509 | #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS) |
73055405 | 510 | #define has_avcc3(data) ((data)->features & FEAT_AVCC3) |
638c1c07 GR |
511 | #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \ |
512 | | FEAT_SIX_PWM)) | |
36c4d98a | 513 | #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM) |
60878bcf | 514 | #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) |
cc18da79 | 515 | #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) |
a9eebd4f | 516 | #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) |
4119693b | 517 | #define has_conf_noexit(data) ((data)->features & FEAT_CONF_NOEXIT) |
968b66ff FC |
518 | #define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \ |
519 | FEAT_10_9MV_ADC)) | |
1da177e4 | 520 | |
b74f3fdd | 521 | struct it87_sio_data { |
384548e5 | 522 | int sioaddr; |
b74f3fdd | 523 | enum chips type; |
524 | /* Values read from Super-I/O config space */ | |
0475169c | 525 | u8 revision; |
b74f3fdd | 526 | u8 vid_value; |
d9b327c3 | 527 | u8 beep_pin; |
738e5e05 | 528 | u8 internal; /* Internal sensors can be labeled */ |
384548e5 | 529 | bool need_in7_reroute; |
591ec650 | 530 | /* Features skipped based on config or DMI */ |
9172b5d1 | 531 | u16 skip_in; |
895ff267 | 532 | u8 skip_vid; |
591ec650 | 533 | u8 skip_fan; |
98dd22c3 | 534 | u8 skip_pwm; |
4573acbc | 535 | u8 skip_temp; |
b74f3fdd | 536 | }; |
537 | ||
4a0d71cf GR |
538 | /* |
539 | * For each registered chip, we need to keep some data in memory. | |
540 | * The structure is dynamically allocated. | |
541 | */ | |
1da177e4 | 542 | struct it87_data { |
8638d0af | 543 | const struct attribute_group *groups[7]; |
384548e5 | 544 | int sioaddr; |
1da177e4 | 545 | enum chips type; |
aa8b187e | 546 | u32 features; |
19529784 GR |
547 | u8 peci_mask; |
548 | u8 old_peci_mask; | |
1da177e4 | 549 | |
b74f3fdd | 550 | unsigned short addr; |
551 | const char *name; | |
9a61bf63 | 552 | struct mutex update_lock; |
952a11ca | 553 | bool valid; /* true if following fields are valid */ |
1da177e4 LT |
554 | unsigned long last_updated; /* In jiffies */ |
555 | ||
44c1bcd4 | 556 | u16 in_scaled; /* Internal voltage sensors are scaled */ |
d3766848 | 557 | u16 in_internal; /* Bitfield, internal sensors (for labels) */ |
52929715 | 558 | u16 has_in; /* Bitfield, voltage sensors enabled */ |
2310048d | 559 | u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */ |
384548e5 | 560 | bool need_in7_reroute; |
9060f8bd | 561 | u8 has_fan; /* Bitfield, fans enabled */ |
2310048d | 562 | u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */ |
4573acbc | 563 | u8 has_temp; /* Bitfield, temp sensors enabled */ |
2310048d | 564 | s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */ |
19529784 GR |
565 | u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */ |
566 | u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */ | |
2310048d | 567 | u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */ |
d3766848 | 568 | bool has_vid; /* True if VID supported */ |
1da177e4 | 569 | u8 vid; /* Register encoding, combined */ |
a7be58a1 | 570 | u8 vrm; |
1da177e4 | 571 | u32 alarms; /* Register encoding, combined */ |
52929715 | 572 | bool has_beep; /* true if beep supported */ |
d9b327c3 | 573 | u8 beeps; /* Register encoding */ |
1da177e4 | 574 | u8 fan_main_ctrl; /* Register value */ |
f8d0c19a | 575 | u8 fan_ctl; /* Register value */ |
b99883dc | 576 | |
4a0d71cf GR |
577 | /* |
578 | * The following 3 arrays correspond to the same registers up to | |
6229cdb2 JD |
579 | * the IT8720F. The meaning of bits 6-0 depends on the value of bit |
580 | * 7, and we want to preserve settings on mode changes, so we have | |
581 | * to track all values separately. | |
582 | * Starting with the IT8721F, the manual PWM duty cycles are stored | |
583 | * in separate registers (8-bit values), so the separate tracking | |
584 | * is no longer needed, but it is still done to keep the driver | |
4a0d71cf GR |
585 | * simple. |
586 | */ | |
5c391261 | 587 | u8 has_pwm; /* Bitfield, pwm control enabled */ |
2310048d GR |
588 | u8 pwm_ctrl[NUM_PWM]; /* Register value */ |
589 | u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ | |
590 | u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ | |
4f3f51bc JD |
591 | |
592 | /* Automatic fan speed control registers */ | |
2310048d GR |
593 | u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ |
594 | s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */ | |
1da177e4 | 595 | }; |
0df6454d | 596 | |
a1bedbcc FC |
597 | /* Board specific settings from DMI matching */ |
598 | struct it87_dmi_data { | |
599 | u8 skip_pwm; /* pwm channels to skip for this board */ | |
600 | }; | |
601 | ||
602 | /* Global for results from DMI matching, if needed */ | |
603 | static struct it87_dmi_data *dmi_data; | |
604 | ||
0531d98b | 605 | static int adc_lsb(const struct it87_data *data, int nr) |
44c1bcd4 | 606 | { |
ead80803 JM |
607 | int lsb; |
608 | ||
609 | if (has_12mv_adc(data)) | |
610 | lsb = 120; | |
611 | else if (has_10_9mv_adc(data)) | |
612 | lsb = 109; | |
613 | else | |
614 | lsb = 160; | |
48b2ae7f | 615 | if (data->in_scaled & BIT(nr)) |
0531d98b GR |
616 | lsb <<= 1; |
617 | return lsb; | |
618 | } | |
44c1bcd4 | 619 | |
0531d98b GR |
620 | static u8 in_to_reg(const struct it87_data *data, int nr, long val) |
621 | { | |
ead80803 | 622 | val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr)); |
2a844c14 | 623 | return clamp_val(val, 0, 255); |
44c1bcd4 JD |
624 | } |
625 | ||
626 | static int in_from_reg(const struct it87_data *data, int nr, int val) | |
627 | { | |
ead80803 | 628 | return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10); |
44c1bcd4 | 629 | } |
0df6454d JD |
630 | |
631 | static inline u8 FAN_TO_REG(long rpm, int div) | |
632 | { | |
633 | if (rpm == 0) | |
634 | return 255; | |
2a844c14 GR |
635 | rpm = clamp_val(rpm, 1, 1000000); |
636 | return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254); | |
0df6454d JD |
637 | } |
638 | ||
639 | static inline u16 FAN16_TO_REG(long rpm) | |
640 | { | |
641 | if (rpm == 0) | |
642 | return 0xffff; | |
2a844c14 | 643 | return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe); |
0df6454d JD |
644 | } |
645 | ||
646 | #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \ | |
647 | 1350000 / ((val) * (div))) | |
648 | /* The divider is fixed to 2 in 16-bit mode */ | |
649 | #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ | |
650 | 1350000 / ((val) * 2)) | |
651 | ||
2a844c14 GR |
652 | #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \ |
653 | ((val) + 500) / 1000), -128, 127)) | |
0df6454d JD |
654 | #define TEMP_FROM_REG(val) ((val) * 1000) |
655 | ||
44c1bcd4 JD |
656 | static u8 pwm_to_reg(const struct it87_data *data, long val) |
657 | { | |
16b5dda2 | 658 | if (has_newer_autopwm(data)) |
44c1bcd4 JD |
659 | return val; |
660 | else | |
661 | return val >> 1; | |
662 | } | |
663 | ||
664 | static int pwm_from_reg(const struct it87_data *data, u8 reg) | |
665 | { | |
16b5dda2 | 666 | if (has_newer_autopwm(data)) |
44c1bcd4 JD |
667 | return reg; |
668 | else | |
669 | return (reg & 0x7f) << 1; | |
670 | } | |
671 | ||
0df6454d JD |
672 | static int DIV_TO_REG(int val) |
673 | { | |
674 | int answer = 0; | |
c962024e | 675 | |
0df6454d JD |
676 | while (answer < 7 && (val >>= 1)) |
677 | answer++; | |
678 | return answer; | |
679 | } | |
48b2ae7f GR |
680 | |
681 | #define DIV_FROM_REG(val) BIT(val) | |
0df6454d | 682 | |
f56c9c0a GR |
683 | /* |
684 | * PWM base frequencies. The frequency has to be divided by either 128 or 256, | |
685 | * depending on the chip type, to calculate the actual PWM frequency. | |
686 | * | |
687 | * Some of the chip datasheets suggest a base frequency of 51 kHz instead | |
688 | * of 750 kHz for the slowest base frequency, resulting in a PWM frequency | |
689 | * of 200 Hz. Sometimes both PWM frequency select registers are affected, | |
690 | * sometimes just one. It is unknown if this is a datasheet error or real, | |
691 | * so this is ignored for now. | |
692 | */ | |
0df6454d | 693 | static const unsigned int pwm_freq[8] = { |
f56c9c0a GR |
694 | 48000000, |
695 | 24000000, | |
696 | 12000000, | |
697 | 8000000, | |
698 | 6000000, | |
699 | 3000000, | |
700 | 1500000, | |
701 | 750000, | |
0df6454d | 702 | }; |
1da177e4 | 703 | |
c1e7a4ca GR |
704 | /* |
705 | * Must be called with data->update_lock held, except during initialization. | |
706 | * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, | |
707 | * would slow down the IT87 access and should not be necessary. | |
708 | */ | |
709 | static int it87_read_value(struct it87_data *data, u8 reg) | |
710 | { | |
711 | outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); | |
712 | return inb_p(data->addr + IT87_DATA_REG_OFFSET); | |
713 | } | |
714 | ||
715 | /* | |
716 | * Must be called with data->update_lock held, except during initialization. | |
717 | * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, | |
718 | * would slow down the IT87 access and should not be necessary. | |
719 | */ | |
720 | static void it87_write_value(struct it87_data *data, u8 reg, u8 value) | |
721 | { | |
722 | outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); | |
723 | outb_p(value, data->addr + IT87_DATA_REG_OFFSET); | |
724 | } | |
725 | ||
726 | static void it87_update_pwm_ctrl(struct it87_data *data, int nr) | |
727 | { | |
728 | data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]); | |
729 | if (has_newer_autopwm(data)) { | |
0624d861 | 730 | data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; |
c1e7a4ca GR |
731 | data->pwm_duty[nr] = it87_read_value(data, |
732 | IT87_REG_PWM_DUTY[nr]); | |
733 | } else { | |
734 | if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ | |
735 | data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; | |
736 | else /* Manual mode */ | |
737 | data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; | |
738 | } | |
1da177e4 | 739 | |
c1e7a4ca GR |
740 | if (has_old_autopwm(data)) { |
741 | int i; | |
1da177e4 | 742 | |
c1e7a4ca GR |
743 | for (i = 0; i < 5 ; i++) |
744 | data->auto_temp[nr][i] = it87_read_value(data, | |
745 | IT87_REG_AUTO_TEMP(nr, i)); | |
746 | for (i = 0; i < 3 ; i++) | |
747 | data->auto_pwm[nr][i] = it87_read_value(data, | |
748 | IT87_REG_AUTO_PWM(nr, i)); | |
2cbb9c37 GR |
749 | } else if (has_newer_autopwm(data)) { |
750 | int i; | |
751 | ||
752 | /* | |
753 | * 0: temperature hysteresis (base + 5) | |
754 | * 1: fan off temperature (base + 0) | |
755 | * 2: fan start temperature (base + 1) | |
756 | * 3: fan max temperature (base + 2) | |
757 | */ | |
758 | data->auto_temp[nr][0] = | |
759 | it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5)); | |
760 | ||
761 | for (i = 0; i < 3 ; i++) | |
762 | data->auto_temp[nr][i + 1] = | |
763 | it87_read_value(data, | |
764 | IT87_REG_AUTO_TEMP(nr, i)); | |
765 | /* | |
766 | * 0: start pwm value (base + 3) | |
767 | * 1: pwm slope (base + 4, 1/8th pwm) | |
768 | */ | |
769 | data->auto_pwm[nr][0] = | |
770 | it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3)); | |
771 | data->auto_pwm[nr][1] = | |
772 | it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4)); | |
c1e7a4ca GR |
773 | } |
774 | } | |
1da177e4 | 775 | |
c1e7a4ca GR |
776 | static struct it87_data *it87_update_device(struct device *dev) |
777 | { | |
778 | struct it87_data *data = dev_get_drvdata(dev); | |
779 | int i; | |
780 | ||
781 | mutex_lock(&data->update_lock); | |
782 | ||
c962024e GR |
783 | if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || |
784 | !data->valid) { | |
c1e7a4ca GR |
785 | if (update_vbat) { |
786 | /* | |
787 | * Cleared after each update, so reenable. Value | |
788 | * returned by this read will be previous value | |
789 | */ | |
790 | it87_write_value(data, IT87_REG_CONFIG, | |
791 | it87_read_value(data, IT87_REG_CONFIG) | 0x40); | |
792 | } | |
2310048d | 793 | for (i = 0; i < NUM_VIN; i++) { |
48b2ae7f | 794 | if (!(data->has_in & BIT(i))) |
559313c4 GR |
795 | continue; |
796 | ||
c1e7a4ca | 797 | data->in[i][0] = |
559313c4 GR |
798 | it87_read_value(data, IT87_REG_VIN[i]); |
799 | ||
800 | /* VBAT and AVCC don't have limit registers */ | |
2310048d | 801 | if (i >= NUM_VIN_LIMIT) |
559313c4 GR |
802 | continue; |
803 | ||
c1e7a4ca GR |
804 | data->in[i][1] = |
805 | it87_read_value(data, IT87_REG_VIN_MIN(i)); | |
806 | data->in[i][2] = | |
807 | it87_read_value(data, IT87_REG_VIN_MAX(i)); | |
808 | } | |
c1e7a4ca | 809 | |
2310048d | 810 | for (i = 0; i < NUM_FAN; i++) { |
c1e7a4ca | 811 | /* Skip disabled fans */ |
48b2ae7f | 812 | if (!(data->has_fan & BIT(i))) |
c1e7a4ca GR |
813 | continue; |
814 | ||
815 | data->fan[i][1] = | |
816 | it87_read_value(data, IT87_REG_FAN_MIN[i]); | |
817 | data->fan[i][0] = it87_read_value(data, | |
818 | IT87_REG_FAN[i]); | |
819 | /* Add high byte if in 16-bit mode */ | |
820 | if (has_16bit_fans(data)) { | |
821 | data->fan[i][0] |= it87_read_value(data, | |
822 | IT87_REG_FANX[i]) << 8; | |
823 | data->fan[i][1] |= it87_read_value(data, | |
824 | IT87_REG_FANX_MIN[i]) << 8; | |
825 | } | |
826 | } | |
2310048d | 827 | for (i = 0; i < NUM_TEMP; i++) { |
48b2ae7f | 828 | if (!(data->has_temp & BIT(i))) |
c1e7a4ca GR |
829 | continue; |
830 | data->temp[i][0] = | |
831 | it87_read_value(data, IT87_REG_TEMP(i)); | |
cc18da79 | 832 | |
2310048d GR |
833 | if (has_temp_offset(data) && i < NUM_TEMP_OFFSET) |
834 | data->temp[i][3] = | |
835 | it87_read_value(data, | |
836 | IT87_REG_TEMP_OFFSET[i]); | |
837 | ||
838 | if (i >= NUM_TEMP_LIMIT) | |
cc18da79 GR |
839 | continue; |
840 | ||
c1e7a4ca GR |
841 | data->temp[i][1] = |
842 | it87_read_value(data, IT87_REG_TEMP_LOW(i)); | |
843 | data->temp[i][2] = | |
844 | it87_read_value(data, IT87_REG_TEMP_HIGH(i)); | |
c1e7a4ca GR |
845 | } |
846 | ||
847 | /* Newer chips don't have clock dividers */ | |
848 | if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { | |
849 | i = it87_read_value(data, IT87_REG_FAN_DIV); | |
850 | data->fan_div[0] = i & 0x07; | |
851 | data->fan_div[1] = (i >> 3) & 0x07; | |
852 | data->fan_div[2] = (i & 0x40) ? 3 : 1; | |
853 | } | |
854 | ||
855 | data->alarms = | |
856 | it87_read_value(data, IT87_REG_ALARM1) | | |
857 | (it87_read_value(data, IT87_REG_ALARM2) << 8) | | |
858 | (it87_read_value(data, IT87_REG_ALARM3) << 16); | |
859 | data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); | |
860 | ||
861 | data->fan_main_ctrl = it87_read_value(data, | |
862 | IT87_REG_FAN_MAIN_CTRL); | |
863 | data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); | |
0624d861 GR |
864 | for (i = 0; i < NUM_PWM; i++) { |
865 | if (!(data->has_pwm & BIT(i))) | |
866 | continue; | |
c1e7a4ca | 867 | it87_update_pwm_ctrl(data, i); |
0624d861 | 868 | } |
c1e7a4ca GR |
869 | |
870 | data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); | |
871 | data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); | |
872 | /* | |
873 | * The IT8705F does not have VID capability. | |
874 | * The IT8718F and later don't use IT87_REG_VID for the | |
875 | * same purpose. | |
876 | */ | |
877 | if (data->type == it8712 || data->type == it8716) { | |
878 | data->vid = it87_read_value(data, IT87_REG_VID); | |
879 | /* | |
880 | * The older IT8712F revisions had only 5 VID pins, | |
881 | * but we assume it is always safe to read 6 bits. | |
882 | */ | |
883 | data->vid &= 0x3f; | |
884 | } | |
885 | data->last_updated = jiffies; | |
952a11ca | 886 | data->valid = true; |
c1e7a4ca GR |
887 | } |
888 | ||
889 | mutex_unlock(&data->update_lock); | |
890 | ||
891 | return data; | |
892 | } | |
fde09509 | 893 | |
20ad93d4 | 894 | static ssize_t show_in(struct device *dev, struct device_attribute *attr, |
929c6a56 | 895 | char *buf) |
1da177e4 | 896 | { |
929c6a56 | 897 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
c962024e | 898 | struct it87_data *data = it87_update_device(dev); |
929c6a56 | 899 | int index = sattr->index; |
c962024e | 900 | int nr = sattr->nr; |
20ad93d4 | 901 | |
929c6a56 | 902 | return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index])); |
1da177e4 LT |
903 | } |
904 | ||
929c6a56 GR |
905 | static ssize_t set_in(struct device *dev, struct device_attribute *attr, |
906 | const char *buf, size_t count) | |
1da177e4 | 907 | { |
929c6a56 | 908 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
b74f3fdd | 909 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e GR |
910 | int index = sattr->index; |
911 | int nr = sattr->nr; | |
f5f64501 JD |
912 | unsigned long val; |
913 | ||
179c4fdb | 914 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 | 915 | return -EINVAL; |
1da177e4 | 916 | |
9a61bf63 | 917 | mutex_lock(&data->update_lock); |
929c6a56 GR |
918 | data->in[nr][index] = in_to_reg(data, nr, val); |
919 | it87_write_value(data, | |
920 | index == 1 ? IT87_REG_VIN_MIN(nr) | |
921 | : IT87_REG_VIN_MAX(nr), | |
922 | data->in[nr][index]); | |
9a61bf63 | 923 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
924 | return count; |
925 | } | |
20ad93d4 | 926 | |
929c6a56 GR |
927 | static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0); |
928 | static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
929 | 0, 1); | |
930 | static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
931 | 0, 2); | |
f5f64501 | 932 | |
929c6a56 GR |
933 | static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0); |
934 | static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
935 | 1, 1); | |
936 | static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
937 | 1, 2); | |
1da177e4 | 938 | |
929c6a56 GR |
939 | static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0); |
940 | static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
941 | 2, 1); | |
942 | static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
943 | 2, 2); | |
1da177e4 | 944 | |
929c6a56 GR |
945 | static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0); |
946 | static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
947 | 3, 1); | |
948 | static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
949 | 3, 2); | |
950 | ||
951 | static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0); | |
952 | static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
953 | 4, 1); | |
954 | static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
955 | 4, 2); | |
956 | ||
957 | static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0); | |
958 | static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
959 | 5, 1); | |
960 | static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
961 | 5, 2); | |
962 | ||
963 | static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0); | |
964 | static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
965 | 6, 1); | |
966 | static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
967 | 6, 2); | |
968 | ||
969 | static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0); | |
970 | static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
971 | 7, 1); | |
972 | static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
973 | 7, 2); | |
974 | ||
975 | static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0); | |
c145d5c6 | 976 | static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0); |
f838aa26 GR |
977 | static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0); |
978 | static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0); | |
979 | static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0); | |
1da177e4 | 980 | |
cc18da79 | 981 | /* Up to 6 temperatures */ |
20ad93d4 | 982 | static ssize_t show_temp(struct device *dev, struct device_attribute *attr, |
60ca385a | 983 | char *buf) |
1da177e4 | 984 | { |
60ca385a GR |
985 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
986 | int nr = sattr->nr; | |
987 | int index = sattr->index; | |
1da177e4 | 988 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 | 989 | |
60ca385a | 990 | return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index])); |
1da177e4 | 991 | } |
20ad93d4 | 992 | |
60ca385a GR |
993 | static ssize_t set_temp(struct device *dev, struct device_attribute *attr, |
994 | const char *buf, size_t count) | |
1da177e4 | 995 | { |
60ca385a GR |
996 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
997 | int nr = sattr->nr; | |
998 | int index = sattr->index; | |
b74f3fdd | 999 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 | 1000 | long val; |
161d898a | 1001 | u8 reg, regval; |
f5f64501 | 1002 | |
179c4fdb | 1003 | if (kstrtol(buf, 10, &val) < 0) |
f5f64501 | 1004 | return -EINVAL; |
1da177e4 | 1005 | |
9a61bf63 | 1006 | mutex_lock(&data->update_lock); |
161d898a GR |
1007 | |
1008 | switch (index) { | |
1009 | default: | |
1010 | case 1: | |
1011 | reg = IT87_REG_TEMP_LOW(nr); | |
1012 | break; | |
1013 | case 2: | |
1014 | reg = IT87_REG_TEMP_HIGH(nr); | |
1015 | break; | |
1016 | case 3: | |
1017 | regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); | |
1018 | if (!(regval & 0x80)) { | |
1019 | regval |= 0x80; | |
1020 | it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); | |
1021 | } | |
952a11ca | 1022 | data->valid = false; |
161d898a GR |
1023 | reg = IT87_REG_TEMP_OFFSET[nr]; |
1024 | break; | |
1025 | } | |
1026 | ||
60ca385a | 1027 | data->temp[nr][index] = TEMP_TO_REG(val); |
161d898a | 1028 | it87_write_value(data, reg, data->temp[nr][index]); |
9a61bf63 | 1029 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1030 | return count; |
1031 | } | |
1da177e4 | 1032 | |
60ca385a GR |
1033 | static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0); |
1034 | static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1035 | 0, 1); | |
1036 | static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1037 | 0, 2); | |
161d898a GR |
1038 | static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp, |
1039 | set_temp, 0, 3); | |
60ca385a GR |
1040 | static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0); |
1041 | static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1042 | 1, 1); | |
1043 | static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1044 | 1, 2); | |
161d898a GR |
1045 | static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp, |
1046 | set_temp, 1, 3); | |
60ca385a GR |
1047 | static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0); |
1048 | static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1049 | 2, 1); | |
1050 | static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1051 | 2, 2); | |
161d898a GR |
1052 | static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp, |
1053 | set_temp, 2, 3); | |
cc18da79 GR |
1054 | static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0); |
1055 | static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0); | |
1056 | static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0); | |
1da177e4 | 1057 | |
2cece01f GR |
1058 | static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr, |
1059 | char *buf) | |
1da177e4 | 1060 | { |
20ad93d4 JD |
1061 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1062 | int nr = sensor_attr->index; | |
1da177e4 | 1063 | struct it87_data *data = it87_update_device(dev); |
4a0d71cf | 1064 | u8 reg = data->sensor; /* In case value is updated while used */ |
19529784 | 1065 | u8 extra = data->extra; |
5f2dc798 | 1066 | |
c962024e GR |
1067 | if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) || |
1068 | (has_temp_old_peci(data, nr) && (extra & 0x80))) | |
5d8d2f2b | 1069 | return sprintf(buf, "6\n"); /* Intel PECI */ |
1da177e4 LT |
1070 | if (reg & (1 << nr)) |
1071 | return sprintf(buf, "3\n"); /* thermal diode */ | |
1072 | if (reg & (8 << nr)) | |
4ed10779 | 1073 | return sprintf(buf, "4\n"); /* thermistor */ |
1da177e4 LT |
1074 | return sprintf(buf, "0\n"); /* disabled */ |
1075 | } | |
2cece01f GR |
1076 | |
1077 | static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr, | |
1078 | const char *buf, size_t count) | |
1da177e4 | 1079 | { |
20ad93d4 JD |
1080 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1081 | int nr = sensor_attr->index; | |
1082 | ||
b74f3fdd | 1083 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 | 1084 | long val; |
19529784 | 1085 | u8 reg, extra; |
f5f64501 | 1086 | |
179c4fdb | 1087 | if (kstrtol(buf, 10, &val) < 0) |
f5f64501 | 1088 | return -EINVAL; |
1da177e4 | 1089 | |
8acf07c5 JD |
1090 | reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); |
1091 | reg &= ~(1 << nr); | |
1092 | reg &= ~(8 << nr); | |
5d8d2f2b GR |
1093 | if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) |
1094 | reg &= 0x3f; | |
19529784 GR |
1095 | extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); |
1096 | if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6)) | |
1097 | extra &= 0x7f; | |
4ed10779 | 1098 | if (val == 2) { /* backwards compatibility */ |
1d9bcf6a GR |
1099 | dev_warn(dev, |
1100 | "Sensor type 2 is deprecated, please use 4 instead\n"); | |
4ed10779 JD |
1101 | val = 4; |
1102 | } | |
5d8d2f2b | 1103 | /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */ |
1da177e4 | 1104 | if (val == 3) |
8acf07c5 | 1105 | reg |= 1 << nr; |
4ed10779 | 1106 | else if (val == 4) |
8acf07c5 | 1107 | reg |= 8 << nr; |
5d8d2f2b GR |
1108 | else if (has_temp_peci(data, nr) && val == 6) |
1109 | reg |= (nr + 1) << 6; | |
19529784 GR |
1110 | else if (has_temp_old_peci(data, nr) && val == 6) |
1111 | extra |= 0x80; | |
8acf07c5 | 1112 | else if (val != 0) |
1da177e4 | 1113 | return -EINVAL; |
8acf07c5 JD |
1114 | |
1115 | mutex_lock(&data->update_lock); | |
1116 | data->sensor = reg; | |
19529784 | 1117 | data->extra = extra; |
b74f3fdd | 1118 | it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor); |
19529784 GR |
1119 | if (has_temp_old_peci(data, nr)) |
1120 | it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); | |
952a11ca | 1121 | data->valid = false; /* Force cache refresh */ |
9a61bf63 | 1122 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1123 | return count; |
1124 | } | |
1da177e4 | 1125 | |
2cece01f GR |
1126 | static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type, |
1127 | set_temp_type, 0); | |
1128 | static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type, | |
1129 | set_temp_type, 1); | |
1130 | static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type, | |
1131 | set_temp_type, 2); | |
1da177e4 | 1132 | |
f1bbe618 | 1133 | /* 6 Fans */ |
b99883dc JD |
1134 | |
1135 | static int pwm_mode(const struct it87_data *data, int nr) | |
1136 | { | |
f1bbe618 GR |
1137 | if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr))) |
1138 | return 0; /* Full speed */ | |
1139 | if (data->pwm_ctrl[nr] & 0x80) | |
1140 | return 2; /* Automatic mode */ | |
1141 | if ((data->type == it8603 || nr >= 3) && | |
1142 | data->pwm_duty[nr] == pwm_to_reg(data, 0xff)) | |
1143 | return 0; /* Full speed */ | |
1144 | ||
1145 | return 1; /* Manual mode */ | |
b99883dc JD |
1146 | } |
1147 | ||
20ad93d4 | 1148 | static ssize_t show_fan(struct device *dev, struct device_attribute *attr, |
e1169ba0 | 1149 | char *buf) |
1da177e4 | 1150 | { |
e1169ba0 GR |
1151 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
1152 | int nr = sattr->nr; | |
1153 | int index = sattr->index; | |
1154 | int speed; | |
1da177e4 | 1155 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 | 1156 | |
e1169ba0 GR |
1157 | speed = has_16bit_fans(data) ? |
1158 | FAN16_FROM_REG(data->fan[nr][index]) : | |
1159 | FAN_FROM_REG(data->fan[nr][index], | |
1160 | DIV_FROM_REG(data->fan_div[nr])); | |
1161 | return sprintf(buf, "%d\n", speed); | |
1da177e4 | 1162 | } |
e1169ba0 | 1163 | |
20ad93d4 | 1164 | static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, |
c962024e | 1165 | char *buf) |
1da177e4 | 1166 | { |
20ad93d4 | 1167 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
c962024e | 1168 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 JD |
1169 | int nr = sensor_attr->index; |
1170 | ||
48b2ae7f | 1171 | return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr])); |
1da177e4 | 1172 | } |
c962024e | 1173 | |
5f2dc798 | 1174 | static ssize_t show_pwm_enable(struct device *dev, |
c962024e | 1175 | struct device_attribute *attr, char *buf) |
1da177e4 | 1176 | { |
20ad93d4 | 1177 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
c962024e | 1178 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 JD |
1179 | int nr = sensor_attr->index; |
1180 | ||
b99883dc | 1181 | return sprintf(buf, "%d\n", pwm_mode(data, nr)); |
1da177e4 | 1182 | } |
c962024e | 1183 | |
20ad93d4 | 1184 | static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, |
c962024e | 1185 | char *buf) |
1da177e4 | 1186 | { |
20ad93d4 | 1187 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
c962024e | 1188 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 JD |
1189 | int nr = sensor_attr->index; |
1190 | ||
44c1bcd4 JD |
1191 | return sprintf(buf, "%d\n", |
1192 | pwm_from_reg(data, data->pwm_duty[nr])); | |
1da177e4 | 1193 | } |
c962024e | 1194 | |
f8d0c19a | 1195 | static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr, |
c962024e | 1196 | char *buf) |
f8d0c19a | 1197 | { |
60878bcf | 1198 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
f8d0c19a | 1199 | struct it87_data *data = it87_update_device(dev); |
60878bcf | 1200 | int nr = sensor_attr->index; |
f56c9c0a | 1201 | unsigned int freq; |
60878bcf GR |
1202 | int index; |
1203 | ||
1204 | if (has_pwm_freq2(data) && nr == 1) | |
1205 | index = (data->extra >> 4) & 0x07; | |
1206 | else | |
1207 | index = (data->fan_ctl >> 4) & 0x07; | |
f8d0c19a | 1208 | |
f56c9c0a GR |
1209 | freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128); |
1210 | ||
1211 | return sprintf(buf, "%u\n", freq); | |
f8d0c19a | 1212 | } |
e1169ba0 GR |
1213 | |
1214 | static ssize_t set_fan(struct device *dev, struct device_attribute *attr, | |
1215 | const char *buf, size_t count) | |
1da177e4 | 1216 | { |
e1169ba0 GR |
1217 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
1218 | int nr = sattr->nr; | |
1219 | int index = sattr->index; | |
20ad93d4 | 1220 | |
b74f3fdd | 1221 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 | 1222 | long val; |
7f999aa7 | 1223 | u8 reg; |
1da177e4 | 1224 | |
179c4fdb | 1225 | if (kstrtol(buf, 10, &val) < 0) |
f5f64501 JD |
1226 | return -EINVAL; |
1227 | ||
9a61bf63 | 1228 | mutex_lock(&data->update_lock); |
e1169ba0 GR |
1229 | |
1230 | if (has_16bit_fans(data)) { | |
1231 | data->fan[nr][index] = FAN16_TO_REG(val); | |
1232 | it87_write_value(data, IT87_REG_FAN_MIN[nr], | |
1233 | data->fan[nr][index] & 0xff); | |
1234 | it87_write_value(data, IT87_REG_FANX_MIN[nr], | |
1235 | data->fan[nr][index] >> 8); | |
1236 | } else { | |
1237 | reg = it87_read_value(data, IT87_REG_FAN_DIV); | |
1238 | switch (nr) { | |
1239 | case 0: | |
1240 | data->fan_div[nr] = reg & 0x07; | |
1241 | break; | |
1242 | case 1: | |
1243 | data->fan_div[nr] = (reg >> 3) & 0x07; | |
1244 | break; | |
1245 | case 2: | |
1246 | data->fan_div[nr] = (reg & 0x40) ? 3 : 1; | |
1247 | break; | |
1248 | } | |
1249 | data->fan[nr][index] = | |
1250 | FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); | |
1251 | it87_write_value(data, IT87_REG_FAN_MIN[nr], | |
1252 | data->fan[nr][index]); | |
07eab46d JD |
1253 | } |
1254 | ||
9a61bf63 | 1255 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1256 | return count; |
1257 | } | |
e1169ba0 | 1258 | |
20ad93d4 | 1259 | static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, |
c962024e | 1260 | const char *buf, size_t count) |
1da177e4 | 1261 | { |
20ad93d4 | 1262 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1263 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1264 | int nr = sensor_attr->index; |
f5f64501 | 1265 | unsigned long val; |
8ab4ec3e | 1266 | int min; |
1da177e4 LT |
1267 | u8 old; |
1268 | ||
179c4fdb | 1269 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 JD |
1270 | return -EINVAL; |
1271 | ||
9a61bf63 | 1272 | mutex_lock(&data->update_lock); |
b74f3fdd | 1273 | old = it87_read_value(data, IT87_REG_FAN_DIV); |
1da177e4 | 1274 | |
8ab4ec3e | 1275 | /* Save fan min limit */ |
e1169ba0 | 1276 | min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr])); |
1da177e4 LT |
1277 | |
1278 | switch (nr) { | |
1279 | case 0: | |
1280 | case 1: | |
1281 | data->fan_div[nr] = DIV_TO_REG(val); | |
1282 | break; | |
1283 | case 2: | |
1284 | if (val < 8) | |
1285 | data->fan_div[nr] = 1; | |
1286 | else | |
1287 | data->fan_div[nr] = 3; | |
1288 | } | |
1289 | val = old & 0x80; | |
1290 | val |= (data->fan_div[0] & 0x07); | |
1291 | val |= (data->fan_div[1] & 0x07) << 3; | |
1292 | if (data->fan_div[2] == 3) | |
1293 | val |= 0x1 << 6; | |
b74f3fdd | 1294 | it87_write_value(data, IT87_REG_FAN_DIV, val); |
1da177e4 | 1295 | |
8ab4ec3e | 1296 | /* Restore fan min limit */ |
e1169ba0 GR |
1297 | data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr])); |
1298 | it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]); | |
8ab4ec3e | 1299 | |
9a61bf63 | 1300 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1301 | return count; |
1302 | } | |
cccfc9c4 JD |
1303 | |
1304 | /* Returns 0 if OK, -EINVAL otherwise */ | |
1305 | static int check_trip_points(struct device *dev, int nr) | |
1306 | { | |
1307 | const struct it87_data *data = dev_get_drvdata(dev); | |
1308 | int i, err = 0; | |
1309 | ||
1310 | if (has_old_autopwm(data)) { | |
1311 | for (i = 0; i < 3; i++) { | |
1312 | if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) | |
1313 | err = -EINVAL; | |
1314 | } | |
1315 | for (i = 0; i < 2; i++) { | |
1316 | if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) | |
1317 | err = -EINVAL; | |
1318 | } | |
2cbb9c37 GR |
1319 | } else if (has_newer_autopwm(data)) { |
1320 | for (i = 1; i < 3; i++) { | |
1321 | if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) | |
1322 | err = -EINVAL; | |
1323 | } | |
cccfc9c4 JD |
1324 | } |
1325 | ||
1326 | if (err) { | |
1d9bcf6a GR |
1327 | dev_err(dev, |
1328 | "Inconsistent trip points, not switching to automatic mode\n"); | |
cccfc9c4 JD |
1329 | dev_err(dev, "Adjust the trip points and try again\n"); |
1330 | } | |
1331 | return err; | |
1332 | } | |
1333 | ||
c962024e GR |
1334 | static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, |
1335 | const char *buf, size_t count) | |
1da177e4 | 1336 | { |
20ad93d4 | 1337 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1338 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1339 | int nr = sensor_attr->index; |
f5f64501 | 1340 | long val; |
1da177e4 | 1341 | |
179c4fdb | 1342 | if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2) |
b99883dc JD |
1343 | return -EINVAL; |
1344 | ||
cccfc9c4 JD |
1345 | /* Check trip points before switching to automatic mode */ |
1346 | if (val == 2) { | |
1347 | if (check_trip_points(dev, nr) < 0) | |
1348 | return -EINVAL; | |
1349 | } | |
1350 | ||
9a61bf63 | 1351 | mutex_lock(&data->update_lock); |
1da177e4 LT |
1352 | |
1353 | if (val == 0) { | |
f1bbe618 GR |
1354 | if (nr < 3 && data->type != it8603) { |
1355 | int tmp; | |
1356 | /* make sure the fan is on when in on/off mode */ | |
1357 | tmp = it87_read_value(data, IT87_REG_FAN_CTL); | |
1358 | it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr)); | |
1359 | /* set on/off mode */ | |
1360 | data->fan_main_ctrl &= ~BIT(nr); | |
1361 | it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, | |
1362 | data->fan_main_ctrl); | |
1363 | } else { | |
4c7b8ca1 GR |
1364 | u8 ctrl; |
1365 | ||
f1bbe618 GR |
1366 | /* No on/off mode, set maximum pwm value */ |
1367 | data->pwm_duty[nr] = pwm_to_reg(data, 0xff); | |
1368 | it87_write_value(data, IT87_REG_PWM_DUTY[nr], | |
1369 | data->pwm_duty[nr]); | |
1370 | /* and set manual mode */ | |
4c7b8ca1 GR |
1371 | if (has_newer_autopwm(data)) { |
1372 | ctrl = (data->pwm_ctrl[nr] & 0x7c) | | |
1373 | data->pwm_temp_map[nr]; | |
1374 | } else { | |
1375 | ctrl = data->pwm_duty[nr]; | |
1376 | } | |
1377 | data->pwm_ctrl[nr] = ctrl; | |
1378 | it87_write_value(data, IT87_REG_PWM[nr], ctrl); | |
f1bbe618 | 1379 | } |
b99883dc | 1380 | } else { |
4c7b8ca1 GR |
1381 | u8 ctrl; |
1382 | ||
1383 | if (has_newer_autopwm(data)) { | |
1384 | ctrl = (data->pwm_ctrl[nr] & 0x7c) | | |
1385 | data->pwm_temp_map[nr]; | |
1386 | if (val != 1) | |
1387 | ctrl |= 0x80; | |
1388 | } else { | |
1389 | ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80); | |
1390 | } | |
1391 | data->pwm_ctrl[nr] = ctrl; | |
1392 | it87_write_value(data, IT87_REG_PWM[nr], ctrl); | |
c145d5c6 | 1393 | |
f1bbe618 | 1394 | if (data->type != it8603 && nr < 3) { |
c145d5c6 | 1395 | /* set SmartGuardian mode */ |
48b2ae7f | 1396 | data->fan_main_ctrl |= BIT(nr); |
c145d5c6 RM |
1397 | it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, |
1398 | data->fan_main_ctrl); | |
1399 | } | |
1da177e4 LT |
1400 | } |
1401 | ||
9a61bf63 | 1402 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1403 | return count; |
1404 | } | |
c962024e | 1405 | |
20ad93d4 | 1406 | static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, |
c962024e | 1407 | const char *buf, size_t count) |
1da177e4 | 1408 | { |
20ad93d4 | 1409 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1410 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1411 | int nr = sensor_attr->index; |
f5f64501 | 1412 | long val; |
1da177e4 | 1413 | |
179c4fdb | 1414 | if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) |
1da177e4 LT |
1415 | return -EINVAL; |
1416 | ||
9a61bf63 | 1417 | mutex_lock(&data->update_lock); |
82dbe987 | 1418 | it87_update_pwm_ctrl(data, nr); |
16b5dda2 | 1419 | if (has_newer_autopwm(data)) { |
4a0d71cf GR |
1420 | /* |
1421 | * If we are in automatic mode, the PWM duty cycle register | |
1422 | * is read-only so we can't write the value. | |
1423 | */ | |
6229cdb2 JD |
1424 | if (data->pwm_ctrl[nr] & 0x80) { |
1425 | mutex_unlock(&data->update_lock); | |
1426 | return -EBUSY; | |
1427 | } | |
1428 | data->pwm_duty[nr] = pwm_to_reg(data, val); | |
36c4d98a | 1429 | it87_write_value(data, IT87_REG_PWM_DUTY[nr], |
6229cdb2 JD |
1430 | data->pwm_duty[nr]); |
1431 | } else { | |
1432 | data->pwm_duty[nr] = pwm_to_reg(data, val); | |
4a0d71cf GR |
1433 | /* |
1434 | * If we are in manual mode, write the duty cycle immediately; | |
1435 | * otherwise, just store it for later use. | |
1436 | */ | |
6229cdb2 JD |
1437 | if (!(data->pwm_ctrl[nr] & 0x80)) { |
1438 | data->pwm_ctrl[nr] = data->pwm_duty[nr]; | |
36c4d98a | 1439 | it87_write_value(data, IT87_REG_PWM[nr], |
6229cdb2 JD |
1440 | data->pwm_ctrl[nr]); |
1441 | } | |
b99883dc | 1442 | } |
9a61bf63 | 1443 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1444 | return count; |
1445 | } | |
c962024e GR |
1446 | |
1447 | static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr, | |
1448 | const char *buf, size_t count) | |
f8d0c19a | 1449 | { |
60878bcf | 1450 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1451 | struct it87_data *data = dev_get_drvdata(dev); |
60878bcf | 1452 | int nr = sensor_attr->index; |
f5f64501 | 1453 | unsigned long val; |
f8d0c19a JD |
1454 | int i; |
1455 | ||
179c4fdb | 1456 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 | 1457 | return -EINVAL; |
f56c9c0a GR |
1458 | |
1459 | val = clamp_val(val, 0, 1000000); | |
1460 | val *= has_newer_autopwm(data) ? 256 : 128; | |
f5f64501 | 1461 | |
f8d0c19a JD |
1462 | /* Search for the nearest available frequency */ |
1463 | for (i = 0; i < 7; i++) { | |
c962024e | 1464 | if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2) |
f8d0c19a JD |
1465 | break; |
1466 | } | |
1467 | ||
1468 | mutex_lock(&data->update_lock); | |
60878bcf GR |
1469 | if (nr == 0) { |
1470 | data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f; | |
1471 | data->fan_ctl |= i << 4; | |
1472 | it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl); | |
1473 | } else { | |
1474 | data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f; | |
1475 | data->extra |= i << 4; | |
1476 | it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); | |
1477 | } | |
f8d0c19a JD |
1478 | mutex_unlock(&data->update_lock); |
1479 | ||
1480 | return count; | |
1481 | } | |
c962024e | 1482 | |
94ac7ee6 | 1483 | static ssize_t show_pwm_temp_map(struct device *dev, |
c962024e | 1484 | struct device_attribute *attr, char *buf) |
94ac7ee6 JD |
1485 | { |
1486 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
94ac7ee6 | 1487 | struct it87_data *data = it87_update_device(dev); |
c962024e | 1488 | int nr = sensor_attr->index; |
94ac7ee6 JD |
1489 | int map; |
1490 | ||
0624d861 GR |
1491 | map = data->pwm_temp_map[nr]; |
1492 | if (map >= 3) | |
1493 | map = 0; /* Should never happen */ | |
1494 | if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */ | |
1495 | map += 3; | |
1496 | ||
1497 | return sprintf(buf, "%d\n", (int)BIT(map)); | |
94ac7ee6 | 1498 | } |
c962024e | 1499 | |
94ac7ee6 | 1500 | static ssize_t set_pwm_temp_map(struct device *dev, |
c962024e GR |
1501 | struct device_attribute *attr, const char *buf, |
1502 | size_t count) | |
94ac7ee6 JD |
1503 | { |
1504 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
94ac7ee6 | 1505 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1506 | int nr = sensor_attr->index; |
94ac7ee6 JD |
1507 | long val; |
1508 | u8 reg; | |
1509 | ||
179c4fdb | 1510 | if (kstrtol(buf, 10, &val) < 0) |
94ac7ee6 JD |
1511 | return -EINVAL; |
1512 | ||
0624d861 GR |
1513 | if (nr >= 3) |
1514 | val -= 3; | |
1515 | ||
94ac7ee6 | 1516 | switch (val) { |
48b2ae7f | 1517 | case BIT(0): |
94ac7ee6 JD |
1518 | reg = 0x00; |
1519 | break; | |
48b2ae7f | 1520 | case BIT(1): |
94ac7ee6 JD |
1521 | reg = 0x01; |
1522 | break; | |
48b2ae7f | 1523 | case BIT(2): |
94ac7ee6 JD |
1524 | reg = 0x02; |
1525 | break; | |
1526 | default: | |
1527 | return -EINVAL; | |
1528 | } | |
1529 | ||
1530 | mutex_lock(&data->update_lock); | |
82dbe987 | 1531 | it87_update_pwm_ctrl(data, nr); |
94ac7ee6 | 1532 | data->pwm_temp_map[nr] = reg; |
4a0d71cf GR |
1533 | /* |
1534 | * If we are in automatic mode, write the temp mapping immediately; | |
1535 | * otherwise, just store it for later use. | |
1536 | */ | |
94ac7ee6 | 1537 | if (data->pwm_ctrl[nr] & 0x80) { |
4c7b8ca1 GR |
1538 | data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) | |
1539 | data->pwm_temp_map[nr]; | |
36c4d98a | 1540 | it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); |
94ac7ee6 JD |
1541 | } |
1542 | mutex_unlock(&data->update_lock); | |
1543 | return count; | |
1544 | } | |
1da177e4 | 1545 | |
c962024e GR |
1546 | static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr, |
1547 | char *buf) | |
4f3f51bc JD |
1548 | { |
1549 | struct it87_data *data = it87_update_device(dev); | |
1550 | struct sensor_device_attribute_2 *sensor_attr = | |
1551 | to_sensor_dev_attr_2(attr); | |
1552 | int nr = sensor_attr->nr; | |
1553 | int point = sensor_attr->index; | |
1554 | ||
44c1bcd4 JD |
1555 | return sprintf(buf, "%d\n", |
1556 | pwm_from_reg(data, data->auto_pwm[nr][point])); | |
4f3f51bc JD |
1557 | } |
1558 | ||
c962024e GR |
1559 | static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr, |
1560 | const char *buf, size_t count) | |
4f3f51bc JD |
1561 | { |
1562 | struct it87_data *data = dev_get_drvdata(dev); | |
1563 | struct sensor_device_attribute_2 *sensor_attr = | |
1564 | to_sensor_dev_attr_2(attr); | |
1565 | int nr = sensor_attr->nr; | |
1566 | int point = sensor_attr->index; | |
2cbb9c37 | 1567 | int regaddr; |
4f3f51bc JD |
1568 | long val; |
1569 | ||
179c4fdb | 1570 | if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) |
4f3f51bc JD |
1571 | return -EINVAL; |
1572 | ||
1573 | mutex_lock(&data->update_lock); | |
44c1bcd4 | 1574 | data->auto_pwm[nr][point] = pwm_to_reg(data, val); |
2cbb9c37 GR |
1575 | if (has_newer_autopwm(data)) |
1576 | regaddr = IT87_REG_AUTO_TEMP(nr, 3); | |
1577 | else | |
1578 | regaddr = IT87_REG_AUTO_PWM(nr, point); | |
1579 | it87_write_value(data, regaddr, data->auto_pwm[nr][point]); | |
1580 | mutex_unlock(&data->update_lock); | |
1581 | return count; | |
1582 | } | |
1583 | ||
1584 | static ssize_t show_auto_pwm_slope(struct device *dev, | |
1585 | struct device_attribute *attr, char *buf) | |
1586 | { | |
1587 | struct it87_data *data = it87_update_device(dev); | |
1588 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1589 | int nr = sensor_attr->index; | |
1590 | ||
1591 | return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f); | |
1592 | } | |
1593 | ||
1594 | static ssize_t set_auto_pwm_slope(struct device *dev, | |
1595 | struct device_attribute *attr, | |
1596 | const char *buf, size_t count) | |
1597 | { | |
1598 | struct it87_data *data = dev_get_drvdata(dev); | |
1599 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1600 | int nr = sensor_attr->index; | |
1601 | unsigned long val; | |
1602 | ||
1603 | if (kstrtoul(buf, 10, &val) < 0 || val > 127) | |
1604 | return -EINVAL; | |
1605 | ||
1606 | mutex_lock(&data->update_lock); | |
1607 | data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val; | |
1608 | it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4), | |
1609 | data->auto_pwm[nr][1]); | |
4f3f51bc JD |
1610 | mutex_unlock(&data->update_lock); |
1611 | return count; | |
1612 | } | |
1613 | ||
c962024e GR |
1614 | static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr, |
1615 | char *buf) | |
4f3f51bc JD |
1616 | { |
1617 | struct it87_data *data = it87_update_device(dev); | |
1618 | struct sensor_device_attribute_2 *sensor_attr = | |
1619 | to_sensor_dev_attr_2(attr); | |
1620 | int nr = sensor_attr->nr; | |
1621 | int point = sensor_attr->index; | |
2cbb9c37 GR |
1622 | int reg; |
1623 | ||
1624 | if (has_old_autopwm(data) || point) | |
1625 | reg = data->auto_temp[nr][point]; | |
1626 | else | |
1627 | reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f); | |
4f3f51bc | 1628 | |
2cbb9c37 | 1629 | return sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); |
4f3f51bc JD |
1630 | } |
1631 | ||
c962024e GR |
1632 | static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr, |
1633 | const char *buf, size_t count) | |
4f3f51bc JD |
1634 | { |
1635 | struct it87_data *data = dev_get_drvdata(dev); | |
1636 | struct sensor_device_attribute_2 *sensor_attr = | |
1637 | to_sensor_dev_attr_2(attr); | |
1638 | int nr = sensor_attr->nr; | |
1639 | int point = sensor_attr->index; | |
1640 | long val; | |
2cbb9c37 | 1641 | int reg; |
4f3f51bc | 1642 | |
179c4fdb | 1643 | if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) |
4f3f51bc JD |
1644 | return -EINVAL; |
1645 | ||
1646 | mutex_lock(&data->update_lock); | |
2cbb9c37 GR |
1647 | if (has_newer_autopwm(data) && !point) { |
1648 | reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); | |
1649 | reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0); | |
1650 | data->auto_temp[nr][0] = reg; | |
1651 | it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg); | |
1652 | } else { | |
1653 | reg = TEMP_TO_REG(val); | |
1654 | data->auto_temp[nr][point] = reg; | |
1655 | if (has_newer_autopwm(data)) | |
1656 | point--; | |
1657 | it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg); | |
1658 | } | |
4f3f51bc JD |
1659 | mutex_unlock(&data->update_lock); |
1660 | return count; | |
1661 | } | |
1662 | ||
e1169ba0 GR |
1663 | static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0); |
1664 | static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1665 | 0, 1); | |
1666 | static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div, | |
1667 | set_fan_div, 0); | |
1668 | ||
1669 | static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0); | |
1670 | static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1671 | 1, 1); | |
1672 | static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div, | |
1673 | set_fan_div, 1); | |
1674 | ||
1675 | static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0); | |
1676 | static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1677 | 2, 1); | |
1678 | static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div, | |
1679 | set_fan_div, 2); | |
1680 | ||
1681 | static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0); | |
1682 | static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1683 | 3, 1); | |
1da177e4 | 1684 | |
e1169ba0 GR |
1685 | static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0); |
1686 | static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1687 | 4, 1); | |
1da177e4 | 1688 | |
fa3f70d6 GR |
1689 | static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0); |
1690 | static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1691 | 5, 1); | |
1692 | ||
c4458db3 GR |
1693 | static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, |
1694 | show_pwm_enable, set_pwm_enable, 0); | |
1695 | static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0); | |
60878bcf GR |
1696 | static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, |
1697 | set_pwm_freq, 0); | |
5c391261 | 1698 | static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO, |
c4458db3 GR |
1699 | show_pwm_temp_map, set_pwm_temp_map, 0); |
1700 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR, | |
1701 | show_auto_pwm, set_auto_pwm, 0, 0); | |
1702 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR, | |
1703 | show_auto_pwm, set_auto_pwm, 0, 1); | |
1704 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR, | |
1705 | show_auto_pwm, set_auto_pwm, 0, 2); | |
1706 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO, | |
1707 | show_auto_pwm, NULL, 0, 3); | |
1708 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR, | |
1709 | show_auto_temp, set_auto_temp, 0, 1); | |
1710 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1711 | show_auto_temp, set_auto_temp, 0, 0); | |
1712 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1713 | show_auto_temp, set_auto_temp, 0, 2); | |
1714 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1715 | show_auto_temp, set_auto_temp, 0, 3); | |
1716 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR, | |
1717 | show_auto_temp, set_auto_temp, 0, 4); | |
2cbb9c37 GR |
1718 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR, |
1719 | show_auto_pwm, set_auto_pwm, 0, 0); | |
1720 | static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR, | |
1721 | show_auto_pwm_slope, set_auto_pwm_slope, 0); | |
c4458db3 GR |
1722 | |
1723 | static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR, | |
1724 | show_pwm_enable, set_pwm_enable, 1); | |
1725 | static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1); | |
60878bcf | 1726 | static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1); |
5c391261 | 1727 | static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO, |
c4458db3 GR |
1728 | show_pwm_temp_map, set_pwm_temp_map, 1); |
1729 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR, | |
1730 | show_auto_pwm, set_auto_pwm, 1, 0); | |
1731 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR, | |
1732 | show_auto_pwm, set_auto_pwm, 1, 1); | |
1733 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR, | |
1734 | show_auto_pwm, set_auto_pwm, 1, 2); | |
1735 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO, | |
1736 | show_auto_pwm, NULL, 1, 3); | |
1737 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR, | |
1738 | show_auto_temp, set_auto_temp, 1, 1); | |
1739 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1740 | show_auto_temp, set_auto_temp, 1, 0); | |
1741 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1742 | show_auto_temp, set_auto_temp, 1, 2); | |
1743 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1744 | show_auto_temp, set_auto_temp, 1, 3); | |
1745 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR, | |
1746 | show_auto_temp, set_auto_temp, 1, 4); | |
2cbb9c37 GR |
1747 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR, |
1748 | show_auto_pwm, set_auto_pwm, 1, 0); | |
1749 | static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR, | |
1750 | show_auto_pwm_slope, set_auto_pwm_slope, 1); | |
c4458db3 GR |
1751 | |
1752 | static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR, | |
1753 | show_pwm_enable, set_pwm_enable, 2); | |
1754 | static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2); | |
60878bcf | 1755 | static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2); |
5c391261 | 1756 | static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO, |
c4458db3 GR |
1757 | show_pwm_temp_map, set_pwm_temp_map, 2); |
1758 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR, | |
1759 | show_auto_pwm, set_auto_pwm, 2, 0); | |
1760 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR, | |
1761 | show_auto_pwm, set_auto_pwm, 2, 1); | |
1762 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR, | |
1763 | show_auto_pwm, set_auto_pwm, 2, 2); | |
1764 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO, | |
1765 | show_auto_pwm, NULL, 2, 3); | |
1766 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR, | |
1767 | show_auto_temp, set_auto_temp, 2, 1); | |
1768 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1769 | show_auto_temp, set_auto_temp, 2, 0); | |
1770 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1771 | show_auto_temp, set_auto_temp, 2, 2); | |
1772 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1773 | show_auto_temp, set_auto_temp, 2, 3); | |
1774 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR, | |
1775 | show_auto_temp, set_auto_temp, 2, 4); | |
2cbb9c37 GR |
1776 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR, |
1777 | show_auto_pwm, set_auto_pwm, 2, 0); | |
1778 | static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR, | |
1779 | show_auto_pwm_slope, set_auto_pwm_slope, 2); | |
1da177e4 | 1780 | |
36c4d98a GR |
1781 | static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR, |
1782 | show_pwm_enable, set_pwm_enable, 3); | |
1783 | static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3); | |
60878bcf | 1784 | static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3); |
5c391261 | 1785 | static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO, |
36c4d98a | 1786 | show_pwm_temp_map, set_pwm_temp_map, 3); |
2cbb9c37 GR |
1787 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR, |
1788 | show_auto_temp, set_auto_temp, 2, 1); | |
1789 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1790 | show_auto_temp, set_auto_temp, 2, 0); | |
1791 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1792 | show_auto_temp, set_auto_temp, 2, 2); | |
1793 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1794 | show_auto_temp, set_auto_temp, 2, 3); | |
1795 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR, | |
1796 | show_auto_pwm, set_auto_pwm, 3, 0); | |
1797 | static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR, | |
1798 | show_auto_pwm_slope, set_auto_pwm_slope, 3); | |
36c4d98a GR |
1799 | |
1800 | static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR, | |
1801 | show_pwm_enable, set_pwm_enable, 4); | |
1802 | static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4); | |
60878bcf | 1803 | static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4); |
5c391261 | 1804 | static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO, |
36c4d98a | 1805 | show_pwm_temp_map, set_pwm_temp_map, 4); |
2cbb9c37 GR |
1806 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR, |
1807 | show_auto_temp, set_auto_temp, 2, 1); | |
1808 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1809 | show_auto_temp, set_auto_temp, 2, 0); | |
1810 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1811 | show_auto_temp, set_auto_temp, 2, 2); | |
1812 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1813 | show_auto_temp, set_auto_temp, 2, 3); | |
1814 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR, | |
1815 | show_auto_pwm, set_auto_pwm, 4, 0); | |
1816 | static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR, | |
1817 | show_auto_pwm_slope, set_auto_pwm_slope, 4); | |
36c4d98a GR |
1818 | |
1819 | static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR, | |
1820 | show_pwm_enable, set_pwm_enable, 5); | |
1821 | static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5); | |
60878bcf | 1822 | static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5); |
5c391261 | 1823 | static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO, |
36c4d98a | 1824 | show_pwm_temp_map, set_pwm_temp_map, 5); |
2cbb9c37 GR |
1825 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR, |
1826 | show_auto_temp, set_auto_temp, 2, 1); | |
1827 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1828 | show_auto_temp, set_auto_temp, 2, 0); | |
1829 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1830 | show_auto_temp, set_auto_temp, 2, 2); | |
1831 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1832 | show_auto_temp, set_auto_temp, 2, 3); | |
1833 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR, | |
1834 | show_auto_pwm, set_auto_pwm, 5, 0); | |
1835 | static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR, | |
1836 | show_auto_pwm_slope, set_auto_pwm_slope, 5); | |
36c4d98a | 1837 | |
1da177e4 | 1838 | /* Alarms */ |
ddc64ae8 | 1839 | static ssize_t alarms_show(struct device *dev, struct device_attribute *attr, |
c962024e | 1840 | char *buf) |
1da177e4 LT |
1841 | { |
1842 | struct it87_data *data = it87_update_device(dev); | |
c962024e | 1843 | |
68188ba7 | 1844 | return sprintf(buf, "%u\n", data->alarms); |
1da177e4 | 1845 | } |
ddc64ae8 | 1846 | static DEVICE_ATTR_RO(alarms); |
1da177e4 | 1847 | |
0124dd78 | 1848 | static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, |
c962024e | 1849 | char *buf) |
0124dd78 | 1850 | { |
0124dd78 | 1851 | struct it87_data *data = it87_update_device(dev); |
c962024e GR |
1852 | int bitnr = to_sensor_dev_attr(attr)->index; |
1853 | ||
0124dd78 JD |
1854 | return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1); |
1855 | } | |
3d30f9e6 | 1856 | |
c962024e GR |
1857 | static ssize_t clear_intrusion(struct device *dev, |
1858 | struct device_attribute *attr, const char *buf, | |
1859 | size_t count) | |
3d30f9e6 JD |
1860 | { |
1861 | struct it87_data *data = dev_get_drvdata(dev); | |
3d30f9e6 | 1862 | int config; |
c962024e | 1863 | long val; |
3d30f9e6 | 1864 | |
179c4fdb | 1865 | if (kstrtol(buf, 10, &val) < 0 || val != 0) |
3d30f9e6 JD |
1866 | return -EINVAL; |
1867 | ||
1868 | mutex_lock(&data->update_lock); | |
1869 | config = it87_read_value(data, IT87_REG_CONFIG); | |
1870 | if (config < 0) { | |
1871 | count = config; | |
1872 | } else { | |
48b2ae7f | 1873 | config |= BIT(5); |
3d30f9e6 JD |
1874 | it87_write_value(data, IT87_REG_CONFIG, config); |
1875 | /* Invalidate cache to force re-read */ | |
952a11ca | 1876 | data->valid = false; |
3d30f9e6 JD |
1877 | } |
1878 | mutex_unlock(&data->update_lock); | |
1879 | ||
1880 | return count; | |
1881 | } | |
1882 | ||
0124dd78 JD |
1883 | static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8); |
1884 | static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9); | |
1885 | static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10); | |
1886 | static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11); | |
1887 | static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12); | |
1888 | static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13); | |
1889 | static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14); | |
1890 | static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15); | |
1891 | static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0); | |
1892 | static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1); | |
1893 | static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2); | |
1894 | static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3); | |
1895 | static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6); | |
fa3f70d6 | 1896 | static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7); |
0124dd78 JD |
1897 | static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); |
1898 | static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); | |
1899 | static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); | |
3d30f9e6 JD |
1900 | static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, |
1901 | show_alarm, clear_intrusion, 4); | |
0124dd78 | 1902 | |
d9b327c3 | 1903 | static ssize_t show_beep(struct device *dev, struct device_attribute *attr, |
c962024e | 1904 | char *buf) |
d9b327c3 | 1905 | { |
d9b327c3 | 1906 | struct it87_data *data = it87_update_device(dev); |
c962024e GR |
1907 | int bitnr = to_sensor_dev_attr(attr)->index; |
1908 | ||
d9b327c3 JD |
1909 | return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1); |
1910 | } | |
c962024e | 1911 | |
d9b327c3 | 1912 | static ssize_t set_beep(struct device *dev, struct device_attribute *attr, |
c962024e | 1913 | const char *buf, size_t count) |
d9b327c3 JD |
1914 | { |
1915 | int bitnr = to_sensor_dev_attr(attr)->index; | |
1916 | struct it87_data *data = dev_get_drvdata(dev); | |
1917 | long val; | |
1918 | ||
c962024e | 1919 | if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1)) |
d9b327c3 JD |
1920 | return -EINVAL; |
1921 | ||
1922 | mutex_lock(&data->update_lock); | |
1923 | data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); | |
1924 | if (val) | |
48b2ae7f | 1925 | data->beeps |= BIT(bitnr); |
d9b327c3 | 1926 | else |
48b2ae7f | 1927 | data->beeps &= ~BIT(bitnr); |
d9b327c3 JD |
1928 | it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps); |
1929 | mutex_unlock(&data->update_lock); | |
1930 | return count; | |
1931 | } | |
1932 | ||
1933 | static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR, | |
1934 | show_beep, set_beep, 1); | |
1935 | static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1); | |
1936 | static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1); | |
1937 | static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1); | |
1938 | static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1); | |
1939 | static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1); | |
1940 | static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1); | |
1941 | static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1); | |
1942 | /* fanX_beep writability is set later */ | |
1943 | static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0); | |
1944 | static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0); | |
1945 | static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0); | |
1946 | static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0); | |
1947 | static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0); | |
fa3f70d6 | 1948 | static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0); |
d9b327c3 JD |
1949 | static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, |
1950 | show_beep, set_beep, 2); | |
1951 | static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); | |
1952 | static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); | |
1953 | ||
ddc64ae8 JL |
1954 | static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, |
1955 | char *buf) | |
1da177e4 | 1956 | { |
90d6619a | 1957 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1958 | |
a7be58a1 | 1959 | return sprintf(buf, "%u\n", data->vrm); |
1da177e4 | 1960 | } |
c962024e | 1961 | |
ddc64ae8 JL |
1962 | static ssize_t vrm_store(struct device *dev, struct device_attribute *attr, |
1963 | const char *buf, size_t count) | |
1da177e4 | 1964 | { |
b74f3fdd | 1965 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 JD |
1966 | unsigned long val; |
1967 | ||
179c4fdb | 1968 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 | 1969 | return -EINVAL; |
1da177e4 | 1970 | |
1da177e4 LT |
1971 | data->vrm = val; |
1972 | ||
1973 | return count; | |
1974 | } | |
ddc64ae8 | 1975 | static DEVICE_ATTR_RW(vrm); |
1da177e4 | 1976 | |
ddc64ae8 JL |
1977 | static ssize_t cpu0_vid_show(struct device *dev, |
1978 | struct device_attribute *attr, char *buf) | |
1da177e4 LT |
1979 | { |
1980 | struct it87_data *data = it87_update_device(dev); | |
c962024e GR |
1981 | |
1982 | return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm)); | |
1da177e4 | 1983 | } |
ddc64ae8 | 1984 | static DEVICE_ATTR_RO(cpu0_vid); |
87808be4 | 1985 | |
738e5e05 | 1986 | static ssize_t show_label(struct device *dev, struct device_attribute *attr, |
c962024e | 1987 | char *buf) |
738e5e05 | 1988 | { |
3c4c4971 | 1989 | static const char * const labels[] = { |
738e5e05 JD |
1990 | "+5V", |
1991 | "5VSB", | |
1992 | "Vbat", | |
638c1c07 | 1993 | "AVCC", |
738e5e05 | 1994 | }; |
3c4c4971 | 1995 | static const char * const labels_it8721[] = { |
44c1bcd4 JD |
1996 | "+3.3V", |
1997 | "3VSB", | |
1998 | "Vbat", | |
638c1c07 | 1999 | "+3.3V", |
44c1bcd4 JD |
2000 | }; |
2001 | struct it87_data *data = dev_get_drvdata(dev); | |
738e5e05 | 2002 | int nr = to_sensor_dev_attr(attr)->index; |
ead80803 | 2003 | const char *label; |
738e5e05 | 2004 | |
a9eebd4f GR |
2005 | if (has_vin3_5v(data) && nr == 0) |
2006 | label = labels[0]; | |
dedbe4c1 | 2007 | else if (has_scaling(data)) |
ead80803 JM |
2008 | label = labels_it8721[nr]; |
2009 | else | |
2010 | label = labels[nr]; | |
2011 | ||
2012 | return sprintf(buf, "%s\n", label); | |
738e5e05 JD |
2013 | } |
2014 | static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0); | |
2015 | static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1); | |
2016 | static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2); | |
73055405 | 2017 | /* AVCC3 */ |
638c1c07 | 2018 | static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3); |
738e5e05 | 2019 | |
52929715 GR |
2020 | static umode_t it87_in_is_visible(struct kobject *kobj, |
2021 | struct attribute *attr, int index) | |
9172b5d1 | 2022 | { |
9d2227bb | 2023 | struct device *dev = kobj_to_dev(kobj); |
52929715 GR |
2024 | struct it87_data *data = dev_get_drvdata(dev); |
2025 | int i = index / 5; /* voltage index */ | |
2026 | int a = index % 5; /* attribute index */ | |
2027 | ||
f838aa26 | 2028 | if (index >= 40) { /* in8 and higher only have input attributes */ |
52929715 GR |
2029 | i = index - 40 + 8; |
2030 | a = 0; | |
2031 | } | |
2032 | ||
48b2ae7f | 2033 | if (!(data->has_in & BIT(i))) |
52929715 GR |
2034 | return 0; |
2035 | ||
2036 | if (a == 4 && !data->has_beep) | |
2037 | return 0; | |
2038 | ||
2039 | return attr->mode; | |
2040 | } | |
2041 | ||
2042 | static struct attribute *it87_attributes_in[] = { | |
87808be4 | 2043 | &sensor_dev_attr_in0_input.dev_attr.attr, |
87808be4 | 2044 | &sensor_dev_attr_in0_min.dev_attr.attr, |
87808be4 | 2045 | &sensor_dev_attr_in0_max.dev_attr.attr, |
0124dd78 | 2046 | &sensor_dev_attr_in0_alarm.dev_attr.attr, |
52929715 GR |
2047 | &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */ |
2048 | ||
9172b5d1 GR |
2049 | &sensor_dev_attr_in1_input.dev_attr.attr, |
2050 | &sensor_dev_attr_in1_min.dev_attr.attr, | |
2051 | &sensor_dev_attr_in1_max.dev_attr.attr, | |
0124dd78 | 2052 | &sensor_dev_attr_in1_alarm.dev_attr.attr, |
52929715 GR |
2053 | &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */ |
2054 | ||
9172b5d1 GR |
2055 | &sensor_dev_attr_in2_input.dev_attr.attr, |
2056 | &sensor_dev_attr_in2_min.dev_attr.attr, | |
2057 | &sensor_dev_attr_in2_max.dev_attr.attr, | |
0124dd78 | 2058 | &sensor_dev_attr_in2_alarm.dev_attr.attr, |
52929715 GR |
2059 | &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */ |
2060 | ||
9172b5d1 GR |
2061 | &sensor_dev_attr_in3_input.dev_attr.attr, |
2062 | &sensor_dev_attr_in3_min.dev_attr.attr, | |
2063 | &sensor_dev_attr_in3_max.dev_attr.attr, | |
0124dd78 | 2064 | &sensor_dev_attr_in3_alarm.dev_attr.attr, |
52929715 GR |
2065 | &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */ |
2066 | ||
9172b5d1 GR |
2067 | &sensor_dev_attr_in4_input.dev_attr.attr, |
2068 | &sensor_dev_attr_in4_min.dev_attr.attr, | |
2069 | &sensor_dev_attr_in4_max.dev_attr.attr, | |
0124dd78 | 2070 | &sensor_dev_attr_in4_alarm.dev_attr.attr, |
52929715 GR |
2071 | &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */ |
2072 | ||
9172b5d1 GR |
2073 | &sensor_dev_attr_in5_input.dev_attr.attr, |
2074 | &sensor_dev_attr_in5_min.dev_attr.attr, | |
2075 | &sensor_dev_attr_in5_max.dev_attr.attr, | |
0124dd78 | 2076 | &sensor_dev_attr_in5_alarm.dev_attr.attr, |
52929715 GR |
2077 | &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */ |
2078 | ||
9172b5d1 GR |
2079 | &sensor_dev_attr_in6_input.dev_attr.attr, |
2080 | &sensor_dev_attr_in6_min.dev_attr.attr, | |
2081 | &sensor_dev_attr_in6_max.dev_attr.attr, | |
0124dd78 | 2082 | &sensor_dev_attr_in6_alarm.dev_attr.attr, |
52929715 GR |
2083 | &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */ |
2084 | ||
9172b5d1 GR |
2085 | &sensor_dev_attr_in7_input.dev_attr.attr, |
2086 | &sensor_dev_attr_in7_min.dev_attr.attr, | |
2087 | &sensor_dev_attr_in7_max.dev_attr.attr, | |
0124dd78 | 2088 | &sensor_dev_attr_in7_alarm.dev_attr.attr, |
52929715 GR |
2089 | &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */ |
2090 | ||
2091 | &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */ | |
d5f3f6c8 JD |
2092 | &sensor_dev_attr_in9_input.dev_attr.attr, |
2093 | &sensor_dev_attr_in10_input.dev_attr.attr, | |
2094 | &sensor_dev_attr_in11_input.dev_attr.attr, | |
2095 | &sensor_dev_attr_in12_input.dev_attr.attr, | |
3c329263 | 2096 | NULL |
52929715 GR |
2097 | }; |
2098 | ||
2099 | static const struct attribute_group it87_group_in = { | |
2100 | .attrs = it87_attributes_in, | |
2101 | .is_visible = it87_in_is_visible, | |
9172b5d1 GR |
2102 | }; |
2103 | ||
87533770 GR |
2104 | static umode_t it87_temp_is_visible(struct kobject *kobj, |
2105 | struct attribute *attr, int index) | |
4573acbc | 2106 | { |
9d2227bb | 2107 | struct device *dev = kobj_to_dev(kobj); |
87533770 GR |
2108 | struct it87_data *data = dev_get_drvdata(dev); |
2109 | int i = index / 7; /* temperature index */ | |
2110 | int a = index % 7; /* attribute index */ | |
2111 | ||
cc18da79 GR |
2112 | if (index >= 21) { |
2113 | i = index - 21 + 3; | |
2114 | a = 0; | |
2115 | } | |
2116 | ||
48b2ae7f | 2117 | if (!(data->has_temp & BIT(i))) |
87533770 GR |
2118 | return 0; |
2119 | ||
2120 | if (a == 5 && !has_temp_offset(data)) | |
2121 | return 0; | |
2122 | ||
2123 | if (a == 6 && !data->has_beep) | |
2124 | return 0; | |
2125 | ||
2126 | return attr->mode; | |
2127 | } | |
2128 | ||
2129 | static struct attribute *it87_attributes_temp[] = { | |
87808be4 | 2130 | &sensor_dev_attr_temp1_input.dev_attr.attr, |
87808be4 | 2131 | &sensor_dev_attr_temp1_max.dev_attr.attr, |
87808be4 | 2132 | &sensor_dev_attr_temp1_min.dev_attr.attr, |
87808be4 | 2133 | &sensor_dev_attr_temp1_type.dev_attr.attr, |
0124dd78 | 2134 | &sensor_dev_attr_temp1_alarm.dev_attr.attr, |
87533770 GR |
2135 | &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */ |
2136 | &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */ | |
2137 | ||
cc18da79 | 2138 | &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */ |
4573acbc GR |
2139 | &sensor_dev_attr_temp2_max.dev_attr.attr, |
2140 | &sensor_dev_attr_temp2_min.dev_attr.attr, | |
2141 | &sensor_dev_attr_temp2_type.dev_attr.attr, | |
0124dd78 | 2142 | &sensor_dev_attr_temp2_alarm.dev_attr.attr, |
87533770 GR |
2143 | &sensor_dev_attr_temp2_offset.dev_attr.attr, |
2144 | &sensor_dev_attr_temp2_beep.dev_attr.attr, | |
2145 | ||
cc18da79 | 2146 | &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */ |
4573acbc GR |
2147 | &sensor_dev_attr_temp3_max.dev_attr.attr, |
2148 | &sensor_dev_attr_temp3_min.dev_attr.attr, | |
2149 | &sensor_dev_attr_temp3_type.dev_attr.attr, | |
0124dd78 | 2150 | &sensor_dev_attr_temp3_alarm.dev_attr.attr, |
87533770 GR |
2151 | &sensor_dev_attr_temp3_offset.dev_attr.attr, |
2152 | &sensor_dev_attr_temp3_beep.dev_attr.attr, | |
4573acbc | 2153 | |
cc18da79 GR |
2154 | &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */ |
2155 | &sensor_dev_attr_temp5_input.dev_attr.attr, | |
2156 | &sensor_dev_attr_temp6_input.dev_attr.attr, | |
87533770 | 2157 | NULL |
4573acbc | 2158 | }; |
87808be4 | 2159 | |
87533770 GR |
2160 | static const struct attribute_group it87_group_temp = { |
2161 | .attrs = it87_attributes_temp, | |
2162 | .is_visible = it87_temp_is_visible, | |
161d898a GR |
2163 | }; |
2164 | ||
d3766848 GR |
2165 | static umode_t it87_is_visible(struct kobject *kobj, |
2166 | struct attribute *attr, int index) | |
2167 | { | |
9d2227bb | 2168 | struct device *dev = kobj_to_dev(kobj); |
d3766848 GR |
2169 | struct it87_data *data = dev_get_drvdata(dev); |
2170 | ||
8638d0af | 2171 | if ((index == 2 || index == 3) && !data->has_vid) |
d3766848 GR |
2172 | return 0; |
2173 | ||
48b2ae7f | 2174 | if (index > 3 && !(data->in_internal & BIT(index - 4))) |
d3766848 GR |
2175 | return 0; |
2176 | ||
2177 | return attr->mode; | |
2178 | } | |
2179 | ||
4573acbc | 2180 | static struct attribute *it87_attributes[] = { |
87808be4 | 2181 | &dev_attr_alarms.attr, |
3d30f9e6 | 2182 | &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, |
8638d0af GR |
2183 | &dev_attr_vrm.attr, /* 2 */ |
2184 | &dev_attr_cpu0_vid.attr, /* 3 */ | |
2185 | &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */ | |
d3766848 GR |
2186 | &sensor_dev_attr_in7_label.dev_attr.attr, |
2187 | &sensor_dev_attr_in8_label.dev_attr.attr, | |
2188 | &sensor_dev_attr_in9_label.dev_attr.attr, | |
87808be4 JD |
2189 | NULL |
2190 | }; | |
2191 | ||
2192 | static const struct attribute_group it87_group = { | |
2193 | .attrs = it87_attributes, | |
d3766848 | 2194 | .is_visible = it87_is_visible, |
87808be4 JD |
2195 | }; |
2196 | ||
9a70ee81 GR |
2197 | static umode_t it87_fan_is_visible(struct kobject *kobj, |
2198 | struct attribute *attr, int index) | |
2199 | { | |
9d2227bb | 2200 | struct device *dev = kobj_to_dev(kobj); |
9a70ee81 GR |
2201 | struct it87_data *data = dev_get_drvdata(dev); |
2202 | int i = index / 5; /* fan index */ | |
2203 | int a = index % 5; /* attribute index */ | |
2204 | ||
2205 | if (index >= 15) { /* fan 4..6 don't have divisor attributes */ | |
2206 | i = (index - 15) / 4 + 3; | |
2207 | a = (index - 15) % 4; | |
2208 | } | |
2209 | ||
48b2ae7f | 2210 | if (!(data->has_fan & BIT(i))) |
9a70ee81 GR |
2211 | return 0; |
2212 | ||
2213 | if (a == 3) { /* beep */ | |
2214 | if (!data->has_beep) | |
2215 | return 0; | |
2216 | /* first fan beep attribute is writable */ | |
2217 | if (i == __ffs(data->has_fan)) | |
2218 | return attr->mode | S_IWUSR; | |
2219 | } | |
2220 | ||
2221 | if (a == 4 && has_16bit_fans(data)) /* divisor */ | |
2222 | return 0; | |
2223 | ||
2224 | return attr->mode; | |
2225 | } | |
2226 | ||
2227 | static struct attribute *it87_attributes_fan[] = { | |
e1169ba0 GR |
2228 | &sensor_dev_attr_fan1_input.dev_attr.attr, |
2229 | &sensor_dev_attr_fan1_min.dev_attr.attr, | |
723a0aa0 | 2230 | &sensor_dev_attr_fan1_alarm.dev_attr.attr, |
9a70ee81 GR |
2231 | &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */ |
2232 | &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */ | |
2233 | ||
e1169ba0 GR |
2234 | &sensor_dev_attr_fan2_input.dev_attr.attr, |
2235 | &sensor_dev_attr_fan2_min.dev_attr.attr, | |
723a0aa0 | 2236 | &sensor_dev_attr_fan2_alarm.dev_attr.attr, |
9a70ee81 GR |
2237 | &sensor_dev_attr_fan2_beep.dev_attr.attr, |
2238 | &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */ | |
2239 | ||
e1169ba0 GR |
2240 | &sensor_dev_attr_fan3_input.dev_attr.attr, |
2241 | &sensor_dev_attr_fan3_min.dev_attr.attr, | |
723a0aa0 | 2242 | &sensor_dev_attr_fan3_alarm.dev_attr.attr, |
9a70ee81 GR |
2243 | &sensor_dev_attr_fan3_beep.dev_attr.attr, |
2244 | &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */ | |
2245 | ||
2246 | &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */ | |
e1169ba0 | 2247 | &sensor_dev_attr_fan4_min.dev_attr.attr, |
723a0aa0 | 2248 | &sensor_dev_attr_fan4_alarm.dev_attr.attr, |
9a70ee81 GR |
2249 | &sensor_dev_attr_fan4_beep.dev_attr.attr, |
2250 | ||
2251 | &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */ | |
e1169ba0 | 2252 | &sensor_dev_attr_fan5_min.dev_attr.attr, |
723a0aa0 | 2253 | &sensor_dev_attr_fan5_alarm.dev_attr.attr, |
9a70ee81 GR |
2254 | &sensor_dev_attr_fan5_beep.dev_attr.attr, |
2255 | ||
2256 | &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */ | |
fa3f70d6 GR |
2257 | &sensor_dev_attr_fan6_min.dev_attr.attr, |
2258 | &sensor_dev_attr_fan6_alarm.dev_attr.attr, | |
9a70ee81 | 2259 | &sensor_dev_attr_fan6_beep.dev_attr.attr, |
fa3f70d6 | 2260 | NULL |
723a0aa0 | 2261 | }; |
87808be4 | 2262 | |
9a70ee81 GR |
2263 | static const struct attribute_group it87_group_fan = { |
2264 | .attrs = it87_attributes_fan, | |
2265 | .is_visible = it87_fan_is_visible, | |
723a0aa0 JD |
2266 | }; |
2267 | ||
5c391261 GR |
2268 | static umode_t it87_pwm_is_visible(struct kobject *kobj, |
2269 | struct attribute *attr, int index) | |
2270 | { | |
9d2227bb | 2271 | struct device *dev = kobj_to_dev(kobj); |
5c391261 GR |
2272 | struct it87_data *data = dev_get_drvdata(dev); |
2273 | int i = index / 4; /* pwm index */ | |
2274 | int a = index % 4; /* attribute index */ | |
2275 | ||
48b2ae7f | 2276 | if (!(data->has_pwm & BIT(i))) |
5c391261 GR |
2277 | return 0; |
2278 | ||
2cbb9c37 GR |
2279 | /* pwmX_auto_channels_temp is only writable if auto pwm is supported */ |
2280 | if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data))) | |
5c391261 GR |
2281 | return attr->mode | S_IWUSR; |
2282 | ||
2283 | /* pwm2_freq is writable if there are two pwm frequency selects */ | |
2284 | if (has_pwm_freq2(data) && i == 1 && a == 2) | |
2285 | return attr->mode | S_IWUSR; | |
2286 | ||
2287 | return attr->mode; | |
2288 | } | |
2289 | ||
2290 | static struct attribute *it87_attributes_pwm[] = { | |
87808be4 | 2291 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, |
87808be4 | 2292 | &sensor_dev_attr_pwm1.dev_attr.attr, |
60878bcf | 2293 | &sensor_dev_attr_pwm1_freq.dev_attr.attr, |
94ac7ee6 | 2294 | &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, |
5c391261 | 2295 | |
723a0aa0 JD |
2296 | &sensor_dev_attr_pwm2_enable.dev_attr.attr, |
2297 | &sensor_dev_attr_pwm2.dev_attr.attr, | |
60878bcf | 2298 | &sensor_dev_attr_pwm2_freq.dev_attr.attr, |
94ac7ee6 | 2299 | &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, |
5c391261 | 2300 | |
723a0aa0 JD |
2301 | &sensor_dev_attr_pwm3_enable.dev_attr.attr, |
2302 | &sensor_dev_attr_pwm3.dev_attr.attr, | |
60878bcf | 2303 | &sensor_dev_attr_pwm3_freq.dev_attr.attr, |
94ac7ee6 | 2304 | &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, |
5c391261 | 2305 | |
36c4d98a GR |
2306 | &sensor_dev_attr_pwm4_enable.dev_attr.attr, |
2307 | &sensor_dev_attr_pwm4.dev_attr.attr, | |
60878bcf | 2308 | &sensor_dev_attr_pwm4_freq.dev_attr.attr, |
36c4d98a | 2309 | &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr, |
5c391261 | 2310 | |
36c4d98a GR |
2311 | &sensor_dev_attr_pwm5_enable.dev_attr.attr, |
2312 | &sensor_dev_attr_pwm5.dev_attr.attr, | |
60878bcf | 2313 | &sensor_dev_attr_pwm5_freq.dev_attr.attr, |
36c4d98a | 2314 | &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr, |
5c391261 | 2315 | |
36c4d98a GR |
2316 | &sensor_dev_attr_pwm6_enable.dev_attr.attr, |
2317 | &sensor_dev_attr_pwm6.dev_attr.attr, | |
60878bcf | 2318 | &sensor_dev_attr_pwm6_freq.dev_attr.attr, |
36c4d98a | 2319 | &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr, |
5c391261 | 2320 | |
36c4d98a | 2321 | NULL |
5c391261 | 2322 | }; |
87808be4 | 2323 | |
5c391261 GR |
2324 | static const struct attribute_group it87_group_pwm = { |
2325 | .attrs = it87_attributes_pwm, | |
2326 | .is_visible = it87_pwm_is_visible, | |
2327 | }; | |
2328 | ||
2329 | static umode_t it87_auto_pwm_is_visible(struct kobject *kobj, | |
2330 | struct attribute *attr, int index) | |
60878bcf | 2331 | { |
9d2227bb | 2332 | struct device *dev = kobj_to_dev(kobj); |
60878bcf | 2333 | struct it87_data *data = dev_get_drvdata(dev); |
2cbb9c37 GR |
2334 | int i = index / 11; /* pwm index */ |
2335 | int a = index % 11; /* attribute index */ | |
2336 | ||
2337 | if (index >= 33) { /* pwm 4..6 */ | |
2338 | i = (index - 33) / 6 + 3; | |
2339 | a = (index - 33) % 6 + 4; | |
2340 | } | |
60878bcf | 2341 | |
48b2ae7f | 2342 | if (!(data->has_pwm & BIT(i))) |
5c391261 | 2343 | return 0; |
60878bcf | 2344 | |
2cbb9c37 GR |
2345 | if (has_newer_autopwm(data)) { |
2346 | if (a < 4) /* no auto point pwm */ | |
2347 | return 0; | |
2348 | if (a == 8) /* no auto_point4 */ | |
2349 | return 0; | |
2350 | } | |
2351 | if (has_old_autopwm(data)) { | |
2352 | if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */ | |
2353 | return 0; | |
2354 | } | |
2355 | ||
60878bcf GR |
2356 | return attr->mode; |
2357 | } | |
2358 | ||
5c391261 | 2359 | static struct attribute *it87_attributes_auto_pwm[] = { |
4f3f51bc JD |
2360 | &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, |
2361 | &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, | |
2362 | &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr, | |
2363 | &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr, | |
2364 | &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, | |
2365 | &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, | |
2366 | &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, | |
2367 | &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, | |
2368 | &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, | |
2cbb9c37 GR |
2369 | &sensor_dev_attr_pwm1_auto_start.dev_attr.attr, |
2370 | &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr, | |
5c391261 | 2371 | |
2cbb9c37 | 2372 | &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */ |
4f3f51bc JD |
2373 | &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, |
2374 | &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr, | |
2375 | &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr, | |
2376 | &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr, | |
2377 | &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr, | |
2378 | &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr, | |
2379 | &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr, | |
2380 | &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr, | |
2cbb9c37 GR |
2381 | &sensor_dev_attr_pwm2_auto_start.dev_attr.attr, |
2382 | &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr, | |
5c391261 | 2383 | |
2cbb9c37 | 2384 | &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */ |
4f3f51bc JD |
2385 | &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, |
2386 | &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr, | |
2387 | &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr, | |
2388 | &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr, | |
2389 | &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr, | |
2390 | &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr, | |
2391 | &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr, | |
2392 | &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr, | |
2cbb9c37 GR |
2393 | &sensor_dev_attr_pwm3_auto_start.dev_attr.attr, |
2394 | &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr, | |
2395 | ||
2396 | &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */ | |
2397 | &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr, | |
2398 | &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr, | |
2399 | &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr, | |
2400 | &sensor_dev_attr_pwm4_auto_start.dev_attr.attr, | |
2401 | &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr, | |
2402 | ||
2403 | &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr, | |
2404 | &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr, | |
2405 | &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr, | |
2406 | &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr, | |
2407 | &sensor_dev_attr_pwm5_auto_start.dev_attr.attr, | |
2408 | &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr, | |
2409 | ||
2410 | &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr, | |
2411 | &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr, | |
2412 | &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr, | |
2413 | &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr, | |
2414 | &sensor_dev_attr_pwm6_auto_start.dev_attr.attr, | |
2415 | &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr, | |
4f3f51bc | 2416 | |
5c391261 GR |
2417 | NULL, |
2418 | }; | |
2419 | ||
2420 | static const struct attribute_group it87_group_auto_pwm = { | |
2421 | .attrs = it87_attributes_auto_pwm, | |
2422 | .is_visible = it87_auto_pwm_is_visible, | |
4f3f51bc JD |
2423 | }; |
2424 | ||
2d8672c5 | 2425 | /* SuperIO detection - will change isa_address if a chip is found */ |
3c2e3512 | 2426 | static int __init it87_find(int sioaddr, unsigned short *address, |
2a64e9d4 | 2427 | struct it87_sio_data *sio_data, int chip_cnt) |
1da177e4 | 2428 | { |
5b0380c9 | 2429 | int err; |
b74f3fdd | 2430 | u16 chip_type; |
4119693b | 2431 | const struct it87_devices *config = NULL; |
1da177e4 | 2432 | |
3c2e3512 | 2433 | err = superio_enter(sioaddr); |
5b0380c9 NG |
2434 | if (err) |
2435 | return err; | |
2436 | ||
2437 | err = -ENODEV; | |
b3b19931 AK |
2438 | chip_type = superio_inw(sioaddr, DEVID); |
2439 | /* check first for a valid chip before forcing chip id */ | |
2440 | if (chip_type == 0xffff) | |
2441 | goto exit; | |
2442 | ||
2a64e9d4 FC |
2443 | if (force_id_cnt == 1) { |
2444 | /* If only one value given use for all chips */ | |
2445 | if (force_id[0]) | |
2446 | chip_type = force_id[0]; | |
2447 | } else if (force_id[chip_cnt]) | |
2448 | chip_type = force_id[chip_cnt]; | |
b74f3fdd | 2449 | |
2450 | switch (chip_type) { | |
2451 | case IT8705F_DEVID: | |
2452 | sio_data->type = it87; | |
2453 | break; | |
2454 | case IT8712F_DEVID: | |
2455 | sio_data->type = it8712; | |
2456 | break; | |
2457 | case IT8716F_DEVID: | |
2458 | case IT8726F_DEVID: | |
2459 | sio_data->type = it8716; | |
2460 | break; | |
2461 | case IT8718F_DEVID: | |
2462 | sio_data->type = it8718; | |
2463 | break; | |
b4da93e4 JMS |
2464 | case IT8720F_DEVID: |
2465 | sio_data->type = it8720; | |
2466 | break; | |
44c1bcd4 JD |
2467 | case IT8721F_DEVID: |
2468 | sio_data->type = it8721; | |
2469 | break; | |
16b5dda2 JD |
2470 | case IT8728F_DEVID: |
2471 | sio_data->type = it8728; | |
2472 | break; | |
ead80803 JM |
2473 | case IT8732F_DEVID: |
2474 | sio_data->type = it8732; | |
2475 | break; | |
e531ffc0 GR |
2476 | case IT8792E_DEVID: |
2477 | sio_data->type = it8792; | |
2478 | break; | |
b0636707 GR |
2479 | case IT8771E_DEVID: |
2480 | sio_data->type = it8771; | |
2481 | break; | |
2482 | case IT8772E_DEVID: | |
2483 | sio_data->type = it8772; | |
2484 | break; | |
7bc32d29 GR |
2485 | case IT8781F_DEVID: |
2486 | sio_data->type = it8781; | |
2487 | break; | |
0531d98b GR |
2488 | case IT8782F_DEVID: |
2489 | sio_data->type = it8782; | |
2490 | break; | |
2491 | case IT8783E_DEVID: | |
2492 | sio_data->type = it8783; | |
2493 | break; | |
a0c1424a TL |
2494 | case IT8786E_DEVID: |
2495 | sio_data->type = it8786; | |
2496 | break; | |
4ee07157 GR |
2497 | case IT8790E_DEVID: |
2498 | sio_data->type = it8790; | |
2499 | break; | |
7183ae8c | 2500 | case IT8603E_DEVID: |
574e9bd8 | 2501 | case IT8623E_DEVID: |
c145d5c6 RM |
2502 | sio_data->type = it8603; |
2503 | break; | |
3ba9d977 GR |
2504 | case IT8620E_DEVID: |
2505 | sio_data->type = it8620; | |
2506 | break; | |
8af1abae GR |
2507 | case IT8622E_DEVID: |
2508 | sio_data->type = it8622; | |
2509 | break; | |
71a9c232 GR |
2510 | case IT8628E_DEVID: |
2511 | sio_data->type = it8628; | |
2512 | break; | |
d44cb4cd FC |
2513 | case IT87952E_DEVID: |
2514 | sio_data->type = it87952; | |
2515 | break; | |
b74f3fdd | 2516 | case 0xffff: /* No device at all */ |
2517 | goto exit; | |
2518 | default: | |
a8ca1037 | 2519 | pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type); |
b74f3fdd | 2520 | goto exit; |
2521 | } | |
1da177e4 | 2522 | |
4119693b FC |
2523 | config = &it87_devices[sio_data->type]; |
2524 | ||
3c2e3512 GR |
2525 | superio_select(sioaddr, PME); |
2526 | if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) { | |
f09c7965 FC |
2527 | pr_info("Device (chip %s ioreg 0x%x) not activated, skipping\n", |
2528 | config->model, sioaddr); | |
1da177e4 LT |
2529 | goto exit; |
2530 | } | |
2531 | ||
3c2e3512 | 2532 | *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1); |
1da177e4 | 2533 | if (*address == 0) { |
f09c7965 FC |
2534 | pr_info("Base address not set (chip %s ioreg 0x%x), skipping\n", |
2535 | config->model, sioaddr); | |
1da177e4 LT |
2536 | goto exit; |
2537 | } | |
2538 | ||
2539 | err = 0; | |
384548e5 | 2540 | sio_data->sioaddr = sioaddr; |
3c2e3512 | 2541 | sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f; |
1f21531d FC |
2542 | pr_info("Found %s chip at 0x%x, revision %d\n", |
2543 | it87_devices[sio_data->type].model, | |
a0c1424a | 2544 | *address, sio_data->revision); |
1da177e4 | 2545 | |
7f5726c3 | 2546 | /* in7 (VSB or VCCH5V) is always internal on some chips */ |
f83a9cb6 | 2547 | if (has_in7_internal(config)) |
48b2ae7f | 2548 | sio_data->internal |= BIT(1); |
7f5726c3 | 2549 | |
738e5e05 | 2550 | /* in8 (Vbat) is always internal */ |
48b2ae7f | 2551 | sio_data->internal |= BIT(2); |
7f5726c3 | 2552 | |
73055405 GR |
2553 | /* in9 (AVCC3), always internal if supported */ |
2554 | if (has_avcc3(config)) | |
48b2ae7f | 2555 | sio_data->internal |= BIT(3); /* in9 is AVCC */ |
73055405 | 2556 | else |
48b2ae7f | 2557 | sio_data->skip_in |= BIT(9); |
738e5e05 | 2558 | |
638c1c07 | 2559 | if (!has_five_pwm(config)) |
48b2ae7f | 2560 | sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5); |
638c1c07 GR |
2561 | else if (!has_six_pwm(config)) |
2562 | sio_data->skip_pwm |= BIT(5); | |
36c4d98a | 2563 | |
f83a9cb6 | 2564 | if (!has_vid(config)) |
895ff267 | 2565 | sio_data->skip_vid = 1; |
d9b327c3 | 2566 | |
32dd7c40 GR |
2567 | /* Read GPIO config and VID value from LDN 7 (GPIO) */ |
2568 | if (sio_data->type == it87) { | |
d9b327c3 | 2569 | /* The IT8705F has a different LD number for GPIO */ |
3c2e3512 GR |
2570 | superio_select(sioaddr, 5); |
2571 | sio_data->beep_pin = superio_inb(sioaddr, | |
2572 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
0531d98b | 2573 | } else if (sio_data->type == it8783) { |
088ce2ac | 2574 | int reg25, reg27, reg2a, reg2c, regef; |
0531d98b | 2575 | |
3c2e3512 | 2576 | superio_select(sioaddr, GPIO); |
0531d98b | 2577 | |
3c2e3512 GR |
2578 | reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); |
2579 | reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); | |
2580 | reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG); | |
2581 | reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG); | |
2582 | regef = superio_inb(sioaddr, IT87_SIO_SPI_REG); | |
0531d98b | 2583 | |
0531d98b | 2584 | /* Check if fan3 is there or not */ |
48b2ae7f GR |
2585 | if ((reg27 & BIT(0)) || !(reg2c & BIT(2))) |
2586 | sio_data->skip_fan |= BIT(2); | |
c962024e GR |
2587 | if ((reg25 & BIT(4)) || |
2588 | (!(reg2a & BIT(1)) && (regef & BIT(0)))) | |
48b2ae7f | 2589 | sio_data->skip_pwm |= BIT(2); |
0531d98b GR |
2590 | |
2591 | /* Check if fan2 is there or not */ | |
48b2ae7f GR |
2592 | if (reg27 & BIT(7)) |
2593 | sio_data->skip_fan |= BIT(1); | |
2594 | if (reg27 & BIT(3)) | |
2595 | sio_data->skip_pwm |= BIT(1); | |
0531d98b GR |
2596 | |
2597 | /* VIN5 */ | |
48b2ae7f GR |
2598 | if ((reg27 & BIT(0)) || (reg2c & BIT(2))) |
2599 | sio_data->skip_in |= BIT(5); /* No VIN5 */ | |
0531d98b GR |
2600 | |
2601 | /* VIN6 */ | |
48b2ae7f GR |
2602 | if (reg27 & BIT(1)) |
2603 | sio_data->skip_in |= BIT(6); /* No VIN6 */ | |
0531d98b GR |
2604 | |
2605 | /* | |
2606 | * VIN7 | |
2607 | * Does not depend on bit 2 of Reg2C, contrary to datasheet. | |
2608 | */ | |
48b2ae7f | 2609 | if (reg27 & BIT(2)) { |
9172b5d1 GR |
2610 | /* |
2611 | * The data sheet is a bit unclear regarding the | |
2612 | * internal voltage divider for VCCH5V. It says | |
2613 | * "This bit enables and switches VIN7 (pin 91) to the | |
2614 | * internal voltage divider for VCCH5V". | |
2615 | * This is different to other chips, where the internal | |
2616 | * voltage divider would connect VIN7 to an internal | |
2617 | * voltage source. Maybe that is the case here as well. | |
2618 | * | |
2619 | * Since we don't know for sure, re-route it if that is | |
2620 | * not the case, and ask the user to report if the | |
2621 | * resulting voltage is sane. | |
2622 | */ | |
48b2ae7f GR |
2623 | if (!(reg2c & BIT(1))) { |
2624 | reg2c |= BIT(1); | |
3c2e3512 GR |
2625 | superio_outb(sioaddr, IT87_SIO_PINX2_REG, |
2626 | reg2c); | |
384548e5 | 2627 | sio_data->need_in7_reroute = true; |
9172b5d1 GR |
2628 | pr_notice("Routing internal VCCH5V to in7.\n"); |
2629 | } | |
2630 | pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n"); | |
2631 | pr_notice("Please report if it displays a reasonable voltage.\n"); | |
2632 | } | |
0531d98b | 2633 | |
48b2ae7f GR |
2634 | if (reg2c & BIT(0)) |
2635 | sio_data->internal |= BIT(0); | |
2636 | if (reg2c & BIT(1)) | |
2637 | sio_data->internal |= BIT(1); | |
0531d98b | 2638 | |
3c2e3512 GR |
2639 | sio_data->beep_pin = superio_inb(sioaddr, |
2640 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
c145d5c6 RM |
2641 | } else if (sio_data->type == it8603) { |
2642 | int reg27, reg29; | |
2643 | ||
3c2e3512 | 2644 | superio_select(sioaddr, GPIO); |
0531d98b | 2645 | |
3c2e3512 | 2646 | reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); |
c145d5c6 RM |
2647 | |
2648 | /* Check if fan3 is there or not */ | |
48b2ae7f GR |
2649 | if (reg27 & BIT(6)) |
2650 | sio_data->skip_pwm |= BIT(2); | |
2651 | if (reg27 & BIT(7)) | |
2652 | sio_data->skip_fan |= BIT(2); | |
c145d5c6 RM |
2653 | |
2654 | /* Check if fan2 is there or not */ | |
3c2e3512 | 2655 | reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); |
48b2ae7f GR |
2656 | if (reg29 & BIT(1)) |
2657 | sio_data->skip_pwm |= BIT(1); | |
2658 | if (reg29 & BIT(2)) | |
2659 | sio_data->skip_fan |= BIT(1); | |
c145d5c6 | 2660 | |
48b2ae7f GR |
2661 | sio_data->skip_in |= BIT(5); /* No VIN5 */ |
2662 | sio_data->skip_in |= BIT(6); /* No VIN6 */ | |
c145d5c6 | 2663 | |
3c2e3512 GR |
2664 | sio_data->beep_pin = superio_inb(sioaddr, |
2665 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
71a9c232 | 2666 | } else if (sio_data->type == it8620 || sio_data->type == it8628) { |
3ba9d977 GR |
2667 | int reg; |
2668 | ||
3c2e3512 | 2669 | superio_select(sioaddr, GPIO); |
3ba9d977 | 2670 | |
36c4d98a | 2671 | /* Check for pwm5 */ |
3c2e3512 | 2672 | reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); |
48b2ae7f GR |
2673 | if (reg & BIT(6)) |
2674 | sio_data->skip_pwm |= BIT(4); | |
36c4d98a | 2675 | |
3ba9d977 | 2676 | /* Check for fan4, fan5 */ |
3c2e3512 | 2677 | reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); |
48b2ae7f GR |
2678 | if (!(reg & BIT(5))) |
2679 | sio_data->skip_fan |= BIT(3); | |
2680 | if (!(reg & BIT(4))) | |
2681 | sio_data->skip_fan |= BIT(4); | |
3ba9d977 GR |
2682 | |
2683 | /* Check for pwm3, fan3 */ | |
3c2e3512 | 2684 | reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); |
48b2ae7f GR |
2685 | if (reg & BIT(6)) |
2686 | sio_data->skip_pwm |= BIT(2); | |
2687 | if (reg & BIT(7)) | |
2688 | sio_data->skip_fan |= BIT(2); | |
3ba9d977 | 2689 | |
36c4d98a | 2690 | /* Check for pwm4 */ |
3c2e3512 | 2691 | reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); |
d66777ca | 2692 | if (reg & BIT(2)) |
48b2ae7f | 2693 | sio_data->skip_pwm |= BIT(3); |
36c4d98a | 2694 | |
3ba9d977 | 2695 | /* Check for pwm2, fan2 */ |
3c2e3512 | 2696 | reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); |
48b2ae7f GR |
2697 | if (reg & BIT(1)) |
2698 | sio_data->skip_pwm |= BIT(1); | |
2699 | if (reg & BIT(2)) | |
2700 | sio_data->skip_fan |= BIT(1); | |
36c4d98a | 2701 | /* Check for pwm6, fan6 */ |
48b2ae7f GR |
2702 | if (!(reg & BIT(7))) { |
2703 | sio_data->skip_pwm |= BIT(5); | |
2704 | sio_data->skip_fan |= BIT(5); | |
36c4d98a | 2705 | } |
3ba9d977 | 2706 | |
638c1c07 GR |
2707 | /* Check if AVCC is on VIN3 */ |
2708 | reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); | |
2709 | if (reg & BIT(0)) | |
2710 | sio_data->internal |= BIT(0); | |
2711 | else | |
2712 | sio_data->skip_in |= BIT(9); | |
2713 | ||
2714 | sio_data->beep_pin = superio_inb(sioaddr, | |
2715 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
2716 | } else if (sio_data->type == it8622) { | |
2717 | int reg; | |
2718 | ||
2719 | superio_select(sioaddr, GPIO); | |
2720 | ||
2721 | /* Check for pwm4, fan4 */ | |
2722 | reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); | |
2723 | if (reg & BIT(6)) | |
2724 | sio_data->skip_fan |= BIT(3); | |
2725 | if (reg & BIT(5)) | |
2726 | sio_data->skip_pwm |= BIT(3); | |
2727 | ||
2728 | /* Check for pwm3, fan3, pwm5, fan5 */ | |
2729 | reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); | |
2730 | if (reg & BIT(6)) | |
2731 | sio_data->skip_pwm |= BIT(2); | |
2732 | if (reg & BIT(7)) | |
2733 | sio_data->skip_fan |= BIT(2); | |
2734 | if (reg & BIT(3)) | |
2735 | sio_data->skip_pwm |= BIT(4); | |
2736 | if (reg & BIT(1)) | |
2737 | sio_data->skip_fan |= BIT(4); | |
2738 | ||
2739 | /* Check for pwm2, fan2 */ | |
2740 | reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); | |
2741 | if (reg & BIT(1)) | |
2742 | sio_data->skip_pwm |= BIT(1); | |
2743 | if (reg & BIT(2)) | |
2744 | sio_data->skip_fan |= BIT(1); | |
2745 | ||
2746 | /* Check for AVCC */ | |
2747 | reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); | |
2748 | if (!(reg & BIT(0))) | |
2749 | sio_data->skip_in |= BIT(9); | |
2750 | ||
3c2e3512 GR |
2751 | sio_data->beep_pin = superio_inb(sioaddr, |
2752 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
895ff267 | 2753 | } else { |
87673dd7 | 2754 | int reg; |
9172b5d1 | 2755 | bool uart6; |
87673dd7 | 2756 | |
3c2e3512 | 2757 | superio_select(sioaddr, GPIO); |
44c1bcd4 | 2758 | |
a0df926d GR |
2759 | /* Check for fan4, fan5 */ |
2760 | if (has_five_fans(config)) { | |
2761 | reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); | |
2762 | switch (sio_data->type) { | |
2763 | case it8718: | |
2764 | if (reg & BIT(5)) | |
2765 | sio_data->skip_fan |= BIT(3); | |
2766 | if (reg & BIT(4)) | |
2767 | sio_data->skip_fan |= BIT(4); | |
2768 | break; | |
2769 | case it8720: | |
2770 | case it8721: | |
2771 | case it8728: | |
2772 | if (!(reg & BIT(5))) | |
2773 | sio_data->skip_fan |= BIT(3); | |
2774 | if (!(reg & BIT(4))) | |
2775 | sio_data->skip_fan |= BIT(4); | |
2776 | break; | |
2777 | default: | |
2778 | break; | |
2779 | } | |
2780 | } | |
2781 | ||
3c2e3512 | 2782 | reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); |
32dd7c40 | 2783 | if (!sio_data->skip_vid) { |
44c1bcd4 JD |
2784 | /* We need at least 4 VID pins */ |
2785 | if (reg & 0x0f) { | |
a8ca1037 | 2786 | pr_info("VID is disabled (pins used for GPIO)\n"); |
44c1bcd4 JD |
2787 | sio_data->skip_vid = 1; |
2788 | } | |
895ff267 JD |
2789 | } |
2790 | ||
591ec650 | 2791 | /* Check if fan3 is there or not */ |
48b2ae7f GR |
2792 | if (reg & BIT(6)) |
2793 | sio_data->skip_pwm |= BIT(2); | |
2794 | if (reg & BIT(7)) | |
2795 | sio_data->skip_fan |= BIT(2); | |
591ec650 JD |
2796 | |
2797 | /* Check if fan2 is there or not */ | |
3c2e3512 | 2798 | reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); |
48b2ae7f GR |
2799 | if (reg & BIT(1)) |
2800 | sio_data->skip_pwm |= BIT(1); | |
2801 | if (reg & BIT(2)) | |
2802 | sio_data->skip_fan |= BIT(1); | |
591ec650 | 2803 | |
c962024e GR |
2804 | if ((sio_data->type == it8718 || sio_data->type == it8720) && |
2805 | !(sio_data->skip_vid)) | |
3c2e3512 GR |
2806 | sio_data->vid_value = superio_inb(sioaddr, |
2807 | IT87_SIO_VID_REG); | |
87673dd7 | 2808 | |
3c2e3512 | 2809 | reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); |
9172b5d1 | 2810 | |
48b2ae7f | 2811 | uart6 = sio_data->type == it8782 && (reg & BIT(2)); |
9172b5d1 | 2812 | |
436cad2a | 2813 | /* |
557cbf49 | 2814 | * The IT8720F has no VIN7 pin, so VCCH5V should always be |
436cad2a JD |
2815 | * routed internally to VIN7 with an internal divider. |
2816 | * Curiously, there still is a configuration bit to control | |
2817 | * this, which means it can be set incorrectly. And even | |
2818 | * more curiously, many boards out there are improperly | |
2819 | * configured, even though the IT8720F datasheet claims | |
557cbf49 | 2820 | * that the internal routing of VCCH5V to VIN7 is the default |
436cad2a | 2821 | * setting. So we force the internal routing in this case. |
0531d98b GR |
2822 | * |
2823 | * On IT8782F, VIN7 is multiplexed with one of the UART6 pins. | |
9172b5d1 GR |
2824 | * If UART6 is enabled, re-route VIN7 to the internal divider |
2825 | * if that is not already the case. | |
436cad2a | 2826 | */ |
48b2ae7f GR |
2827 | if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { |
2828 | reg |= BIT(1); | |
3c2e3512 | 2829 | superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg); |
384548e5 | 2830 | sio_data->need_in7_reroute = true; |
557cbf49 | 2831 | pr_notice("Routing internal VCCH5V to in7\n"); |
436cad2a | 2832 | } |
48b2ae7f GR |
2833 | if (reg & BIT(0)) |
2834 | sio_data->internal |= BIT(0); | |
2835 | if (reg & BIT(1)) | |
2836 | sio_data->internal |= BIT(1); | |
d9b327c3 | 2837 | |
9172b5d1 GR |
2838 | /* |
2839 | * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7. | |
2840 | * While VIN7 can be routed to the internal voltage divider, | |
2841 | * VIN5 and VIN6 are not available if UART6 is enabled. | |
4573acbc GR |
2842 | * |
2843 | * Also, temp3 is not available if UART6 is enabled and TEMPIN3 | |
2844 | * is the temperature source. Since we can not read the | |
2845 | * temperature source here, skip_temp is preliminary. | |
9172b5d1 | 2846 | */ |
4573acbc | 2847 | if (uart6) { |
48b2ae7f GR |
2848 | sio_data->skip_in |= BIT(5) | BIT(6); |
2849 | sio_data->skip_temp |= BIT(2); | |
4573acbc | 2850 | } |
9172b5d1 | 2851 | |
3c2e3512 GR |
2852 | sio_data->beep_pin = superio_inb(sioaddr, |
2853 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
87673dd7 | 2854 | } |
d9b327c3 | 2855 | if (sio_data->beep_pin) |
a8ca1037 | 2856 | pr_info("Beeping is supported\n"); |
87673dd7 | 2857 | |
a1bedbcc FC |
2858 | /* Set values based on DMI matches */ |
2859 | if (dmi_data) | |
2860 | sio_data->skip_pwm |= dmi_data->skip_pwm; | |
98dd22c3 | 2861 | |
1da177e4 | 2862 | exit: |
4119693b | 2863 | superio_exit(sioaddr, config ? has_conf_noexit(config) : false); |
1da177e4 LT |
2864 | return err; |
2865 | } | |
2866 | ||
557cbf49 MS |
2867 | /* |
2868 | * Some chips seem to have default value 0xff for all limit | |
2869 | * registers. For low voltage limits it makes no sense and triggers | |
2870 | * alarms, so change to 0 instead. For high temperature limits, it | |
2871 | * means -1 degree C, which surprisingly doesn't trigger an alarm, | |
2872 | * but is still confusing, so change to 127 degrees C. | |
2873 | */ | |
2874 | static void it87_check_limit_regs(struct it87_data *data) | |
2875 | { | |
2876 | int i, reg; | |
2877 | ||
2878 | for (i = 0; i < NUM_VIN_LIMIT; i++) { | |
2879 | reg = it87_read_value(data, IT87_REG_VIN_MIN(i)); | |
2880 | if (reg == 0xff) | |
2881 | it87_write_value(data, IT87_REG_VIN_MIN(i), 0); | |
2882 | } | |
2883 | for (i = 0; i < NUM_TEMP_LIMIT; i++) { | |
2884 | reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i)); | |
2885 | if (reg == 0xff) | |
2886 | it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127); | |
2887 | } | |
2888 | } | |
2889 | ||
2890 | /* Check if voltage monitors are reset manually or by some reason */ | |
2891 | static void it87_check_voltage_monitors_reset(struct it87_data *data) | |
2892 | { | |
2893 | int reg; | |
2894 | ||
2895 | reg = it87_read_value(data, IT87_REG_VIN_ENABLE); | |
2896 | if ((reg & 0xff) == 0) { | |
2897 | /* Enable all voltage monitors */ | |
2898 | it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff); | |
2899 | } | |
2900 | } | |
2901 | ||
2902 | /* Check if tachometers are reset manually or by some reason */ | |
2903 | static void it87_check_tachometers_reset(struct platform_device *pdev) | |
2904 | { | |
2905 | struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); | |
2906 | struct it87_data *data = platform_get_drvdata(pdev); | |
2907 | u8 mask, fan_main_ctrl; | |
2908 | ||
2909 | mask = 0x70 & ~(sio_data->skip_fan << 4); | |
2910 | fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); | |
2911 | if ((fan_main_ctrl & mask) == 0) { | |
2912 | /* Enable all fan tachometers */ | |
2913 | fan_main_ctrl |= mask; | |
2914 | it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, | |
2915 | fan_main_ctrl); | |
2916 | } | |
2917 | } | |
2918 | ||
2919 | /* Set tachometers to 16-bit mode if needed */ | |
2920 | static void it87_check_tachometers_16bit_mode(struct platform_device *pdev) | |
2921 | { | |
2922 | struct it87_data *data = platform_get_drvdata(pdev); | |
2923 | int reg; | |
2924 | ||
2925 | if (!has_fan16_config(data)) | |
2926 | return; | |
2927 | ||
2928 | reg = it87_read_value(data, IT87_REG_FAN_16BIT); | |
2929 | if (~reg & 0x07 & data->has_fan) { | |
2930 | dev_dbg(&pdev->dev, | |
2931 | "Setting fan1-3 to 16-bit mode\n"); | |
2932 | it87_write_value(data, IT87_REG_FAN_16BIT, | |
2933 | reg | 0x07); | |
2934 | } | |
2935 | } | |
2936 | ||
2937 | static void it87_start_monitoring(struct it87_data *data) | |
2938 | { | |
2939 | it87_write_value(data, IT87_REG_CONFIG, | |
2940 | (it87_read_value(data, IT87_REG_CONFIG) & 0x3e) | |
2941 | | (update_vbat ? 0x41 : 0x01)); | |
2942 | } | |
2943 | ||
c1e7a4ca GR |
2944 | /* Called when we have found a new IT87. */ |
2945 | static void it87_init_device(struct platform_device *pdev) | |
1da177e4 | 2946 | { |
c1e7a4ca GR |
2947 | struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); |
2948 | struct it87_data *data = platform_get_drvdata(pdev); | |
2949 | int tmp, i; | |
b74f3fdd | 2950 | |
c1e7a4ca GR |
2951 | /* |
2952 | * For each PWM channel: | |
2953 | * - If it is in automatic mode, setting to manual mode should set | |
2954 | * the fan to full speed by default. | |
2955 | * - If it is in manual mode, we need a mapping to temperature | |
2956 | * channels to use when later setting to automatic mode later. | |
2957 | * Use a 1:1 mapping by default (we are clueless.) | |
2958 | * In both cases, the value can (and should) be changed by the user | |
2959 | * prior to switching to a different mode. | |
2960 | * Note that this is no longer needed for the IT8721F and later, as | |
2961 | * these have separate registers for the temperature mapping and the | |
2962 | * manual duty cycle. | |
2963 | */ | |
2310048d | 2964 | for (i = 0; i < NUM_AUTO_PWM; i++) { |
c1e7a4ca GR |
2965 | data->pwm_temp_map[i] = i; |
2966 | data->pwm_duty[i] = 0x7f; /* Full speed */ | |
2967 | data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ | |
8e9afcbb | 2968 | } |
1da177e4 | 2969 | |
557cbf49 | 2970 | it87_check_limit_regs(data); |
1da177e4 | 2971 | |
c1e7a4ca GR |
2972 | /* |
2973 | * Temperature channels are not forcibly enabled, as they can be | |
2974 | * set to two different sensor types and we can't guess which one | |
2975 | * is correct for a given system. These channels can be enabled at | |
2976 | * run-time through the temp{1-3}_type sysfs accessors if needed. | |
2977 | */ | |
1da177e4 | 2978 | |
557cbf49 MS |
2979 | it87_check_voltage_monitors_reset(data); |
2980 | ||
2981 | it87_check_tachometers_reset(pdev); | |
c1e7a4ca | 2982 | |
c1e7a4ca | 2983 | data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); |
c1e7a4ca GR |
2984 | data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; |
2985 | ||
557cbf49 | 2986 | it87_check_tachometers_16bit_mode(pdev); |
c1e7a4ca GR |
2987 | |
2988 | /* Check for additional fans */ | |
2989 | if (has_five_fans(data)) { | |
557cbf49 MS |
2990 | tmp = it87_read_value(data, IT87_REG_FAN_16BIT); |
2991 | ||
48b2ae7f GR |
2992 | if (tmp & BIT(4)) |
2993 | data->has_fan |= BIT(3); /* fan4 enabled */ | |
2994 | if (tmp & BIT(5)) | |
2995 | data->has_fan |= BIT(4); /* fan5 enabled */ | |
2996 | if (has_six_fans(data) && (tmp & BIT(2))) | |
2997 | data->has_fan |= BIT(5); /* fan6 enabled */ | |
c1e7a4ca GR |
2998 | } |
2999 | ||
3000 | /* Fan input pins may be used for alternative functions */ | |
3001 | data->has_fan &= ~sio_data->skip_fan; | |
3002 | ||
3003 | /* Check if pwm5, pwm6 are enabled */ | |
3004 | if (has_six_pwm(data)) { | |
3005 | /* The following code may be IT8620E specific */ | |
3006 | tmp = it87_read_value(data, IT87_REG_FAN_DIV); | |
3007 | if ((tmp & 0xc0) == 0xc0) | |
48b2ae7f GR |
3008 | sio_data->skip_pwm |= BIT(4); |
3009 | if (!(tmp & BIT(3))) | |
3010 | sio_data->skip_pwm |= BIT(5); | |
c1e7a4ca GR |
3011 | } |
3012 | ||
557cbf49 | 3013 | it87_start_monitoring(data); |
c1e7a4ca GR |
3014 | } |
3015 | ||
3016 | /* Return 1 if and only if the PWM interface is safe to use */ | |
3017 | static int it87_check_pwm(struct device *dev) | |
3018 | { | |
3019 | struct it87_data *data = dev_get_drvdata(dev); | |
3020 | /* | |
3021 | * Some BIOSes fail to correctly configure the IT87 fans. All fans off | |
3022 | * and polarity set to active low is sign that this is the case so we | |
3023 | * disable pwm control to protect the user. | |
3024 | */ | |
3025 | int tmp = it87_read_value(data, IT87_REG_FAN_CTL); | |
3026 | ||
3027 | if ((tmp & 0x87) == 0) { | |
3028 | if (fix_pwm_polarity) { | |
3029 | /* | |
3030 | * The user asks us to attempt a chip reconfiguration. | |
3031 | * This means switching to active high polarity and | |
3032 | * inverting all fan speed values. | |
3033 | */ | |
3034 | int i; | |
3035 | u8 pwm[3]; | |
3036 | ||
2310048d | 3037 | for (i = 0; i < ARRAY_SIZE(pwm); i++) |
c1e7a4ca GR |
3038 | pwm[i] = it87_read_value(data, |
3039 | IT87_REG_PWM[i]); | |
3040 | ||
3041 | /* | |
3042 | * If any fan is in automatic pwm mode, the polarity | |
3043 | * might be correct, as suspicious as it seems, so we | |
3044 | * better don't change anything (but still disable the | |
3045 | * PWM interface). | |
3046 | */ | |
3047 | if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) { | |
3048 | dev_info(dev, | |
3049 | "Reconfiguring PWM to active high polarity\n"); | |
3050 | it87_write_value(data, IT87_REG_FAN_CTL, | |
3051 | tmp | 0x87); | |
3052 | for (i = 0; i < 3; i++) | |
3053 | it87_write_value(data, | |
3054 | IT87_REG_PWM[i], | |
3055 | 0x7f & ~pwm[i]); | |
3056 | return 1; | |
3057 | } | |
3058 | ||
3059 | dev_info(dev, | |
3060 | "PWM configuration is too broken to be fixed\n"); | |
3061 | } | |
3062 | ||
c1e7a4ca GR |
3063 | return 0; |
3064 | } else if (fix_pwm_polarity) { | |
3065 | dev_info(dev, | |
3066 | "PWM configuration looks sane, won't touch\n"); | |
3067 | } | |
3068 | ||
3069 | return 1; | |
3070 | } | |
3071 | ||
3072 | static int it87_probe(struct platform_device *pdev) | |
3073 | { | |
3074 | struct it87_data *data; | |
3075 | struct resource *res; | |
3076 | struct device *dev = &pdev->dev; | |
3077 | struct it87_sio_data *sio_data = dev_get_platdata(dev); | |
c1e7a4ca | 3078 | int enable_pwm_interface; |
8638d0af | 3079 | struct device *hwmon_dev; |
c1e7a4ca GR |
3080 | |
3081 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
3082 | if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT, | |
3083 | DRVNAME)) { | |
3084 | dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", | |
3085 | (unsigned long)res->start, | |
3086 | (unsigned long)(res->start + IT87_EC_EXTENT - 1)); | |
3087 | return -EBUSY; | |
3088 | } | |
3089 | ||
3090 | data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL); | |
3091 | if (!data) | |
3092 | return -ENOMEM; | |
3093 | ||
3094 | data->addr = res->start; | |
384548e5 | 3095 | data->sioaddr = sio_data->sioaddr; |
c1e7a4ca GR |
3096 | data->type = sio_data->type; |
3097 | data->features = it87_devices[sio_data->type].features; | |
3098 | data->peci_mask = it87_devices[sio_data->type].peci_mask; | |
3099 | data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask; | |
c1e7a4ca GR |
3100 | /* |
3101 | * IT8705F Datasheet 0.4.1, 3h == Version G. | |
3102 | * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J. | |
3103 | * These are the first revisions with 16-bit tachometer support. | |
3104 | */ | |
3105 | switch (data->type) { | |
3106 | case it87: | |
3107 | if (sio_data->revision >= 0x03) { | |
3108 | data->features &= ~FEAT_OLD_AUTOPWM; | |
3109 | data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS; | |
3110 | } | |
3111 | break; | |
3112 | case it8712: | |
3113 | if (sio_data->revision >= 0x08) { | |
3114 | data->features &= ~FEAT_OLD_AUTOPWM; | |
3115 | data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS | | |
3116 | FEAT_FIVE_FANS; | |
3117 | } | |
3118 | break; | |
3119 | default: | |
3120 | break; | |
3121 | } | |
3122 | ||
3123 | /* Now, we do the remaining detection. */ | |
c962024e GR |
3124 | if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) || |
3125 | it87_read_value(data, IT87_REG_CHIPID) != 0x90) | |
c1e7a4ca GR |
3126 | return -ENODEV; |
3127 | ||
3128 | platform_set_drvdata(pdev, data); | |
1da177e4 | 3129 | |
9a61bf63 | 3130 | mutex_init(&data->update_lock); |
1da177e4 | 3131 | |
1da177e4 | 3132 | /* Check PWM configuration */ |
b74f3fdd | 3133 | enable_pwm_interface = it87_check_pwm(dev); |
384548e5 MS |
3134 | if (!enable_pwm_interface) |
3135 | dev_info(dev, | |
3136 | "Detected broken BIOS defaults, disabling PWM interface\n"); | |
1da177e4 | 3137 | |
44c1bcd4 | 3138 | /* Starting with IT8721F, we handle scaling of internal voltages */ |
968b66ff | 3139 | if (has_scaling(data)) { |
48b2ae7f GR |
3140 | if (sio_data->internal & BIT(0)) |
3141 | data->in_scaled |= BIT(3); /* in3 is AVCC */ | |
3142 | if (sio_data->internal & BIT(1)) | |
3143 | data->in_scaled |= BIT(7); /* in7 is VSB */ | |
3144 | if (sio_data->internal & BIT(2)) | |
3145 | data->in_scaled |= BIT(8); /* in8 is Vbat */ | |
3146 | if (sio_data->internal & BIT(3)) | |
3147 | data->in_scaled |= BIT(9); /* in9 is AVCC */ | |
7bc32d29 GR |
3148 | } else if (sio_data->type == it8781 || sio_data->type == it8782 || |
3149 | sio_data->type == it8783) { | |
48b2ae7f GR |
3150 | if (sio_data->internal & BIT(0)) |
3151 | data->in_scaled |= BIT(3); /* in3 is VCC5V */ | |
3152 | if (sio_data->internal & BIT(1)) | |
3153 | data->in_scaled |= BIT(7); /* in7 is VCCH5V */ | |
44c1bcd4 JD |
3154 | } |
3155 | ||
4573acbc | 3156 | data->has_temp = 0x07; |
48b2ae7f | 3157 | if (sio_data->skip_temp & BIT(2)) { |
c962024e GR |
3158 | if (sio_data->type == it8782 && |
3159 | !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80)) | |
48b2ae7f | 3160 | data->has_temp &= ~BIT(2); |
4573acbc GR |
3161 | } |
3162 | ||
d3766848 | 3163 | data->in_internal = sio_data->internal; |
384548e5 | 3164 | data->need_in7_reroute = sio_data->need_in7_reroute; |
52929715 GR |
3165 | data->has_in = 0x3ff & ~sio_data->skip_in; |
3166 | ||
cc18da79 GR |
3167 | if (has_six_temp(data)) { |
3168 | u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE); | |
3169 | ||
f838aa26 | 3170 | /* Check for additional temperature sensors */ |
cc18da79 | 3171 | if ((reg & 0x03) >= 0x02) |
48b2ae7f | 3172 | data->has_temp |= BIT(3); |
cc18da79 | 3173 | if (((reg >> 2) & 0x03) >= 0x02) |
48b2ae7f | 3174 | data->has_temp |= BIT(4); |
cc18da79 | 3175 | if (((reg >> 4) & 0x03) >= 0x02) |
48b2ae7f | 3176 | data->has_temp |= BIT(5); |
f838aa26 GR |
3177 | |
3178 | /* Check for additional voltage sensors */ | |
3179 | if ((reg & 0x03) == 0x01) | |
48b2ae7f | 3180 | data->has_in |= BIT(10); |
f838aa26 | 3181 | if (((reg >> 2) & 0x03) == 0x01) |
48b2ae7f | 3182 | data->has_in |= BIT(11); |
f838aa26 | 3183 | if (((reg >> 4) & 0x03) == 0x01) |
48b2ae7f | 3184 | data->has_in |= BIT(12); |
cc18da79 GR |
3185 | } |
3186 | ||
52929715 GR |
3187 | data->has_beep = !!sio_data->beep_pin; |
3188 | ||
1da177e4 | 3189 | /* Initialize the IT87 chip */ |
b74f3fdd | 3190 | it87_init_device(pdev); |
1da177e4 | 3191 | |
d3766848 GR |
3192 | if (!sio_data->skip_vid) { |
3193 | data->has_vid = true; | |
3194 | data->vrm = vid_which_vrm(); | |
3195 | /* VID reading from Super-I/O config space if available */ | |
3196 | data->vid = sio_data->vid_value; | |
3197 | } | |
3198 | ||
8638d0af GR |
3199 | /* Prepare for sysfs hooks */ |
3200 | data->groups[0] = &it87_group; | |
3201 | data->groups[1] = &it87_group_in; | |
3202 | data->groups[2] = &it87_group_temp; | |
3203 | data->groups[3] = &it87_group_fan; | |
17d648bf | 3204 | |
1da177e4 | 3205 | if (enable_pwm_interface) { |
48b2ae7f | 3206 | data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1; |
5c391261 | 3207 | data->has_pwm &= ~sio_data->skip_pwm; |
4f3f51bc | 3208 | |
8638d0af | 3209 | data->groups[4] = &it87_group_pwm; |
2cbb9c37 | 3210 | if (has_old_autopwm(data) || has_newer_autopwm(data)) |
8638d0af | 3211 | data->groups[5] = &it87_group_auto_pwm; |
1da177e4 LT |
3212 | } |
3213 | ||
8638d0af GR |
3214 | hwmon_dev = devm_hwmon_device_register_with_groups(dev, |
3215 | it87_devices[sio_data->type].name, | |
3216 | data, data->groups); | |
3217 | return PTR_ERR_OR_ZERO(hwmon_dev); | |
1da177e4 LT |
3218 | } |
3219 | ||
31b34d62 | 3220 | static void it87_resume_sio(struct platform_device *pdev) |
384548e5 MS |
3221 | { |
3222 | struct it87_data *data = dev_get_drvdata(&pdev->dev); | |
3223 | int err; | |
3224 | int reg2c; | |
3225 | ||
3226 | if (!data->need_in7_reroute) | |
3227 | return; | |
3228 | ||
3229 | err = superio_enter(data->sioaddr); | |
3230 | if (err) { | |
3231 | dev_warn(&pdev->dev, | |
3232 | "Unable to enter Super I/O to reroute in7 (%d)", | |
3233 | err); | |
3234 | return; | |
3235 | } | |
3236 | ||
3237 | superio_select(data->sioaddr, GPIO); | |
3238 | ||
3239 | reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG); | |
3240 | if (!(reg2c & BIT(1))) { | |
3241 | dev_dbg(&pdev->dev, | |
3242 | "Routing internal VCCH5V to in7 again"); | |
3243 | ||
3244 | reg2c |= BIT(1); | |
3245 | superio_outb(data->sioaddr, IT87_SIO_PINX2_REG, | |
3246 | reg2c); | |
3247 | } | |
3248 | ||
4119693b | 3249 | superio_exit(data->sioaddr, has_conf_noexit(data)); |
384548e5 MS |
3250 | } |
3251 | ||
31b34d62 | 3252 | static int it87_resume(struct device *dev) |
384548e5 MS |
3253 | { |
3254 | struct platform_device *pdev = to_platform_device(dev); | |
3255 | struct it87_data *data = dev_get_drvdata(dev); | |
3256 | ||
3257 | it87_resume_sio(pdev); | |
3258 | ||
3259 | mutex_lock(&data->update_lock); | |
3260 | ||
3261 | it87_check_pwm(dev); | |
3262 | it87_check_limit_regs(data); | |
3263 | it87_check_voltage_monitors_reset(data); | |
3264 | it87_check_tachometers_reset(pdev); | |
3265 | it87_check_tachometers_16bit_mode(pdev); | |
3266 | ||
3267 | it87_start_monitoring(data); | |
3268 | ||
3269 | /* force update */ | |
952a11ca | 3270 | data->valid = false; |
384548e5 MS |
3271 | |
3272 | mutex_unlock(&data->update_lock); | |
3273 | ||
3274 | it87_update_device(dev); | |
3275 | ||
3276 | return 0; | |
3277 | } | |
3278 | ||
31b34d62 | 3279 | static DEFINE_SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume); |
384548e5 | 3280 | |
c1e7a4ca GR |
3281 | static struct platform_driver it87_driver = { |
3282 | .driver = { | |
3283 | .name = DRVNAME, | |
31b34d62 | 3284 | .pm = pm_sleep_ptr(&it87_dev_pm_ops), |
c1e7a4ca GR |
3285 | }, |
3286 | .probe = it87_probe, | |
c1e7a4ca | 3287 | }; |
1da177e4 | 3288 | |
e84bd953 | 3289 | static int __init it87_device_add(int index, unsigned short address, |
b74f3fdd | 3290 | const struct it87_sio_data *sio_data) |
3291 | { | |
8e50e3c3 | 3292 | struct platform_device *pdev; |
b74f3fdd | 3293 | struct resource res = { |
87b4b663 BH |
3294 | .start = address + IT87_EC_OFFSET, |
3295 | .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1, | |
b74f3fdd | 3296 | .name = DRVNAME, |
3297 | .flags = IORESOURCE_IO, | |
3298 | }; | |
3299 | int err; | |
3300 | ||
b9acb64a | 3301 | err = acpi_check_resource_conflict(&res); |
12c44ab8 AK |
3302 | if (err) { |
3303 | if (!ignore_resource_conflict) | |
3304 | return err; | |
3305 | } | |
b9acb64a | 3306 | |
b74f3fdd | 3307 | pdev = platform_device_alloc(DRVNAME, address); |
5cae84a5 GR |
3308 | if (!pdev) |
3309 | return -ENOMEM; | |
b74f3fdd | 3310 | |
3311 | err = platform_device_add_resources(pdev, &res, 1); | |
3312 | if (err) { | |
a8ca1037 | 3313 | pr_err("Device resource addition failed (%d)\n", err); |
b74f3fdd | 3314 | goto exit_device_put; |
3315 | } | |
3316 | ||
3317 | err = platform_device_add_data(pdev, sio_data, | |
3318 | sizeof(struct it87_sio_data)); | |
3319 | if (err) { | |
a8ca1037 | 3320 | pr_err("Platform data allocation failed\n"); |
b74f3fdd | 3321 | goto exit_device_put; |
3322 | } | |
3323 | ||
3324 | err = platform_device_add(pdev); | |
3325 | if (err) { | |
a8ca1037 | 3326 | pr_err("Device addition failed (%d)\n", err); |
b74f3fdd | 3327 | goto exit_device_put; |
3328 | } | |
3329 | ||
e84bd953 | 3330 | it87_pdev[index] = pdev; |
b74f3fdd | 3331 | return 0; |
3332 | ||
3333 | exit_device_put: | |
3334 | platform_device_put(pdev); | |
b74f3fdd | 3335 | return err; |
3336 | } | |
3337 | ||
a1bedbcc FC |
3338 | /* callback function for DMI */ |
3339 | static int it87_dmi_cb(const struct dmi_system_id *dmi_entry) | |
3340 | { | |
3341 | dmi_data = dmi_entry->driver_data; | |
3342 | ||
3343 | if (dmi_data && dmi_data->skip_pwm) | |
3344 | pr_info("Disabling pwm2 due to hardware constraints\n"); | |
3345 | ||
3346 | return 1; | |
3347 | } | |
3348 | ||
ff9dedd2 FC |
3349 | /* |
3350 | * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip | |
3351 | * (IT8792E) needs to be in configuration mode before accessing the first | |
3352 | * due to a bug in IT8792E which otherwise results in LPC bus access errors. | |
3353 | * This needs to be done before accessing the first Super-IO chip since | |
3354 | * the second chip may have been accessed prior to loading this driver. | |
3355 | * | |
3356 | * The problem is also reported to affect IT8795E, which is used on X299 boards | |
3357 | * and has the same chip ID as IT8792E (0x8733). It also appears to affect | |
3358 | * systems with IT8790E, which is used on some Z97X-Gaming boards as well as | |
3359 | * Z87X-OC. | |
3360 | * DMI entries for those systems will be added as they become available and | |
3361 | * as the problem is confirmed to affect those boards. | |
3362 | */ | |
3363 | static int it87_sio_force(const struct dmi_system_id *dmi_entry) | |
3364 | { | |
3365 | __superio_enter(REG_4E); | |
3366 | ||
3367 | return it87_dmi_cb(dmi_entry); | |
3368 | }; | |
3369 | ||
a1bedbcc FC |
3370 | /* |
3371 | * On the Shuttle SN68PT, FAN_CTL2 is apparently not | |
3372 | * connected to a fan, but to something else. One user | |
3373 | * has reported instant system power-off when changing | |
3374 | * the PWM2 duty cycle, so we disable it. | |
3375 | * I use the board name string as the trigger in case | |
3376 | * the same board is ever used in other systems. | |
3377 | */ | |
3378 | static struct it87_dmi_data nvidia_fn68pt = { | |
3379 | .skip_pwm = BIT(1), | |
3380 | }; | |
3381 | ||
3382 | #define IT87_DMI_MATCH_VND(vendor, name, cb, data) \ | |
3383 | { \ | |
3384 | .callback = cb, \ | |
3385 | .matches = { \ | |
3386 | DMI_EXACT_MATCH(DMI_BOARD_VENDOR, vendor), \ | |
3387 | DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \ | |
3388 | }, \ | |
3389 | .driver_data = data, \ | |
3390 | } | |
3391 | ||
ff9dedd2 FC |
3392 | #define IT87_DMI_MATCH_GBT(name, cb, data) \ |
3393 | IT87_DMI_MATCH_VND("Gigabyte Technology Co., Ltd.", name, cb, data) | |
3394 | ||
a1bedbcc | 3395 | static const struct dmi_system_id it87_dmi_table[] __initconst = { |
ff9dedd2 FC |
3396 | IT87_DMI_MATCH_GBT("AB350", it87_sio_force, NULL), |
3397 | /* ? + IT8792E/IT8795E */ | |
3398 | IT87_DMI_MATCH_GBT("AX370", it87_sio_force, NULL), | |
3399 | /* ? + IT8792E/IT8795E */ | |
3400 | IT87_DMI_MATCH_GBT("Z97X-Gaming G1", it87_sio_force, NULL), | |
3401 | /* ? + IT8790E */ | |
3402 | IT87_DMI_MATCH_GBT("TRX40 AORUS XTREME", it87_sio_force, NULL), | |
3403 | /* IT8688E + IT8792E/IT8795E */ | |
3404 | IT87_DMI_MATCH_GBT("Z390 AORUS ULTRA-CF", it87_sio_force, NULL), | |
3405 | /* IT8688E + IT8792E/IT8795E */ | |
3406 | IT87_DMI_MATCH_GBT("B550 AORUS PRO AC", it87_sio_force, NULL), | |
3407 | /* IT8688E + IT8792E/IT8795E */ | |
3408 | IT87_DMI_MATCH_GBT("X570 AORUS MASTER", it87_sio_force, NULL), | |
3409 | /* IT8688E + IT8792E/IT8795E */ | |
3410 | IT87_DMI_MATCH_GBT("X570 AORUS PRO", it87_sio_force, NULL), | |
3411 | /* IT8688E + IT8792E/IT8795E */ | |
3412 | IT87_DMI_MATCH_GBT("X570 AORUS PRO WIFI", it87_sio_force, NULL), | |
3413 | /* IT8688E + IT8792E/IT8795E */ | |
3414 | IT87_DMI_MATCH_GBT("X570S AERO G", it87_sio_force, NULL), | |
3415 | /* IT8689E + IT87952E */ | |
3416 | IT87_DMI_MATCH_GBT("Z690 AORUS PRO DDR4", it87_sio_force, NULL), | |
3417 | /* IT8689E + IT87952E */ | |
3418 | IT87_DMI_MATCH_GBT("Z690 AORUS PRO", it87_sio_force, NULL), | |
3419 | /* IT8689E + IT87952E */ | |
a1bedbcc FC |
3420 | IT87_DMI_MATCH_VND("nVIDIA", "FN68PT", it87_dmi_cb, &nvidia_fn68pt), |
3421 | { } | |
3422 | ||
3423 | }; | |
3424 | MODULE_DEVICE_TABLE(dmi, it87_dmi_table); | |
3425 | ||
1da177e4 LT |
3426 | static int __init sm_it87_init(void) |
3427 | { | |
e84bd953 | 3428 | int sioaddr[2] = { REG_2E, REG_4E }; |
b74f3fdd | 3429 | struct it87_sio_data sio_data; |
8358378b | 3430 | unsigned short isa_address[2]; |
e84bd953 GR |
3431 | bool found = false; |
3432 | int i, err; | |
b74f3fdd | 3433 | |
b74f3fdd | 3434 | err = platform_driver_register(&it87_driver); |
3435 | if (err) | |
3436 | return err; | |
fde09509 | 3437 | |
a1bedbcc FC |
3438 | dmi_check_system(it87_dmi_table); |
3439 | ||
e84bd953 GR |
3440 | for (i = 0; i < ARRAY_SIZE(sioaddr); i++) { |
3441 | memset(&sio_data, 0, sizeof(struct it87_sio_data)); | |
8358378b | 3442 | isa_address[i] = 0; |
2a64e9d4 | 3443 | err = it87_find(sioaddr[i], &isa_address[i], &sio_data, i); |
8358378b | 3444 | if (err || isa_address[i] == 0) |
e84bd953 | 3445 | continue; |
8358378b GR |
3446 | /* |
3447 | * Don't register second chip if its ISA address matches | |
3448 | * the first chip's ISA address. | |
3449 | */ | |
3450 | if (i && isa_address[i] == isa_address[0]) | |
3451 | break; | |
e84bd953 | 3452 | |
8358378b | 3453 | err = it87_device_add(i, isa_address[i], &sio_data); |
e84bd953 GR |
3454 | if (err) |
3455 | goto exit_dev_unregister; | |
8358378b | 3456 | |
e84bd953 | 3457 | found = true; |
8358378b GR |
3458 | |
3459 | /* | |
3460 | * IT8705F may respond on both SIO addresses. | |
3461 | * Stop probing after finding one. | |
3462 | */ | |
3463 | if (sio_data.type == it87) | |
3464 | break; | |
b74f3fdd | 3465 | } |
3466 | ||
e84bd953 GR |
3467 | if (!found) { |
3468 | err = -ENODEV; | |
3469 | goto exit_unregister; | |
3470 | } | |
b74f3fdd | 3471 | return 0; |
e84bd953 GR |
3472 | |
3473 | exit_dev_unregister: | |
3474 | /* NULL check handled by platform_device_unregister */ | |
3475 | platform_device_unregister(it87_pdev[0]); | |
3476 | exit_unregister: | |
3477 | platform_driver_unregister(&it87_driver); | |
3478 | return err; | |
1da177e4 LT |
3479 | } |
3480 | ||
3481 | static void __exit sm_it87_exit(void) | |
3482 | { | |
e84bd953 GR |
3483 | /* NULL check handled by platform_device_unregister */ |
3484 | platform_device_unregister(it87_pdev[1]); | |
3485 | platform_device_unregister(it87_pdev[0]); | |
b74f3fdd | 3486 | platform_driver_unregister(&it87_driver); |
1da177e4 LT |
3487 | } |
3488 | ||
7c81c60f | 3489 | MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>"); |
44c1bcd4 | 3490 | MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver"); |
b361a1cf | 3491 | |
2a64e9d4 FC |
3492 | module_param_array(force_id, ushort, &force_id_cnt, 0); |
3493 | MODULE_PARM_DESC(force_id, "Override one or more detected device ID(s)"); | |
b361a1cf FC |
3494 | |
3495 | module_param(ignore_resource_conflict, bool, 0); | |
3496 | MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict"); | |
3497 | ||
1da177e4 LT |
3498 | module_param(update_vbat, bool, 0); |
3499 | MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); | |
b361a1cf | 3500 | |
1da177e4 | 3501 | module_param(fix_pwm_polarity, bool, 0); |
5f2dc798 JD |
3502 | MODULE_PARM_DESC(fix_pwm_polarity, |
3503 | "Force PWM polarity to active high (DANGEROUS)"); | |
b361a1cf | 3504 | |
1da177e4 LT |
3505 | MODULE_LICENSE("GPL"); |
3506 | ||
3507 | module_init(sm_it87_init); | |
3508 | module_exit(sm_it87_exit); |