Commit | Line | Data |
---|---|---|
1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7cb6dcff AD |
2 | /* |
3 | * INA3221 Triple Current/Voltage Monitor | |
4 | * | |
5 | * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * Andrew F. Davis <afd@ti.com> | |
7cb6dcff AD |
7 | */ |
8 | ||
9 | #include <linux/hwmon.h> | |
10 | #include <linux/hwmon-sysfs.h> | |
11 | #include <linux/i2c.h> | |
12 | #include <linux/module.h> | |
87625b24 | 13 | #include <linux/mutex.h> |
7cb6dcff | 14 | #include <linux/of.h> |
323aeb0e | 15 | #include <linux/pm_runtime.h> |
7cb6dcff | 16 | #include <linux/regmap.h> |
5c090abf | 17 | #include <linux/util_macros.h> |
7cb6dcff AD |
18 | |
19 | #define INA3221_DRIVER_NAME "ina3221" | |
20 | ||
21 | #define INA3221_CONFIG 0x00 | |
22 | #define INA3221_SHUNT1 0x01 | |
23 | #define INA3221_BUS1 0x02 | |
24 | #define INA3221_SHUNT2 0x03 | |
25 | #define INA3221_BUS2 0x04 | |
26 | #define INA3221_SHUNT3 0x05 | |
27 | #define INA3221_BUS3 0x06 | |
28 | #define INA3221_CRIT1 0x07 | |
29 | #define INA3221_WARN1 0x08 | |
30 | #define INA3221_CRIT2 0x09 | |
31 | #define INA3221_WARN2 0x0a | |
32 | #define INA3221_CRIT3 0x0b | |
33 | #define INA3221_WARN3 0x0c | |
34 | #define INA3221_MASK_ENABLE 0x0f | |
35 | ||
59d608e1 NC |
36 | #define INA3221_CONFIG_MODE_MASK GENMASK(2, 0) |
37 | #define INA3221_CONFIG_MODE_POWERDOWN 0 | |
791ebc9d NC |
38 | #define INA3221_CONFIG_MODE_SHUNT BIT(0) |
39 | #define INA3221_CONFIG_MODE_BUS BIT(1) | |
40 | #define INA3221_CONFIG_MODE_CONTINUOUS BIT(2) | |
4c0415a3 NC |
41 | #define INA3221_CONFIG_VSH_CT_SHIFT 3 |
42 | #define INA3221_CONFIG_VSH_CT_MASK GENMASK(5, 3) | |
43 | #define INA3221_CONFIG_VSH_CT(x) (((x) & GENMASK(5, 3)) >> 3) | |
44 | #define INA3221_CONFIG_VBUS_CT_SHIFT 6 | |
45 | #define INA3221_CONFIG_VBUS_CT_MASK GENMASK(8, 6) | |
46 | #define INA3221_CONFIG_VBUS_CT(x) (((x) & GENMASK(8, 6)) >> 6) | |
5c090abf NC |
47 | #define INA3221_CONFIG_AVG_SHIFT 9 |
48 | #define INA3221_CONFIG_AVG_MASK GENMASK(11, 9) | |
49 | #define INA3221_CONFIG_AVG(x) (((x) & GENMASK(11, 9)) >> 9) | |
4c0415a3 | 50 | #define INA3221_CONFIG_CHs_EN_MASK GENMASK(14, 12) |
a9e9dd9c | 51 | #define INA3221_CONFIG_CHx_EN(x) BIT(14 - (x)) |
7cb6dcff | 52 | |
323aeb0e | 53 | #define INA3221_CONFIG_DEFAULT 0x7127 |
7cb6dcff AD |
54 | #define INA3221_RSHUNT_DEFAULT 10000 |
55 | ||
56 | enum ina3221_fields { | |
57 | /* Configuration */ | |
58 | F_RST, | |
59 | ||
4c0415a3 NC |
60 | /* Status Flags */ |
61 | F_CVRF, | |
62 | ||
7cb6dcff AD |
63 | /* Alert Flags */ |
64 | F_WF3, F_WF2, F_WF1, | |
65 | F_CF3, F_CF2, F_CF1, | |
66 | ||
67 | /* sentinel */ | |
68 | F_MAX_FIELDS | |
69 | }; | |
70 | ||
71 | static const struct reg_field ina3221_reg_fields[] = { | |
72 | [F_RST] = REG_FIELD(INA3221_CONFIG, 15, 15), | |
73 | ||
4c0415a3 | 74 | [F_CVRF] = REG_FIELD(INA3221_MASK_ENABLE, 0, 0), |
7cb6dcff AD |
75 | [F_WF3] = REG_FIELD(INA3221_MASK_ENABLE, 3, 3), |
76 | [F_WF2] = REG_FIELD(INA3221_MASK_ENABLE, 4, 4), | |
77 | [F_WF1] = REG_FIELD(INA3221_MASK_ENABLE, 5, 5), | |
78 | [F_CF3] = REG_FIELD(INA3221_MASK_ENABLE, 7, 7), | |
79 | [F_CF2] = REG_FIELD(INA3221_MASK_ENABLE, 8, 8), | |
80 | [F_CF1] = REG_FIELD(INA3221_MASK_ENABLE, 9, 9), | |
81 | }; | |
82 | ||
83 | enum ina3221_channels { | |
84 | INA3221_CHANNEL1, | |
85 | INA3221_CHANNEL2, | |
86 | INA3221_CHANNEL3, | |
87 | INA3221_NUM_CHANNELS | |
88 | }; | |
89 | ||
a9e9dd9c NC |
90 | /** |
91 | * struct ina3221_input - channel input source specific information | |
92 | * @label: label of channel input source | |
93 | * @shunt_resistor: shunt resistor value of channel input source | |
94 | * @disconnected: connection status of channel input source | |
95 | */ | |
96 | struct ina3221_input { | |
97 | const char *label; | |
98 | int shunt_resistor; | |
99 | bool disconnected; | |
100 | }; | |
101 | ||
7cb6dcff AD |
102 | /** |
103 | * struct ina3221_data - device specific information | |
323aeb0e | 104 | * @pm_dev: Device pointer for pm runtime |
7cb6dcff AD |
105 | * @regmap: Register map of the device |
106 | * @fields: Register fields of the device | |
a9e9dd9c | 107 | * @inputs: Array of channel input source specific structures |
87625b24 | 108 | * @lock: mutex lock to serialize sysfs attribute accesses |
59d608e1 | 109 | * @reg_config: Register value of INA3221_CONFIG |
43dece16 | 110 | * @single_shot: running in single-shot operating mode |
7cb6dcff AD |
111 | */ |
112 | struct ina3221_data { | |
323aeb0e | 113 | struct device *pm_dev; |
7cb6dcff AD |
114 | struct regmap *regmap; |
115 | struct regmap_field *fields[F_MAX_FIELDS]; | |
a9e9dd9c | 116 | struct ina3221_input inputs[INA3221_NUM_CHANNELS]; |
87625b24 | 117 | struct mutex lock; |
59d608e1 | 118 | u32 reg_config; |
43dece16 NC |
119 | |
120 | bool single_shot; | |
7cb6dcff AD |
121 | }; |
122 | ||
a9e9dd9c NC |
123 | static inline bool ina3221_is_enabled(struct ina3221_data *ina, int channel) |
124 | { | |
323aeb0e NC |
125 | return pm_runtime_active(ina->pm_dev) && |
126 | (ina->reg_config & INA3221_CONFIG_CHx_EN(channel)); | |
a9e9dd9c NC |
127 | } |
128 | ||
4c0415a3 NC |
129 | /* Lookup table for Bus and Shunt conversion times in usec */ |
130 | static const u16 ina3221_conv_time[] = { | |
131 | 140, 204, 332, 588, 1100, 2116, 4156, 8244, | |
132 | }; | |
133 | ||
5c090abf NC |
134 | /* Lookup table for number of samples using in averaging mode */ |
135 | static const int ina3221_avg_samples[] = { | |
136 | 1, 4, 16, 64, 128, 256, 512, 1024, | |
137 | }; | |
138 | ||
023912db NC |
139 | /* Converting update_interval in msec to conversion time in usec */ |
140 | static inline u32 ina3221_interval_ms_to_conv_time(u16 config, int interval) | |
141 | { | |
142 | u32 channels = hweight16(config & INA3221_CONFIG_CHs_EN_MASK); | |
143 | u32 samples_idx = INA3221_CONFIG_AVG(config); | |
144 | u32 samples = ina3221_avg_samples[samples_idx]; | |
145 | ||
146 | /* Bisect the result to Bus and Shunt conversion times */ | |
147 | return DIV_ROUND_CLOSEST(interval * 1000 / 2, channels * samples); | |
148 | } | |
149 | ||
150 | /* Converting CONFIG register value to update_interval in usec */ | |
151 | static inline u32 ina3221_reg_to_interval_us(u16 config) | |
4c0415a3 | 152 | { |
023912db NC |
153 | u32 channels = hweight16(config & INA3221_CONFIG_CHs_EN_MASK); |
154 | u32 vbus_ct_idx = INA3221_CONFIG_VBUS_CT(config); | |
155 | u32 vsh_ct_idx = INA3221_CONFIG_VSH_CT(config); | |
156 | u32 samples_idx = INA3221_CONFIG_AVG(config); | |
5c090abf | 157 | u32 samples = ina3221_avg_samples[samples_idx]; |
4c0415a3 NC |
158 | u32 vbus_ct = ina3221_conv_time[vbus_ct_idx]; |
159 | u32 vsh_ct = ina3221_conv_time[vsh_ct_idx]; | |
4c0415a3 NC |
160 | |
161 | /* Calculate total conversion time */ | |
023912db NC |
162 | return channels * (vbus_ct + vsh_ct) * samples; |
163 | } | |
164 | ||
165 | static inline int ina3221_wait_for_data(struct ina3221_data *ina) | |
166 | { | |
167 | u32 wait, cvrf; | |
168 | ||
169 | wait = ina3221_reg_to_interval_us(ina->reg_config); | |
4c0415a3 NC |
170 | |
171 | /* Polling the CVRF bit to make sure read data is ready */ | |
172 | return regmap_field_read_poll_timeout(ina->fields[F_CVRF], | |
173 | cvrf, cvrf, wait, 100000); | |
174 | } | |
175 | ||
d4b0166d NC |
176 | static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg, |
177 | int *val) | |
178 | { | |
179 | unsigned int regval; | |
180 | int ret; | |
181 | ||
182 | ret = regmap_read(ina->regmap, reg, ®val); | |
183 | if (ret) | |
184 | return ret; | |
185 | ||
186 | *val = sign_extend32(regval >> 3, 12); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static const u8 ina3221_in_reg[] = { | |
192 | INA3221_BUS1, | |
193 | INA3221_BUS2, | |
194 | INA3221_BUS3, | |
195 | INA3221_SHUNT1, | |
196 | INA3221_SHUNT2, | |
197 | INA3221_SHUNT3, | |
198 | }; | |
199 | ||
5c090abf NC |
200 | static int ina3221_read_chip(struct device *dev, u32 attr, long *val) |
201 | { | |
202 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
203 | int regval; | |
204 | ||
205 | switch (attr) { | |
206 | case hwmon_chip_samples: | |
207 | regval = INA3221_CONFIG_AVG(ina->reg_config); | |
208 | *val = ina3221_avg_samples[regval]; | |
209 | return 0; | |
023912db NC |
210 | case hwmon_chip_update_interval: |
211 | /* Return in msec */ | |
212 | *val = ina3221_reg_to_interval_us(ina->reg_config); | |
213 | *val = DIV_ROUND_CLOSEST(*val, 1000); | |
214 | return 0; | |
5c090abf NC |
215 | default: |
216 | return -EOPNOTSUPP; | |
217 | } | |
218 | } | |
219 | ||
d4b0166d NC |
220 | static int ina3221_read_in(struct device *dev, u32 attr, int channel, long *val) |
221 | { | |
222 | const bool is_shunt = channel > INA3221_CHANNEL3; | |
223 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
224 | u8 reg = ina3221_in_reg[channel]; | |
225 | int regval, ret; | |
226 | ||
227 | /* Translate shunt channel index to sensor channel index */ | |
228 | channel %= INA3221_NUM_CHANNELS; | |
229 | ||
230 | switch (attr) { | |
231 | case hwmon_in_input: | |
232 | if (!ina3221_is_enabled(ina, channel)) | |
233 | return -ENODATA; | |
234 | ||
43dece16 NC |
235 | /* Write CONFIG register to trigger a single-shot measurement */ |
236 | if (ina->single_shot) | |
237 | regmap_write(ina->regmap, INA3221_CONFIG, | |
238 | ina->reg_config); | |
239 | ||
4c0415a3 NC |
240 | ret = ina3221_wait_for_data(ina); |
241 | if (ret) | |
242 | return ret; | |
243 | ||
d4b0166d NC |
244 | ret = ina3221_read_value(ina, reg, ®val); |
245 | if (ret) | |
246 | return ret; | |
247 | ||
248 | /* | |
249 | * Scale of shunt voltage (uV): LSB is 40uV | |
250 | * Scale of bus voltage (mV): LSB is 8mV | |
251 | */ | |
252 | *val = regval * (is_shunt ? 40 : 8); | |
253 | return 0; | |
254 | case hwmon_in_enable: | |
255 | *val = ina3221_is_enabled(ina, channel); | |
256 | return 0; | |
257 | default: | |
258 | return -EOPNOTSUPP; | |
259 | } | |
260 | } | |
261 | ||
262 | static const u8 ina3221_curr_reg[][INA3221_NUM_CHANNELS] = { | |
263 | [hwmon_curr_input] = { INA3221_SHUNT1, INA3221_SHUNT2, INA3221_SHUNT3 }, | |
264 | [hwmon_curr_max] = { INA3221_WARN1, INA3221_WARN2, INA3221_WARN3 }, | |
265 | [hwmon_curr_crit] = { INA3221_CRIT1, INA3221_CRIT2, INA3221_CRIT3 }, | |
266 | [hwmon_curr_max_alarm] = { F_WF1, F_WF2, F_WF3 }, | |
267 | [hwmon_curr_crit_alarm] = { F_CF1, F_CF2, F_CF3 }, | |
268 | }; | |
269 | ||
270 | static int ina3221_read_curr(struct device *dev, u32 attr, | |
271 | int channel, long *val) | |
a9e9dd9c | 272 | { |
a9e9dd9c | 273 | struct ina3221_data *ina = dev_get_drvdata(dev); |
a9e9dd9c | 274 | struct ina3221_input *input = &ina->inputs[channel]; |
d4b0166d NC |
275 | int resistance_uo = input->shunt_resistor; |
276 | u8 reg = ina3221_curr_reg[attr][channel]; | |
277 | int regval, voltage_nv, ret; | |
278 | ||
279 | switch (attr) { | |
280 | case hwmon_curr_input: | |
281 | if (!ina3221_is_enabled(ina, channel)) | |
282 | return -ENODATA; | |
4c0415a3 | 283 | |
43dece16 NC |
284 | /* Write CONFIG register to trigger a single-shot measurement */ |
285 | if (ina->single_shot) | |
286 | regmap_write(ina->regmap, INA3221_CONFIG, | |
287 | ina->reg_config); | |
288 | ||
4c0415a3 NC |
289 | ret = ina3221_wait_for_data(ina); |
290 | if (ret) | |
291 | return ret; | |
292 | ||
d4b0166d NC |
293 | /* fall through */ |
294 | case hwmon_curr_crit: | |
295 | case hwmon_curr_max: | |
296 | ret = ina3221_read_value(ina, reg, ®val); | |
297 | if (ret) | |
298 | return ret; | |
a9e9dd9c | 299 | |
d4b0166d NC |
300 | /* Scale of shunt voltage: LSB is 40uV (40000nV) */ |
301 | voltage_nv = regval * 40000; | |
302 | /* Return current in mA */ | |
303 | *val = DIV_ROUND_CLOSEST(voltage_nv, resistance_uo); | |
304 | return 0; | |
305 | case hwmon_curr_crit_alarm: | |
306 | case hwmon_curr_max_alarm: | |
efb0489e NC |
307 | /* No actual register read if channel is disabled */ |
308 | if (!ina3221_is_enabled(ina, channel)) { | |
309 | /* Return 0 for alert flags */ | |
310 | *val = 0; | |
311 | return 0; | |
312 | } | |
d4b0166d NC |
313 | ret = regmap_field_read(ina->fields[reg], ®val); |
314 | if (ret) | |
315 | return ret; | |
316 | *val = regval; | |
317 | return 0; | |
318 | default: | |
319 | return -EOPNOTSUPP; | |
320 | } | |
a9e9dd9c NC |
321 | } |
322 | ||
5c090abf NC |
323 | static int ina3221_write_chip(struct device *dev, u32 attr, long val) |
324 | { | |
325 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
326 | int ret, idx; | |
521c0b61 | 327 | u32 tmp; |
5c090abf NC |
328 | |
329 | switch (attr) { | |
330 | case hwmon_chip_samples: | |
331 | idx = find_closest(val, ina3221_avg_samples, | |
332 | ARRAY_SIZE(ina3221_avg_samples)); | |
333 | ||
521c0b61 NC |
334 | tmp = (ina->reg_config & ~INA3221_CONFIG_AVG_MASK) | |
335 | (idx << INA3221_CONFIG_AVG_SHIFT); | |
336 | ret = regmap_write(ina->regmap, INA3221_CONFIG, tmp); | |
5c090abf NC |
337 | if (ret) |
338 | return ret; | |
339 | ||
023912db NC |
340 | /* Update reg_config accordingly */ |
341 | ina->reg_config = tmp; | |
342 | return 0; | |
343 | case hwmon_chip_update_interval: | |
344 | tmp = ina3221_interval_ms_to_conv_time(ina->reg_config, val); | |
345 | idx = find_closest(tmp, ina3221_conv_time, | |
346 | ARRAY_SIZE(ina3221_conv_time)); | |
347 | ||
348 | /* Update Bus and Shunt voltage conversion times */ | |
349 | tmp = INA3221_CONFIG_VBUS_CT_MASK | INA3221_CONFIG_VSH_CT_MASK; | |
350 | tmp = (ina->reg_config & ~tmp) | | |
351 | (idx << INA3221_CONFIG_VBUS_CT_SHIFT) | | |
352 | (idx << INA3221_CONFIG_VSH_CT_SHIFT); | |
353 | ret = regmap_write(ina->regmap, INA3221_CONFIG, tmp); | |
354 | if (ret) | |
355 | return ret; | |
356 | ||
5c090abf | 357 | /* Update reg_config accordingly */ |
521c0b61 NC |
358 | ina->reg_config = tmp; |
359 | return 0; | |
5c090abf NC |
360 | default: |
361 | return -EOPNOTSUPP; | |
362 | } | |
363 | } | |
364 | ||
d4b0166d NC |
365 | static int ina3221_write_curr(struct device *dev, u32 attr, |
366 | int channel, long val) | |
a9e9dd9c | 367 | { |
a9e9dd9c | 368 | struct ina3221_data *ina = dev_get_drvdata(dev); |
d4b0166d NC |
369 | struct ina3221_input *input = &ina->inputs[channel]; |
370 | int resistance_uo = input->shunt_resistor; | |
371 | u8 reg = ina3221_curr_reg[attr][channel]; | |
372 | int regval, current_ma, voltage_uv; | |
373 | ||
374 | /* clamp current */ | |
375 | current_ma = clamp_val(val, | |
376 | INT_MIN / resistance_uo, | |
377 | INT_MAX / resistance_uo); | |
378 | ||
379 | voltage_uv = DIV_ROUND_CLOSEST(current_ma * resistance_uo, 1000); | |
380 | ||
381 | /* clamp voltage */ | |
382 | voltage_uv = clamp_val(voltage_uv, -163800, 163800); | |
383 | ||
384 | /* 1 / 40uV(scale) << 3(register shift) = 5 */ | |
385 | regval = DIV_ROUND_CLOSEST(voltage_uv, 5) & 0xfff8; | |
a9e9dd9c | 386 | |
d4b0166d | 387 | return regmap_write(ina->regmap, reg, regval); |
a9e9dd9c NC |
388 | } |
389 | ||
d4b0166d | 390 | static int ina3221_write_enable(struct device *dev, int channel, bool enable) |
a9e9dd9c | 391 | { |
a9e9dd9c | 392 | struct ina3221_data *ina = dev_get_drvdata(dev); |
a9e9dd9c | 393 | u16 config, mask = INA3221_CONFIG_CHx_EN(channel); |
323aeb0e | 394 | u16 config_old = ina->reg_config & mask; |
521c0b61 | 395 | u32 tmp; |
a9e9dd9c NC |
396 | int ret; |
397 | ||
a9e9dd9c NC |
398 | config = enable ? mask : 0; |
399 | ||
323aeb0e NC |
400 | /* Bypass if enable status is not being changed */ |
401 | if (config_old == config) | |
402 | return 0; | |
403 | ||
404 | /* For enabling routine, increase refcount and resume() at first */ | |
405 | if (enable) { | |
406 | ret = pm_runtime_get_sync(ina->pm_dev); | |
407 | if (ret < 0) { | |
408 | dev_err(dev, "Failed to get PM runtime\n"); | |
409 | return ret; | |
410 | } | |
411 | } | |
412 | ||
a9e9dd9c | 413 | /* Enable or disable the channel */ |
521c0b61 NC |
414 | tmp = (ina->reg_config & ~mask) | (config & mask); |
415 | ret = regmap_write(ina->regmap, INA3221_CONFIG, tmp); | |
a9e9dd9c | 416 | if (ret) |
323aeb0e | 417 | goto fail; |
a9e9dd9c NC |
418 | |
419 | /* Cache the latest config register value */ | |
521c0b61 | 420 | ina->reg_config = tmp; |
323aeb0e NC |
421 | |
422 | /* For disabling routine, decrease refcount or suspend() at last */ | |
423 | if (!enable) | |
424 | pm_runtime_put_sync(ina->pm_dev); | |
a9e9dd9c | 425 | |
d4b0166d | 426 | return 0; |
323aeb0e NC |
427 | |
428 | fail: | |
429 | if (enable) { | |
430 | dev_err(dev, "Failed to enable channel %d: error %d\n", | |
431 | channel, ret); | |
432 | pm_runtime_put_sync(ina->pm_dev); | |
433 | } | |
434 | ||
435 | return ret; | |
a9e9dd9c NC |
436 | } |
437 | ||
d4b0166d NC |
438 | static int ina3221_read(struct device *dev, enum hwmon_sensor_types type, |
439 | u32 attr, int channel, long *val) | |
7cb6dcff | 440 | { |
87625b24 NC |
441 | struct ina3221_data *ina = dev_get_drvdata(dev); |
442 | int ret; | |
443 | ||
444 | mutex_lock(&ina->lock); | |
445 | ||
d4b0166d | 446 | switch (type) { |
5c090abf NC |
447 | case hwmon_chip: |
448 | ret = ina3221_read_chip(dev, attr, val); | |
449 | break; | |
d4b0166d NC |
450 | case hwmon_in: |
451 | /* 0-align channel ID */ | |
87625b24 NC |
452 | ret = ina3221_read_in(dev, attr, channel - 1, val); |
453 | break; | |
d4b0166d | 454 | case hwmon_curr: |
87625b24 NC |
455 | ret = ina3221_read_curr(dev, attr, channel, val); |
456 | break; | |
d4b0166d | 457 | default: |
87625b24 NC |
458 | ret = -EOPNOTSUPP; |
459 | break; | |
d4b0166d | 460 | } |
87625b24 NC |
461 | |
462 | mutex_unlock(&ina->lock); | |
463 | ||
464 | return ret; | |
7cb6dcff AD |
465 | } |
466 | ||
d4b0166d NC |
467 | static int ina3221_write(struct device *dev, enum hwmon_sensor_types type, |
468 | u32 attr, int channel, long val) | |
7cb6dcff | 469 | { |
87625b24 NC |
470 | struct ina3221_data *ina = dev_get_drvdata(dev); |
471 | int ret; | |
472 | ||
473 | mutex_lock(&ina->lock); | |
474 | ||
d4b0166d | 475 | switch (type) { |
5c090abf NC |
476 | case hwmon_chip: |
477 | ret = ina3221_write_chip(dev, attr, val); | |
478 | break; | |
d4b0166d NC |
479 | case hwmon_in: |
480 | /* 0-align channel ID */ | |
87625b24 NC |
481 | ret = ina3221_write_enable(dev, channel - 1, val); |
482 | break; | |
d4b0166d | 483 | case hwmon_curr: |
87625b24 NC |
484 | ret = ina3221_write_curr(dev, attr, channel, val); |
485 | break; | |
d4b0166d | 486 | default: |
87625b24 NC |
487 | ret = -EOPNOTSUPP; |
488 | break; | |
d4b0166d | 489 | } |
87625b24 NC |
490 | |
491 | mutex_unlock(&ina->lock); | |
492 | ||
493 | return ret; | |
7cb6dcff AD |
494 | } |
495 | ||
d4b0166d NC |
496 | static int ina3221_read_string(struct device *dev, enum hwmon_sensor_types type, |
497 | u32 attr, int channel, const char **str) | |
7cb6dcff | 498 | { |
7cb6dcff | 499 | struct ina3221_data *ina = dev_get_drvdata(dev); |
d4b0166d | 500 | int index = channel - 1; |
7cb6dcff | 501 | |
d4b0166d | 502 | *str = ina->inputs[index].label; |
a9e9dd9c | 503 | |
d4b0166d | 504 | return 0; |
7cb6dcff AD |
505 | } |
506 | ||
d4b0166d NC |
507 | static umode_t ina3221_is_visible(const void *drvdata, |
508 | enum hwmon_sensor_types type, | |
509 | u32 attr, int channel) | |
7cb6dcff | 510 | { |
d4b0166d NC |
511 | const struct ina3221_data *ina = drvdata; |
512 | const struct ina3221_input *input = NULL; | |
513 | ||
514 | switch (type) { | |
5c090abf NC |
515 | case hwmon_chip: |
516 | switch (attr) { | |
517 | case hwmon_chip_samples: | |
023912db | 518 | case hwmon_chip_update_interval: |
5c090abf NC |
519 | return 0644; |
520 | default: | |
521 | return 0; | |
522 | } | |
d4b0166d NC |
523 | case hwmon_in: |
524 | /* Ignore in0_ */ | |
525 | if (channel == 0) | |
526 | return 0; | |
527 | ||
528 | switch (attr) { | |
529 | case hwmon_in_label: | |
530 | if (channel - 1 <= INA3221_CHANNEL3) | |
531 | input = &ina->inputs[channel - 1]; | |
532 | /* Hide label node if label is not provided */ | |
533 | return (input && input->label) ? 0444 : 0; | |
534 | case hwmon_in_input: | |
535 | return 0444; | |
536 | case hwmon_in_enable: | |
537 | return 0644; | |
538 | default: | |
539 | return 0; | |
540 | } | |
541 | case hwmon_curr: | |
542 | switch (attr) { | |
543 | case hwmon_curr_input: | |
544 | case hwmon_curr_crit_alarm: | |
545 | case hwmon_curr_max_alarm: | |
546 | return 0444; | |
547 | case hwmon_curr_crit: | |
548 | case hwmon_curr_max: | |
549 | return 0644; | |
550 | default: | |
551 | return 0; | |
552 | } | |
553 | default: | |
554 | return 0; | |
555 | } | |
7cb6dcff AD |
556 | } |
557 | ||
d4b0166d NC |
558 | #define INA3221_HWMON_CURR_CONFIG (HWMON_C_INPUT | \ |
559 | HWMON_C_CRIT | HWMON_C_CRIT_ALARM | \ | |
560 | HWMON_C_MAX | HWMON_C_MAX_ALARM) | |
7cb6dcff | 561 | |
d4b0166d | 562 | static const struct hwmon_channel_info *ina3221_info[] = { |
5c090abf | 563 | HWMON_CHANNEL_INFO(chip, |
023912db NC |
564 | HWMON_C_SAMPLES, |
565 | HWMON_C_UPDATE_INTERVAL), | |
6f307b7c GR |
566 | HWMON_CHANNEL_INFO(in, |
567 | /* 0: dummy, skipped in is_visible */ | |
568 | HWMON_I_INPUT, | |
569 | /* 1-3: input voltage Channels */ | |
570 | HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, | |
571 | HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, | |
572 | HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, | |
573 | /* 4-6: shunt voltage Channels */ | |
574 | HWMON_I_INPUT, | |
575 | HWMON_I_INPUT, | |
576 | HWMON_I_INPUT), | |
577 | HWMON_CHANNEL_INFO(curr, | |
578 | INA3221_HWMON_CURR_CONFIG, | |
579 | INA3221_HWMON_CURR_CONFIG, | |
580 | INA3221_HWMON_CURR_CONFIG), | |
d4b0166d NC |
581 | NULL |
582 | }; | |
7cb6dcff | 583 | |
d4b0166d NC |
584 | static const struct hwmon_ops ina3221_hwmon_ops = { |
585 | .is_visible = ina3221_is_visible, | |
586 | .read_string = ina3221_read_string, | |
587 | .read = ina3221_read, | |
588 | .write = ina3221_write, | |
589 | }; | |
7cb6dcff | 590 | |
d4b0166d NC |
591 | static const struct hwmon_chip_info ina3221_chip_info = { |
592 | .ops = &ina3221_hwmon_ops, | |
593 | .info = ina3221_info, | |
594 | }; | |
7cb6dcff | 595 | |
d4b0166d | 596 | /* Extra attribute groups */ |
a4ec92ed | 597 | static ssize_t ina3221_shunt_show(struct device *dev, |
7cb6dcff AD |
598 | struct device_attribute *attr, char *buf) |
599 | { | |
600 | struct sensor_device_attribute *sd_attr = to_sensor_dev_attr(attr); | |
601 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
602 | unsigned int channel = sd_attr->index; | |
a9e9dd9c | 603 | struct ina3221_input *input = &ina->inputs[channel]; |
7cb6dcff | 604 | |
a9e9dd9c | 605 | return snprintf(buf, PAGE_SIZE, "%d\n", input->shunt_resistor); |
7cb6dcff AD |
606 | } |
607 | ||
a4ec92ed GR |
608 | static ssize_t ina3221_shunt_store(struct device *dev, |
609 | struct device_attribute *attr, | |
610 | const char *buf, size_t count) | |
7cb6dcff AD |
611 | { |
612 | struct sensor_device_attribute *sd_attr = to_sensor_dev_attr(attr); | |
613 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
614 | unsigned int channel = sd_attr->index; | |
a9e9dd9c | 615 | struct ina3221_input *input = &ina->inputs[channel]; |
9ad0df1a | 616 | int val; |
7cb6dcff AD |
617 | int ret; |
618 | ||
9ad0df1a | 619 | ret = kstrtoint(buf, 0, &val); |
7cb6dcff AD |
620 | if (ret) |
621 | return ret; | |
622 | ||
9ad0df1a | 623 | val = clamp_val(val, 1, INT_MAX); |
7cb6dcff | 624 | |
a9e9dd9c | 625 | input->shunt_resistor = val; |
7cb6dcff AD |
626 | |
627 | return count; | |
628 | } | |
629 | ||
7cb6dcff | 630 | /* shunt resistance */ |
a4ec92ed GR |
631 | static SENSOR_DEVICE_ATTR_RW(shunt1_resistor, ina3221_shunt, INA3221_CHANNEL1); |
632 | static SENSOR_DEVICE_ATTR_RW(shunt2_resistor, ina3221_shunt, INA3221_CHANNEL2); | |
633 | static SENSOR_DEVICE_ATTR_RW(shunt3_resistor, ina3221_shunt, INA3221_CHANNEL3); | |
7cb6dcff | 634 | |
7cb6dcff | 635 | static struct attribute *ina3221_attrs[] = { |
7cb6dcff | 636 | &sensor_dev_attr_shunt1_resistor.dev_attr.attr, |
7cb6dcff | 637 | &sensor_dev_attr_shunt2_resistor.dev_attr.attr, |
7cb6dcff | 638 | &sensor_dev_attr_shunt3_resistor.dev_attr.attr, |
7cb6dcff AD |
639 | NULL, |
640 | }; | |
d4b0166d | 641 | ATTRIBUTE_GROUPS(ina3221); |
7cb6dcff AD |
642 | |
643 | static const struct regmap_range ina3221_yes_ranges[] = { | |
c20217b3 | 644 | regmap_reg_range(INA3221_CONFIG, INA3221_BUS3), |
7cb6dcff AD |
645 | regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE), |
646 | }; | |
647 | ||
648 | static const struct regmap_access_table ina3221_volatile_table = { | |
649 | .yes_ranges = ina3221_yes_ranges, | |
650 | .n_yes_ranges = ARRAY_SIZE(ina3221_yes_ranges), | |
651 | }; | |
652 | ||
653 | static const struct regmap_config ina3221_regmap_config = { | |
654 | .reg_bits = 8, | |
655 | .val_bits = 16, | |
656 | ||
657 | .cache_type = REGCACHE_RBTREE, | |
658 | .volatile_table = &ina3221_volatile_table, | |
659 | }; | |
660 | ||
a9e9dd9c NC |
661 | static int ina3221_probe_child_from_dt(struct device *dev, |
662 | struct device_node *child, | |
663 | struct ina3221_data *ina) | |
664 | { | |
665 | struct ina3221_input *input; | |
666 | u32 val; | |
667 | int ret; | |
668 | ||
669 | ret = of_property_read_u32(child, "reg", &val); | |
670 | if (ret) { | |
1b1f4efa | 671 | dev_err(dev, "missing reg property of %pOFn\n", child); |
a9e9dd9c NC |
672 | return ret; |
673 | } else if (val > INA3221_CHANNEL3) { | |
1b1f4efa | 674 | dev_err(dev, "invalid reg %d of %pOFn\n", val, child); |
a9e9dd9c NC |
675 | return ret; |
676 | } | |
677 | ||
678 | input = &ina->inputs[val]; | |
679 | ||
680 | /* Log the disconnected channel input */ | |
681 | if (!of_device_is_available(child)) { | |
682 | input->disconnected = true; | |
683 | return 0; | |
684 | } | |
685 | ||
686 | /* Save the connected input label if available */ | |
687 | of_property_read_string(child, "label", &input->label); | |
688 | ||
689 | /* Overwrite default shunt resistor value optionally */ | |
a6e43263 NC |
690 | if (!of_property_read_u32(child, "shunt-resistor-micro-ohms", &val)) { |
691 | if (val < 1 || val > INT_MAX) { | |
1b1f4efa RH |
692 | dev_err(dev, "invalid shunt resistor value %u of %pOFn\n", |
693 | val, child); | |
a6e43263 NC |
694 | return -EINVAL; |
695 | } | |
a9e9dd9c | 696 | input->shunt_resistor = val; |
a6e43263 | 697 | } |
a9e9dd9c NC |
698 | |
699 | return 0; | |
700 | } | |
701 | ||
702 | static int ina3221_probe_from_dt(struct device *dev, struct ina3221_data *ina) | |
703 | { | |
704 | const struct device_node *np = dev->of_node; | |
705 | struct device_node *child; | |
706 | int ret; | |
707 | ||
708 | /* Compatible with non-DT platforms */ | |
709 | if (!np) | |
710 | return 0; | |
711 | ||
43dece16 NC |
712 | ina->single_shot = of_property_read_bool(np, "ti,single-shot"); |
713 | ||
a9e9dd9c NC |
714 | for_each_child_of_node(np, child) { |
715 | ret = ina3221_probe_child_from_dt(dev, child, ina); | |
9f754657 ND |
716 | if (ret) { |
717 | of_node_put(child); | |
a9e9dd9c | 718 | return ret; |
9f754657 | 719 | } |
a9e9dd9c NC |
720 | } |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
7cb6dcff AD |
725 | static int ina3221_probe(struct i2c_client *client, |
726 | const struct i2c_device_id *id) | |
727 | { | |
728 | struct device *dev = &client->dev; | |
729 | struct ina3221_data *ina; | |
730 | struct device *hwmon_dev; | |
731 | int i, ret; | |
732 | ||
733 | ina = devm_kzalloc(dev, sizeof(*ina), GFP_KERNEL); | |
734 | if (!ina) | |
735 | return -ENOMEM; | |
736 | ||
737 | ina->regmap = devm_regmap_init_i2c(client, &ina3221_regmap_config); | |
738 | if (IS_ERR(ina->regmap)) { | |
739 | dev_err(dev, "Unable to allocate register map\n"); | |
740 | return PTR_ERR(ina->regmap); | |
741 | } | |
742 | ||
743 | for (i = 0; i < F_MAX_FIELDS; i++) { | |
744 | ina->fields[i] = devm_regmap_field_alloc(dev, | |
745 | ina->regmap, | |
746 | ina3221_reg_fields[i]); | |
747 | if (IS_ERR(ina->fields[i])) { | |
748 | dev_err(dev, "Unable to allocate regmap fields\n"); | |
749 | return PTR_ERR(ina->fields[i]); | |
750 | } | |
751 | } | |
752 | ||
753 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) | |
a9e9dd9c NC |
754 | ina->inputs[i].shunt_resistor = INA3221_RSHUNT_DEFAULT; |
755 | ||
756 | ret = ina3221_probe_from_dt(dev, ina); | |
757 | if (ret) { | |
758 | dev_err(dev, "Unable to probe from device tree\n"); | |
759 | return ret; | |
760 | } | |
7cb6dcff | 761 | |
323aeb0e NC |
762 | /* The driver will be reset, so use reset value */ |
763 | ina->reg_config = INA3221_CONFIG_DEFAULT; | |
a9e9dd9c | 764 | |
43dece16 NC |
765 | /* Clear continuous bit to use single-shot mode */ |
766 | if (ina->single_shot) | |
767 | ina->reg_config &= ~INA3221_CONFIG_MODE_CONTINUOUS; | |
768 | ||
a9e9dd9c NC |
769 | /* Disable channels if their inputs are disconnected */ |
770 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) { | |
771 | if (ina->inputs[i].disconnected) | |
772 | ina->reg_config &= ~INA3221_CONFIG_CHx_EN(i); | |
773 | } | |
a9e9dd9c | 774 | |
323aeb0e | 775 | ina->pm_dev = dev; |
87625b24 | 776 | mutex_init(&ina->lock); |
59d608e1 NC |
777 | dev_set_drvdata(dev, ina); |
778 | ||
323aeb0e NC |
779 | /* Enable PM runtime -- status is suspended by default */ |
780 | pm_runtime_enable(ina->pm_dev); | |
781 | ||
782 | /* Initialize (resume) the device */ | |
783 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) { | |
784 | if (ina->inputs[i].disconnected) | |
785 | continue; | |
786 | /* Match the refcount with number of enabled channels */ | |
787 | ret = pm_runtime_get_sync(ina->pm_dev); | |
788 | if (ret < 0) | |
789 | goto fail; | |
790 | } | |
791 | ||
d4b0166d NC |
792 | hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, ina, |
793 | &ina3221_chip_info, | |
794 | ina3221_groups); | |
7cb6dcff AD |
795 | if (IS_ERR(hwmon_dev)) { |
796 | dev_err(dev, "Unable to register hwmon device\n"); | |
323aeb0e NC |
797 | ret = PTR_ERR(hwmon_dev); |
798 | goto fail; | |
7cb6dcff AD |
799 | } |
800 | ||
801 | return 0; | |
323aeb0e NC |
802 | |
803 | fail: | |
804 | pm_runtime_disable(ina->pm_dev); | |
805 | pm_runtime_set_suspended(ina->pm_dev); | |
806 | /* pm_runtime_put_noidle() will decrease the PM refcount until 0 */ | |
807 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) | |
808 | pm_runtime_put_noidle(ina->pm_dev); | |
809 | mutex_destroy(&ina->lock); | |
810 | ||
811 | return ret; | |
7cb6dcff AD |
812 | } |
813 | ||
87625b24 NC |
814 | static int ina3221_remove(struct i2c_client *client) |
815 | { | |
816 | struct ina3221_data *ina = dev_get_drvdata(&client->dev); | |
323aeb0e NC |
817 | int i; |
818 | ||
819 | pm_runtime_disable(ina->pm_dev); | |
820 | pm_runtime_set_suspended(ina->pm_dev); | |
821 | ||
822 | /* pm_runtime_put_noidle() will decrease the PM refcount until 0 */ | |
823 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) | |
824 | pm_runtime_put_noidle(ina->pm_dev); | |
87625b24 NC |
825 | |
826 | mutex_destroy(&ina->lock); | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
ead21c77 | 831 | static int __maybe_unused ina3221_suspend(struct device *dev) |
59d608e1 NC |
832 | { |
833 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
834 | int ret; | |
835 | ||
836 | /* Save config register value and enable cache-only */ | |
837 | ret = regmap_read(ina->regmap, INA3221_CONFIG, &ina->reg_config); | |
838 | if (ret) | |
839 | return ret; | |
840 | ||
841 | /* Set to power-down mode for power saving */ | |
842 | ret = regmap_update_bits(ina->regmap, INA3221_CONFIG, | |
843 | INA3221_CONFIG_MODE_MASK, | |
844 | INA3221_CONFIG_MODE_POWERDOWN); | |
845 | if (ret) | |
846 | return ret; | |
847 | ||
848 | regcache_cache_only(ina->regmap, true); | |
849 | regcache_mark_dirty(ina->regmap); | |
850 | ||
851 | return 0; | |
852 | } | |
853 | ||
ead21c77 | 854 | static int __maybe_unused ina3221_resume(struct device *dev) |
59d608e1 NC |
855 | { |
856 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
857 | int ret; | |
858 | ||
859 | regcache_cache_only(ina->regmap, false); | |
860 | ||
861 | /* Software reset the chip */ | |
862 | ret = regmap_field_write(ina->fields[F_RST], true); | |
863 | if (ret) { | |
864 | dev_err(dev, "Unable to reset device\n"); | |
865 | return ret; | |
866 | } | |
867 | ||
868 | /* Restore cached register values to hardware */ | |
869 | ret = regcache_sync(ina->regmap); | |
870 | if (ret) | |
871 | return ret; | |
872 | ||
873 | /* Restore config register value to hardware */ | |
874 | ret = regmap_write(ina->regmap, INA3221_CONFIG, ina->reg_config); | |
875 | if (ret) | |
876 | return ret; | |
877 | ||
878 | return 0; | |
879 | } | |
59d608e1 NC |
880 | |
881 | static const struct dev_pm_ops ina3221_pm = { | |
323aeb0e NC |
882 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
883 | pm_runtime_force_resume) | |
884 | SET_RUNTIME_PM_OPS(ina3221_suspend, ina3221_resume, NULL) | |
59d608e1 NC |
885 | }; |
886 | ||
7cb6dcff AD |
887 | static const struct of_device_id ina3221_of_match_table[] = { |
888 | { .compatible = "ti,ina3221", }, | |
889 | { /* sentinel */ } | |
890 | }; | |
891 | MODULE_DEVICE_TABLE(of, ina3221_of_match_table); | |
892 | ||
893 | static const struct i2c_device_id ina3221_ids[] = { | |
894 | { "ina3221", 0 }, | |
895 | { /* sentinel */ } | |
896 | }; | |
897 | MODULE_DEVICE_TABLE(i2c, ina3221_ids); | |
898 | ||
899 | static struct i2c_driver ina3221_i2c_driver = { | |
900 | .probe = ina3221_probe, | |
87625b24 | 901 | .remove = ina3221_remove, |
7cb6dcff AD |
902 | .driver = { |
903 | .name = INA3221_DRIVER_NAME, | |
904 | .of_match_table = ina3221_of_match_table, | |
59d608e1 | 905 | .pm = &ina3221_pm, |
7cb6dcff AD |
906 | }, |
907 | .id_table = ina3221_ids, | |
908 | }; | |
909 | module_i2c_driver(ina3221_i2c_driver); | |
910 | ||
911 | MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>"); | |
912 | MODULE_DESCRIPTION("Texas Instruments INA3221 HWMon Driver"); | |
913 | MODULE_LICENSE("GPL v2"); |