[linux-2.6-block.git] / drivers / hwmon / fam15h_power.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * fam15h_power.c - AMD Family 15h processor power monitoring
 *
 * Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
 * Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
 */

#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/bitops.h>
#include <linux/cpu.h>
#include <linux/cpumask.h>
#include <linux/time.h>
#include <linux/sched.h>
#include <linux/topology.h>
#include <asm/processor.h>
#include <asm/msr.h>

MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
MODULE_LICENSE("GPL");

/* D18F3 */
#define REG_NORTHBRIDGE_CAP		0xe8

/* D18F4 */
#define REG_PROCESSOR_TDP		0x1b8

/* D18F5 */
#define REG_TDP_RUNNING_AVERAGE		0xe0
#define REG_TDP_LIMIT3			0xe8

#define FAM15H_MIN_NUM_ATTRS		2
#define FAM15H_NUM_GROUPS		2
#define MAX_CUS				8

/* set maximum interval as 1 second */
#define MAX_INTERVAL			1000

#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4

struct fam15h_power_data {
	struct pci_dev *pdev;
	unsigned int tdp_to_watts;
	unsigned int base_tdp;
	unsigned int processor_pwr_watts;
	unsigned int cpu_pwr_sample_ratio;
	const struct attribute_group *groups[FAM15H_NUM_GROUPS];
	struct attribute_group group;
	/* maximum accumulated power of a compute unit */
	u64 max_cu_acc_power;
	/* accumulated power of the compute units */
	u64 cu_acc_power[MAX_CUS];
	/* performance timestamp counter */
	u64 cpu_sw_pwr_ptsc[MAX_CUS];
	/* online/offline status of current compute unit */
	int cu_on[MAX_CUS];
	unsigned long power_period;
};

static bool is_carrizo_or_later(void)
{
	return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
}

static ssize_t power1_input_show(struct device *dev,
				 struct device_attribute *attr, char *buf)
{
	u32 val, tdp_limit, running_avg_range;
	s32 running_avg_capture;
	u64 curr_pwr_watts;
	struct fam15h_power_data *data = dev_get_drvdata(dev);
	struct pci_dev *f4 = data->pdev;

	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
				  REG_TDP_RUNNING_AVERAGE, &val);

	/*
	 * On Carrizo and later platforms, TdpRunAvgAccCap bit field
	 * is extended to 4:31 from 4:25.
	 */
	if (is_carrizo_or_later()) {
		running_avg_capture = val >> 4;
		running_avg_capture = sign_extend32(running_avg_capture, 27);
	} else {
		running_avg_capture = (val >> 4) & 0x3fffff;
		running_avg_capture = sign_extend32(running_avg_capture, 21);
	}

	running_avg_range = (val & 0xf) + 1;

	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
				  REG_TDP_LIMIT3, &val);

	/*
	 * On Carrizo and later platforms, ApmTdpLimit bit field
	 * is extended to 16:31 from 16:28.
	 */
	if (is_carrizo_or_later())
		tdp_limit = val >> 16;
	else
		tdp_limit = (val >> 16) & 0x1fff;

	curr_pwr_watts = ((u64)(tdp_limit +
				data->base_tdp)) << running_avg_range;
	curr_pwr_watts -= running_avg_capture;
	curr_pwr_watts *= data->tdp_to_watts;

	/*
	 * Convert to microWatt
	 *
	 * power is in Watt provided as fixed point integer with
	 * scaling factor 1/(2^16).  For conversion we use
	 * (10^6)/(2^16) = 15625/(2^10)
	 */
	curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
	return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
}
static DEVICE_ATTR_RO(power1_input);

static ssize_t power1_crit_show(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	struct fam15h_power_data *data = dev_get_drvdata(dev);

	return sprintf(buf, "%u\n", data->processor_pwr_watts);
}
static DEVICE_ATTR_RO(power1_crit);

static void do_read_registers_on_cu(void *_data)
{
	struct fam15h_power_data *data = _data;
	int cu;

	/*
	 * With the new x86 topology modelling, cpu core id actually
	 * is compute unit id.
	 */
	cu = topology_core_id(smp_processor_id());

	rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
	rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);

	data->cu_on[cu] = 1;
}

/*
 * This function is only able to be called when CPUID
 * Fn8000_0007:EDX[12] is set.
 */
static int read_registers(struct fam15h_power_data *data)
{
	int core, this_core;
	cpumask_var_t mask;
	int ret, cpu;

	ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
	if (!ret)
		return -ENOMEM;

	memset(data->cu_on, 0, sizeof(int) * MAX_CUS);

	cpus_read_lock();

	/*
	 * Choose the first online core of each compute unit, and then
	 * read their MSR value of power and ptsc in a single IPI,
	 * because the MSR value of CPU core represent the compute
	 * unit's.
	 */
	core = -1;

	for_each_online_cpu(cpu) {
		this_core = topology_core_id(cpu);

		if (this_core == core)
			continue;

		core = this_core;

		/* get any CPU on this compute unit */
		cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
	}

	on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);

	cpus_read_unlock();
	free_cpumask_var(mask);

	return 0;
}

static ssize_t power1_average_show(struct device *dev,
				   struct device_attribute *attr, char *buf)
{
	struct fam15h_power_data *data = dev_get_drvdata(dev);
	u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
	    jdelta[MAX_CUS];
	u64 tdelta, avg_acc;
	int cu, cu_num, ret;
	signed long leftover;

	/*
	 * With the new x86 topology modelling, x86_max_cores is the
	 * compute unit number.
	 */
	cu_num = topology_num_cores_per_package();

	ret = read_registers(data);
	if (ret)
		return 0;

	for (cu = 0; cu < cu_num; cu++) {
		prev_cu_acc_power[cu] = data->cu_acc_power[cu];
		prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
	}

	leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
	if (leftover)
		return 0;

	ret = read_registers(data);
	if (ret)
		return 0;

	for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
		/* check if current compute unit is online */
		if (data->cu_on[cu] == 0)
			continue;

		if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
			jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
			jdelta[cu] -= prev_cu_acc_power[cu];
		} else {
			jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
		}
		tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
		jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000;
		do_div(jdelta[cu], tdelta);

		/* the unit is microWatt */
		avg_acc += jdelta[cu];
	}

	return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
}
static DEVICE_ATTR_RO(power1_average);

static ssize_t power1_average_interval_show(struct device *dev,
					    struct device_attribute *attr,
					    char *buf)
{
	struct fam15h_power_data *data = dev_get_drvdata(dev);

	return sprintf(buf, "%lu\n", data->power_period);
}

static ssize_t power1_average_interval_store(struct device *dev,
					     struct device_attribute *attr,
					     const char *buf, size_t count)
{
	struct fam15h_power_data *data = dev_get_drvdata(dev);
	unsigned long temp;
	int ret;

	ret = kstrtoul(buf, 10, &temp);
	if (ret)
		return ret;

	if (temp > MAX_INTERVAL)
		return -EINVAL;

	/* the interval value should be greater than 0 */
	if (temp <= 0)
		return -EINVAL;

	data->power_period = temp;

	return count;
}
static DEVICE_ATTR_RW(power1_average_interval);

static int fam15h_power_init_attrs(struct pci_dev *pdev,
				   struct fam15h_power_data *data)
{
	int n = FAM15H_MIN_NUM_ATTRS;
	struct attribute **fam15h_power_attrs;
	struct cpuinfo_x86 *c = &boot_cpu_data;

	if (c->x86 == 0x15 &&
	    (c->x86_model <= 0xf ||
	     (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
		n += 1;

	/* check if processor supports accumulated power */
	if (boot_cpu_has(X86_FEATURE_ACC_POWER))
		n += 2;

	fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
					  sizeof(*fam15h_power_attrs),
					  GFP_KERNEL);

	if (!fam15h_power_attrs)
		return -ENOMEM;

	n = 0;
	fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
	if (c->x86 == 0x15 &&
	    (c->x86_model <= 0xf ||
	     (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
		fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;

	if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
		fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
		fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
	}

	data->group.attrs = fam15h_power_attrs;

	return 0;
}

static bool should_load_on_this_node(struct pci_dev *f4)
{
	u32 val;

	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
				  REG_NORTHBRIDGE_CAP, &val);
	if ((val & BIT(29)) && ((val >> 30) & 3))
		return false;

	return true;
}

/*
 * Newer BKDG versions have an updated recommendation on how to properly
 * initialize the running average range (was: 0xE, now: 0x9). This avoids
 * counter saturations resulting in bogus power readings.
 * We correct this value ourselves to cope with older BIOSes.
 */
static const struct pci_device_id affected_device[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
	{ 0 }
};

static void tweak_runavg_range(struct pci_dev *pdev)
{
	u32 val;

	/*
	 * let this quirk apply only to the current version of the
	 * northbridge, since future versions may change the behavior
	 */
	if (!pci_match_id(affected_device, pdev))
		return;

	pci_bus_read_config_dword(pdev->bus,
		PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
		REG_TDP_RUNNING_AVERAGE, &val);
	if ((val & 0xf) != 0xe)
		return;

	val &= ~0xf;
	val |=  0x9;
	pci_bus_write_config_dword(pdev->bus,
		PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
		REG_TDP_RUNNING_AVERAGE, val);
}

#ifdef CONFIG_PM
static int fam15h_power_resume(struct pci_dev *pdev)
{
	tweak_runavg_range(pdev);
	return 0;
}
#else
#define fam15h_power_resume NULL
#endif

static int fam15h_power_init_data(struct pci_dev *f4,
				  struct fam15h_power_data *data)
{
	u32 val;
	u64 tmp;
	int ret;

	pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
	data->base_tdp = val >> 16;
	tmp = val & 0xffff;

	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
				  REG_TDP_LIMIT3, &val);

	data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
	tmp *= data->tdp_to_watts;

	/* result not allowed to be >= 256W */
	if ((tmp >> 16) >= 256)
		dev_warn(&f4->dev,
			 "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
			 (unsigned int) (tmp >> 16));

	/* convert to microWatt */
	data->processor_pwr_watts = (tmp * 15625) >> 10;

	ret = fam15h_power_init_attrs(f4, data);
	if (ret)
		return ret;


	/* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
	if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
		return 0;

	/*
	 * determine the ratio of the compute unit power accumulator
	 * sample period to the PTSC counter period by executing CPUID
	 * Fn8000_0007:ECX
	 */
	data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);

	if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
		pr_err("Failed to read max compute unit power accumulator MSR\n");
		return -ENODEV;
	}

	data->max_cu_acc_power = tmp;

	/*
	 * Milliseconds are a reasonable interval for the measurement.
	 * But it shouldn't set too long here, because several seconds
	 * would cause the read function to hang. So set default
	 * interval as 10 ms.
	 */
	data->power_period = 10;

	return read_registers(data);
}

static int fam15h_power_probe(struct pci_dev *pdev,
			      const struct pci_device_id *id)
{
	struct fam15h_power_data *data;
	struct device *dev = &pdev->dev;
	struct device *hwmon_dev;
	int ret;

	/*
	 * though we ignore every other northbridge, we still have to
	 * do the tweaking on _each_ node in MCM processors as the counters
	 * are working hand-in-hand
	 */
	tweak_runavg_range(pdev);

	if (!should_load_on_this_node(pdev))
		return -ENODEV;

	data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	ret = fam15h_power_init_data(pdev, data);
	if (ret)
		return ret;

	data->pdev = pdev;

	data->groups[0] = &data->group;

	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
							   data,
							   &data->groups[0]);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static const struct pci_device_id fam15h_power_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
	{}
};
MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);

static struct pci_driver fam15h_power_driver = {
	.name = "fam15h_power",
	.id_table = fam15h_power_id_table,
	.probe = fam15h_power_probe,
	.resume = fam15h_power_resume,
};

module_pci_driver(fam15h_power_driver);
Commit	Line	Data
6e7c1094	1	// SPDX-License-Identifier: GPL-2.0-or-later
512d1027 AH	2	/*
	3	* fam15h_power.c - AMD Family 15h processor power monitoring
	4	*
a6e232f7	5	* Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
d034fbf0	6	* Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
512d1027 AH	7	*/
	8
	9	#include <linux/err.h>
	10	#include <linux/hwmon.h>
	11	#include <linux/hwmon-sysfs.h>
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/pci.h>
	15	#include <linux/bitops.h>
fa794344 HR	16	#include <linux/cpu.h>
fa794344 HR	17	#include <linux/cpumask.h>
11bf0d78 HR	18	#include <linux/time.h>
11bf0d78 HR	19	#include <linux/sched.h>
94f0b397	20	#include <linux/topology.h>
512d1027	21	#include <asm/processor.h>
3b5ea47d	22	#include <asm/msr.h>
512d1027 AH	23
512d1027 AH	24	MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
d034fbf0	25	MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
512d1027 AH	26	MODULE_LICENSE("GPL");
	27
	28	/* D18F3 */
	29	#define REG_NORTHBRIDGE_CAP 0xe8
	30
	31	/* D18F4 */
	32	#define REG_PROCESSOR_TDP 0x1b8
	33
	34	/* D18F5 */
	35	#define REG_TDP_RUNNING_AVERAGE 0xe0
	36	#define REG_TDP_LIMIT3 0xe8
	37
7deb14b1 HR	38	#define FAM15H_MIN_NUM_ATTRS 2
7deb14b1 HR	39	#define FAM15H_NUM_GROUPS 2
fa794344	40	#define MAX_CUS 8
7deb14b1	41
11bf0d78 HR	42	/* set maximum interval as 1 second */
	43	#define MAX_INTERVAL 1000
	44
eff2a945 HR	45	#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
eff2a945 HR	46
512d1027	47	struct fam15h_power_data {
562dc973	48	struct pci_dev *pdev;
512d1027 AH	49	unsigned int tdp_to_watts;
	50	unsigned int base_tdp;
	51	unsigned int processor_pwr_watts;
1ed32160	52	unsigned int cpu_pwr_sample_ratio;
7deb14b1 HR	53	const struct attribute_group *groups[FAM15H_NUM_GROUPS];
7deb14b1 HR	54	struct attribute_group group;
3b5ea47d HR	55	/* maximum accumulated power of a compute unit */
3b5ea47d HR	56	u64 max_cu_acc_power;
fa794344 HR	57	/* accumulated power of the compute units */
fa794344 HR	58	u64 cu_acc_power[MAX_CUS];
cdb9e110 HR	59	/* performance timestamp counter */
cdb9e110 HR	60	u64 cpu_sw_pwr_ptsc[MAX_CUS];
11bf0d78 HR	61	/* online/offline status of current compute unit */
	62	int cu_on[MAX_CUS];
	63	unsigned long power_period;
512d1027 AH	64	};
512d1027 AH	65
1d28e016 HR	66	static bool is_carrizo_or_later(void)
	67	{
	68	return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
	69	}
	70
d013f7f5 JL	71	static ssize_t power1_input_show(struct device *dev,
d013f7f5 JL	72	struct device_attribute attr, char buf)
512d1027 AH	73	{
	74	u32 val, tdp_limit, running_avg_range;
	75	s32 running_avg_capture;
	76	u64 curr_pwr_watts;
512d1027	77	struct fam15h_power_data *data = dev_get_drvdata(dev);
562dc973	78	struct pci_dev *f4 = data->pdev;
512d1027 AH	79
	80	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
	81	REG_TDP_RUNNING_AVERAGE, &val);
e9cd4d55 HR	82
	83	/*
	84	* On Carrizo and later platforms, TdpRunAvgAccCap bit field
	85	* is extended to 4:31 from 4:25.
	86	*/
1d28e016	87	if (is_carrizo_or_later()) {
e9cd4d55 HR	88	running_avg_capture = val >> 4;
	89	running_avg_capture = sign_extend32(running_avg_capture, 27);
	90	} else {
	91	running_avg_capture = (val >> 4) & 0x3fffff;
	92	running_avg_capture = sign_extend32(running_avg_capture, 21);
	93	}
	94
941a956b	95	running_avg_range = (val & 0xf) + 1;
512d1027 AH	96
	97	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
	98	REG_TDP_LIMIT3, &val);
	99
60dee3ca GK	100	/*
	101	* On Carrizo and later platforms, ApmTdpLimit bit field
	102	* is extended to 16:31 from 16:28.
	103	*/
1d28e016	104	if (is_carrizo_or_later())
60dee3ca GK	105	tdp_limit = val >> 16;
	106	else
	107	tdp_limit = (val >> 16) & 0x1fff;
	108
62867d49 GR	109	curr_pwr_watts = ((u64)(tdp_limit +
62867d49 GR	110	data->base_tdp)) << running_avg_range;
941a956b	111	curr_pwr_watts -= running_avg_capture;
512d1027 AH	112	curr_pwr_watts *= data->tdp_to_watts;
	113
	114	/*
	115	* Convert to microWatt
	116	*
	117	* power is in Watt provided as fixed point integer with
	118	* scaling factor 1/(2^16). For conversion we use
	119	* (10^6)/(2^16) = 15625/(2^10)
	120	*/
941a956b	121	curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
512d1027 AH	122	return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
512d1027 AH	123	}
d013f7f5	124	static DEVICE_ATTR_RO(power1_input);
512d1027	125
d013f7f5 JL	126	static ssize_t power1_crit_show(struct device *dev,
d013f7f5 JL	127	struct device_attribute attr, char buf)
512d1027 AH	128	{
	129	struct fam15h_power_data *data = dev_get_drvdata(dev);
	130
	131	return sprintf(buf, "%u\n", data->processor_pwr_watts);
	132	}
d013f7f5	133	static DEVICE_ATTR_RO(power1_crit);
512d1027	134
fa794344 HR	135	static void do_read_registers_on_cu(void *_data)
	136	{
	137	struct fam15h_power_data *data = _data;
94f0b397	138	int cu;
fa794344 HR	139
	140	/*
	141	* With the new x86 topology modelling, cpu core id actually
	142	* is compute unit id.
	143	*/
94f0b397	144	cu = topology_core_id(smp_processor_id());
fa794344 HR	145
fa794344 HR	146	rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
cdb9e110	147	rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);
11bf0d78 HR	148
11bf0d78 HR	149	data->cu_on[cu] = 1;
fa794344 HR	150	}
	151
	152	/*
	153	* This function is only able to be called when CPUID
	154	* Fn8000_0007:EDX[12] is set.
	155	*/
	156	static int read_registers(struct fam15h_power_data *data)
	157	{
fa794344 HR	158	int core, this_core;
fa794344 HR	159	cpumask_var_t mask;
7be48818	160	int ret, cpu;
fa794344 HR	161
	162	ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
	163	if (!ret)
	164	return -ENOMEM;
	165
11bf0d78 HR	166	memset(data->cu_on, 0, sizeof(int) * MAX_CUS);
11bf0d78 HR	167
e104d530	168	cpus_read_lock();
fa794344 HR	169
	170	/*
	171	* Choose the first online core of each compute unit, and then
	172	* read their MSR value of power and ptsc in a single IPI,
	173	* because the MSR value of CPU core represent the compute
	174	* unit's.
	175	*/
	176	core = -1;
	177
	178	for_each_online_cpu(cpu) {
	179	this_core = topology_core_id(cpu);
	180
	181	if (this_core == core)
	182	continue;
	183
	184	core = this_core;
	185
	186	/* get any CPU on this compute unit */
	187	cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
	188	}
	189
7be48818	190	on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);
fa794344	191
e104d530	192	cpus_read_unlock();
fa794344 HR	193	free_cpumask_var(mask);
	194
	195	return 0;
	196	}
	197
d013f7f5 JL	198	static ssize_t power1_average_show(struct device *dev,
d013f7f5 JL	199	struct device_attribute attr, char buf)
11bf0d78 HR	200	{
	201	struct fam15h_power_data *data = dev_get_drvdata(dev);
	202	u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
	203	jdelta[MAX_CUS];
	204	u64 tdelta, avg_acc;
	205	int cu, cu_num, ret;
	206	signed long leftover;
	207
	208	/*
	209	* With the new x86 topology modelling, x86_max_cores is the
	210	* compute unit number.
	211	*/
89b0f15f	212	cu_num = topology_num_cores_per_package();
11bf0d78 HR	213
	214	ret = read_registers(data);
	215	if (ret)
	216	return 0;
	217
	218	for (cu = 0; cu < cu_num; cu++) {
	219	prev_cu_acc_power[cu] = data->cu_acc_power[cu];
	220	prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
	221	}
	222
	223	leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
	224	if (leftover)
	225	return 0;
	226
	227	ret = read_registers(data);
	228	if (ret)
	229	return 0;
	230
	231	for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
	232	/* check if current compute unit is online */
	233	if (data->cu_on[cu] == 0)
	234	continue;
	235
	236	if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
	237	jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
	238	jdelta[cu] -= prev_cu_acc_power[cu];
	239	} else {
	240	jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
	241	}
	242	tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
	243	jdelta[cu] = data->cpu_pwr_sample_ratio 1000;
	244	do_div(jdelta[cu], tdelta);
	245
	246	/* the unit is microWatt */
	247	avg_acc += jdelta[cu];
	248	}
	249
	250	return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
	251	}
d013f7f5	252	static DEVICE_ATTR_RO(power1_average);
11bf0d78	253
d013f7f5 JL	254	static ssize_t power1_average_interval_show(struct device *dev,
	255	struct device_attribute *attr,
	256	char *buf)
11bf0d78 HR	257	{
	258	struct fam15h_power_data *data = dev_get_drvdata(dev);
	259
	260	return sprintf(buf, "%lu\n", data->power_period);
	261	}
	262
d013f7f5 JL	263	static ssize_t power1_average_interval_store(struct device *dev,
	264	struct device_attribute *attr,
	265	const char *buf, size_t count)
11bf0d78 HR	266	{
	267	struct fam15h_power_data *data = dev_get_drvdata(dev);
	268	unsigned long temp;
	269	int ret;
	270
	271	ret = kstrtoul(buf, 10, &temp);
	272	if (ret)
	273	return ret;
	274
	275	if (temp > MAX_INTERVAL)
	276	return -EINVAL;
	277
	278	/* the interval value should be greater than 0 */
	279	if (temp <= 0)
	280	return -EINVAL;
	281
	282	data->power_period = temp;
	283
	284	return count;
	285	}
d013f7f5	286	static DEVICE_ATTR_RW(power1_average_interval);
11bf0d78	287
7deb14b1 HR	288	static int fam15h_power_init_attrs(struct pci_dev *pdev,
7deb14b1 HR	289	struct fam15h_power_data *data)
961a2378	290	{
7deb14b1 HR	291	int n = FAM15H_MIN_NUM_ATTRS;
7deb14b1 HR	292	struct attribute **fam15h_power_attrs;
46f29c2b	293	struct cpuinfo_x86 *c = &boot_cpu_data;
961a2378	294
46f29c2b HR	295	if (c->x86 == 0x15 &&
46f29c2b HR	296	(c->x86_model <= 0xf \|\|
eff2a945	297	(c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
7deb14b1	298	n += 1;
961a2378	299
11bf0d78 HR	300	/* check if processor supports accumulated power */
	301	if (boot_cpu_has(X86_FEATURE_ACC_POWER))
	302	n += 2;
	303
7deb14b1 HR	304	fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
	305	sizeof(*fam15h_power_attrs),
	306	GFP_KERNEL);
512d1027	307
7deb14b1 HR	308	if (!fam15h_power_attrs)
	309	return -ENOMEM;
	310
	311	n = 0;
	312	fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
46f29c2b HR	313	if (c->x86 == 0x15 &&
46f29c2b HR	314	(c->x86_model <= 0xf \|\|
eff2a945	315	(c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
7deb14b1 HR	316	fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
7deb14b1 HR	317
11bf0d78 HR	318	if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
	319	fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
	320	fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
	321	}
	322
7deb14b1 HR	323	data->group.attrs = fam15h_power_attrs;
	324
	325	return 0;
	326	}
512d1027	327
d83e92b3	328	static bool should_load_on_this_node(struct pci_dev *f4)
512d1027 AH	329	{
	330	u32 val;
	331
	332	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
	333	REG_NORTHBRIDGE_CAP, &val);
	334	if ((val & BIT(29)) && ((val >> 30) & 3))
	335	return false;
	336
	337	return true;
	338	}
	339
00250ec9 AP	340	/*
	341	* Newer BKDG versions have an updated recommendation on how to properly
	342	* initialize the running average range (was: 0xE, now: 0x9). This avoids
	343	* counter saturations resulting in bogus power readings.
	344	* We correct this value ourselves to cope with older BIOSes.
	345	*/
5f0ecb90	346	static const struct pci_device_id affected_device[] = {
c3e40a99 GR	347	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
	348	{ 0 }
	349	};
	350
5f0ecb90	351	static void tweak_runavg_range(struct pci_dev *pdev)
00250ec9 AP	352	{
00250ec9 AP	353	u32 val;
00250ec9 AP	354
	355	/*
	356	* let this quirk apply only to the current version of the
	357	* northbridge, since future versions may change the behavior
	358	*/
c3e40a99	359	if (!pci_match_id(affected_device, pdev))
00250ec9 AP	360	return;
	361
	362	pci_bus_read_config_dword(pdev->bus,
	363	PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
	364	REG_TDP_RUNNING_AVERAGE, &val);
	365	if ((val & 0xf) != 0xe)
	366	return;
	367
	368	val &= ~0xf;
	369	val \|= 0x9;
	370	pci_bus_write_config_dword(pdev->bus,
	371	PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
	372	REG_TDP_RUNNING_AVERAGE, val);
	373	}
	374
5f0ecb90 AH	375	#ifdef CONFIG_PM
	376	static int fam15h_power_resume(struct pci_dev *pdev)
	377	{
	378	tweak_runavg_range(pdev);
	379	return 0;
	380	}
	381	#else
	382	#define fam15h_power_resume NULL
	383	#endif
	384
7deb14b1 HR	385	static int fam15h_power_init_data(struct pci_dev *f4,
7deb14b1 HR	386	struct fam15h_power_data *data)
512d1027	387	{
11bf0d78	388	u32 val;
512d1027	389	u64 tmp;
7deb14b1	390	int ret;
512d1027 AH	391
	392	pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
	393	data->base_tdp = val >> 16;
	394	tmp = val & 0xffff;
	395
	396	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
	397	REG_TDP_LIMIT3, &val);
	398
	399	data->tdp_to_watts = ((val & 0x3ff) << 6) \| ((val >> 10) & 0x3f);
	400	tmp *= data->tdp_to_watts;
	401
	402	/* result not allowed to be >= 256W */
	403	if ((tmp >> 16) >= 256)
b55f3757 GR	404	dev_warn(&f4->dev,
b55f3757 GR	405	"Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
512d1027 AH	406	(unsigned int) (tmp >> 16));
	407
	408	/* convert to microWatt */
	409	data->processor_pwr_watts = (tmp * 15625) >> 10;
1ed32160	410
7deb14b1 HR	411	ret = fam15h_power_init_attrs(f4, data);
	412	if (ret)
	413	return ret;
	414
1ed32160 HR	415
1ed32160 HR	416	/* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
11bf0d78	417	if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
7deb14b1	418	return 0;
1ed32160 HR	419
	420	/*
	421	* determine the ratio of the compute unit power accumulator
	422	* sample period to the PTSC counter period by executing CPUID
	423	* Fn8000_0007:ECX
	424	*/
11bf0d78	425	data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
7deb14b1	426
3b5ea47d HR	427	if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
	428	pr_err("Failed to read max compute unit power accumulator MSR\n");
	429	return -ENODEV;
	430	}
	431
	432	data->max_cu_acc_power = tmp;
	433
11bf0d78 HR	434	/*
	435	* Milliseconds are a reasonable interval for the measurement.
	436	* But it shouldn't set too long here, because several seconds
	437	* would cause the read function to hang. So set default
	438	* interval as 10 ms.
	439	*/
	440	data->power_period = 10;
	441
fa794344	442	return read_registers(data);
512d1027 AH	443	}
512d1027 AH	444
6c931ae1	445	static int fam15h_power_probe(struct pci_dev *pdev,
7deb14b1	446	const struct pci_device_id *id)
512d1027 AH	447	{
512d1027 AH	448	struct fam15h_power_data *data;
87432a2e	449	struct device *dev = &pdev->dev;
562dc973	450	struct device *hwmon_dev;
7deb14b1	451	int ret;
512d1027	452
00250ec9 AP	453	/*
	454	* though we ignore every other northbridge, we still have to
	455	* do the tweaking on _each_ node in MCM processors as the counters
	456	* are working hand-in-hand
	457	*/
	458	tweak_runavg_range(pdev);
	459
d83e92b3	460	if (!should_load_on_this_node(pdev))
87432a2e GR	461	return -ENODEV;
	462
	463	data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
	464	if (!data)
	465	return -ENOMEM;
512d1027	466
7deb14b1 HR	467	ret = fam15h_power_init_data(pdev, data);
	468	if (ret)
	469	return ret;
	470
562dc973	471	data->pdev = pdev;
512d1027	472
7deb14b1 HR	473	data->groups[0] = &data->group;
7deb14b1 HR	474
562dc973 AL	475	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
562dc973 AL	476	data,
7deb14b1	477	&data->groups[0]);
562dc973	478	return PTR_ERR_OR_ZERO(hwmon_dev);
512d1027 AH	479	}
512d1027 AH	480
cd9bb056	481	static const struct pci_device_id fam15h_power_id_table[] = {
512d1027	482	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
0a0039ad	483	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
5dc08725	484	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
eff2a945	485	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
22e32f4f	486	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
0bd52941	487	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
512d1027 AH	488	{}
	489	};
	490	MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
	491
	492	static struct pci_driver fam15h_power_driver = {
	493	.name = "fam15h_power",
	494	.id_table = fam15h_power_id_table,
	495	.probe = fam15h_power_probe,
5f0ecb90	496	.resume = fam15h_power_resume,
512d1027 AH	497	};
512d1027 AH	498
f71f5a55	499	module_pci_driver(fam15h_power_driver);