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hwmon: (emc1403) Add EMC1423 support
[linux-2.6-block.git] / drivers / hwmon / dme1737.c
CommitLineData
9431996f 1/*
ea694431
JH		 2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027,
3 * and SCH5127 Super-I/O chips integrated hardware monitoring
4 * features.
5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com>
9431996f 6 *
e95c237d 7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access
549edb83 8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus
ea694431
JH		 9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very
10 * similar hardware monitoring capabilities but differ in the way they can be
11 * accessed.
9431996f
JH		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
9c6e13b4
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9431996f
JH		 30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/slab.h>
33#include <linux/jiffies.h>
34#include <linux/i2c.h>
e95c237d 35#include <linux/platform_device.h>
9431996f
JH		 36#include <linux/hwmon.h>
37#include <linux/hwmon-sysfs.h>
38#include <linux/hwmon-vid.h>
39#include <linux/err.h>
40#include <linux/mutex.h>
b9acb64a 41#include <linux/acpi.h>
6055fae8 42#include <linux/io.h>
9431996f 43
e95c237d
JH		 44/* ISA device, if found */
45static struct platform_device *pdev;
46
9431996f
JH		 47/* Module load parameters */
48static int force_start;
49module_param(force_start, bool, 0);
50MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs");
51
67b671bc
JD		 52static unsigned short force_id;
53module_param(force_id, ushort, 0);
54MODULE_PARM_DESC(force_id, "Override the detected device ID");
55
92430b6f
JH		 56static int probe_all_addr;
57module_param(probe_all_addr, bool, 0);
58MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC "
59 "addresses");
60
9431996f 61/* Addresses to scan */
25e9c86d 62static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END};
9431996f 63
ea694431 64enum chips { dme1737, sch5027, sch311x, sch5127 };
9431996f
JH		 65
66/* ---------------------------------------------------------------------
67 * Registers
68 *
69 * The sensors are defined as follows:
70 *
71 * Voltages Temperatures
72 * -------- ------------
73 * in0 +5VTR (+5V stdby) temp1 Remote diode 1
74 * in1 Vccp (proc core) temp2 Internal temp
75 * in2 VCC (internal +3.3V) temp3 Remote diode 2
76 * in3 +5V
77 * in4 +12V
78 * in5 VTR (+3.3V stby)
79 * in6 Vbat
80 *
81 * --------------------------------------------------------------------- */
82
83/* Voltages (in) numbered 0-6 (ix) */
84#define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) \
85 : 0x94 + (ix))
86#define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
87 : 0x91 + (ix) * 2)
88#define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
89 : 0x92 + (ix) * 2)
90
91/* Temperatures (temp) numbered 0-2 (ix) */
92#define DME1737_REG_TEMP(ix) (0x25 + (ix))
93#define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2)
94#define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2)
95#define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
96 : 0x1c + (ix))
97
98/* Voltage and temperature LSBs
99 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
100 * IN_TEMP_LSB(0) = [in5, in6]
101 * IN_TEMP_LSB(1) = [temp3, temp1]
102 * IN_TEMP_LSB(2) = [in4, temp2]
103 * IN_TEMP_LSB(3) = [in3, in0]
104 * IN_TEMP_LSB(4) = [in2, in1] */
105#define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
106static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0};
107static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4};
108static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1};
109static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};
110
111/* Fans numbered 0-5 (ix) */
112#define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \
113 : 0xa1 + (ix) * 2)
114#define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \
115 : 0xa5 + (ix) * 2)
116#define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \
117 : 0xb2 + (ix))
118#define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */
119
120/* PWMs numbered 0-2, 4-5 (ix) */
121#define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \
122 : 0xa1 + (ix))
123#define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */
124#define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
125#define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
126 : 0xa3 + (ix))
127/* The layout of the ramp rate registers is different from the other pwm
128 * registers. The bits for the 3 PWMs are stored in 2 registers:
129 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
130 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] */
131#define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
132
133/* Thermal zones 0-2 */
134#define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
135#define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
136/* The layout of the hysteresis registers is different from the other zone
137 * registers. The bits for the 3 zones are stored in 2 registers:
138 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
139 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] */
140#define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
141
142/* Alarm registers and bit mapping
143 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
144 * alarm value [0, ALARM3, ALARM2, ALARM1]. */
145#define DME1737_REG_ALARM1 0x41
146#define DME1737_REG_ALARM2 0x42
147#define DME1737_REG_ALARM3 0x83
148static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17};
149static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6};
150static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23};
151
152/* Miscellaneous registers */
e95c237d 153#define DME1737_REG_DEVICE 0x3d
9431996f
JH		 154#define DME1737_REG_COMPANY 0x3e
155#define DME1737_REG_VERSTEP 0x3f
156#define DME1737_REG_CONFIG 0x40
157#define DME1737_REG_CONFIG2 0x7f
158#define DME1737_REG_VID 0x43
159#define DME1737_REG_TACH_PWM 0x81
160
161/* ---------------------------------------------------------------------
162 * Misc defines
163 * --------------------------------------------------------------------- */
164
165/* Chip identification */
166#define DME1737_COMPANY_SMSC 0x5c
167#define DME1737_VERSTEP 0x88
168#define DME1737_VERSTEP_MASK 0xf8
e95c237d 169#define SCH311X_DEVICE 0x8c
549edb83 170#define SCH5027_VERSTEP 0x69
ea694431
JH		 171#define SCH5127_DEVICE 0x8e
172
173/* Device ID values (global configuration register index 0x20) */
174#define DME1737_ID_1 0x77
175#define DME1737_ID_2 0x78
176#define SCH3112_ID 0x7c
177#define SCH3114_ID 0x7d
178#define SCH3116_ID 0x7f
179#define SCH5027_ID 0x89
180#define SCH5127_ID 0x86
e95c237d
JH		 181
182/* Length of ISA address segment */
183#define DME1737_EXTENT 2
9431996f 184
ea694431
JH		 185/* chip-dependent features */
186#define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */
187#define HAS_VID (1 << 1) /* bit 1 */
188#define HAS_ZONE3 (1 << 2) /* bit 2 */
189#define HAS_ZONE_HYST (1 << 3) /* bit 3 */
190#define HAS_PWM_MIN (1 << 4) /* bit 4 */
191#define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */
192#define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */
193
9431996f
JH		 194/* ---------------------------------------------------------------------
195 * Data structures and manipulation thereof
196 * --------------------------------------------------------------------- */
197
198struct dme1737_data {
dbc2bc25 199 struct i2c_client *client; /* for I2C devices only */
1beeffe4 200 struct device *hwmon_dev;
dbc2bc25
JD		 201 const char *name;
202 unsigned int addr; /* for ISA devices only */
9431996f
JH		 203
204 struct mutex update_lock;
205 int valid; /* !=0 if following fields are valid */
206 unsigned long last_update; /* in jiffies */
207 unsigned long last_vbat; /* in jiffies */
f994fb23 208 enum chips type;
549edb83 209 const int *in_nominal; /* pointer to IN_NOMINAL array */
9431996f
JH		 210
211 u8 vid;
212 u8 pwm_rr_en;
ea694431 213 u32 has_features;
9431996f
JH		 214
215 /* Register values */
216 u16 in[7];
217 u8 in_min[7];
218 u8 in_max[7];
219 s16 temp[3];
220 s8 temp_min[3];
221 s8 temp_max[3];
222 s8 temp_offset[3];
223 u8 config;
224 u8 config2;
225 u8 vrm;
226 u16 fan[6];
227 u16 fan_min[6];
228 u8 fan_max[2];
229 u8 fan_opt[6];
230 u8 pwm[6];
231 u8 pwm_min[3];
232 u8 pwm_config[3];
233 u8 pwm_acz[3];
234 u8 pwm_freq[6];
235 u8 pwm_rr[2];
236 u8 zone_low[3];
237 u8 zone_abs[3];
238 u8 zone_hyst[2];
239 u32 alarms;
240};
241
242/* Nominal voltage values */
f994fb23
JH		 243static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300,
244 3300};
245static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300,
246 3300};
549edb83
JH		 247static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300,
248 3300};
ea694431
JH		 249static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300,
250 3300};
549edb83
JH		 251#define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \
252 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \
ea694431 253 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
549edb83 254 IN_NOMINAL_DME1737)
9431996f
JH		 255
256/* Voltage input
257 * Voltage inputs have 16 bits resolution, limit values have 8 bits
258 * resolution. */
549edb83 259static inline int IN_FROM_REG(int reg, int nominal, int res)
9431996f 260{
549edb83 261 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
9431996f
JH		 262}
263
549edb83 264static inline int IN_TO_REG(int val, int nominal)
9431996f 265{
549edb83 266 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255);
9431996f
JH		 267}
268
269/* Temperature input
270 * The register values represent temperatures in 2's complement notation from
271 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
272 * values have 8 bits resolution. */
273static inline int TEMP_FROM_REG(int reg, int res)
274{
275 return (reg * 1000) >> (res - 8);
276}
277
278static inline int TEMP_TO_REG(int val)
279{
280 return SENSORS_LIMIT((val < 0 ? val - 500 : val + 500) / 1000,
281 -128, 127);
282}
283
284/* Temperature range */
285static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000,
286 10000, 13333, 16000, 20000, 26666, 32000,
287 40000, 53333, 80000};
288
289static inline int TEMP_RANGE_FROM_REG(int reg)
290{
291 return TEMP_RANGE[(reg >> 4) & 0x0f];
292}
293
294static int TEMP_RANGE_TO_REG(int val, int reg)
295{
296 int i;
297
298 for (i = 15; i > 0; i--) {
299 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) {
300 break;
301 }
302 }
303
304 return (reg & 0x0f) | (i << 4);
305}
306
307/* Temperature hysteresis
308 * Register layout:
309 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
310 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx] */
311static inline int TEMP_HYST_FROM_REG(int reg, int ix)
312{
313 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
314}
315
316static inline int TEMP_HYST_TO_REG(int val, int ix, int reg)
317{
318 int hyst = SENSORS_LIMIT((val + 500) / 1000, 0, 15);
319
320 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4);
321}
322
323/* Fan input RPM */
324static inline int FAN_FROM_REG(int reg, int tpc)
325{
ff8421f7
JH		 326 if (tpc) {
327 return tpc * reg;
328 } else {
329 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
330 }
9431996f
JH		 331}
332
333static inline int FAN_TO_REG(int val, int tpc)
334{
ff8421f7
JH		 335 if (tpc) {
336 return SENSORS_LIMIT(val / tpc, 0, 0xffff);
337 } else {
338 return (val <= 0) ? 0xffff :
339 SENSORS_LIMIT(90000 * 60 / val, 0, 0xfffe);
340 }
9431996f
JH		 341}
342
343/* Fan TPC (tach pulse count)
344 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
345 * is configured in legacy (non-tpc) mode */
346static inline int FAN_TPC_FROM_REG(int reg)
347{
348 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
349}
350
351/* Fan type
352 * The type of a fan is expressed in number of pulses-per-revolution that it
353 * emits */
354static inline int FAN_TYPE_FROM_REG(int reg)
355{
356 int edge = (reg >> 1) & 0x03;
357
358 return (edge > 0) ? 1 << (edge - 1) : 0;
359}
360
361static inline int FAN_TYPE_TO_REG(int val, int reg)
362{
363 int edge = (val == 4) ? 3 : val;
364
365 return (reg & 0xf9) | (edge << 1);
366}
367
368/* Fan max RPM */
369static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12,
370 0x11, 0x0f, 0x0e};
371
372static int FAN_MAX_FROM_REG(int reg)
373{
374 int i;
375
376 for (i = 10; i > 0; i--) {
377 if (reg == FAN_MAX[i]) {
378 break;
379 }
380 }
381
382 return 1000 + i * 500;
383}
384
385static int FAN_MAX_TO_REG(int val)
386{
387 int i;
388
389 for (i = 10; i > 0; i--) {
390 if (val > (1000 + (i - 1) * 500)) {
391 break;
392 }
393 }
394
395 return FAN_MAX[i];
396}
397
398/* PWM enable
399 * Register to enable mapping:
400 * 000: 2 fan on zone 1 auto
401 * 001: 2 fan on zone 2 auto
402 * 010: 2 fan on zone 3 auto
403 * 011: 0 fan full on
404 * 100: -1 fan disabled
405 * 101: 2 fan on hottest of zones 2,3 auto
406 * 110: 2 fan on hottest of zones 1,2,3 auto
407 * 111: 1 fan in manual mode */
408static inline int PWM_EN_FROM_REG(int reg)
409{
410 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
411
412 return en[(reg >> 5) & 0x07];
413}
414
415static inline int PWM_EN_TO_REG(int val, int reg)
416{
417 int en = (val == 1) ? 7 : 3;
418
419 return (reg & 0x1f) | ((en & 0x07) << 5);
420}
421
422/* PWM auto channels zone
423 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
424 * corresponding to zone x+1):
425 * 000: 001 fan on zone 1 auto
426 * 001: 010 fan on zone 2 auto
427 * 010: 100 fan on zone 3 auto
428 * 011: 000 fan full on
429 * 100: 000 fan disabled
430 * 101: 110 fan on hottest of zones 2,3 auto
431 * 110: 111 fan on hottest of zones 1,2,3 auto
432 * 111: 000 fan in manual mode */
433static inline int PWM_ACZ_FROM_REG(int reg)
434{
435 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
436
437 return acz[(reg >> 5) & 0x07];
438}
439
440static inline int PWM_ACZ_TO_REG(int val, int reg)
441{
442 int acz = (val == 4) ? 2 : val - 1;
443
444 return (reg & 0x1f) | ((acz & 0x07) << 5);
445}
446
447/* PWM frequency */
448static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88,
449 15000, 20000, 30000, 25000, 0, 0, 0, 0};
450
451static inline int PWM_FREQ_FROM_REG(int reg)
452{
453 return PWM_FREQ[reg & 0x0f];
454}
455
456static int PWM_FREQ_TO_REG(int val, int reg)
457{
458 int i;
459
460 /* the first two cases are special - stupid chip design! */
461 if (val > 27500) {
462 i = 10;
463 } else if (val > 22500) {
464 i = 11;
465 } else {
466 for (i = 9; i > 0; i--) {
467 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) {
468 break;
469 }
470 }
471 }
472
473 return (reg & 0xf0) | i;
474}
475
476/* PWM ramp rate
477 * Register layout:
478 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
479 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] */
480static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
481
482static inline int PWM_RR_FROM_REG(int reg, int ix)
483{
484 int rr = (ix == 1) ? reg >> 4 : reg;
485
486 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0;
487}
488
489static int PWM_RR_TO_REG(int val, int ix, int reg)
490{
491 int i;
492
493 for (i = 0; i < 7; i++) {
494 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) {
495 break;
496 }
497 }
498
499 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
500}
501
502/* PWM ramp rate enable */
503static inline int PWM_RR_EN_FROM_REG(int reg, int ix)
504{
505 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0;
506}
507
508static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg)
509{
510 int en = (ix == 1) ? 0x80 : 0x08;
511
512 return val ? reg | en : reg & ~en;
513}
514
515/* PWM min/off
516 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
517 * the register layout). */
518static inline int PWM_OFF_FROM_REG(int reg, int ix)
519{
520 return (reg >> (ix + 5)) & 0x01;
521}
522
523static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
524{
525 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5));
526}
527
528/* ---------------------------------------------------------------------
529 * Device I/O access
e95c237d
JH		 530 *
531 * ISA access is performed through an index/data register pair and needs to
532 * be protected by a mutex during runtime (not required for initialization).
533 * We use data->update_lock for this and need to ensure that we acquire it
534 * before calling dme1737_read or dme1737_write.
9431996f
JH		 535 * --------------------------------------------------------------------- */
536
dbc2bc25 537static u8 dme1737_read(const struct dme1737_data *data, u8 reg)
9431996f 538{
dbc2bc25 539 struct i2c_client *client = data->client;
e95c237d 540 s32 val;
9431996f 541
dbc2bc25 542 if (client) { /* I2C device */
e95c237d
JH		 543 val = i2c_smbus_read_byte_data(client, reg);
544
545 if (val < 0) {
546 dev_warn(&client->dev, "Read from register "
547 "0x%02x failed! Please report to the driver "
548 "maintainer.\n", reg);
549 }
550 } else { /* ISA device */
dbc2bc25
JD		 551 outb(reg, data->addr);
552 val = inb(data->addr + 1);
9431996f
JH		 553 }
554
555 return val;
556}
557
dbc2bc25 558static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
9431996f 559{
dbc2bc25 560 struct i2c_client *client = data->client;
e95c237d
JH		 561 s32 res = 0;
562
dbc2bc25 563 if (client) { /* I2C device */
e95c237d 564 res = i2c_smbus_write_byte_data(client, reg, val);
9431996f 565
e95c237d
JH		 566 if (res < 0) {
567 dev_warn(&client->dev, "Write to register "
568 "0x%02x failed! Please report to the driver "
569 "maintainer.\n", reg);
570 }
571 } else { /* ISA device */
dbc2bc25
JD		 572 outb(reg, data->addr);
573 outb(val, data->addr + 1);
9431996f
JH		 574 }
575
576 return res;
577}
578
579static struct dme1737_data *dme1737_update_device(struct device *dev)
580{
b237eb25 581 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 582 int ix;
583 u8 lsb[5];
584
585 mutex_lock(&data->update_lock);
586
587 /* Enable a Vbat monitoring cycle every 10 mins */
588 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) {
dbc2bc25 589 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data,
9431996f
JH		 590 DME1737_REG_CONFIG) | 0x10);
591 data->last_vbat = jiffies;
592 }
593
594 /* Sample register contents every 1 sec */
595 if (time_after(jiffies, data->last_update + HZ) || !data->valid) {
ea694431 596 if (data->has_features & HAS_VID) {
dbc2bc25 597 data->vid = dme1737_read(data, DME1737_REG_VID) &
549edb83
JH		 598 0x3f;
599 }
9431996f
JH		 600
601 /* In (voltage) registers */
602 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
603 /* Voltage inputs are stored as 16 bit values even
604 * though they have only 12 bits resolution. This is
605 * to make it consistent with the temp inputs. */
dbc2bc25 606 data->in[ix] = dme1737_read(data,
9431996f 607 DME1737_REG_IN(ix)) << 8;
dbc2bc25 608 data->in_min[ix] = dme1737_read(data,
9431996f 609 DME1737_REG_IN_MIN(ix));
dbc2bc25 610 data->in_max[ix] = dme1737_read(data,
9431996f
JH		 611 DME1737_REG_IN_MAX(ix));
612 }
613
614 /* Temp registers */
615 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
616 /* Temp inputs are stored as 16 bit values even
617 * though they have only 12 bits resolution. This is
618 * to take advantage of implicit conversions between
619 * register values (2's complement) and temp values
620 * (signed decimal). */
dbc2bc25 621 data->temp[ix] = dme1737_read(data,
9431996f 622 DME1737_REG_TEMP(ix)) << 8;
dbc2bc25 623 data->temp_min[ix] = dme1737_read(data,
9431996f 624 DME1737_REG_TEMP_MIN(ix));
dbc2bc25 625 data->temp_max[ix] = dme1737_read(data,
9431996f 626 DME1737_REG_TEMP_MAX(ix));
ea694431 627 if (data->has_features & HAS_TEMP_OFFSET) {
dbc2bc25 628 data->temp_offset[ix] = dme1737_read(data,
549edb83
JH		 629 DME1737_REG_TEMP_OFFSET(ix));
630 }
9431996f
JH		 631 }
632
633 /* In and temp LSB registers
634 * The LSBs are latched when the MSBs are read, so the order in
635 * which the registers are read (MSB first, then LSB) is
636 * important! */
637 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
dbc2bc25 638 lsb[ix] = dme1737_read(data,
9431996f
JH		 639 DME1737_REG_IN_TEMP_LSB(ix));
640 }
641 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
642 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
643 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
644 }
645 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
646 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] <<
647 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0;
648 }
649
650 /* Fan registers */
651 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
652 /* Skip reading registers if optional fans are not
653 * present */
ea694431 654 if (!(data->has_features & HAS_FAN(ix))) {
9431996f
JH		 655 continue;
656 }
dbc2bc25 657 data->fan[ix] = dme1737_read(data,
9431996f 658 DME1737_REG_FAN(ix));
dbc2bc25 659 data->fan[ix] |= dme1737_read(data,
9431996f 660 DME1737_REG_FAN(ix) + 1) << 8;
dbc2bc25 661 data->fan_min[ix] = dme1737_read(data,
9431996f 662 DME1737_REG_FAN_MIN(ix));
dbc2bc25 663 data->fan_min[ix] |= dme1737_read(data,
9431996f 664 DME1737_REG_FAN_MIN(ix) + 1) << 8;
dbc2bc25 665 data->fan_opt[ix] = dme1737_read(data,
9431996f
JH		 666 DME1737_REG_FAN_OPT(ix));
667 /* fan_max exists only for fan[5-6] */
668 if (ix > 3) {
dbc2bc25 669 data->fan_max[ix - 4] = dme1737_read(data,
9431996f
JH		 670 DME1737_REG_FAN_MAX(ix));
671 }
672 }
673
674 /* PWM registers */
675 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
676 /* Skip reading registers if optional PWMs are not
677 * present */
ea694431 678 if (!(data->has_features & HAS_PWM(ix))) {
9431996f
JH		 679 continue;
680 }
dbc2bc25 681 data->pwm[ix] = dme1737_read(data,
9431996f 682 DME1737_REG_PWM(ix));
dbc2bc25 683 data->pwm_freq[ix] = dme1737_read(data,
9431996f
JH		 684 DME1737_REG_PWM_FREQ(ix));
685 /* pwm_config and pwm_min exist only for pwm[1-3] */
686 if (ix < 3) {
dbc2bc25 687 data->pwm_config[ix] = dme1737_read(data,
9431996f 688 DME1737_REG_PWM_CONFIG(ix));
dbc2bc25 689 data->pwm_min[ix] = dme1737_read(data,
9431996f
JH		 690 DME1737_REG_PWM_MIN(ix));
691 }
692 }
693 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) {
dbc2bc25 694 data->pwm_rr[ix] = dme1737_read(data,
9431996f
JH		 695 DME1737_REG_PWM_RR(ix));
696 }
697
698 /* Thermal zone registers */
699 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
ea694431
JH		 700 /* Skip reading registers if zone3 is not present */
701 if ((ix == 2) && !(data->has_features & HAS_ZONE3)) {
702 continue;
703 }
704 /* sch5127 zone2 registers are special */
705 if ((ix == 1) && (data->type == sch5127)) {
706 data->zone_low[1] = dme1737_read(data,
707 DME1737_REG_ZONE_LOW(2));
708 data->zone_abs[1] = dme1737_read(data,
709 DME1737_REG_ZONE_ABS(2));
710 } else {
711 data->zone_low[ix] = dme1737_read(data,
712 DME1737_REG_ZONE_LOW(ix));
713 data->zone_abs[ix] = dme1737_read(data,
714 DME1737_REG_ZONE_ABS(ix));
715 }
9431996f 716 }
ea694431 717 if (data->has_features & HAS_ZONE_HYST) {
549edb83 718 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) {
dbc2bc25 719 data->zone_hyst[ix] = dme1737_read(data,
9431996f 720 DME1737_REG_ZONE_HYST(ix));
549edb83 721 }
9431996f
JH		 722 }
723
724 /* Alarm registers */
dbc2bc25 725 data->alarms = dme1737_read(data,
9431996f
JH		 726 DME1737_REG_ALARM1);
727 /* Bit 7 tells us if the other alarm registers are non-zero and
728 * therefore also need to be read */
729 if (data->alarms & 0x80) {
dbc2bc25 730 data->alarms |= dme1737_read(data,
9431996f 731 DME1737_REG_ALARM2) << 8;
dbc2bc25 732 data->alarms |= dme1737_read(data,
9431996f
JH		 733 DME1737_REG_ALARM3) << 16;
734 }
735
e95c237d
JH		 736 /* The ISA chips require explicit clearing of alarm bits.
737 * Don't worry, an alarm will come back if the condition
738 * that causes it still exists */
dbc2bc25 739 if (!data->client) {
e95c237d 740 if (data->alarms & 0xff0000) {
dbc2bc25 741 dme1737_write(data, DME1737_REG_ALARM3,
e95c237d
JH		 742 0xff);
743 }
744 if (data->alarms & 0xff00) {
dbc2bc25 745 dme1737_write(data, DME1737_REG_ALARM2,
e95c237d
JH		 746 0xff);
747 }
748 if (data->alarms & 0xff) {
dbc2bc25 749 dme1737_write(data, DME1737_REG_ALARM1,
e95c237d
JH		 750 0xff);
751 }
752 }
753
9431996f
JH		 754 data->last_update = jiffies;
755 data->valid = 1;
756 }
757
758 mutex_unlock(&data->update_lock);
759
760 return data;
761}
762
763/* ---------------------------------------------------------------------
764 * Voltage sysfs attributes
765 * ix = [0-5]
766 * --------------------------------------------------------------------- */
767
768#define SYS_IN_INPUT 0
769#define SYS_IN_MIN 1
770#define SYS_IN_MAX 2
771#define SYS_IN_ALARM 3
772
773static ssize_t show_in(struct device *dev, struct device_attribute *attr,
774 char *buf)
775{
776 struct dme1737_data *data = dme1737_update_device(dev);
777 struct sensor_device_attribute_2
778 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
779 int ix = sensor_attr_2->index;
780 int fn = sensor_attr_2->nr;
781 int res;
782
783 switch (fn) {
784 case SYS_IN_INPUT:
549edb83 785 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16);
9431996f
JH		 786 break;
787 case SYS_IN_MIN:
549edb83 788 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8);
9431996f
JH		 789 break;
790 case SYS_IN_MAX:
549edb83 791 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8);
9431996f
JH		 792 break;
793 case SYS_IN_ALARM:
794 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01;
795 break;
796 default:
797 res = 0;
b237eb25 798 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 799 }
800
801 return sprintf(buf, "%d\n", res);
802}
803
804static ssize_t set_in(struct device *dev, struct device_attribute *attr,
805 const char *buf, size_t count)
806{
b237eb25 807 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 808 struct sensor_device_attribute_2
809 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
810 int ix = sensor_attr_2->index;
811 int fn = sensor_attr_2->nr;
812 long val = simple_strtol(buf, NULL, 10);
813
814 mutex_lock(&data->update_lock);
815 switch (fn) {
816 case SYS_IN_MIN:
549edb83 817 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]);
dbc2bc25 818 dme1737_write(data, DME1737_REG_IN_MIN(ix),
9431996f
JH		 819 data->in_min[ix]);
820 break;
821 case SYS_IN_MAX:
549edb83 822 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]);
dbc2bc25 823 dme1737_write(data, DME1737_REG_IN_MAX(ix),
9431996f
JH		 824 data->in_max[ix]);
825 break;
826 default:
b237eb25 827 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 828 }
829 mutex_unlock(&data->update_lock);
830
831 return count;
832}
833
834/* ---------------------------------------------------------------------
835 * Temperature sysfs attributes
836 * ix = [0-2]
837 * --------------------------------------------------------------------- */
838
839#define SYS_TEMP_INPUT 0
840#define SYS_TEMP_MIN 1
841#define SYS_TEMP_MAX 2
842#define SYS_TEMP_OFFSET 3
843#define SYS_TEMP_ALARM 4
844#define SYS_TEMP_FAULT 5
845
846static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
847 char *buf)
848{
849 struct dme1737_data *data = dme1737_update_device(dev);
850 struct sensor_device_attribute_2
851 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
852 int ix = sensor_attr_2->index;
853 int fn = sensor_attr_2->nr;
854 int res;
855
856 switch (fn) {
857 case SYS_TEMP_INPUT:
858 res = TEMP_FROM_REG(data->temp[ix], 16);
859 break;
860 case SYS_TEMP_MIN:
861 res = TEMP_FROM_REG(data->temp_min[ix], 8);
862 break;
863 case SYS_TEMP_MAX:
864 res = TEMP_FROM_REG(data->temp_max[ix], 8);
865 break;
866 case SYS_TEMP_OFFSET:
867 res = TEMP_FROM_REG(data->temp_offset[ix], 8);
868 break;
869 case SYS_TEMP_ALARM:
870 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
871 break;
872 case SYS_TEMP_FAULT:
c0f31403 873 res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
9431996f
JH		 874 break;
875 default:
876 res = 0;
b237eb25 877 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 878 }
879
880 return sprintf(buf, "%d\n", res);
881}
882
883static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
884 const char *buf, size_t count)
885{
b237eb25 886 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 887 struct sensor_device_attribute_2
888 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
889 int ix = sensor_attr_2->index;
890 int fn = sensor_attr_2->nr;
891 long val = simple_strtol(buf, NULL, 10);
892
893 mutex_lock(&data->update_lock);
894 switch (fn) {
895 case SYS_TEMP_MIN:
896 data->temp_min[ix] = TEMP_TO_REG(val);
dbc2bc25 897 dme1737_write(data, DME1737_REG_TEMP_MIN(ix),
9431996f
JH		 898 data->temp_min[ix]);
899 break;
900 case SYS_TEMP_MAX:
901 data->temp_max[ix] = TEMP_TO_REG(val);
dbc2bc25 902 dme1737_write(data, DME1737_REG_TEMP_MAX(ix),
9431996f
JH		 903 data->temp_max[ix]);
904 break;
905 case SYS_TEMP_OFFSET:
906 data->temp_offset[ix] = TEMP_TO_REG(val);
dbc2bc25 907 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix),
9431996f
JH		 908 data->temp_offset[ix]);
909 break;
910 default:
b237eb25 911 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 912 }
913 mutex_unlock(&data->update_lock);
914
915 return count;
916}
917
918/* ---------------------------------------------------------------------
919 * Zone sysfs attributes
920 * ix = [0-2]
921 * --------------------------------------------------------------------- */
922
923#define SYS_ZONE_AUTO_CHANNELS_TEMP 0
924#define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1
925#define SYS_ZONE_AUTO_POINT1_TEMP 2
926#define SYS_ZONE_AUTO_POINT2_TEMP 3
927#define SYS_ZONE_AUTO_POINT3_TEMP 4
928
929static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
930 char *buf)
931{
932 struct dme1737_data *data = dme1737_update_device(dev);
933 struct sensor_device_attribute_2
934 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
935 int ix = sensor_attr_2->index;
936 int fn = sensor_attr_2->nr;
937 int res;
938
939 switch (fn) {
940 case SYS_ZONE_AUTO_CHANNELS_TEMP:
941 /* check config2 for non-standard temp-to-zone mapping */
942 if ((ix == 1) && (data->config2 & 0x02)) {
943 res = 4;
944 } else {
945 res = 1 << ix;
946 }
947 break;
948 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
949 res = TEMP_FROM_REG(data->zone_low[ix], 8) -
950 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix);
951 break;
952 case SYS_ZONE_AUTO_POINT1_TEMP:
953 res = TEMP_FROM_REG(data->zone_low[ix], 8);
954 break;
955 case SYS_ZONE_AUTO_POINT2_TEMP:
956 /* pwm_freq holds the temp range bits in the upper nibble */
957 res = TEMP_FROM_REG(data->zone_low[ix], 8) +
958 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]);
959 break;
960 case SYS_ZONE_AUTO_POINT3_TEMP:
961 res = TEMP_FROM_REG(data->zone_abs[ix], 8);
962 break;
963 default:
964 res = 0;
b237eb25 965 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 966 }
967
968 return sprintf(buf, "%d\n", res);
969}
970
971static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
972 const char *buf, size_t count)
973{
b237eb25 974 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 975 struct sensor_device_attribute_2
976 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
977 int ix = sensor_attr_2->index;
978 int fn = sensor_attr_2->nr;
979 long val = simple_strtol(buf, NULL, 10);
980
981 mutex_lock(&data->update_lock);
982 switch (fn) {
983 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
984 /* Refresh the cache */
dbc2bc25 985 data->zone_low[ix] = dme1737_read(data,
9431996f
JH		 986 DME1737_REG_ZONE_LOW(ix));
987 /* Modify the temp hyst value */
988 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(
989 TEMP_FROM_REG(data->zone_low[ix], 8) -
dbc2bc25 990 val, ix, dme1737_read(data,
9431996f 991 DME1737_REG_ZONE_HYST(ix == 2)));
dbc2bc25 992 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2),
9431996f
JH		 993 data->zone_hyst[ix == 2]);
994 break;
995 case SYS_ZONE_AUTO_POINT1_TEMP:
996 data->zone_low[ix] = TEMP_TO_REG(val);
dbc2bc25 997 dme1737_write(data, DME1737_REG_ZONE_LOW(ix),
9431996f
JH		 998 data->zone_low[ix]);
999 break;
1000 case SYS_ZONE_AUTO_POINT2_TEMP:
1001 /* Refresh the cache */
dbc2bc25 1002 data->zone_low[ix] = dme1737_read(data,
9431996f
JH		 1003 DME1737_REG_ZONE_LOW(ix));
1004 /* Modify the temp range value (which is stored in the upper
1005 * nibble of the pwm_freq register) */
1006 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val -
1007 TEMP_FROM_REG(data->zone_low[ix], 8),
dbc2bc25 1008 dme1737_read(data,
9431996f 1009 DME1737_REG_PWM_FREQ(ix)));
dbc2bc25 1010 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
9431996f
JH		 1011 data->pwm_freq[ix]);
1012 break;
1013 case SYS_ZONE_AUTO_POINT3_TEMP:
1014 data->zone_abs[ix] = TEMP_TO_REG(val);
dbc2bc25 1015 dme1737_write(data, DME1737_REG_ZONE_ABS(ix),
9431996f
JH		 1016 data->zone_abs[ix]);
1017 break;
1018 default:
b237eb25 1019 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1020 }
1021 mutex_unlock(&data->update_lock);
1022
1023 return count;
1024}
1025
1026/* ---------------------------------------------------------------------
1027 * Fan sysfs attributes
1028 * ix = [0-5]
1029 * --------------------------------------------------------------------- */
1030
1031#define SYS_FAN_INPUT 0
1032#define SYS_FAN_MIN 1
1033#define SYS_FAN_MAX 2
1034#define SYS_FAN_ALARM 3
1035#define SYS_FAN_TYPE 4
1036
1037static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1038 char *buf)
1039{
1040 struct dme1737_data *data = dme1737_update_device(dev);
1041 struct sensor_device_attribute_2
1042 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1043 int ix = sensor_attr_2->index;
1044 int fn = sensor_attr_2->nr;
1045 int res;
1046
1047 switch (fn) {
1048 case SYS_FAN_INPUT:
1049 res = FAN_FROM_REG(data->fan[ix],
1050 ix < 4 ? 0 :
1051 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1052 break;
1053 case SYS_FAN_MIN:
1054 res = FAN_FROM_REG(data->fan_min[ix],
1055 ix < 4 ? 0 :
1056 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1057 break;
1058 case SYS_FAN_MAX:
1059 /* only valid for fan[5-6] */
1060 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]);
1061 break;
1062 case SYS_FAN_ALARM:
1063 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01;
1064 break;
1065 case SYS_FAN_TYPE:
1066 /* only valid for fan[1-4] */
1067 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]);
1068 break;
1069 default:
1070 res = 0;
b237eb25 1071 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1072 }
1073
1074 return sprintf(buf, "%d\n", res);
1075}
1076
1077static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1078 const char *buf, size_t count)
1079{
b237eb25 1080 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 1081 struct sensor_device_attribute_2
1082 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1083 int ix = sensor_attr_2->index;
1084 int fn = sensor_attr_2->nr;
1085 long val = simple_strtol(buf, NULL, 10);
1086
1087 mutex_lock(&data->update_lock);
1088 switch (fn) {
1089 case SYS_FAN_MIN:
1090 if (ix < 4) {
1091 data->fan_min[ix] = FAN_TO_REG(val, 0);
1092 } else {
1093 /* Refresh the cache */
dbc2bc25 1094 data->fan_opt[ix] = dme1737_read(data,
9431996f
JH		 1095 DME1737_REG_FAN_OPT(ix));
1096 /* Modify the fan min value */
1097 data->fan_min[ix] = FAN_TO_REG(val,
1098 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1099 }
dbc2bc25 1100 dme1737_write(data, DME1737_REG_FAN_MIN(ix),
9431996f 1101 data->fan_min[ix] & 0xff);
dbc2bc25 1102 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1,
9431996f
JH		 1103 data->fan_min[ix] >> 8);
1104 break;
1105 case SYS_FAN_MAX:
1106 /* Only valid for fan[5-6] */
1107 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val);
dbc2bc25 1108 dme1737_write(data, DME1737_REG_FAN_MAX(ix),
9431996f
JH		 1109 data->fan_max[ix - 4]);
1110 break;
1111 case SYS_FAN_TYPE:
1112 /* Only valid for fan[1-4] */
1113 if (!(val == 1 || val == 2 || val == 4)) {
1114 count = -EINVAL;
e95c237d 1115 dev_warn(dev, "Fan type value %ld not "
9431996f
JH		 1116 "supported. Choose one of 1, 2, or 4.\n",
1117 val);
1118 goto exit;
1119 }
dbc2bc25 1120 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data,
9431996f 1121 DME1737_REG_FAN_OPT(ix)));
dbc2bc25 1122 dme1737_write(data, DME1737_REG_FAN_OPT(ix),
9431996f
JH		 1123 data->fan_opt[ix]);
1124 break;
1125 default:
b237eb25 1126 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1127 }
1128exit:
1129 mutex_unlock(&data->update_lock);
1130
1131 return count;
1132}
1133
1134/* ---------------------------------------------------------------------
1135 * PWM sysfs attributes
1136 * ix = [0-4]
1137 * --------------------------------------------------------------------- */
1138
1139#define SYS_PWM 0
1140#define SYS_PWM_FREQ 1
1141#define SYS_PWM_ENABLE 2
1142#define SYS_PWM_RAMP_RATE 3
1143#define SYS_PWM_AUTO_CHANNELS_ZONE 4
1144#define SYS_PWM_AUTO_PWM_MIN 5
1145#define SYS_PWM_AUTO_POINT1_PWM 6
1146#define SYS_PWM_AUTO_POINT2_PWM 7
1147
1148static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1149 char *buf)
1150{
1151 struct dme1737_data *data = dme1737_update_device(dev);
1152 struct sensor_device_attribute_2
1153 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1154 int ix = sensor_attr_2->index;
1155 int fn = sensor_attr_2->nr;
1156 int res;
1157
1158 switch (fn) {
1159 case SYS_PWM:
1160 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) {
1161 res = 255;
1162 } else {
1163 res = data->pwm[ix];
1164 }
1165 break;
1166 case SYS_PWM_FREQ:
1167 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
1168 break;
1169 case SYS_PWM_ENABLE:
912e837a 1170 if (ix >= 3) {
9431996f
JH		 1171 res = 1; /* pwm[5-6] hard-wired to manual mode */
1172 } else {
1173 res = PWM_EN_FROM_REG(data->pwm_config[ix]);
1174 }
1175 break;
1176 case SYS_PWM_RAMP_RATE:
1177 /* Only valid for pwm[1-3] */
1178 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix);
1179 break;
1180 case SYS_PWM_AUTO_CHANNELS_ZONE:
1181 /* Only valid for pwm[1-3] */
1182 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1183 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
1184 } else {
1185 res = data->pwm_acz[ix];
1186 }
1187 break;
1188 case SYS_PWM_AUTO_PWM_MIN:
1189 /* Only valid for pwm[1-3] */
1190 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) {
1191 res = data->pwm_min[ix];
1192 } else {
1193 res = 0;
1194 }
1195 break;
1196 case SYS_PWM_AUTO_POINT1_PWM:
1197 /* Only valid for pwm[1-3] */
1198 res = data->pwm_min[ix];
1199 break;
1200 case SYS_PWM_AUTO_POINT2_PWM:
1201 /* Only valid for pwm[1-3] */
1202 res = 255; /* hard-wired */
1203 break;
1204 default:
1205 res = 0;
b237eb25 1206 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1207 }
1208
1209 return sprintf(buf, "%d\n", res);
1210}
1211
73ce48f6 1212static struct attribute *dme1737_pwm_chmod_attr[];
b237eb25 1213static void dme1737_chmod_file(struct device*, struct attribute*, mode_t);
9431996f
JH		 1214
1215static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1216 const char *buf, size_t count)
1217{
b237eb25 1218 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 1219 struct sensor_device_attribute_2
1220 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1221 int ix = sensor_attr_2->index;
1222 int fn = sensor_attr_2->nr;
1223 long val = simple_strtol(buf, NULL, 10);
1224
1225 mutex_lock(&data->update_lock);
1226 switch (fn) {
1227 case SYS_PWM:
1228 data->pwm[ix] = SENSORS_LIMIT(val, 0, 255);
dbc2bc25 1229 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]);
9431996f
JH		 1230 break;
1231 case SYS_PWM_FREQ:
dbc2bc25 1232 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data,
9431996f 1233 DME1737_REG_PWM_FREQ(ix)));
dbc2bc25 1234 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
9431996f
JH		 1235 data->pwm_freq[ix]);
1236 break;
1237 case SYS_PWM_ENABLE:
1238 /* Only valid for pwm[1-3] */
1239 if (val < 0 || val > 2) {
1240 count = -EINVAL;
e95c237d 1241 dev_warn(dev, "PWM enable %ld not "
9431996f
JH		 1242 "supported. Choose one of 0, 1, or 2.\n",
1243 val);
1244 goto exit;
1245 }
1246 /* Refresh the cache */
dbc2bc25 1247 data->pwm_config[ix] = dme1737_read(data,
9431996f
JH		 1248 DME1737_REG_PWM_CONFIG(ix));
1249 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) {
1250 /* Bail out if no change */
1251 goto exit;
1252 }
1253 /* Do some housekeeping if we are currently in auto mode */
1254 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1255 /* Save the current zone channel assignment */
1256 data->pwm_acz[ix] = PWM_ACZ_FROM_REG(
1257 data->pwm_config[ix]);
1258 /* Save the current ramp rate state and disable it */
dbc2bc25 1259 data->pwm_rr[ix > 0] = dme1737_read(data,
9431996f
JH		 1260 DME1737_REG_PWM_RR(ix > 0));
1261 data->pwm_rr_en &= ~(1 << ix);
1262 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) {
1263 data->pwm_rr_en |= (1 << ix);
1264 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix,
1265 data->pwm_rr[ix > 0]);
dbc2bc25 1266 dme1737_write(data,
9431996f
JH		 1267 DME1737_REG_PWM_RR(ix > 0),
1268 data->pwm_rr[ix > 0]);
1269 }
1270 }
1271 /* Set the new PWM mode */
1272 switch (val) {
1273 case 0:
1274 /* Change permissions of pwm[ix] to read-only */
73ce48f6 1275 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
9431996f
JH		 1276 S_IRUGO);
1277 /* Turn fan fully on */
1278 data->pwm_config[ix] = PWM_EN_TO_REG(0,
1279 data->pwm_config[ix]);
dbc2bc25 1280 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1281 data->pwm_config[ix]);
1282 break;
1283 case 1:
1284 /* Turn on manual mode */
1285 data->pwm_config[ix] = PWM_EN_TO_REG(1,
1286 data->pwm_config[ix]);
dbc2bc25 1287 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1288 data->pwm_config[ix]);
1289 /* Change permissions of pwm[ix] to read-writeable */
73ce48f6 1290 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
9431996f
JH		 1291 S_IRUGO | S_IWUSR);
1292 break;
1293 case 2:
1294 /* Change permissions of pwm[ix] to read-only */
73ce48f6 1295 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
9431996f
JH		 1296 S_IRUGO);
1297 /* Turn on auto mode using the saved zone channel
1298 * assignment */
1299 data->pwm_config[ix] = PWM_ACZ_TO_REG(
1300 data->pwm_acz[ix],
1301 data->pwm_config[ix]);
dbc2bc25 1302 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1303 data->pwm_config[ix]);
1304 /* Enable PWM ramp rate if previously enabled */
1305 if (data->pwm_rr_en & (1 << ix)) {
1306 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix,
dbc2bc25 1307 dme1737_read(data,
9431996f 1308 DME1737_REG_PWM_RR(ix > 0)));
dbc2bc25 1309 dme1737_write(data,
9431996f
JH		 1310 DME1737_REG_PWM_RR(ix > 0),
1311 data->pwm_rr[ix > 0]);
1312 }
1313 break;
1314 }
1315 break;
1316 case SYS_PWM_RAMP_RATE:
1317 /* Only valid for pwm[1-3] */
1318 /* Refresh the cache */
dbc2bc25 1319 data->pwm_config[ix] = dme1737_read(data,
9431996f 1320 DME1737_REG_PWM_CONFIG(ix));
dbc2bc25 1321 data->pwm_rr[ix > 0] = dme1737_read(data,
9431996f
JH		 1322 DME1737_REG_PWM_RR(ix > 0));
1323 /* Set the ramp rate value */
1324 if (val > 0) {
1325 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
1326 data->pwm_rr[ix > 0]);
1327 }
1328 /* Enable/disable the feature only if the associated PWM
1329 * output is in automatic mode. */
1330 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1331 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
1332 data->pwm_rr[ix > 0]);
1333 }
dbc2bc25 1334 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0),
9431996f
JH		 1335 data->pwm_rr[ix > 0]);
1336 break;
1337 case SYS_PWM_AUTO_CHANNELS_ZONE:
1338 /* Only valid for pwm[1-3] */
1339 if (!(val == 1 || val == 2 || val == 4 ||
1340 val == 6 || val == 7)) {
1341 count = -EINVAL;
e95c237d 1342 dev_warn(dev, "PWM auto channels zone %ld "
9431996f
JH		 1343 "not supported. Choose one of 1, 2, 4, 6, "
1344 "or 7.\n", val);
1345 goto exit;
1346 }
1347 /* Refresh the cache */
dbc2bc25 1348 data->pwm_config[ix] = dme1737_read(data,
9431996f
JH		 1349 DME1737_REG_PWM_CONFIG(ix));
1350 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1351 /* PWM is already in auto mode so update the temp
1352 * channel assignment */
1353 data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
1354 data->pwm_config[ix]);
dbc2bc25 1355 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1356 data->pwm_config[ix]);
1357 } else {
1358 /* PWM is not in auto mode so we save the temp
1359 * channel assignment for later use */
1360 data->pwm_acz[ix] = val;
1361 }
1362 break;
1363 case SYS_PWM_AUTO_PWM_MIN:
1364 /* Only valid for pwm[1-3] */
1365 /* Refresh the cache */
dbc2bc25 1366 data->pwm_min[ix] = dme1737_read(data,
9431996f
JH		 1367 DME1737_REG_PWM_MIN(ix));
1368 /* There are only 2 values supported for the auto_pwm_min
1369 * value: 0 or auto_point1_pwm. So if the temperature drops
1370 * below the auto_point1_temp_hyst value, the fan either turns
1371 * off or runs at auto_point1_pwm duty-cycle. */
1372 if (val > ((data->pwm_min[ix] + 1) / 2)) {
1373 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
dbc2bc25 1374 dme1737_read(data,
9431996f 1375 DME1737_REG_PWM_RR(0)));
9431996f
JH		 1376 } else {
1377 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix,
dbc2bc25 1378 dme1737_read(data,
9431996f 1379 DME1737_REG_PWM_RR(0)));
9431996f 1380 }
dbc2bc25 1381 dme1737_write(data, DME1737_REG_PWM_RR(0),
9431996f
JH		 1382 data->pwm_rr[0]);
1383 break;
1384 case SYS_PWM_AUTO_POINT1_PWM:
1385 /* Only valid for pwm[1-3] */
1386 data->pwm_min[ix] = SENSORS_LIMIT(val, 0, 255);
dbc2bc25 1387 dme1737_write(data, DME1737_REG_PWM_MIN(ix),
9431996f
JH		 1388 data->pwm_min[ix]);
1389 break;
1390 default:
b237eb25 1391 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1392 }
1393exit:
1394 mutex_unlock(&data->update_lock);
1395
1396 return count;
1397}
1398
1399/* ---------------------------------------------------------------------
1400 * Miscellaneous sysfs attributes
1401 * --------------------------------------------------------------------- */
1402
1403static ssize_t show_vrm(struct device *dev, struct device_attribute *attr,
1404 char *buf)
1405{
1406 struct i2c_client *client = to_i2c_client(dev);
1407 struct dme1737_data *data = i2c_get_clientdata(client);
1408
1409 return sprintf(buf, "%d\n", data->vrm);
1410}
1411
1412static ssize_t set_vrm(struct device *dev, struct device_attribute *attr,
1413 const char *buf, size_t count)
1414{
b237eb25 1415 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 1416 long val = simple_strtol(buf, NULL, 10);
1417
1418 data->vrm = val;
1419 return count;
1420}
1421
1422static ssize_t show_vid(struct device *dev, struct device_attribute *attr,
1423 char *buf)
1424{
1425 struct dme1737_data *data = dme1737_update_device(dev);
1426
1427 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1428}
1429
e95c237d
JH		 1430static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1431 char *buf)
1432{
1433 struct dme1737_data *data = dev_get_drvdata(dev);
1434
dbc2bc25 1435 return sprintf(buf, "%s\n", data->name);
e95c237d
JH		 1436}
1437
9431996f
JH		 1438/* ---------------------------------------------------------------------
1439 * Sysfs device attribute defines and structs
1440 * --------------------------------------------------------------------- */
1441
1442/* Voltages 0-6 */
1443
1444#define SENSOR_DEVICE_ATTR_IN(ix) \
1445static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \
b237eb25 1446 show_in, NULL, SYS_IN_INPUT, ix); \
9431996f 1447static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1448 show_in, set_in, SYS_IN_MIN, ix); \
9431996f 1449static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \
b237eb25 1450 show_in, set_in, SYS_IN_MAX, ix); \
9431996f 1451static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \
b237eb25 1452 show_in, NULL, SYS_IN_ALARM, ix)
9431996f
JH		 1453
1454SENSOR_DEVICE_ATTR_IN(0);
1455SENSOR_DEVICE_ATTR_IN(1);
1456SENSOR_DEVICE_ATTR_IN(2);
1457SENSOR_DEVICE_ATTR_IN(3);
1458SENSOR_DEVICE_ATTR_IN(4);
1459SENSOR_DEVICE_ATTR_IN(5);
1460SENSOR_DEVICE_ATTR_IN(6);
1461
1462/* Temperatures 1-3 */
1463
1464#define SENSOR_DEVICE_ATTR_TEMP(ix) \
1465static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \
b237eb25 1466 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \
9431996f 1467static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1468 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \
9431996f 1469static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \
b237eb25 1470 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \
9431996f 1471static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \
b237eb25 1472 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \
9431996f 1473static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \
b237eb25 1474 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \
9431996f 1475static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \
b237eb25 1476 show_temp, NULL, SYS_TEMP_FAULT, ix-1)
9431996f
JH		 1477
1478SENSOR_DEVICE_ATTR_TEMP(1);
1479SENSOR_DEVICE_ATTR_TEMP(2);
1480SENSOR_DEVICE_ATTR_TEMP(3);
1481
1482/* Zones 1-3 */
1483
1484#define SENSOR_DEVICE_ATTR_ZONE(ix) \
1485static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \
b237eb25 1486 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \
9431996f 1487static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \
b237eb25 1488 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \
9431996f 1489static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \
b237eb25 1490 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \
9431996f 1491static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \
b237eb25 1492 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \
9431996f 1493static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \
b237eb25 1494 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1)
9431996f
JH		 1495
1496SENSOR_DEVICE_ATTR_ZONE(1);
1497SENSOR_DEVICE_ATTR_ZONE(2);
1498SENSOR_DEVICE_ATTR_ZONE(3);
1499
1500/* Fans 1-4 */
1501
1502#define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \
1503static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
b237eb25 1504 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
9431996f 1505static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1506 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
9431996f 1507static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
b237eb25 1508 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
9431996f 1509static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \
b237eb25 1510 show_fan, set_fan, SYS_FAN_TYPE, ix-1)
9431996f
JH		 1511
1512SENSOR_DEVICE_ATTR_FAN_1TO4(1);
1513SENSOR_DEVICE_ATTR_FAN_1TO4(2);
1514SENSOR_DEVICE_ATTR_FAN_1TO4(3);
1515SENSOR_DEVICE_ATTR_FAN_1TO4(4);
1516
1517/* Fans 5-6 */
1518
1519#define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \
1520static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
b237eb25 1521 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
9431996f 1522static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1523 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
9431996f 1524static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
b237eb25 1525 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
9431996f 1526static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \
b237eb25 1527 show_fan, set_fan, SYS_FAN_MAX, ix-1)
9431996f
JH		 1528
1529SENSOR_DEVICE_ATTR_FAN_5TO6(5);
1530SENSOR_DEVICE_ATTR_FAN_5TO6(6);
1531
1532/* PWMs 1-3 */
1533
1534#define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \
1535static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
b237eb25 1536 show_pwm, set_pwm, SYS_PWM, ix-1); \
9431996f 1537static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
b237eb25 1538 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
9431996f 1539static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
b237eb25 1540 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \
9431996f 1541static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \
b237eb25 1542 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \
9431996f 1543static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \
b237eb25 1544 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \
9431996f 1545static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \
b237eb25 1546 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \
9431996f 1547static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \
b237eb25 1548 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \
9431996f 1549static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \
b237eb25 1550 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1)
9431996f
JH		 1551
1552SENSOR_DEVICE_ATTR_PWM_1TO3(1);
1553SENSOR_DEVICE_ATTR_PWM_1TO3(2);
1554SENSOR_DEVICE_ATTR_PWM_1TO3(3);
1555
1556/* PWMs 5-6 */
1557
1558#define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \
9b257714 1559static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
b237eb25 1560 show_pwm, set_pwm, SYS_PWM, ix-1); \
9b257714 1561static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
b237eb25 1562 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
9431996f 1563static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
b237eb25 1564 show_pwm, NULL, SYS_PWM_ENABLE, ix-1)
9431996f
JH		 1565
1566SENSOR_DEVICE_ATTR_PWM_5TO6(5);
1567SENSOR_DEVICE_ATTR_PWM_5TO6(6);
1568
1569/* Misc */
1570
1571static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm);
1572static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
e95c237d 1573static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */
9431996f 1574
9431996f
JH		 1575/* This struct holds all the attributes that are always present and need to be
1576 * created unconditionally. The attributes that need modification of their
1577 * permissions are created read-only and write permissions are added or removed
1578 * on the fly when required */
1579static struct attribute *dme1737_attr[] ={
b237eb25 1580 /* Voltages */
9b257714
JH		 1581 &sensor_dev_attr_in0_input.dev_attr.attr,
1582 &sensor_dev_attr_in0_min.dev_attr.attr,
1583 &sensor_dev_attr_in0_max.dev_attr.attr,
1584 &sensor_dev_attr_in0_alarm.dev_attr.attr,
1585 &sensor_dev_attr_in1_input.dev_attr.attr,
1586 &sensor_dev_attr_in1_min.dev_attr.attr,
1587 &sensor_dev_attr_in1_max.dev_attr.attr,
1588 &sensor_dev_attr_in1_alarm.dev_attr.attr,
1589 &sensor_dev_attr_in2_input.dev_attr.attr,
1590 &sensor_dev_attr_in2_min.dev_attr.attr,
1591 &sensor_dev_attr_in2_max.dev_attr.attr,
1592 &sensor_dev_attr_in2_alarm.dev_attr.attr,
1593 &sensor_dev_attr_in3_input.dev_attr.attr,
1594 &sensor_dev_attr_in3_min.dev_attr.attr,
1595 &sensor_dev_attr_in3_max.dev_attr.attr,
1596 &sensor_dev_attr_in3_alarm.dev_attr.attr,
1597 &sensor_dev_attr_in4_input.dev_attr.attr,
1598 &sensor_dev_attr_in4_min.dev_attr.attr,
1599 &sensor_dev_attr_in4_max.dev_attr.attr,
1600 &sensor_dev_attr_in4_alarm.dev_attr.attr,
1601 &sensor_dev_attr_in5_input.dev_attr.attr,
1602 &sensor_dev_attr_in5_min.dev_attr.attr,
1603 &sensor_dev_attr_in5_max.dev_attr.attr,
1604 &sensor_dev_attr_in5_alarm.dev_attr.attr,
1605 &sensor_dev_attr_in6_input.dev_attr.attr,
1606 &sensor_dev_attr_in6_min.dev_attr.attr,
1607 &sensor_dev_attr_in6_max.dev_attr.attr,
1608 &sensor_dev_attr_in6_alarm.dev_attr.attr,
b237eb25 1609 /* Temperatures */
9b257714
JH		 1610 &sensor_dev_attr_temp1_input.dev_attr.attr,
1611 &sensor_dev_attr_temp1_min.dev_attr.attr,
1612 &sensor_dev_attr_temp1_max.dev_attr.attr,
1613 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
1614 &sensor_dev_attr_temp1_fault.dev_attr.attr,
9b257714
JH		 1615 &sensor_dev_attr_temp2_input.dev_attr.attr,
1616 &sensor_dev_attr_temp2_min.dev_attr.attr,
1617 &sensor_dev_attr_temp2_max.dev_attr.attr,
1618 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
1619 &sensor_dev_attr_temp2_fault.dev_attr.attr,
9b257714
JH		 1620 &sensor_dev_attr_temp3_input.dev_attr.attr,
1621 &sensor_dev_attr_temp3_min.dev_attr.attr,
1622 &sensor_dev_attr_temp3_max.dev_attr.attr,
1623 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1624 &sensor_dev_attr_temp3_fault.dev_attr.attr,
b237eb25 1625 /* Zones */
9b257714
JH		 1626 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1627 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1628 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1629 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr,
9b257714
JH		 1630 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1631 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1632 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1633 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr,
549edb83
JH		 1634 NULL
1635};
1636
1637static const struct attribute_group dme1737_group = {
1638 .attrs = dme1737_attr,
1639};
1640
ea694431
JH		 1641/* The following struct holds temp offset attributes, which are not available
1642 * in all chips. The following chips support them:
1643 * DME1737, SCH311x */
1644static struct attribute *dme1737_temp_offset_attr[] = {
549edb83
JH		 1645 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1646 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1647 &sensor_dev_attr_temp3_offset.dev_attr.attr,
9431996f
JH		 1648 NULL
1649};
1650
ea694431
JH		 1651static const struct attribute_group dme1737_temp_offset_group = {
1652 .attrs = dme1737_temp_offset_attr,
9431996f
JH		 1653};
1654
ea694431
JH		 1655/* The following struct holds VID related attributes, which are not available
1656 * in all chips. The following chips support them:
1657 * DME1737 */
9d091446
JD		 1658static struct attribute *dme1737_vid_attr[] = {
1659 &dev_attr_vrm.attr,
1660 &dev_attr_cpu0_vid.attr,
1661 NULL
1662};
1663
1664static const struct attribute_group dme1737_vid_group = {
1665 .attrs = dme1737_vid_attr,
1666};
1667
ea694431
JH		 1668/* The following struct holds temp zone 3 related attributes, which are not
1669 * available in all chips. The following chips support them:
1670 * DME1737, SCH311x, SCH5027 */
1671static struct attribute *dme1737_zone3_attr[] = {
1672 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1673 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1674 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1675 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr,
1676 NULL
1677};
1678
1679static const struct attribute_group dme1737_zone3_group = {
1680 .attrs = dme1737_zone3_attr,
1681};
1682
1683
1684/* The following struct holds temp zone hysteresis related attributes, which
1685 * are not available in all chips. The following chips support them:
1686 * DME1737, SCH311x */
1687static struct attribute *dme1737_zone_hyst_attr[] = {
1688 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
1689 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
1690 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr,
1691 NULL
1692};
1693
1694static const struct attribute_group dme1737_zone_hyst_group = {
1695 .attrs = dme1737_zone_hyst_attr,
1696};
1697
9431996f
JH		 1698/* The following structs hold the PWM attributes, some of which are optional.
1699 * Their creation depends on the chip configuration which is determined during
1700 * module load. */
73ce48f6 1701static struct attribute *dme1737_pwm1_attr[] = {
9b257714
JH		 1702 &sensor_dev_attr_pwm1.dev_attr.attr,
1703 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1704 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1705 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1706 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
9b257714
JH		 1707 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1708 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
9431996f
JH		 1709 NULL
1710};
73ce48f6 1711static struct attribute *dme1737_pwm2_attr[] = {
9b257714
JH		 1712 &sensor_dev_attr_pwm2.dev_attr.attr,
1713 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1714 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1715 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1716 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
9b257714
JH		 1717 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1718 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
9431996f
JH		 1719 NULL
1720};
73ce48f6 1721static struct attribute *dme1737_pwm3_attr[] = {
9b257714
JH		 1722 &sensor_dev_attr_pwm3.dev_attr.attr,
1723 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1724 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1725 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1726 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
9b257714
JH		 1727 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1728 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
9431996f
JH		 1729 NULL
1730};
73ce48f6 1731static struct attribute *dme1737_pwm5_attr[] = {
9b257714
JH		 1732 &sensor_dev_attr_pwm5.dev_attr.attr,
1733 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1734 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
9431996f
JH		 1735 NULL
1736};
73ce48f6 1737static struct attribute *dme1737_pwm6_attr[] = {
9b257714
JH		 1738 &sensor_dev_attr_pwm6.dev_attr.attr,
1739 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1740 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
9431996f
JH		 1741 NULL
1742};
1743
1744static const struct attribute_group dme1737_pwm_group[] = {
73ce48f6
JH		 1745 { .attrs = dme1737_pwm1_attr },
1746 { .attrs = dme1737_pwm2_attr },
1747 { .attrs = dme1737_pwm3_attr },
9431996f 1748 { .attrs = NULL },
73ce48f6
JH		 1749 { .attrs = dme1737_pwm5_attr },
1750 { .attrs = dme1737_pwm6_attr },
9431996f
JH		 1751};
1752
ea694431
JH		 1753/* The following struct holds auto PWM min attributes, which are not available
1754 * in all chips. Their creation depends on the chip type which is determined
549edb83 1755 * during module load. */
ea694431 1756static struct attribute *dme1737_auto_pwm_min_attr[] = {
549edb83
JH		 1757 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
1758 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
1759 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
1760};
1761
9431996f
JH		 1762/* The following structs hold the fan attributes, some of which are optional.
1763 * Their creation depends on the chip configuration which is determined during
1764 * module load. */
73ce48f6 1765static struct attribute *dme1737_fan1_attr[] = {
9b257714
JH		 1766 &sensor_dev_attr_fan1_input.dev_attr.attr,
1767 &sensor_dev_attr_fan1_min.dev_attr.attr,
1768 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1769 &sensor_dev_attr_fan1_type.dev_attr.attr,
9431996f
JH		 1770 NULL
1771};
73ce48f6 1772static struct attribute *dme1737_fan2_attr[] = {
9b257714
JH		 1773 &sensor_dev_attr_fan2_input.dev_attr.attr,
1774 &sensor_dev_attr_fan2_min.dev_attr.attr,
1775 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1776 &sensor_dev_attr_fan2_type.dev_attr.attr,
9431996f
JH		 1777 NULL
1778};
73ce48f6 1779static struct attribute *dme1737_fan3_attr[] = {
9b257714
JH		 1780 &sensor_dev_attr_fan3_input.dev_attr.attr,
1781 &sensor_dev_attr_fan3_min.dev_attr.attr,
1782 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1783 &sensor_dev_attr_fan3_type.dev_attr.attr,
9431996f
JH		 1784 NULL
1785};
73ce48f6 1786static struct attribute *dme1737_fan4_attr[] = {
9b257714
JH		 1787 &sensor_dev_attr_fan4_input.dev_attr.attr,
1788 &sensor_dev_attr_fan4_min.dev_attr.attr,
1789 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1790 &sensor_dev_attr_fan4_type.dev_attr.attr,
9431996f
JH		 1791 NULL
1792};
73ce48f6 1793static struct attribute *dme1737_fan5_attr[] = {
9b257714
JH		 1794 &sensor_dev_attr_fan5_input.dev_attr.attr,
1795 &sensor_dev_attr_fan5_min.dev_attr.attr,
1796 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1797 &sensor_dev_attr_fan5_max.dev_attr.attr,
9431996f
JH		 1798 NULL
1799};
73ce48f6 1800static struct attribute *dme1737_fan6_attr[] = {
9b257714
JH		 1801 &sensor_dev_attr_fan6_input.dev_attr.attr,
1802 &sensor_dev_attr_fan6_min.dev_attr.attr,
1803 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
1804 &sensor_dev_attr_fan6_max.dev_attr.attr,
9431996f
JH		 1805 NULL
1806};
1807
1808static const struct attribute_group dme1737_fan_group[] = {
73ce48f6
JH		 1809 { .attrs = dme1737_fan1_attr },
1810 { .attrs = dme1737_fan2_attr },
1811 { .attrs = dme1737_fan3_attr },
1812 { .attrs = dme1737_fan4_attr },
1813 { .attrs = dme1737_fan5_attr },
1814 { .attrs = dme1737_fan6_attr },
9431996f
JH		 1815};
1816
549edb83 1817/* The permissions of the following zone attributes are changed to read-
9431996f 1818 * writeable if the chip is *not* locked. Otherwise they stay read-only. */
549edb83 1819static struct attribute *dme1737_zone_chmod_attr[] = {
9b257714
JH		 1820 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1821 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1822 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
9b257714
JH		 1823 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1824 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1825 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
ea694431
JH		 1826 NULL
1827};
1828
1829static const struct attribute_group dme1737_zone_chmod_group = {
1830 .attrs = dme1737_zone_chmod_attr,
1831};
1832
1833
1834/* The permissions of the following zone 3 attributes are changed to read-
1835 * writeable if the chip is *not* locked. Otherwise they stay read-only. */
1836static struct attribute *dme1737_zone3_chmod_attr[] = {
9b257714
JH		 1837 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1838 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1839 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
9431996f
JH		 1840 NULL
1841};
1842
ea694431
JH		 1843static const struct attribute_group dme1737_zone3_chmod_group = {
1844 .attrs = dme1737_zone3_chmod_attr,
9431996f
JH		 1845};
1846
1847/* The permissions of the following PWM attributes are changed to read-
1848 * writeable if the chip is *not* locked and the respective PWM is available.
1849 * Otherwise they stay read-only. */
73ce48f6 1850static struct attribute *dme1737_pwm1_chmod_attr[] = {
9b257714
JH		 1851 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1852 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1853 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1854 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
9b257714 1855 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
9431996f
JH		 1856 NULL
1857};
73ce48f6 1858static struct attribute *dme1737_pwm2_chmod_attr[] = {
9b257714
JH		 1859 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1860 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1861 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1862 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
9b257714 1863 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
9431996f
JH		 1864 NULL
1865};
73ce48f6 1866static struct attribute *dme1737_pwm3_chmod_attr[] = {
9b257714
JH		 1867 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1868 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1869 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1870 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
9b257714 1871 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
9431996f
JH		 1872 NULL
1873};
73ce48f6 1874static struct attribute *dme1737_pwm5_chmod_attr[] = {
9b257714
JH		 1875 &sensor_dev_attr_pwm5.dev_attr.attr,
1876 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
9431996f
JH		 1877 NULL
1878};
73ce48f6 1879static struct attribute *dme1737_pwm6_chmod_attr[] = {
9b257714
JH		 1880 &sensor_dev_attr_pwm6.dev_attr.attr,
1881 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
9431996f
JH		 1882 NULL
1883};
1884
73ce48f6
JH		 1885static const struct attribute_group dme1737_pwm_chmod_group[] = {
1886 { .attrs = dme1737_pwm1_chmod_attr },
1887 { .attrs = dme1737_pwm2_chmod_attr },
1888 { .attrs = dme1737_pwm3_chmod_attr },
9431996f 1889 { .attrs = NULL },
73ce48f6
JH		 1890 { .attrs = dme1737_pwm5_chmod_attr },
1891 { .attrs = dme1737_pwm6_chmod_attr },
9431996f
JH		 1892};
1893
1894/* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
1895 * chip is not locked. Otherwise they are read-only. */
73ce48f6 1896static struct attribute *dme1737_pwm_chmod_attr[] = {
9431996f
JH		 1897 &sensor_dev_attr_pwm1.dev_attr.attr,
1898 &sensor_dev_attr_pwm2.dev_attr.attr,
1899 &sensor_dev_attr_pwm3.dev_attr.attr,
1900};
1901
1902/* ---------------------------------------------------------------------
1903 * Super-IO functions
1904 * --------------------------------------------------------------------- */
1905
b237eb25
JH		 1906static inline void dme1737_sio_enter(int sio_cip)
1907{
1908 outb(0x55, sio_cip);
1909}
1910
1911static inline void dme1737_sio_exit(int sio_cip)
1912{
1913 outb(0xaa, sio_cip);
1914}
1915
9431996f
JH		 1916static inline int dme1737_sio_inb(int sio_cip, int reg)
1917{
1918 outb(reg, sio_cip);
1919 return inb(sio_cip + 1);
1920}
1921
1922static inline void dme1737_sio_outb(int sio_cip, int reg, int val)
1923{
1924 outb(reg, sio_cip);
1925 outb(val, sio_cip + 1);
1926}
1927
9431996f 1928/* ---------------------------------------------------------------------
e95c237d 1929 * Device initialization
9431996f
JH		 1930 * --------------------------------------------------------------------- */
1931
67e2f328 1932static int dme1737_i2c_get_features(int, struct dme1737_data*);
9431996f 1933
b237eb25 1934static void dme1737_chmod_file(struct device *dev,
9431996f
JH		 1935 struct attribute *attr, mode_t mode)
1936{
b237eb25
JH		 1937 if (sysfs_chmod_file(&dev->kobj, attr, mode)) {
1938 dev_warn(dev, "Failed to change permissions of %s.\n",
9431996f
JH		 1939 attr->name);
1940 }
1941}
1942
b237eb25 1943static void dme1737_chmod_group(struct device *dev,
9431996f
JH		 1944 const struct attribute_group *group,
1945 mode_t mode)
1946{
1947 struct attribute **attr;
1948
1949 for (attr = group->attrs; *attr; attr++) {
b237eb25 1950 dme1737_chmod_file(dev, *attr, mode);
9431996f
JH		 1951 }
1952}
1953
b237eb25 1954static void dme1737_remove_files(struct device *dev)
9431996f 1955{
b237eb25
JH		 1956 struct dme1737_data *data = dev_get_drvdata(dev);
1957 int ix;
1958
1959 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
ea694431 1960 if (data->has_features & HAS_FAN(ix)) {
b237eb25
JH		 1961 sysfs_remove_group(&dev->kobj,
1962 &dme1737_fan_group[ix]);
1963 }
1964 }
1965
1966 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
ea694431 1967 if (data->has_features & HAS_PWM(ix)) {
b237eb25
JH		 1968 sysfs_remove_group(&dev->kobj,
1969 &dme1737_pwm_group[ix]);
ea694431 1970 if ((data->has_features & HAS_PWM_MIN) && ix < 3) {
549edb83 1971 sysfs_remove_file(&dev->kobj,
ea694431 1972 dme1737_auto_pwm_min_attr[ix]);
549edb83 1973 }
b237eb25
JH		 1974 }
1975 }
1976
ea694431
JH		 1977 if (data->has_features & HAS_TEMP_OFFSET) {
1978 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group);
549edb83 1979 }
ea694431 1980 if (data->has_features & HAS_VID) {
9d091446
JD		 1981 sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
1982 }
ea694431
JH		 1983 if (data->has_features & HAS_ZONE3) {
1984 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group);
1985 }
1986 if (data->has_features & HAS_ZONE_HYST) {
1987 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group);
1988 }
b237eb25 1989 sysfs_remove_group(&dev->kobj, &dme1737_group);
e95c237d 1990
dbc2bc25 1991 if (!data->client) {
e95c237d
JH		 1992 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
1993 }
b237eb25
JH		 1994}
1995
1996static int dme1737_create_files(struct device *dev)
1997{
1998 struct dme1737_data *data = dev_get_drvdata(dev);
1999 int err, ix;
2000
e95c237d 2001 /* Create a name attribute for ISA devices */
dbc2bc25 2002 if (!data->client &&
e95c237d
JH		 2003 (err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr))) {
2004 goto exit;
2005 }
2006
b237eb25
JH		 2007 /* Create standard sysfs attributes */
2008 if ((err = sysfs_create_group(&dev->kobj, &dme1737_group))) {
e95c237d 2009 goto exit_remove;
b237eb25
JH		 2010 }
2011
ea694431
JH		 2012 /* Create chip-dependent sysfs attributes */
2013 if ((data->has_features & HAS_TEMP_OFFSET) &&
549edb83 2014 (err = sysfs_create_group(&dev->kobj,
ea694431 2015 &dme1737_temp_offset_group))) {
549edb83
JH		 2016 goto exit_remove;
2017 }
ea694431 2018 if ((data->has_features & HAS_VID) &&
9d091446
JD		 2019 (err = sysfs_create_group(&dev->kobj,
2020 &dme1737_vid_group))) {
2021 goto exit_remove;
2022 }
ea694431
JH		 2023 if ((data->has_features & HAS_ZONE3) &&
2024 (err = sysfs_create_group(&dev->kobj,
2025 &dme1737_zone3_group))) {
2026 goto exit_remove;
2027 }
2028 if ((data->has_features & HAS_ZONE_HYST) &&
2029 (err = sysfs_create_group(&dev->kobj,
2030 &dme1737_zone_hyst_group))) {
2031 goto exit_remove;
2032 }
9d091446 2033
b237eb25
JH		 2034 /* Create fan sysfs attributes */
2035 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
ea694431 2036 if (data->has_features & HAS_FAN(ix)) {
b237eb25
JH		 2037 if ((err = sysfs_create_group(&dev->kobj,
2038 &dme1737_fan_group[ix]))) {
2039 goto exit_remove;
2040 }
2041 }
2042 }
2043
2044 /* Create PWM sysfs attributes */
2045 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
ea694431 2046 if (data->has_features & HAS_PWM(ix)) {
b237eb25
JH		 2047 if ((err = sysfs_create_group(&dev->kobj,
2048 &dme1737_pwm_group[ix]))) {
2049 goto exit_remove;
2050 }
ea694431 2051 if ((data->has_features & HAS_PWM_MIN) && ix < 3 &&
549edb83 2052 (err = sysfs_create_file(&dev->kobj,
ea694431 2053 dme1737_auto_pwm_min_attr[ix]))) {
549edb83
JH		 2054 goto exit_remove;
2055 }
b237eb25
JH		 2056 }
2057 }
2058
2059 /* Inform if the device is locked. Otherwise change the permissions of
2060 * selected attributes from read-only to read-writeable. */
2061 if (data->config & 0x02) {
2062 dev_info(dev, "Device is locked. Some attributes "
2063 "will be read-only.\n");
2064 } else {
549edb83
JH		 2065 /* Change permissions of zone sysfs attributes */
2066 dme1737_chmod_group(dev, &dme1737_zone_chmod_group,
b237eb25
JH		 2067 S_IRUGO | S_IWUSR);
2068
ea694431
JH		 2069 /* Change permissions of chip-dependent sysfs attributes */
2070 if (data->has_features & HAS_TEMP_OFFSET) {
2071 dme1737_chmod_group(dev, &dme1737_temp_offset_group,
2072 S_IRUGO | S_IWUSR);
2073 }
2074 if (data->has_features & HAS_ZONE3) {
2075 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group,
2076 S_IRUGO | S_IWUSR);
2077 }
2078 if (data->has_features & HAS_ZONE_HYST) {
2079 dme1737_chmod_group(dev, &dme1737_zone_hyst_group,
549edb83
JH		 2080 S_IRUGO | S_IWUSR);
2081 }
2082
73ce48f6
JH		 2083 /* Change permissions of PWM sysfs attributes */
2084 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) {
ea694431 2085 if (data->has_features & HAS_PWM(ix)) {
b237eb25 2086 dme1737_chmod_group(dev,
73ce48f6 2087 &dme1737_pwm_chmod_group[ix],
b237eb25 2088 S_IRUGO | S_IWUSR);
ea694431
JH		 2089 if ((data->has_features & HAS_PWM_MIN) &&
2090 ix < 3) {
549edb83 2091 dme1737_chmod_file(dev,
ea694431 2092 dme1737_auto_pwm_min_attr[ix],
549edb83
JH		 2093 S_IRUGO | S_IWUSR);
2094 }
b237eb25
JH		 2095 }
2096 }
2097
2098 /* Change permissions of pwm[1-3] if in manual mode */
2099 for (ix = 0; ix < 3; ix++) {
ea694431 2100 if ((data->has_features & HAS_PWM(ix)) &&
b237eb25
JH		 2101 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) {
2102 dme1737_chmod_file(dev,
73ce48f6 2103 dme1737_pwm_chmod_attr[ix],
b237eb25
JH		 2104 S_IRUGO | S_IWUSR);
2105 }
2106 }
2107 }
2108
2109 return 0;
2110
2111exit_remove:
2112 dme1737_remove_files(dev);
2113exit:
2114 return err;
2115}
2116
2117static int dme1737_init_device(struct device *dev)
2118{
2119 struct dme1737_data *data = dev_get_drvdata(dev);
dbc2bc25 2120 struct i2c_client *client = data->client;
9431996f
JH		 2121 int ix;
2122 u8 reg;
2123
549edb83
JH		 2124 /* Point to the right nominal voltages array */
2125 data->in_nominal = IN_NOMINAL(data->type);
2126
dbc2bc25 2127 data->config = dme1737_read(data, DME1737_REG_CONFIG);
b237eb25
JH		 2128 /* Inform if part is not monitoring/started */
2129 if (!(data->config & 0x01)) {
2130 if (!force_start) {
2131 dev_err(dev, "Device is not monitoring. "
2132 "Use the force_start load parameter to "
2133 "override.\n");
2134 return -EFAULT;
2135 }
2136
2137 /* Force monitoring */
2138 data->config |= 0x01;
dbc2bc25 2139 dme1737_write(data, DME1737_REG_CONFIG, data->config);
b237eb25 2140 }
9431996f
JH		 2141 /* Inform if part is not ready */
2142 if (!(data->config & 0x04)) {
b237eb25 2143 dev_err(dev, "Device is not ready.\n");
9431996f
JH		 2144 return -EFAULT;
2145 }
2146
ea694431
JH		 2147 /* Determine which optional fan and pwm features are enabled (only
2148 * valid for I2C devices) */
dbc2bc25
JD		 2149 if (client) { /* I2C chip */
2150 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
e95c237d
JH		 2151 /* Check if optional fan3 input is enabled */
2152 if (data->config2 & 0x04) {
ea694431 2153 data->has_features |= HAS_FAN(2);
e95c237d 2154 }
9431996f 2155
e95c237d
JH		 2156 /* Fan4 and pwm3 are only available if the client's I2C address
2157 * is the default 0x2e. Otherwise the I/Os associated with
2158 * these functions are used for addr enable/select. */
dbc2bc25 2159 if (client->addr == 0x2e) {
ea694431 2160 data->has_features |= HAS_FAN(3) | HAS_PWM(2);
e95c237d 2161 }
9431996f 2162
e95c237d
JH		 2163 /* Determine which of the optional fan[5-6] and pwm[5-6]
2164 * features are enabled. For this, we need to query the runtime
2165 * registers through the Super-IO LPC interface. Try both
2166 * config ports 0x2e and 0x4e. */
2167 if (dme1737_i2c_get_features(0x2e, data) &&
2168 dme1737_i2c_get_features(0x4e, data)) {
2169 dev_warn(dev, "Failed to query Super-IO for optional "
2170 "features.\n");
2171 }
9431996f
JH		 2172 }
2173
ea694431
JH		 2174 /* Fan[1-2] and pwm[1-2] are present in all chips */
2175 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1);
2176
2177 /* Chip-dependent features */
2178 switch (data->type) {
2179 case dme1737:
2180 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 |
2181 HAS_ZONE_HYST | HAS_PWM_MIN;
2182 break;
2183 case sch311x:
2184 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 |
2185 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2);
2186 break;
2187 case sch5027:
2188 data->has_features |= HAS_ZONE3;
2189 break;
2190 case sch5127:
2191 data->has_features |= HAS_FAN(2) | HAS_PWM(2);
2192 break;
2193 default:
2194 break;
2195 }
9431996f 2196
b237eb25 2197 dev_info(dev, "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, "
9431996f 2198 "fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n",
ea694431
JH		 2199 (data->has_features & HAS_PWM(2)) ? "yes" : "no",
2200 (data->has_features & HAS_PWM(4)) ? "yes" : "no",
2201 (data->has_features & HAS_PWM(5)) ? "yes" : "no",
2202 (data->has_features & HAS_FAN(2)) ? "yes" : "no",
2203 (data->has_features & HAS_FAN(3)) ? "yes" : "no",
2204 (data->has_features & HAS_FAN(4)) ? "yes" : "no",
2205 (data->has_features & HAS_FAN(5)) ? "yes" : "no");
9431996f 2206
dbc2bc25 2207 reg = dme1737_read(data, DME1737_REG_TACH_PWM);
9431996f 2208 /* Inform if fan-to-pwm mapping differs from the default */
dbc2bc25 2209 if (client && reg != 0xa4) { /* I2C chip */
b237eb25 2210 dev_warn(dev, "Non-standard fan to pwm mapping: "
9431996f
JH		 2211 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, "
2212 "fan4->pwm%d. Please report to the driver "
2213 "maintainer.\n",
2214 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2215 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1);
dbc2bc25 2216 } else if (!client && reg != 0x24) { /* ISA chip */
e95c237d
JH		 2217 dev_warn(dev, "Non-standard fan to pwm mapping: "
2218 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. "
2219 "Please report to the driver maintainer.\n",
2220 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2221 ((reg >> 4) & 0x03) + 1);
9431996f
JH		 2222 }
2223
2224 /* Switch pwm[1-3] to manual mode if they are currently disabled and
2225 * set the duty-cycles to 0% (which is identical to the PWMs being
2226 * disabled). */
2227 if (!(data->config & 0x02)) {
2228 for (ix = 0; ix < 3; ix++) {
dbc2bc25 2229 data->pwm_config[ix] = dme1737_read(data,
9431996f 2230 DME1737_REG_PWM_CONFIG(ix));
ea694431 2231 if ((data->has_features & HAS_PWM(ix)) &&
9431996f 2232 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) {
b237eb25 2233 dev_info(dev, "Switching pwm%d to "
9431996f
JH		 2234 "manual mode.\n", ix + 1);
2235 data->pwm_config[ix] = PWM_EN_TO_REG(1,
2236 data->pwm_config[ix]);
dbc2bc25
JD		 2237 dme1737_write(data, DME1737_REG_PWM(ix), 0);
2238 dme1737_write(data,
9431996f
JH		 2239 DME1737_REG_PWM_CONFIG(ix),
2240 data->pwm_config[ix]);
2241 }
2242 }
2243 }
2244
2245 /* Initialize the default PWM auto channels zone (acz) assignments */
2246 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */
2247 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */
2248 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
2249
2250 /* Set VRM */
ea694431 2251 if (data->has_features & HAS_VID) {
549edb83
JH		 2252 data->vrm = vid_which_vrm();
2253 }
9431996f
JH		 2254
2255 return 0;
2256}
2257
67e2f328
JH		 2258/* ---------------------------------------------------------------------
2259 * I2C device detection and registration
2260 * --------------------------------------------------------------------- */
2261
2262static struct i2c_driver dme1737_i2c_driver;
2263
2264static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
2265{
2266 int err = 0, reg;
2267 u16 addr;
2268
2269 dme1737_sio_enter(sio_cip);
2270
2271 /* Check device ID
ea694431 2272 * We currently know about two kinds of DME1737 and SCH5027. */
345a2224 2273 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
ea694431
JH		 2274 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 ||
2275 reg == SCH5027_ID)) {
67e2f328
JH		 2276 err = -ENODEV;
2277 goto exit;
2278 }
2279
2280 /* Select logical device A (runtime registers) */
2281 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2282
2283 /* Get the base address of the runtime registers */
2284 if (!(addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2285 dme1737_sio_inb(sio_cip, 0x61))) {
2286 err = -ENODEV;
2287 goto exit;
2288 }
2289
2290 /* Read the runtime registers to determine which optional features
2291 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
2292 * to '10' if the respective feature is enabled. */
2293 if ((inb(addr + 0x43) & 0x0c) == 0x08) { /* fan6 */
ea694431 2294 data->has_features |= HAS_FAN(5);
67e2f328
JH		 2295 }
2296 if ((inb(addr + 0x44) & 0x0c) == 0x08) { /* pwm6 */
ea694431 2297 data->has_features |= HAS_PWM(5);
67e2f328
JH		 2298 }
2299 if ((inb(addr + 0x45) & 0x0c) == 0x08) { /* fan5 */
ea694431 2300 data->has_features |= HAS_FAN(4);
67e2f328
JH		 2301 }
2302 if ((inb(addr + 0x46) & 0x0c) == 0x08) { /* pwm5 */
ea694431 2303 data->has_features |= HAS_PWM(4);
67e2f328
JH		 2304 }
2305
2306exit:
2307 dme1737_sio_exit(sio_cip);
2308
2309 return err;
2310}
2311
67a37308 2312/* Return 0 if detection is successful, -ENODEV otherwise */
310ec792 2313static int dme1737_i2c_detect(struct i2c_client *client,
67a37308 2314 struct i2c_board_info *info)
9431996f 2315{
67a37308
JD		 2316 struct i2c_adapter *adapter = client->adapter;
2317 struct device *dev = &adapter->dev;
9431996f 2318 u8 company, verstep = 0;
9431996f
JH		 2319 const char *name;
2320
2321 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
67a37308 2322 return -ENODEV;
9431996f
JH		 2323 }
2324
52df6440
JD		 2325 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
2326 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
9431996f 2327
52df6440
JD		 2328 if (company == DME1737_COMPANY_SMSC &&
2329 verstep == SCH5027_VERSTEP) {
549edb83 2330 name = "sch5027";
52df6440
JD		 2331 } else if (company == DME1737_COMPANY_SMSC &&
2332 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) {
549edb83 2333 name = "dme1737";
52df6440
JD		 2334 } else {
2335 return -ENODEV;
549edb83 2336 }
9431996f 2337
549edb83 2338 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n",
52df6440
JD		 2339 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737",
2340 client->addr, verstep);
67a37308
JD		 2341 strlcpy(info->type, name, I2C_NAME_SIZE);
2342
2343 return 0;
2344}
2345
2346static int dme1737_i2c_probe(struct i2c_client *client,
2347 const struct i2c_device_id *id)
2348{
2349 struct dme1737_data *data;
2350 struct device *dev = &client->dev;
2351 int err;
2352
2353 data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL);
2354 if (!data) {
2355 err = -ENOMEM;
2356 goto exit;
2357 }
2358
2359 i2c_set_clientdata(client, data);
2360 data->type = id->driver_data;
2361 data->client = client;
2362 data->name = client->name;
2363 mutex_init(&data->update_lock);
b237eb25 2364
9431996f 2365 /* Initialize the DME1737 chip */
b237eb25
JH		 2366 if ((err = dme1737_init_device(dev))) {
2367 dev_err(dev, "Failed to initialize device.\n");
67a37308 2368 goto exit_kfree;
9431996f
JH		 2369 }
2370
b237eb25
JH		 2371 /* Create sysfs files */
2372 if ((err = dme1737_create_files(dev))) {
2373 dev_err(dev, "Failed to create sysfs files.\n");
67a37308 2374 goto exit_kfree;
9431996f
JH		 2375 }
2376
2377 /* Register device */
62ee3e10 2378 data->hwmon_dev = hwmon_device_register(dev);
1beeffe4 2379 if (IS_ERR(data->hwmon_dev)) {
b237eb25 2380 dev_err(dev, "Failed to register device.\n");
1beeffe4 2381 err = PTR_ERR(data->hwmon_dev);
9431996f
JH		 2382 goto exit_remove;
2383 }
2384
9431996f
JH		 2385 return 0;
2386
2387exit_remove:
b237eb25 2388 dme1737_remove_files(dev);
9431996f
JH		 2389exit_kfree:
2390 kfree(data);
2391exit:
2392 return err;
2393}
2394
67a37308 2395static int dme1737_i2c_remove(struct i2c_client *client)
9431996f
JH		 2396{
2397 struct dme1737_data *data = i2c_get_clientdata(client);
9431996f 2398
1beeffe4 2399 hwmon_device_unregister(data->hwmon_dev);
b237eb25 2400 dme1737_remove_files(&client->dev);
9431996f 2401
9431996f
JH		 2402 kfree(data);
2403 return 0;
2404}
2405
67a37308
JD		 2406static const struct i2c_device_id dme1737_id[] = {
2407 { "dme1737", dme1737 },
2408 { "sch5027", sch5027 },
2409 { }
2410};
2411MODULE_DEVICE_TABLE(i2c, dme1737_id);
2412
b237eb25 2413static struct i2c_driver dme1737_i2c_driver = {
67a37308 2414 .class = I2C_CLASS_HWMON,
9431996f
JH		 2415 .driver = {
2416 .name = "dme1737",
2417 },
67a37308
JD		 2418 .probe = dme1737_i2c_probe,
2419 .remove = dme1737_i2c_remove,
2420 .id_table = dme1737_id,
2421 .detect = dme1737_i2c_detect,
c3813d6a 2422 .address_list = normal_i2c,
9431996f
JH		 2423};
2424
e95c237d
JH		 2425/* ---------------------------------------------------------------------
2426 * ISA device detection and registration
2427 * --------------------------------------------------------------------- */
2428
2429static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
2430{
2431 int err = 0, reg;
2432 unsigned short base_addr;
2433
2434 dme1737_sio_enter(sio_cip);
2435
2436 /* Check device ID
ea694431 2437 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127 */
67b671bc 2438 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
ea694431
JH		 2439 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID ||
2440 reg == SCH5127_ID)) {
e95c237d
JH		 2441 err = -ENODEV;
2442 goto exit;
2443 }
2444
2445 /* Select logical device A (runtime registers) */
2446 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2447
2448 /* Get the base address of the runtime registers */
2449 if (!(base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2450 dme1737_sio_inb(sio_cip, 0x61))) {
9c6e13b4 2451 pr_err("Base address not set\n");
e95c237d
JH		 2452 err = -ENODEV;
2453 goto exit;
2454 }
2455
2456 /* Access to the hwmon registers is through an index/data register
2457 * pair located at offset 0x70/0x71. */
2458 *addr = base_addr + 0x70;
2459
2460exit:
2461 dme1737_sio_exit(sio_cip);
2462 return err;
2463}
2464
2465static int __init dme1737_isa_device_add(unsigned short addr)
2466{
2467 struct resource res = {
2468 .start = addr,
2469 .end = addr + DME1737_EXTENT - 1,
2470 .name = "dme1737",
2471 .flags = IORESOURCE_IO,
2472 };
2473 int err;
2474
b9acb64a
JD		 2475 err = acpi_check_resource_conflict(&res);
2476 if (err)
2477 goto exit;
2478
e95c237d 2479 if (!(pdev = platform_device_alloc("dme1737", addr))) {
9c6e13b4 2480 pr_err("Failed to allocate device\n");
e95c237d
JH		 2481 err = -ENOMEM;
2482 goto exit;
2483 }
2484
2485 if ((err = platform_device_add_resources(pdev, &res, 1))) {
9c6e13b4 2486 pr_err("Failed to add device resource (err = %d)\n", err);
e95c237d
JH		 2487 goto exit_device_put;
2488 }
2489
2490 if ((err = platform_device_add(pdev))) {
9c6e13b4 2491 pr_err("Failed to add device (err = %d)\n", err);
e95c237d
JH		 2492 goto exit_device_put;
2493 }
2494
2495 return 0;
2496
2497exit_device_put:
2498 platform_device_put(pdev);
2499 pdev = NULL;
2500exit:
2501 return err;
2502}
2503
2504static int __devinit dme1737_isa_probe(struct platform_device *pdev)
2505{
2506 u8 company, device;
2507 struct resource *res;
e95c237d
JH		 2508 struct dme1737_data *data;
2509 struct device *dev = &pdev->dev;
2510 int err;
2511
2512 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2513 if (!request_region(res->start, DME1737_EXTENT, "dme1737")) {
2514 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
2515 (unsigned short)res->start,
2516 (unsigned short)res->start + DME1737_EXTENT - 1);
2517 err = -EBUSY;
2518 goto exit;
2519 }
2520
2521 if (!(data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL))) {
2522 err = -ENOMEM;
2523 goto exit_release_region;
2524 }
2525
dbc2bc25 2526 data->addr = res->start;
e95c237d
JH		 2527 platform_set_drvdata(pdev, data);
2528
55d68d75 2529 /* Skip chip detection if module is loaded with force_id parameter */
ea694431
JH		 2530 switch (force_id) {
2531 case SCH3112_ID:
2532 case SCH3114_ID:
2533 case SCH3116_ID:
2534 data->type = sch311x;
2535 break;
2536 case SCH5127_ID:
2537 data->type = sch5127;
2538 break;
2539 default:
dbc2bc25
JD		 2540 company = dme1737_read(data, DME1737_REG_COMPANY);
2541 device = dme1737_read(data, DME1737_REG_DEVICE);
e95c237d 2542
ea694431
JH		 2543 if ((company == DME1737_COMPANY_SMSC) &&
2544 (device == SCH311X_DEVICE)) {
2545 data->type = sch311x;
2546 } else if ((company == DME1737_COMPANY_SMSC) &&
2547 (device == SCH5127_DEVICE)) {
2548 data->type = sch5127;
2549 } else {
55d68d75
JH		 2550 err = -ENODEV;
2551 goto exit_kfree;
2552 }
e95c237d
JH		 2553 }
2554
ea694431
JH		 2555 if (data->type == sch5127) {
2556 data->name = "sch5127";
2557 } else {
2558 data->name = "sch311x";
2559 }
2560
2561 /* Initialize the mutex */
e95c237d
JH		 2562 mutex_init(&data->update_lock);
2563
ea694431
JH		 2564 dev_info(dev, "Found a %s chip at 0x%04x\n",
2565 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr);
e95c237d
JH		 2566
2567 /* Initialize the chip */
2568 if ((err = dme1737_init_device(dev))) {
2569 dev_err(dev, "Failed to initialize device.\n");
2570 goto exit_kfree;
2571 }
2572
2573 /* Create sysfs files */
2574 if ((err = dme1737_create_files(dev))) {
2575 dev_err(dev, "Failed to create sysfs files.\n");
2576 goto exit_kfree;
2577 }
2578
2579 /* Register device */
2580 data->hwmon_dev = hwmon_device_register(dev);
2581 if (IS_ERR(data->hwmon_dev)) {
2582 dev_err(dev, "Failed to register device.\n");
2583 err = PTR_ERR(data->hwmon_dev);
2584 goto exit_remove_files;
2585 }
2586
2587 return 0;
2588
2589exit_remove_files:
2590 dme1737_remove_files(dev);
2591exit_kfree:
2592 platform_set_drvdata(pdev, NULL);
2593 kfree(data);
2594exit_release_region:
2595 release_region(res->start, DME1737_EXTENT);
2596exit:
2597 return err;
2598}
2599
2600static int __devexit dme1737_isa_remove(struct platform_device *pdev)
2601{
2602 struct dme1737_data *data = platform_get_drvdata(pdev);
2603
2604 hwmon_device_unregister(data->hwmon_dev);
2605 dme1737_remove_files(&pdev->dev);
dbc2bc25 2606 release_region(data->addr, DME1737_EXTENT);
e95c237d
JH		 2607 platform_set_drvdata(pdev, NULL);
2608 kfree(data);
2609
2610 return 0;
2611}
2612
2613static struct platform_driver dme1737_isa_driver = {
2614 .driver = {
2615 .owner = THIS_MODULE,
2616 .name = "dme1737",
2617 },
2618 .probe = dme1737_isa_probe,
2619 .remove = __devexit_p(dme1737_isa_remove),
2620};
2621
67e2f328
JH		 2622/* ---------------------------------------------------------------------
2623 * Module initialization and cleanup
2624 * --------------------------------------------------------------------- */
2625
9431996f
JH		 2626static int __init dme1737_init(void)
2627{
e95c237d
JH		 2628 int err;
2629 unsigned short addr;
2630
2631 if ((err = i2c_add_driver(&dme1737_i2c_driver))) {
2632 goto exit;
2633 }
2634
2635 if (dme1737_isa_detect(0x2e, &addr) &&
92430b6f
JH		 2636 dme1737_isa_detect(0x4e, &addr) &&
2637 (!probe_all_addr ||
2638 (dme1737_isa_detect(0x162e, &addr) &&
2639 dme1737_isa_detect(0x164e, &addr)))) {
e95c237d
JH		 2640 /* Return 0 if we didn't find an ISA device */
2641 return 0;
2642 }
2643
2644 if ((err = platform_driver_register(&dme1737_isa_driver))) {
2645 goto exit_del_i2c_driver;
2646 }
2647
2648 /* Sets global pdev as a side effect */
2649 if ((err = dme1737_isa_device_add(addr))) {
2650 goto exit_del_isa_driver;
2651 }
2652
2653 return 0;
2654
2655exit_del_isa_driver:
2656 platform_driver_unregister(&dme1737_isa_driver);
2657exit_del_i2c_driver:
2658 i2c_del_driver(&dme1737_i2c_driver);
2659exit:
2660 return err;
9431996f
JH		 2661}
2662
2663static void __exit dme1737_exit(void)
2664{
e95c237d
JH		 2665 if (pdev) {
2666 platform_device_unregister(pdev);
2667 platform_driver_unregister(&dme1737_isa_driver);
2668 }
2669
b237eb25 2670 i2c_del_driver(&dme1737_i2c_driver);
9431996f
JH		 2671}
2672
2673MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>");
2674MODULE_DESCRIPTION("DME1737 sensors");
2675MODULE_LICENSE("GPL");
2676
2677module_init(dme1737_init);
2678module_exit(dme1737_exit);
Linux 6.x block layer and io_uring tree(s)