Commit | Line | Data |
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935912c5 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
bebe4678 RM |
2 | /* |
3 | * coretemp.c - Linux kernel module for hardware monitoring | |
4 | * | |
5 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
6 | * | |
7 | * Inspired from many hwmon drivers | |
bebe4678 RM |
8 | */ |
9 | ||
f8bb8925 JP |
10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
11 | ||
bebe4678 | 12 | #include <linux/module.h> |
bebe4678 RM |
13 | #include <linux/init.h> |
14 | #include <linux/slab.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/hwmon.h> | |
17 | #include <linux/sysfs.h> | |
18 | #include <linux/hwmon-sysfs.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/mutex.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/cpu.h> | |
4cc45275 | 24 | #include <linux/smp.h> |
a45a8c85 | 25 | #include <linux/moduleparam.h> |
14513ee6 | 26 | #include <linux/pci.h> |
bebe4678 RM |
27 | #include <asm/msr.h> |
28 | #include <asm/processor.h> | |
9b38096f | 29 | #include <asm/cpu_device_id.h> |
bebe4678 RM |
30 | |
31 | #define DRVNAME "coretemp" | |
32 | ||
a45a8c85 JD |
33 | /* |
34 | * force_tjmax only matters when TjMax can't be read from the CPU itself. | |
35 | * When set, it replaces the driver's suboptimal heuristic. | |
36 | */ | |
37 | static int force_tjmax; | |
38 | module_param_named(tjmax, force_tjmax, int, 0444); | |
39 | MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); | |
40 | ||
723f5734 | 41 | #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ |
199e0de7 | 42 | #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ |
cc904f9c | 43 | #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ |
3f9aec76 | 44 | #define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ |
c814a4c7 | 45 | #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ |
f4af6fd6 | 46 | #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) |
199e0de7 D |
47 | #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) |
48 | ||
141168c3 | 49 | #ifdef CONFIG_SMP |
19a34eea BG |
50 | #define for_each_sibling(i, cpu) \ |
51 | for_each_cpu(i, topology_sibling_cpumask(cpu)) | |
199e0de7 | 52 | #else |
bb74e8ca | 53 | #define for_each_sibling(i, cpu) for (i = 0; false; ) |
199e0de7 | 54 | #endif |
bebe4678 RM |
55 | |
56 | /* | |
199e0de7 | 57 | * Per-Core Temperature Data |
c0c67f87 ZR |
58 | * @tjmax: The static tjmax value when tjmax cannot be retrieved from |
59 | * IA32_TEMPERATURE_TARGET MSR. | |
199e0de7 D |
60 | * @last_updated: The time when the current temperature value was updated |
61 | * earlier (in jiffies). | |
62 | * @cpu_core_id: The CPU Core from which temperature values should be read | |
63 | * This value is passed as "id" field to rdmsr/wrmsr functions. | |
64 | * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS, | |
65 | * from where the temperature values should be read. | |
c814a4c7 | 66 | * @attr_size: Total number of pre-core attrs displayed in the sysfs. |
199e0de7 D |
67 | * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data. |
68 | * Otherwise, temp_data holds coretemp data. | |
bebe4678 | 69 | */ |
199e0de7 | 70 | struct temp_data { |
bebe4678 | 71 | int temp; |
199e0de7 D |
72 | int tjmax; |
73 | unsigned long last_updated; | |
74 | unsigned int cpu; | |
75 | u32 cpu_core_id; | |
76 | u32 status_reg; | |
c814a4c7 | 77 | int attr_size; |
199e0de7 | 78 | bool is_pkg_data; |
c814a4c7 D |
79 | struct sensor_device_attribute sd_attrs[TOTAL_ATTRS]; |
80 | char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH]; | |
1075305d GR |
81 | struct attribute *attrs[TOTAL_ATTRS + 1]; |
82 | struct attribute_group attr_group; | |
199e0de7 | 83 | struct mutex update_lock; |
bebe4678 RM |
84 | }; |
85 | ||
199e0de7 D |
86 | /* Platform Data per Physical CPU */ |
87 | struct platform_data { | |
e1b370b6 | 88 | struct device *hwmon_dev; |
71266846 | 89 | u16 pkg_id; |
7108b80a ZR |
90 | u16 cpu_map[NUM_REAL_CORES]; |
91 | struct ida ida; | |
e1b370b6 TG |
92 | struct cpumask cpumask; |
93 | struct temp_data *core_data[MAX_CORE_DATA]; | |
199e0de7 D |
94 | struct device_attribute name_attr; |
95 | }; | |
bebe4678 | 96 | |
14513ee6 GR |
97 | struct tjmax_pci { |
98 | unsigned int device; | |
99 | int tjmax; | |
100 | }; | |
101 | ||
102 | static const struct tjmax_pci tjmax_pci_table[] = { | |
347c16cf | 103 | { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */ |
14513ee6 GR |
104 | { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */ |
105 | { 0x0c73, 95000 }, /* Atom S1220 (Centerton) */ | |
106 | { 0x0c75, 95000 }, /* Atom S1260 (Centerton) */ | |
107 | }; | |
108 | ||
41e58a1f GR |
109 | struct tjmax { |
110 | char const *id; | |
111 | int tjmax; | |
112 | }; | |
113 | ||
d23e2ae1 | 114 | static const struct tjmax tjmax_table[] = { |
1102dcab GR |
115 | { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */ |
116 | { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */ | |
41e58a1f GR |
117 | }; |
118 | ||
2fa5222e GR |
119 | struct tjmax_model { |
120 | u8 model; | |
121 | u8 mask; | |
122 | int tjmax; | |
123 | }; | |
124 | ||
125 | #define ANY 0xff | |
126 | ||
d23e2ae1 | 127 | static const struct tjmax_model tjmax_model_table[] = { |
9e3970fb | 128 | { 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */ |
2fa5222e GR |
129 | { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others |
130 | * Note: Also matches 230 and 330, | |
131 | * which are covered by tjmax_table | |
132 | */ | |
133 | { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx) | |
134 | * Note: TjMax for E6xxT is 110C, but CPU type | |
135 | * is undetectable by software | |
136 | */ | |
137 | { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */ | |
14513ee6 GR |
138 | { 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */ |
139 | { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) | |
140 | * Also matches S12x0 (stepping 9), covered by | |
141 | * PCI table | |
142 | */ | |
2fa5222e GR |
143 | }; |
144 | ||
d23e2ae1 | 145 | static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
118a8871 RM |
146 | { |
147 | /* The 100C is default for both mobile and non mobile CPUs */ | |
148 | ||
149 | int tjmax = 100000; | |
eccfed42 | 150 | int tjmax_ee = 85000; |
708a62bc | 151 | int usemsr_ee = 1; |
118a8871 RM |
152 | int err; |
153 | u32 eax, edx; | |
41e58a1f | 154 | int i; |
b9ccff23 SK |
155 | u16 devfn = PCI_DEVFN(0, 0); |
156 | struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn); | |
14513ee6 GR |
157 | |
158 | /* | |
159 | * Explicit tjmax table entries override heuristics. | |
160 | * First try PCI host bridge IDs, followed by model ID strings | |
161 | * and model/stepping information. | |
162 | */ | |
163 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
164 | for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) { | |
7dec1453 YY |
165 | if (host_bridge->device == tjmax_pci_table[i].device) { |
166 | pci_dev_put(host_bridge); | |
14513ee6 | 167 | return tjmax_pci_table[i].tjmax; |
7dec1453 | 168 | } |
14513ee6 GR |
169 | } |
170 | } | |
7dec1453 | 171 | pci_dev_put(host_bridge); |
41e58a1f | 172 | |
41e58a1f GR |
173 | for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) { |
174 | if (strstr(c->x86_model_id, tjmax_table[i].id)) | |
175 | return tjmax_table[i].tjmax; | |
176 | } | |
118a8871 | 177 | |
2fa5222e GR |
178 | for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { |
179 | const struct tjmax_model *tm = &tjmax_model_table[i]; | |
180 | if (c->x86_model == tm->model && | |
b399151c | 181 | (tm->mask == ANY || c->x86_stepping == tm->mask)) |
2fa5222e | 182 | return tm->tjmax; |
72cbdddc | 183 | } |
1fe63ab4 | 184 | |
72cbdddc | 185 | /* Early chips have no MSR for TjMax */ |
1fe63ab4 | 186 | |
b399151c | 187 | if (c->x86_model == 0xf && c->x86_stepping < 4) |
5592906f | 188 | usemsr_ee = 0; |
708a62bc | 189 | |
4cc45275 | 190 | if (c->x86_model > 0xe && usemsr_ee) { |
eccfed42 | 191 | u8 platform_id; |
118a8871 | 192 | |
4cc45275 GR |
193 | /* |
194 | * Now we can detect the mobile CPU using Intel provided table | |
195 | * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
196 | * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
197 | */ | |
118a8871 RM |
198 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); |
199 | if (err) { | |
200 | dev_warn(dev, | |
201 | "Unable to access MSR 0x17, assuming desktop" | |
202 | " CPU\n"); | |
708a62bc | 203 | usemsr_ee = 0; |
eccfed42 | 204 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
4cc45275 GR |
205 | /* |
206 | * Trust bit 28 up to Penryn, I could not find any | |
207 | * documentation on that; if you happen to know | |
208 | * someone at Intel please ask | |
209 | */ | |
708a62bc | 210 | usemsr_ee = 0; |
eccfed42 RM |
211 | } else { |
212 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
213 | platform_id = (edx >> 18) & 0x7; | |
214 | ||
4cc45275 GR |
215 | /* |
216 | * Mobile Penryn CPU seems to be platform ID 7 or 5 | |
217 | * (guesswork) | |
218 | */ | |
219 | if (c->x86_model == 0x17 && | |
220 | (platform_id == 5 || platform_id == 7)) { | |
221 | /* | |
222 | * If MSR EE bit is set, set it to 90 degrees C, | |
223 | * otherwise 105 degrees C | |
224 | */ | |
eccfed42 RM |
225 | tjmax_ee = 90000; |
226 | tjmax = 105000; | |
227 | } | |
118a8871 RM |
228 | } |
229 | } | |
230 | ||
708a62bc | 231 | if (usemsr_ee) { |
118a8871 RM |
232 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); |
233 | if (err) { | |
234 | dev_warn(dev, | |
235 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 236 | " at default\n"); |
118a8871 | 237 | } else if (eax & 0x40000000) { |
eccfed42 | 238 | tjmax = tjmax_ee; |
118a8871 | 239 | } |
708a62bc | 240 | } else if (tjmax == 100000) { |
4cc45275 GR |
241 | /* |
242 | * If we don't use msr EE it means we are desktop CPU | |
243 | * (with exeception of Atom) | |
244 | */ | |
118a8871 RM |
245 | dev_warn(dev, "Using relative temperature scale!\n"); |
246 | } | |
247 | ||
248 | return tjmax; | |
249 | } | |
250 | ||
1c2faa22 GR |
251 | static bool cpu_has_tjmax(struct cpuinfo_x86 *c) |
252 | { | |
253 | u8 model = c->x86_model; | |
254 | ||
255 | return model > 0xe && | |
256 | model != 0x1c && | |
257 | model != 0x26 && | |
258 | model != 0x27 && | |
259 | model != 0x35 && | |
260 | model != 0x36; | |
261 | } | |
262 | ||
c0c67f87 | 263 | static int get_tjmax(struct temp_data *tdata, struct device *dev) |
a321cedb | 264 | { |
c0c67f87 | 265 | struct cpuinfo_x86 *c = &cpu_data(tdata->cpu); |
a321cedb CE |
266 | int err; |
267 | u32 eax, edx; | |
268 | u32 val; | |
269 | ||
c0c67f87 ZR |
270 | /* use static tjmax once it is set */ |
271 | if (tdata->tjmax) | |
272 | return tdata->tjmax; | |
273 | ||
4cc45275 GR |
274 | /* |
275 | * A new feature of current Intel(R) processors, the | |
276 | * IA32_TEMPERATURE_TARGET contains the TjMax value | |
277 | */ | |
c0c67f87 | 278 | err = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
a321cedb | 279 | if (err) { |
1c2faa22 | 280 | if (cpu_has_tjmax(c)) |
c0c67f87 | 281 | dev_warn(dev, "Unable to read TjMax from CPU %u\n", tdata->cpu); |
a321cedb | 282 | } else { |
c0940e95 | 283 | val = (eax >> 16) & 0xff; |
a321cedb CE |
284 | /* |
285 | * If the TjMax is not plausible, an assumption | |
286 | * will be used | |
287 | */ | |
c0940e95 | 288 | if (val) { |
6bf9e9b0 | 289 | dev_dbg(dev, "TjMax is %d degrees C\n", val); |
a321cedb CE |
290 | return val * 1000; |
291 | } | |
292 | } | |
293 | ||
a45a8c85 JD |
294 | if (force_tjmax) { |
295 | dev_notice(dev, "TjMax forced to %d degrees C by user\n", | |
296 | force_tjmax); | |
c0c67f87 ZR |
297 | tdata->tjmax = force_tjmax * 1000; |
298 | } else { | |
299 | /* | |
300 | * An assumption is made for early CPUs and unreadable MSR. | |
301 | * NOTE: the calculated value may not be correct. | |
302 | */ | |
303 | tdata->tjmax = adjust_tjmax(c, tdata->cpu, dev); | |
a45a8c85 | 304 | } |
c0c67f87 | 305 | return tdata->tjmax; |
a321cedb CE |
306 | } |
307 | ||
fae30e3c ZR |
308 | static int get_ttarget(struct temp_data *tdata, struct device *dev) |
309 | { | |
310 | u32 eax, edx; | |
311 | int tjmax, ttarget_offset, ret; | |
312 | ||
313 | /* | |
314 | * ttarget is valid only if tjmax can be retrieved from | |
315 | * MSR_IA32_TEMPERATURE_TARGET | |
316 | */ | |
317 | if (tdata->tjmax) | |
318 | return -ENODEV; | |
319 | ||
320 | ret = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); | |
321 | if (ret) | |
322 | return ret; | |
323 | ||
324 | tjmax = (eax >> 16) & 0xff; | |
325 | ||
326 | /* Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. */ | |
327 | ttarget_offset = (eax >> 8) & 0xff; | |
328 | ||
329 | return (tjmax - ttarget_offset) * 1000; | |
330 | } | |
331 | ||
2bc0e6d0 ZR |
332 | /* Keep track of how many zone pointers we allocated in init() */ |
333 | static int max_zones __read_mostly; | |
334 | /* Array of zone pointers. Serialized by cpu hotplug lock */ | |
335 | static struct platform_device **zone_devices; | |
336 | ||
337 | static ssize_t show_label(struct device *dev, | |
338 | struct device_attribute *devattr, char *buf) | |
339 | { | |
340 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
341 | struct platform_data *pdata = dev_get_drvdata(dev); | |
342 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
343 | ||
344 | if (tdata->is_pkg_data) | |
345 | return sprintf(buf, "Package id %u\n", pdata->pkg_id); | |
346 | ||
347 | return sprintf(buf, "Core %u\n", tdata->cpu_core_id); | |
348 | } | |
349 | ||
350 | static ssize_t show_crit_alarm(struct device *dev, | |
351 | struct device_attribute *devattr, char *buf) | |
352 | { | |
353 | u32 eax, edx; | |
354 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
355 | struct platform_data *pdata = dev_get_drvdata(dev); | |
356 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
357 | ||
358 | mutex_lock(&tdata->update_lock); | |
359 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
360 | mutex_unlock(&tdata->update_lock); | |
361 | ||
362 | return sprintf(buf, "%d\n", (eax >> 5) & 1); | |
363 | } | |
364 | ||
365 | static ssize_t show_tjmax(struct device *dev, | |
366 | struct device_attribute *devattr, char *buf) | |
367 | { | |
368 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
369 | struct platform_data *pdata = dev_get_drvdata(dev); | |
c0c67f87 ZR |
370 | struct temp_data *tdata = pdata->core_data[attr->index]; |
371 | int tjmax; | |
372 | ||
373 | mutex_lock(&tdata->update_lock); | |
374 | tjmax = get_tjmax(tdata, dev); | |
375 | mutex_unlock(&tdata->update_lock); | |
2bc0e6d0 | 376 | |
c0c67f87 | 377 | return sprintf(buf, "%d\n", tjmax); |
2bc0e6d0 ZR |
378 | } |
379 | ||
380 | static ssize_t show_ttarget(struct device *dev, | |
381 | struct device_attribute *devattr, char *buf) | |
382 | { | |
383 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
384 | struct platform_data *pdata = dev_get_drvdata(dev); | |
fae30e3c ZR |
385 | struct temp_data *tdata = pdata->core_data[attr->index]; |
386 | int ttarget; | |
2bc0e6d0 | 387 | |
fae30e3c ZR |
388 | mutex_lock(&tdata->update_lock); |
389 | ttarget = get_ttarget(tdata, dev); | |
390 | mutex_unlock(&tdata->update_lock); | |
391 | ||
392 | if (ttarget < 0) | |
393 | return ttarget; | |
394 | return sprintf(buf, "%d\n", ttarget); | |
2bc0e6d0 ZR |
395 | } |
396 | ||
397 | static ssize_t show_temp(struct device *dev, | |
398 | struct device_attribute *devattr, char *buf) | |
399 | { | |
400 | u32 eax, edx; | |
401 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
402 | struct platform_data *pdata = dev_get_drvdata(dev); | |
403 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
c0c67f87 | 404 | int tjmax; |
2bc0e6d0 ZR |
405 | |
406 | mutex_lock(&tdata->update_lock); | |
407 | ||
c0c67f87 | 408 | tjmax = get_tjmax(tdata, dev); |
2bc0e6d0 ZR |
409 | /* Check whether the time interval has elapsed */ |
410 | if (time_after(jiffies, tdata->last_updated + HZ)) { | |
411 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
412 | /* | |
413 | * Ignore the valid bit. In all observed cases the register | |
414 | * value is either low or zero if the valid bit is 0. | |
415 | * Return it instead of reporting an error which doesn't | |
416 | * really help at all. | |
417 | */ | |
c0c67f87 | 418 | tdata->temp = tjmax - ((eax >> 16) & 0x7f) * 1000; |
2bc0e6d0 ZR |
419 | tdata->last_updated = jiffies; |
420 | } | |
421 | ||
422 | mutex_unlock(&tdata->update_lock); | |
423 | return sprintf(buf, "%d\n", tdata->temp); | |
424 | } | |
425 | ||
d23e2ae1 PG |
426 | static int create_core_attrs(struct temp_data *tdata, struct device *dev, |
427 | int attr_no) | |
199e0de7 | 428 | { |
1075305d | 429 | int i; |
e3204ed3 | 430 | static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev, |
199e0de7 | 431 | struct device_attribute *devattr, char *buf) = { |
c814a4c7 | 432 | show_label, show_crit_alarm, show_temp, show_tjmax, |
f4af6fd6 | 433 | show_ttarget }; |
1055b5f9 RV |
434 | static const char *const suffixes[TOTAL_ATTRS] = { |
435 | "label", "crit_alarm", "input", "crit", "max" | |
436 | }; | |
199e0de7 | 437 | |
c814a4c7 | 438 | for (i = 0; i < tdata->attr_size; i++) { |
1055b5f9 RV |
439 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, |
440 | "temp%d_%s", attr_no, suffixes[i]); | |
4258781a | 441 | sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr); |
199e0de7 | 442 | tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i]; |
0cd709d0 | 443 | tdata->sd_attrs[i].dev_attr.attr.mode = 0444; |
199e0de7 | 444 | tdata->sd_attrs[i].dev_attr.show = rd_ptr[i]; |
199e0de7 | 445 | tdata->sd_attrs[i].index = attr_no; |
1075305d | 446 | tdata->attrs[i] = &tdata->sd_attrs[i].dev_attr.attr; |
bebe4678 | 447 | } |
1075305d GR |
448 | tdata->attr_group.attrs = tdata->attrs; |
449 | return sysfs_create_group(&dev->kobj, &tdata->attr_group); | |
199e0de7 D |
450 | } |
451 | ||
199e0de7 | 452 | |
d23e2ae1 | 453 | static int chk_ucode_version(unsigned int cpu) |
199e0de7 | 454 | { |
0eb9782a | 455 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
67f363b1 | 456 | |
199e0de7 D |
457 | /* |
458 | * Check if we have problem with errata AE18 of Core processors: | |
459 | * Readings might stop update when processor visited too deep sleep, | |
460 | * fixed for stepping D0 (6EC). | |
461 | */ | |
b399151c | 462 | if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) { |
b55f3757 | 463 | pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); |
ca8bc8dc | 464 | return -ENODEV; |
67f363b1 | 465 | } |
199e0de7 D |
466 | return 0; |
467 | } | |
468 | ||
d23e2ae1 | 469 | static struct platform_device *coretemp_get_pdev(unsigned int cpu) |
199e0de7 | 470 | { |
835896a5 | 471 | int id = topology_logical_die_id(cpu); |
199e0de7 | 472 | |
835896a5 LB |
473 | if (id >= 0 && id < max_zones) |
474 | return zone_devices[id]; | |
199e0de7 D |
475 | return NULL; |
476 | } | |
477 | ||
d23e2ae1 | 478 | static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag) |
199e0de7 D |
479 | { |
480 | struct temp_data *tdata; | |
481 | ||
482 | tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL); | |
483 | if (!tdata) | |
484 | return NULL; | |
485 | ||
486 | tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS : | |
487 | MSR_IA32_THERM_STATUS; | |
488 | tdata->is_pkg_data = pkg_flag; | |
489 | tdata->cpu = cpu; | |
7108b80a | 490 | tdata->cpu_core_id = topology_core_id(cpu); |
c814a4c7 | 491 | tdata->attr_size = MAX_CORE_ATTRS; |
199e0de7 D |
492 | mutex_init(&tdata->update_lock); |
493 | return tdata; | |
494 | } | |
67f363b1 | 495 | |
d23e2ae1 PG |
496 | static int create_core_data(struct platform_device *pdev, unsigned int cpu, |
497 | int pkg_flag) | |
199e0de7 D |
498 | { |
499 | struct temp_data *tdata; | |
2f1c3db0 | 500 | struct platform_data *pdata = platform_get_drvdata(pdev); |
199e0de7 D |
501 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
502 | u32 eax, edx; | |
fae30e3c | 503 | int err, index, attr_no; |
bebe4678 | 504 | |
a321cedb | 505 | /* |
199e0de7 D |
506 | * Find attr number for sysfs: |
507 | * We map the attr number to core id of the CPU | |
508 | * The attr number is always core id + 2 | |
509 | * The Pkgtemp will always show up as temp1_*, if available | |
a321cedb | 510 | */ |
7108b80a ZR |
511 | if (pkg_flag) { |
512 | attr_no = PKG_SYSFS_ATTR_NO; | |
513 | } else { | |
514 | index = ida_alloc(&pdata->ida, GFP_KERNEL); | |
515 | if (index < 0) | |
516 | return index; | |
517 | pdata->cpu_map[index] = topology_core_id(cpu); | |
518 | attr_no = index + BASE_SYSFS_ATTR_NO; | |
519 | } | |
6369a288 | 520 | |
7108b80a ZR |
521 | if (attr_no > MAX_CORE_DATA - 1) { |
522 | err = -ERANGE; | |
523 | goto ida_free; | |
524 | } | |
199e0de7 | 525 | |
199e0de7 | 526 | tdata = init_temp_data(cpu, pkg_flag); |
7108b80a ZR |
527 | if (!tdata) { |
528 | err = -ENOMEM; | |
529 | goto ida_free; | |
530 | } | |
bebe4678 | 531 | |
199e0de7 D |
532 | /* Test if we can access the status register */ |
533 | err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); | |
534 | if (err) | |
535 | goto exit_free; | |
536 | ||
fae30e3c ZR |
537 | /* Make sure tdata->tjmax is a valid indicator for dynamic/static tjmax */ |
538 | get_tjmax(tdata, &pdev->dev); | |
199e0de7 | 539 | |
c814a4c7 | 540 | /* |
fae30e3c ZR |
541 | * The target temperature is available on older CPUs but not in the |
542 | * MSR_IA32_TEMPERATURE_TARGET register. Atoms don't have the register | |
543 | * at all. | |
c814a4c7 | 544 | */ |
fae30e3c ZR |
545 | if (c->x86_model > 0xe && c->x86_model != 0x1c) |
546 | if (get_ttarget(tdata, &pdev->dev) >= 0) | |
f4af6fd6 | 547 | tdata->attr_size++; |
c814a4c7 | 548 | |
199e0de7 D |
549 | pdata->core_data[attr_no] = tdata; |
550 | ||
551 | /* Create sysfs interfaces */ | |
d72d19c2 | 552 | err = create_core_attrs(tdata, pdata->hwmon_dev, attr_no); |
199e0de7 D |
553 | if (err) |
554 | goto exit_free; | |
bebe4678 RM |
555 | |
556 | return 0; | |
199e0de7 | 557 | exit_free: |
20ecb499 | 558 | pdata->core_data[attr_no] = NULL; |
199e0de7 | 559 | kfree(tdata); |
7108b80a ZR |
560 | ida_free: |
561 | if (!pkg_flag) | |
562 | ida_free(&pdata->ida, index); | |
199e0de7 D |
563 | return err; |
564 | } | |
565 | ||
4b138cf7 TG |
566 | static void |
567 | coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag) | |
199e0de7 | 568 | { |
4b138cf7 | 569 | if (create_core_data(pdev, cpu, pkg_flag)) |
199e0de7 D |
570 | dev_err(&pdev->dev, "Adding Core %u failed\n", cpu); |
571 | } | |
572 | ||
4b138cf7 | 573 | static void coretemp_remove_core(struct platform_data *pdata, int indx) |
199e0de7 | 574 | { |
199e0de7 D |
575 | struct temp_data *tdata = pdata->core_data[indx]; |
576 | ||
a89ff5f5 PA |
577 | /* if we errored on add then this is already gone */ |
578 | if (!tdata) | |
579 | return; | |
580 | ||
199e0de7 | 581 | /* Remove the sysfs attributes */ |
d72d19c2 | 582 | sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group); |
199e0de7 D |
583 | |
584 | kfree(pdata->core_data[indx]); | |
585 | pdata->core_data[indx] = NULL; | |
7108b80a ZR |
586 | |
587 | if (indx >= BASE_SYSFS_ATTR_NO) | |
588 | ida_free(&pdata->ida, indx - BASE_SYSFS_ATTR_NO); | |
199e0de7 D |
589 | } |
590 | ||
6c931ae1 | 591 | static int coretemp_probe(struct platform_device *pdev) |
199e0de7 | 592 | { |
c503a811 | 593 | struct device *dev = &pdev->dev; |
199e0de7 | 594 | struct platform_data *pdata; |
bebe4678 | 595 | |
835896a5 | 596 | /* Initialize the per-zone data structures */ |
c503a811 | 597 | pdata = devm_kzalloc(dev, sizeof(struct platform_data), GFP_KERNEL); |
199e0de7 D |
598 | if (!pdata) |
599 | return -ENOMEM; | |
600 | ||
71266846 | 601 | pdata->pkg_id = pdev->id; |
7108b80a | 602 | ida_init(&pdata->ida); |
199e0de7 D |
603 | platform_set_drvdata(pdev, pdata); |
604 | ||
d72d19c2 GR |
605 | pdata->hwmon_dev = devm_hwmon_device_register_with_groups(dev, DRVNAME, |
606 | pdata, NULL); | |
607 | return PTR_ERR_OR_ZERO(pdata->hwmon_dev); | |
bebe4678 RM |
608 | } |
609 | ||
281dfd0b | 610 | static int coretemp_remove(struct platform_device *pdev) |
bebe4678 | 611 | { |
199e0de7 D |
612 | struct platform_data *pdata = platform_get_drvdata(pdev); |
613 | int i; | |
bebe4678 | 614 | |
199e0de7 D |
615 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) |
616 | if (pdata->core_data[i]) | |
d72d19c2 | 617 | coretemp_remove_core(pdata, i); |
199e0de7 | 618 | |
7108b80a | 619 | ida_destroy(&pdata->ida); |
bebe4678 RM |
620 | return 0; |
621 | } | |
622 | ||
623 | static struct platform_driver coretemp_driver = { | |
624 | .driver = { | |
bebe4678 RM |
625 | .name = DRVNAME, |
626 | }, | |
627 | .probe = coretemp_probe, | |
9e5e9b7a | 628 | .remove = coretemp_remove, |
bebe4678 RM |
629 | }; |
630 | ||
71266846 | 631 | static struct platform_device *coretemp_device_add(unsigned int cpu) |
bebe4678 | 632 | { |
835896a5 | 633 | int err, zoneid = topology_logical_die_id(cpu); |
bebe4678 | 634 | struct platform_device *pdev; |
d883b9f0 | 635 | |
835896a5 | 636 | if (zoneid < 0) |
71266846 | 637 | return ERR_PTR(-ENOMEM); |
d883b9f0 | 638 | |
835896a5 | 639 | pdev = platform_device_alloc(DRVNAME, zoneid); |
71266846 TG |
640 | if (!pdev) |
641 | return ERR_PTR(-ENOMEM); | |
bebe4678 RM |
642 | |
643 | err = platform_device_add(pdev); | |
644 | if (err) { | |
71266846 TG |
645 | platform_device_put(pdev); |
646 | return ERR_PTR(err); | |
bebe4678 RM |
647 | } |
648 | ||
835896a5 | 649 | zone_devices[zoneid] = pdev; |
71266846 | 650 | return pdev; |
bebe4678 RM |
651 | } |
652 | ||
e00ca5df | 653 | static int coretemp_cpu_online(unsigned int cpu) |
199e0de7 | 654 | { |
199e0de7 | 655 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 TG |
656 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
657 | struct platform_data *pdata; | |
199e0de7 | 658 | |
90b4f30b TG |
659 | /* |
660 | * Don't execute this on resume as the offline callback did | |
661 | * not get executed on suspend. | |
662 | */ | |
663 | if (cpuhp_tasks_frozen) | |
664 | return 0; | |
665 | ||
199e0de7 D |
666 | /* |
667 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
668 | * sensors. We check this bit only, all the early CPUs | |
669 | * without thermal sensors will be filtered out. | |
670 | */ | |
4ad33411 | 671 | if (!cpu_has(c, X86_FEATURE_DTHERM)) |
2195c31b | 672 | return -ENODEV; |
199e0de7 D |
673 | |
674 | if (!pdev) { | |
0eb9782a JD |
675 | /* Check the microcode version of the CPU */ |
676 | if (chk_ucode_version(cpu)) | |
2195c31b | 677 | return -EINVAL; |
0eb9782a | 678 | |
199e0de7 D |
679 | /* |
680 | * Alright, we have DTS support. | |
681 | * We are bringing the _first_ core in this pkg | |
682 | * online. So, initialize per-pkg data structures and | |
683 | * then bring this core online. | |
684 | */ | |
71266846 TG |
685 | pdev = coretemp_device_add(cpu); |
686 | if (IS_ERR(pdev)) | |
687 | return PTR_ERR(pdev); | |
e1b370b6 | 688 | |
199e0de7 D |
689 | /* |
690 | * Check whether pkgtemp support is available. | |
691 | * If so, add interfaces for pkgtemp. | |
692 | */ | |
693 | if (cpu_has(c, X86_FEATURE_PTS)) | |
4b138cf7 | 694 | coretemp_add_core(pdev, cpu, 1); |
199e0de7 | 695 | } |
e1b370b6 TG |
696 | |
697 | pdata = platform_get_drvdata(pdev); | |
199e0de7 | 698 | /* |
e1b370b6 TG |
699 | * Check whether a thread sibling is already online. If not add the |
700 | * interface for this CPU core. | |
199e0de7 | 701 | */ |
e1b370b6 | 702 | if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu))) |
4b138cf7 | 703 | coretemp_add_core(pdev, cpu, 0); |
e1b370b6 TG |
704 | |
705 | cpumask_set_cpu(cpu, &pdata->cpumask); | |
e00ca5df | 706 | return 0; |
199e0de7 D |
707 | } |
708 | ||
e00ca5df | 709 | static int coretemp_cpu_offline(unsigned int cpu) |
199e0de7 | 710 | { |
199e0de7 | 711 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 | 712 | struct platform_data *pd; |
723f5734 | 713 | struct temp_data *tdata; |
7108b80a | 714 | int i, indx = -1, target; |
199e0de7 | 715 | |
90b4f30b TG |
716 | /* |
717 | * Don't execute this on suspend as the device remove locks | |
718 | * up the machine. | |
719 | */ | |
720 | if (cpuhp_tasks_frozen) | |
721 | return 0; | |
722 | ||
199e0de7 D |
723 | /* If the physical CPU device does not exist, just return */ |
724 | if (!pdev) | |
e00ca5df | 725 | return 0; |
199e0de7 | 726 | |
7108b80a ZR |
727 | pd = platform_get_drvdata(pdev); |
728 | ||
729 | for (i = 0; i < NUM_REAL_CORES; i++) { | |
730 | if (pd->cpu_map[i] == topology_core_id(cpu)) { | |
731 | indx = i + BASE_SYSFS_ATTR_NO; | |
732 | break; | |
733 | } | |
734 | } | |
735 | ||
736 | /* Too many cores and this core is not populated, just return */ | |
737 | if (indx < 0) | |
e00ca5df | 738 | return 0; |
b7048711 | 739 | |
e1b370b6 TG |
740 | tdata = pd->core_data[indx]; |
741 | ||
742 | cpumask_clear_cpu(cpu, &pd->cpumask); | |
199e0de7 | 743 | |
f4e0bcf0 | 744 | /* |
e1b370b6 TG |
745 | * If this is the last thread sibling, remove the CPU core |
746 | * interface, If there is still a sibling online, transfer the | |
747 | * target cpu of that core interface to it. | |
f4e0bcf0 | 748 | */ |
e1b370b6 TG |
749 | target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu)); |
750 | if (target >= nr_cpu_ids) { | |
751 | coretemp_remove_core(pd, indx); | |
752 | } else if (tdata && tdata->cpu == cpu) { | |
753 | mutex_lock(&tdata->update_lock); | |
754 | tdata->cpu = target; | |
755 | mutex_unlock(&tdata->update_lock); | |
199e0de7 | 756 | } |
e1b370b6 | 757 | |
199e0de7 | 758 | /* |
71266846 TG |
759 | * If all cores in this pkg are offline, remove the device. This |
760 | * will invoke the platform driver remove function, which cleans up | |
761 | * the rest. | |
199e0de7 | 762 | */ |
e1b370b6 | 763 | if (cpumask_empty(&pd->cpumask)) { |
835896a5 | 764 | zone_devices[topology_logical_die_id(cpu)] = NULL; |
71266846 | 765 | platform_device_unregister(pdev); |
e00ca5df | 766 | return 0; |
723f5734 | 767 | } |
71266846 | 768 | |
723f5734 TG |
769 | /* |
770 | * Check whether this core is the target for the package | |
771 | * interface. We need to assign it to some other cpu. | |
772 | */ | |
e1b370b6 | 773 | tdata = pd->core_data[PKG_SYSFS_ATTR_NO]; |
723f5734 | 774 | if (tdata && tdata->cpu == cpu) { |
e1b370b6 | 775 | target = cpumask_first(&pd->cpumask); |
723f5734 TG |
776 | mutex_lock(&tdata->update_lock); |
777 | tdata->cpu = target; | |
778 | mutex_unlock(&tdata->update_lock); | |
779 | } | |
e00ca5df | 780 | return 0; |
199e0de7 | 781 | } |
e273bd98 | 782 | static const struct x86_cpu_id __initconst coretemp_ids[] = { |
5cfc7ac7 | 783 | X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_DTHERM, NULL), |
9b38096f AK |
784 | {} |
785 | }; | |
786 | MODULE_DEVICE_TABLE(x86cpu, coretemp_ids); | |
787 | ||
e00ca5df TG |
788 | static enum cpuhp_state coretemp_hp_online; |
789 | ||
bebe4678 RM |
790 | static int __init coretemp_init(void) |
791 | { | |
e00ca5df | 792 | int err; |
bebe4678 | 793 | |
9b38096f AK |
794 | /* |
795 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
796 | * sensors. We check this bit only, all the early CPUs | |
797 | * without thermal sensors will be filtered out. | |
798 | */ | |
799 | if (!x86_match_cpu(coretemp_ids)) | |
800 | return -ENODEV; | |
bebe4678 | 801 | |
835896a5 LB |
802 | max_zones = topology_max_packages() * topology_max_die_per_package(); |
803 | zone_devices = kcalloc(max_zones, sizeof(struct platform_device *), | |
71266846 | 804 | GFP_KERNEL); |
835896a5 | 805 | if (!zone_devices) |
71266846 TG |
806 | return -ENOMEM; |
807 | ||
bebe4678 RM |
808 | err = platform_driver_register(&coretemp_driver); |
809 | if (err) | |
e027a2de | 810 | goto outzone; |
bebe4678 | 811 | |
e00ca5df TG |
812 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online", |
813 | coretemp_cpu_online, coretemp_cpu_offline); | |
814 | if (err < 0) | |
2195c31b | 815 | goto outdrv; |
e00ca5df | 816 | coretemp_hp_online = err; |
bebe4678 RM |
817 | return 0; |
818 | ||
2195c31b | 819 | outdrv: |
bebe4678 | 820 | platform_driver_unregister(&coretemp_driver); |
e027a2de | 821 | outzone: |
835896a5 | 822 | kfree(zone_devices); |
bebe4678 RM |
823 | return err; |
824 | } | |
e00ca5df | 825 | module_init(coretemp_init) |
bebe4678 RM |
826 | |
827 | static void __exit coretemp_exit(void) | |
828 | { | |
e00ca5df | 829 | cpuhp_remove_state(coretemp_hp_online); |
bebe4678 | 830 | platform_driver_unregister(&coretemp_driver); |
835896a5 | 831 | kfree(zone_devices); |
bebe4678 | 832 | } |
e00ca5df | 833 | module_exit(coretemp_exit) |
bebe4678 RM |
834 | |
835 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
836 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
837 | MODULE_LICENSE("GPL"); |