Commit | Line | Data |
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935912c5 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
bebe4678 RM |
2 | /* |
3 | * coretemp.c - Linux kernel module for hardware monitoring | |
4 | * | |
5 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
6 | * | |
7 | * Inspired from many hwmon drivers | |
bebe4678 RM |
8 | */ |
9 | ||
f8bb8925 JP |
10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
11 | ||
bebe4678 | 12 | #include <linux/module.h> |
bebe4678 RM |
13 | #include <linux/init.h> |
14 | #include <linux/slab.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/hwmon.h> | |
17 | #include <linux/sysfs.h> | |
18 | #include <linux/hwmon-sysfs.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/mutex.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/cpu.h> | |
4cc45275 | 24 | #include <linux/smp.h> |
a45a8c85 | 25 | #include <linux/moduleparam.h> |
14513ee6 | 26 | #include <linux/pci.h> |
bebe4678 RM |
27 | #include <asm/msr.h> |
28 | #include <asm/processor.h> | |
9b38096f | 29 | #include <asm/cpu_device_id.h> |
0f8b916b | 30 | #include <linux/sched/isolation.h> |
bebe4678 RM |
31 | |
32 | #define DRVNAME "coretemp" | |
33 | ||
a45a8c85 JD |
34 | /* |
35 | * force_tjmax only matters when TjMax can't be read from the CPU itself. | |
36 | * When set, it replaces the driver's suboptimal heuristic. | |
37 | */ | |
38 | static int force_tjmax; | |
39 | module_param_named(tjmax, force_tjmax, int, 0444); | |
40 | MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); | |
41 | ||
34cf8c65 | 42 | #define NUM_REAL_CORES 512 /* Number of Real cores per cpu */ |
bbfff736 | 43 | #define CORETEMP_NAME_LENGTH 28 /* String Length of attrs */ |
199e0de7 | 44 | |
c8c20740 ZR |
45 | enum coretemp_attr_index { |
46 | ATTR_LABEL, | |
47 | ATTR_CRIT_ALARM, | |
48 | ATTR_TEMP, | |
49 | ATTR_TJMAX, | |
50 | ATTR_TTARGET, | |
51 | MAX_CORE_ATTRS = ATTR_TJMAX + 1, /* Maximum no of basic attrs */ | |
52 | TOTAL_ATTRS = ATTR_TTARGET + 1 /* Maximum no of possible attrs */ | |
53 | }; | |
199e0de7 | 54 | |
141168c3 | 55 | #ifdef CONFIG_SMP |
19a34eea BG |
56 | #define for_each_sibling(i, cpu) \ |
57 | for_each_cpu(i, topology_sibling_cpumask(cpu)) | |
199e0de7 | 58 | #else |
bb74e8ca | 59 | #define for_each_sibling(i, cpu) for (i = 0; false; ) |
199e0de7 | 60 | #endif |
bebe4678 RM |
61 | |
62 | /* | |
199e0de7 | 63 | * Per-Core Temperature Data |
c0c67f87 ZR |
64 | * @tjmax: The static tjmax value when tjmax cannot be retrieved from |
65 | * IA32_TEMPERATURE_TARGET MSR. | |
199e0de7 D |
66 | * @last_updated: The time when the current temperature value was updated |
67 | * earlier (in jiffies). | |
68 | * @cpu_core_id: The CPU Core from which temperature values should be read | |
69 | * This value is passed as "id" field to rdmsr/wrmsr functions. | |
70 | * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS, | |
71 | * from where the temperature values should be read. | |
c814a4c7 | 72 | * @attr_size: Total number of pre-core attrs displayed in the sysfs. |
bebe4678 | 73 | */ |
199e0de7 | 74 | struct temp_data { |
bebe4678 | 75 | int temp; |
199e0de7 D |
76 | int tjmax; |
77 | unsigned long last_updated; | |
78 | unsigned int cpu; | |
18b24a5f | 79 | int index; |
199e0de7 D |
80 | u32 cpu_core_id; |
81 | u32 status_reg; | |
c814a4c7 | 82 | int attr_size; |
18d8f558 | 83 | struct device_attribute sd_attrs[TOTAL_ATTRS]; |
c814a4c7 | 84 | char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH]; |
1075305d GR |
85 | struct attribute *attrs[TOTAL_ATTRS + 1]; |
86 | struct attribute_group attr_group; | |
199e0de7 | 87 | struct mutex update_lock; |
bebe4678 RM |
88 | }; |
89 | ||
199e0de7 D |
90 | /* Platform Data per Physical CPU */ |
91 | struct platform_data { | |
e1b370b6 | 92 | struct device *hwmon_dev; |
71266846 | 93 | u16 pkg_id; |
1a793caf | 94 | int nr_cores; |
7108b80a | 95 | struct ida ida; |
e1b370b6 | 96 | struct cpumask cpumask; |
326241f7 | 97 | struct temp_data *pkg_data; |
1a793caf | 98 | struct temp_data **core_data; |
199e0de7 D |
99 | struct device_attribute name_attr; |
100 | }; | |
bebe4678 | 101 | |
14513ee6 GR |
102 | struct tjmax_pci { |
103 | unsigned int device; | |
104 | int tjmax; | |
105 | }; | |
106 | ||
107 | static const struct tjmax_pci tjmax_pci_table[] = { | |
347c16cf | 108 | { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */ |
14513ee6 GR |
109 | { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */ |
110 | { 0x0c73, 95000 }, /* Atom S1220 (Centerton) */ | |
111 | { 0x0c75, 95000 }, /* Atom S1260 (Centerton) */ | |
112 | }; | |
113 | ||
41e58a1f GR |
114 | struct tjmax { |
115 | char const *id; | |
116 | int tjmax; | |
117 | }; | |
118 | ||
d23e2ae1 | 119 | static const struct tjmax tjmax_table[] = { |
1102dcab GR |
120 | { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */ |
121 | { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */ | |
41e58a1f GR |
122 | }; |
123 | ||
2fa5222e GR |
124 | struct tjmax_model { |
125 | u8 model; | |
126 | u8 mask; | |
127 | int tjmax; | |
128 | }; | |
129 | ||
130 | #define ANY 0xff | |
131 | ||
d23e2ae1 | 132 | static const struct tjmax_model tjmax_model_table[] = { |
9e3970fb | 133 | { 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */ |
2fa5222e GR |
134 | { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others |
135 | * Note: Also matches 230 and 330, | |
136 | * which are covered by tjmax_table | |
137 | */ | |
138 | { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx) | |
139 | * Note: TjMax for E6xxT is 110C, but CPU type | |
140 | * is undetectable by software | |
141 | */ | |
142 | { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */ | |
14513ee6 GR |
143 | { 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */ |
144 | { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) | |
145 | * Also matches S12x0 (stepping 9), covered by | |
146 | * PCI table | |
147 | */ | |
2fa5222e GR |
148 | }; |
149 | ||
18b24a5f ZR |
150 | static bool is_pkg_temp_data(struct temp_data *tdata) |
151 | { | |
152 | return tdata->index < 0; | |
153 | } | |
154 | ||
d23e2ae1 | 155 | static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
118a8871 RM |
156 | { |
157 | /* The 100C is default for both mobile and non mobile CPUs */ | |
158 | ||
159 | int tjmax = 100000; | |
eccfed42 | 160 | int tjmax_ee = 85000; |
708a62bc | 161 | int usemsr_ee = 1; |
118a8871 RM |
162 | int err; |
163 | u32 eax, edx; | |
41e58a1f | 164 | int i; |
b9ccff23 SK |
165 | u16 devfn = PCI_DEVFN(0, 0); |
166 | struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn); | |
14513ee6 GR |
167 | |
168 | /* | |
169 | * Explicit tjmax table entries override heuristics. | |
170 | * First try PCI host bridge IDs, followed by model ID strings | |
171 | * and model/stepping information. | |
172 | */ | |
173 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
174 | for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) { | |
7dec1453 YY |
175 | if (host_bridge->device == tjmax_pci_table[i].device) { |
176 | pci_dev_put(host_bridge); | |
14513ee6 | 177 | return tjmax_pci_table[i].tjmax; |
7dec1453 | 178 | } |
14513ee6 GR |
179 | } |
180 | } | |
7dec1453 | 181 | pci_dev_put(host_bridge); |
41e58a1f | 182 | |
41e58a1f GR |
183 | for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) { |
184 | if (strstr(c->x86_model_id, tjmax_table[i].id)) | |
185 | return tjmax_table[i].tjmax; | |
186 | } | |
118a8871 | 187 | |
2fa5222e GR |
188 | for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { |
189 | const struct tjmax_model *tm = &tjmax_model_table[i]; | |
190 | if (c->x86_model == tm->model && | |
b399151c | 191 | (tm->mask == ANY || c->x86_stepping == tm->mask)) |
2fa5222e | 192 | return tm->tjmax; |
72cbdddc | 193 | } |
1fe63ab4 | 194 | |
72cbdddc | 195 | /* Early chips have no MSR for TjMax */ |
1fe63ab4 | 196 | |
b399151c | 197 | if (c->x86_model == 0xf && c->x86_stepping < 4) |
5592906f | 198 | usemsr_ee = 0; |
708a62bc | 199 | |
4cc45275 | 200 | if (c->x86_model > 0xe && usemsr_ee) { |
eccfed42 | 201 | u8 platform_id; |
118a8871 | 202 | |
4cc45275 GR |
203 | /* |
204 | * Now we can detect the mobile CPU using Intel provided table | |
205 | * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
206 | * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
207 | */ | |
118a8871 RM |
208 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); |
209 | if (err) { | |
210 | dev_warn(dev, | |
211 | "Unable to access MSR 0x17, assuming desktop" | |
212 | " CPU\n"); | |
708a62bc | 213 | usemsr_ee = 0; |
eccfed42 | 214 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
4cc45275 GR |
215 | /* |
216 | * Trust bit 28 up to Penryn, I could not find any | |
217 | * documentation on that; if you happen to know | |
218 | * someone at Intel please ask | |
219 | */ | |
708a62bc | 220 | usemsr_ee = 0; |
eccfed42 RM |
221 | } else { |
222 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
223 | platform_id = (edx >> 18) & 0x7; | |
224 | ||
4cc45275 GR |
225 | /* |
226 | * Mobile Penryn CPU seems to be platform ID 7 or 5 | |
227 | * (guesswork) | |
228 | */ | |
229 | if (c->x86_model == 0x17 && | |
230 | (platform_id == 5 || platform_id == 7)) { | |
231 | /* | |
232 | * If MSR EE bit is set, set it to 90 degrees C, | |
233 | * otherwise 105 degrees C | |
234 | */ | |
eccfed42 RM |
235 | tjmax_ee = 90000; |
236 | tjmax = 105000; | |
237 | } | |
118a8871 RM |
238 | } |
239 | } | |
240 | ||
708a62bc | 241 | if (usemsr_ee) { |
118a8871 RM |
242 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); |
243 | if (err) { | |
244 | dev_warn(dev, | |
245 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 246 | " at default\n"); |
118a8871 | 247 | } else if (eax & 0x40000000) { |
eccfed42 | 248 | tjmax = tjmax_ee; |
118a8871 | 249 | } |
708a62bc | 250 | } else if (tjmax == 100000) { |
4cc45275 GR |
251 | /* |
252 | * If we don't use msr EE it means we are desktop CPU | |
253 | * (with exeception of Atom) | |
254 | */ | |
118a8871 RM |
255 | dev_warn(dev, "Using relative temperature scale!\n"); |
256 | } | |
257 | ||
258 | return tjmax; | |
259 | } | |
260 | ||
1c2faa22 GR |
261 | static bool cpu_has_tjmax(struct cpuinfo_x86 *c) |
262 | { | |
263 | u8 model = c->x86_model; | |
264 | ||
265 | return model > 0xe && | |
266 | model != 0x1c && | |
267 | model != 0x26 && | |
268 | model != 0x27 && | |
269 | model != 0x35 && | |
270 | model != 0x36; | |
271 | } | |
272 | ||
c0c67f87 | 273 | static int get_tjmax(struct temp_data *tdata, struct device *dev) |
a321cedb | 274 | { |
c0c67f87 | 275 | struct cpuinfo_x86 *c = &cpu_data(tdata->cpu); |
a321cedb CE |
276 | int err; |
277 | u32 eax, edx; | |
278 | u32 val; | |
279 | ||
c0c67f87 ZR |
280 | /* use static tjmax once it is set */ |
281 | if (tdata->tjmax) | |
282 | return tdata->tjmax; | |
283 | ||
4cc45275 GR |
284 | /* |
285 | * A new feature of current Intel(R) processors, the | |
286 | * IA32_TEMPERATURE_TARGET contains the TjMax value | |
287 | */ | |
c0c67f87 | 288 | err = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
a321cedb | 289 | if (err) { |
1c2faa22 | 290 | if (cpu_has_tjmax(c)) |
c0c67f87 | 291 | dev_warn(dev, "Unable to read TjMax from CPU %u\n", tdata->cpu); |
a321cedb | 292 | } else { |
c0940e95 | 293 | val = (eax >> 16) & 0xff; |
6c2b6599 | 294 | if (val) |
a321cedb | 295 | return val * 1000; |
a321cedb CE |
296 | } |
297 | ||
a45a8c85 JD |
298 | if (force_tjmax) { |
299 | dev_notice(dev, "TjMax forced to %d degrees C by user\n", | |
300 | force_tjmax); | |
c0c67f87 ZR |
301 | tdata->tjmax = force_tjmax * 1000; |
302 | } else { | |
303 | /* | |
304 | * An assumption is made for early CPUs and unreadable MSR. | |
305 | * NOTE: the calculated value may not be correct. | |
306 | */ | |
307 | tdata->tjmax = adjust_tjmax(c, tdata->cpu, dev); | |
a45a8c85 | 308 | } |
c0c67f87 | 309 | return tdata->tjmax; |
a321cedb CE |
310 | } |
311 | ||
fae30e3c ZR |
312 | static int get_ttarget(struct temp_data *tdata, struct device *dev) |
313 | { | |
314 | u32 eax, edx; | |
315 | int tjmax, ttarget_offset, ret; | |
316 | ||
317 | /* | |
318 | * ttarget is valid only if tjmax can be retrieved from | |
319 | * MSR_IA32_TEMPERATURE_TARGET | |
320 | */ | |
321 | if (tdata->tjmax) | |
322 | return -ENODEV; | |
323 | ||
324 | ret = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); | |
325 | if (ret) | |
326 | return ret; | |
327 | ||
328 | tjmax = (eax >> 16) & 0xff; | |
329 | ||
330 | /* Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. */ | |
331 | ttarget_offset = (eax >> 8) & 0xff; | |
332 | ||
333 | return (tjmax - ttarget_offset) * 1000; | |
334 | } | |
335 | ||
2bc0e6d0 ZR |
336 | /* Keep track of how many zone pointers we allocated in init() */ |
337 | static int max_zones __read_mostly; | |
338 | /* Array of zone pointers. Serialized by cpu hotplug lock */ | |
339 | static struct platform_device **zone_devices; | |
340 | ||
341 | static ssize_t show_label(struct device *dev, | |
342 | struct device_attribute *devattr, char *buf) | |
343 | { | |
2bc0e6d0 | 344 | struct platform_data *pdata = dev_get_drvdata(dev); |
18d8f558 | 345 | struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_LABEL]); |
2bc0e6d0 | 346 | |
18b24a5f | 347 | if (is_pkg_temp_data(tdata)) |
2bc0e6d0 ZR |
348 | return sprintf(buf, "Package id %u\n", pdata->pkg_id); |
349 | ||
350 | return sprintf(buf, "Core %u\n", tdata->cpu_core_id); | |
351 | } | |
352 | ||
353 | static ssize_t show_crit_alarm(struct device *dev, | |
354 | struct device_attribute *devattr, char *buf) | |
355 | { | |
356 | u32 eax, edx; | |
18d8f558 ZR |
357 | struct temp_data *tdata = container_of(devattr, struct temp_data, |
358 | sd_attrs[ATTR_CRIT_ALARM]); | |
2bc0e6d0 ZR |
359 | |
360 | mutex_lock(&tdata->update_lock); | |
361 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
362 | mutex_unlock(&tdata->update_lock); | |
363 | ||
364 | return sprintf(buf, "%d\n", (eax >> 5) & 1); | |
365 | } | |
366 | ||
367 | static ssize_t show_tjmax(struct device *dev, | |
368 | struct device_attribute *devattr, char *buf) | |
369 | { | |
18d8f558 | 370 | struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TJMAX]); |
c0c67f87 ZR |
371 | int tjmax; |
372 | ||
373 | mutex_lock(&tdata->update_lock); | |
374 | tjmax = get_tjmax(tdata, dev); | |
375 | mutex_unlock(&tdata->update_lock); | |
2bc0e6d0 | 376 | |
c0c67f87 | 377 | return sprintf(buf, "%d\n", tjmax); |
2bc0e6d0 ZR |
378 | } |
379 | ||
380 | static ssize_t show_ttarget(struct device *dev, | |
381 | struct device_attribute *devattr, char *buf) | |
382 | { | |
18d8f558 | 383 | struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TTARGET]); |
fae30e3c | 384 | int ttarget; |
2bc0e6d0 | 385 | |
fae30e3c ZR |
386 | mutex_lock(&tdata->update_lock); |
387 | ttarget = get_ttarget(tdata, dev); | |
388 | mutex_unlock(&tdata->update_lock); | |
389 | ||
390 | if (ttarget < 0) | |
391 | return ttarget; | |
392 | return sprintf(buf, "%d\n", ttarget); | |
2bc0e6d0 ZR |
393 | } |
394 | ||
395 | static ssize_t show_temp(struct device *dev, | |
396 | struct device_attribute *devattr, char *buf) | |
397 | { | |
398 | u32 eax, edx; | |
18d8f558 | 399 | struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TEMP]); |
c0c67f87 | 400 | int tjmax; |
2bc0e6d0 ZR |
401 | |
402 | mutex_lock(&tdata->update_lock); | |
403 | ||
c0c67f87 | 404 | tjmax = get_tjmax(tdata, dev); |
2bc0e6d0 ZR |
405 | /* Check whether the time interval has elapsed */ |
406 | if (time_after(jiffies, tdata->last_updated + HZ)) { | |
407 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
408 | /* | |
409 | * Ignore the valid bit. In all observed cases the register | |
410 | * value is either low or zero if the valid bit is 0. | |
411 | * Return it instead of reporting an error which doesn't | |
412 | * really help at all. | |
413 | */ | |
f0c344c0 | 414 | tdata->temp = tjmax - ((eax >> 16) & 0xff) * 1000; |
2bc0e6d0 ZR |
415 | tdata->last_updated = jiffies; |
416 | } | |
417 | ||
418 | mutex_unlock(&tdata->update_lock); | |
419 | return sprintf(buf, "%d\n", tdata->temp); | |
420 | } | |
421 | ||
25f8e01b | 422 | static int create_core_attrs(struct temp_data *tdata, struct device *dev) |
199e0de7 | 423 | { |
1075305d | 424 | int i; |
e3204ed3 | 425 | static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev, |
199e0de7 | 426 | struct device_attribute *devattr, char *buf) = { |
c814a4c7 | 427 | show_label, show_crit_alarm, show_temp, show_tjmax, |
f4af6fd6 | 428 | show_ttarget }; |
1055b5f9 RV |
429 | static const char *const suffixes[TOTAL_ATTRS] = { |
430 | "label", "crit_alarm", "input", "crit", "max" | |
431 | }; | |
199e0de7 | 432 | |
c814a4c7 | 433 | for (i = 0; i < tdata->attr_size; i++) { |
fdaf0c86 ZR |
434 | /* |
435 | * We map the attr number to core id of the CPU | |
436 | * The attr number is always core id + 2 | |
437 | * The Pkgtemp will always show up as temp1_*, if available | |
438 | */ | |
18b24a5f | 439 | int attr_no = is_pkg_temp_data(tdata) ? 1 : tdata->cpu_core_id + 2; |
fdaf0c86 | 440 | |
1055b5f9 RV |
441 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, |
442 | "temp%d_%s", attr_no, suffixes[i]); | |
18d8f558 ZR |
443 | sysfs_attr_init(&tdata->sd_attrs[i].attr); |
444 | tdata->sd_attrs[i].attr.name = tdata->attr_name[i]; | |
445 | tdata->sd_attrs[i].attr.mode = 0444; | |
446 | tdata->sd_attrs[i].show = rd_ptr[i]; | |
447 | tdata->attrs[i] = &tdata->sd_attrs[i].attr; | |
bebe4678 | 448 | } |
1075305d GR |
449 | tdata->attr_group.attrs = tdata->attrs; |
450 | return sysfs_create_group(&dev->kobj, &tdata->attr_group); | |
199e0de7 D |
451 | } |
452 | ||
199e0de7 | 453 | |
d23e2ae1 | 454 | static int chk_ucode_version(unsigned int cpu) |
199e0de7 | 455 | { |
0eb9782a | 456 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
67f363b1 | 457 | |
199e0de7 D |
458 | /* |
459 | * Check if we have problem with errata AE18 of Core processors: | |
460 | * Readings might stop update when processor visited too deep sleep, | |
461 | * fixed for stepping D0 (6EC). | |
462 | */ | |
b399151c | 463 | if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) { |
b55f3757 | 464 | pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); |
ca8bc8dc | 465 | return -ENODEV; |
67f363b1 | 466 | } |
199e0de7 D |
467 | return 0; |
468 | } | |
469 | ||
d23e2ae1 | 470 | static struct platform_device *coretemp_get_pdev(unsigned int cpu) |
199e0de7 | 471 | { |
835896a5 | 472 | int id = topology_logical_die_id(cpu); |
199e0de7 | 473 | |
835896a5 LB |
474 | if (id >= 0 && id < max_zones) |
475 | return zone_devices[id]; | |
199e0de7 D |
476 | return NULL; |
477 | } | |
478 | ||
b0b01414 ZR |
479 | static struct temp_data * |
480 | init_temp_data(struct platform_data *pdata, unsigned int cpu, int pkg_flag) | |
199e0de7 D |
481 | { |
482 | struct temp_data *tdata; | |
483 | ||
1a793caf ZR |
484 | if (!pdata->core_data) { |
485 | /* | |
486 | * TODO: | |
487 | * The information of actual possible cores in a package is broken for now. | |
488 | * Will replace hardcoded NUM_REAL_CORES with actual per package core count | |
489 | * when this information becomes available. | |
490 | */ | |
491 | pdata->nr_cores = NUM_REAL_CORES; | |
492 | pdata->core_data = kcalloc(pdata->nr_cores, sizeof(struct temp_data *), | |
493 | GFP_KERNEL); | |
494 | if (!pdata->core_data) | |
495 | return NULL; | |
496 | } | |
497 | ||
199e0de7 D |
498 | tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL); |
499 | if (!tdata) | |
500 | return NULL; | |
501 | ||
b0b01414 | 502 | if (pkg_flag) { |
326241f7 | 503 | pdata->pkg_data = tdata; |
18b24a5f ZR |
504 | /* Use tdata->index as indicator of package temp data */ |
505 | tdata->index = -1; | |
b0b01414 | 506 | } else { |
1a793caf | 507 | tdata->index = ida_alloc_max(&pdata->ida, pdata->nr_cores - 1, GFP_KERNEL); |
326241f7 | 508 | if (tdata->index < 0) { |
b0b01414 ZR |
509 | kfree(tdata); |
510 | return NULL; | |
511 | } | |
326241f7 | 512 | pdata->core_data[tdata->index] = tdata; |
b0b01414 | 513 | } |
b0b01414 | 514 | |
199e0de7 D |
515 | tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS : |
516 | MSR_IA32_THERM_STATUS; | |
199e0de7 | 517 | tdata->cpu = cpu; |
7108b80a | 518 | tdata->cpu_core_id = topology_core_id(cpu); |
c814a4c7 | 519 | tdata->attr_size = MAX_CORE_ATTRS; |
199e0de7 D |
520 | mutex_init(&tdata->update_lock); |
521 | return tdata; | |
522 | } | |
67f363b1 | 523 | |
b0b01414 ZR |
524 | static void destroy_temp_data(struct platform_data *pdata, struct temp_data *tdata) |
525 | { | |
18b24a5f | 526 | if (is_pkg_temp_data(tdata)) { |
326241f7 | 527 | pdata->pkg_data = NULL; |
1a793caf ZR |
528 | kfree(pdata->core_data); |
529 | pdata->core_data = NULL; | |
530 | pdata->nr_cores = 0; | |
326241f7 ZR |
531 | } else { |
532 | pdata->core_data[tdata->index] = NULL; | |
533 | ida_free(&pdata->ida, tdata->index); | |
534 | } | |
b0b01414 ZR |
535 | kfree(tdata); |
536 | } | |
537 | ||
538 | static struct temp_data *get_temp_data(struct platform_data *pdata, int cpu) | |
539 | { | |
540 | int i; | |
541 | ||
542 | /* cpu < 0 means get pkg temp_data */ | |
543 | if (cpu < 0) | |
326241f7 | 544 | return pdata->pkg_data; |
b0b01414 | 545 | |
1a793caf | 546 | for (i = 0; i < pdata->nr_cores; i++) { |
b0b01414 ZR |
547 | if (pdata->core_data[i] && |
548 | pdata->core_data[i]->cpu_core_id == topology_core_id(cpu)) | |
549 | return pdata->core_data[i]; | |
550 | } | |
551 | return NULL; | |
552 | } | |
553 | ||
d23e2ae1 PG |
554 | static int create_core_data(struct platform_device *pdev, unsigned int cpu, |
555 | int pkg_flag) | |
199e0de7 D |
556 | { |
557 | struct temp_data *tdata; | |
2f1c3db0 | 558 | struct platform_data *pdata = platform_get_drvdata(pdev); |
199e0de7 D |
559 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
560 | u32 eax, edx; | |
b0b01414 | 561 | int err; |
bebe4678 | 562 | |
0f8b916b MT |
563 | if (!housekeeping_cpu(cpu, HK_TYPE_MISC)) |
564 | return 0; | |
565 | ||
b0b01414 ZR |
566 | tdata = init_temp_data(pdata, cpu, pkg_flag); |
567 | if (!tdata) | |
568 | return -ENOMEM; | |
bebe4678 | 569 | |
199e0de7 D |
570 | /* Test if we can access the status register */ |
571 | err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); | |
572 | if (err) | |
b0b01414 | 573 | goto err; |
199e0de7 | 574 | |
fae30e3c ZR |
575 | /* Make sure tdata->tjmax is a valid indicator for dynamic/static tjmax */ |
576 | get_tjmax(tdata, &pdev->dev); | |
199e0de7 | 577 | |
c814a4c7 | 578 | /* |
fae30e3c ZR |
579 | * The target temperature is available on older CPUs but not in the |
580 | * MSR_IA32_TEMPERATURE_TARGET register. Atoms don't have the register | |
581 | * at all. | |
c814a4c7 | 582 | */ |
fae30e3c ZR |
583 | if (c->x86_model > 0xe && c->x86_model != 0x1c) |
584 | if (get_ttarget(tdata, &pdev->dev) >= 0) | |
f4af6fd6 | 585 | tdata->attr_size++; |
c814a4c7 | 586 | |
199e0de7 | 587 | /* Create sysfs interfaces */ |
25f8e01b | 588 | err = create_core_attrs(tdata, pdata->hwmon_dev); |
199e0de7 | 589 | if (err) |
b0b01414 | 590 | goto err; |
bebe4678 RM |
591 | |
592 | return 0; | |
b0b01414 ZR |
593 | |
594 | err: | |
595 | destroy_temp_data(pdata, tdata); | |
199e0de7 D |
596 | return err; |
597 | } | |
598 | ||
4b138cf7 TG |
599 | static void |
600 | coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag) | |
199e0de7 | 601 | { |
4b138cf7 | 602 | if (create_core_data(pdev, cpu, pkg_flag)) |
199e0de7 D |
603 | dev_err(&pdev->dev, "Adding Core %u failed\n", cpu); |
604 | } | |
605 | ||
b0b01414 | 606 | static void coretemp_remove_core(struct platform_data *pdata, struct temp_data *tdata) |
199e0de7 | 607 | { |
a89ff5f5 PA |
608 | /* if we errored on add then this is already gone */ |
609 | if (!tdata) | |
610 | return; | |
611 | ||
199e0de7 | 612 | /* Remove the sysfs attributes */ |
d72d19c2 | 613 | sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group); |
199e0de7 | 614 | |
b0b01414 | 615 | destroy_temp_data(pdata, tdata); |
199e0de7 D |
616 | } |
617 | ||
6d03bbff | 618 | static int coretemp_device_add(int zoneid) |
199e0de7 | 619 | { |
6d03bbff | 620 | struct platform_device *pdev; |
199e0de7 | 621 | struct platform_data *pdata; |
6d03bbff | 622 | int err; |
bebe4678 | 623 | |
835896a5 | 624 | /* Initialize the per-zone data structures */ |
6d03bbff | 625 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
199e0de7 D |
626 | if (!pdata) |
627 | return -ENOMEM; | |
628 | ||
6d03bbff | 629 | pdata->pkg_id = zoneid; |
7108b80a | 630 | ida_init(&pdata->ida); |
199e0de7 | 631 | |
6d03bbff RM |
632 | pdev = platform_device_alloc(DRVNAME, zoneid); |
633 | if (!pdev) { | |
634 | err = -ENOMEM; | |
635 | goto err_free_pdata; | |
636 | } | |
bebe4678 | 637 | |
6d03bbff RM |
638 | err = platform_device_add(pdev); |
639 | if (err) | |
640 | goto err_put_dev; | |
199e0de7 | 641 | |
6d03bbff RM |
642 | platform_set_drvdata(pdev, pdata); |
643 | zone_devices[zoneid] = pdev; | |
bebe4678 | 644 | return 0; |
bebe4678 | 645 | |
6d03bbff RM |
646 | err_put_dev: |
647 | platform_device_put(pdev); | |
648 | err_free_pdata: | |
649 | kfree(pdata); | |
650 | return err; | |
651 | } | |
bebe4678 | 652 | |
6d03bbff | 653 | static void coretemp_device_remove(int zoneid) |
bebe4678 | 654 | { |
6d03bbff RM |
655 | struct platform_device *pdev = zone_devices[zoneid]; |
656 | struct platform_data *pdata = platform_get_drvdata(pdev); | |
bebe4678 | 657 | |
6d03bbff RM |
658 | ida_destroy(&pdata->ida); |
659 | kfree(pdata); | |
660 | platform_device_unregister(pdev); | |
bebe4678 RM |
661 | } |
662 | ||
e00ca5df | 663 | static int coretemp_cpu_online(unsigned int cpu) |
199e0de7 | 664 | { |
199e0de7 | 665 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 TG |
666 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
667 | struct platform_data *pdata; | |
199e0de7 | 668 | |
90b4f30b TG |
669 | /* |
670 | * Don't execute this on resume as the offline callback did | |
671 | * not get executed on suspend. | |
672 | */ | |
673 | if (cpuhp_tasks_frozen) | |
674 | return 0; | |
675 | ||
199e0de7 D |
676 | /* |
677 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
678 | * sensors. We check this bit only, all the early CPUs | |
679 | * without thermal sensors will be filtered out. | |
680 | */ | |
4ad33411 | 681 | if (!cpu_has(c, X86_FEATURE_DTHERM)) |
2195c31b | 682 | return -ENODEV; |
199e0de7 | 683 | |
6d03bbff RM |
684 | pdata = platform_get_drvdata(pdev); |
685 | if (!pdata->hwmon_dev) { | |
686 | struct device *hwmon; | |
687 | ||
0eb9782a JD |
688 | /* Check the microcode version of the CPU */ |
689 | if (chk_ucode_version(cpu)) | |
2195c31b | 690 | return -EINVAL; |
0eb9782a | 691 | |
199e0de7 D |
692 | /* |
693 | * Alright, we have DTS support. | |
694 | * We are bringing the _first_ core in this pkg | |
695 | * online. So, initialize per-pkg data structures and | |
696 | * then bring this core online. | |
697 | */ | |
6d03bbff RM |
698 | hwmon = hwmon_device_register_with_groups(&pdev->dev, DRVNAME, |
699 | pdata, NULL); | |
700 | if (IS_ERR(hwmon)) | |
701 | return PTR_ERR(hwmon); | |
702 | pdata->hwmon_dev = hwmon; | |
e1b370b6 | 703 | |
199e0de7 D |
704 | /* |
705 | * Check whether pkgtemp support is available. | |
706 | * If so, add interfaces for pkgtemp. | |
707 | */ | |
708 | if (cpu_has(c, X86_FEATURE_PTS)) | |
4b138cf7 | 709 | coretemp_add_core(pdev, cpu, 1); |
199e0de7 | 710 | } |
e1b370b6 | 711 | |
199e0de7 | 712 | /* |
e1b370b6 TG |
713 | * Check whether a thread sibling is already online. If not add the |
714 | * interface for this CPU core. | |
199e0de7 | 715 | */ |
e1b370b6 | 716 | if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu))) |
4b138cf7 | 717 | coretemp_add_core(pdev, cpu, 0); |
e1b370b6 TG |
718 | |
719 | cpumask_set_cpu(cpu, &pdata->cpumask); | |
e00ca5df | 720 | return 0; |
199e0de7 D |
721 | } |
722 | ||
e00ca5df | 723 | static int coretemp_cpu_offline(unsigned int cpu) |
199e0de7 | 724 | { |
199e0de7 | 725 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 | 726 | struct platform_data *pd; |
723f5734 | 727 | struct temp_data *tdata; |
b0b01414 | 728 | int target; |
199e0de7 | 729 | |
6d03bbff | 730 | /* No need to tear down any interfaces for suspend */ |
90b4f30b TG |
731 | if (cpuhp_tasks_frozen) |
732 | return 0; | |
733 | ||
199e0de7 | 734 | /* If the physical CPU device does not exist, just return */ |
7108b80a | 735 | pd = platform_get_drvdata(pdev); |
6d03bbff RM |
736 | if (!pd->hwmon_dev) |
737 | return 0; | |
7108b80a | 738 | |
b0b01414 | 739 | tdata = get_temp_data(pd, cpu); |
e1b370b6 TG |
740 | |
741 | cpumask_clear_cpu(cpu, &pd->cpumask); | |
199e0de7 | 742 | |
f4e0bcf0 | 743 | /* |
e1b370b6 TG |
744 | * If this is the last thread sibling, remove the CPU core |
745 | * interface, If there is still a sibling online, transfer the | |
746 | * target cpu of that core interface to it. | |
f4e0bcf0 | 747 | */ |
e1b370b6 TG |
748 | target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu)); |
749 | if (target >= nr_cpu_ids) { | |
b0b01414 | 750 | coretemp_remove_core(pd, tdata); |
e1b370b6 TG |
751 | } else if (tdata && tdata->cpu == cpu) { |
752 | mutex_lock(&tdata->update_lock); | |
753 | tdata->cpu = target; | |
754 | mutex_unlock(&tdata->update_lock); | |
199e0de7 | 755 | } |
e1b370b6 | 756 | |
199e0de7 | 757 | /* |
6d03bbff | 758 | * If all cores in this pkg are offline, remove the interface. |
199e0de7 | 759 | */ |
b0b01414 | 760 | tdata = get_temp_data(pd, -1); |
e1b370b6 | 761 | if (cpumask_empty(&pd->cpumask)) { |
6d03bbff | 762 | if (tdata) |
b0b01414 | 763 | coretemp_remove_core(pd, tdata); |
6d03bbff RM |
764 | hwmon_device_unregister(pd->hwmon_dev); |
765 | pd->hwmon_dev = NULL; | |
e00ca5df | 766 | return 0; |
723f5734 | 767 | } |
71266846 | 768 | |
723f5734 TG |
769 | /* |
770 | * Check whether this core is the target for the package | |
771 | * interface. We need to assign it to some other cpu. | |
772 | */ | |
723f5734 | 773 | if (tdata && tdata->cpu == cpu) { |
e1b370b6 | 774 | target = cpumask_first(&pd->cpumask); |
723f5734 TG |
775 | mutex_lock(&tdata->update_lock); |
776 | tdata->cpu = target; | |
777 | mutex_unlock(&tdata->update_lock); | |
778 | } | |
e00ca5df | 779 | return 0; |
199e0de7 | 780 | } |
e273bd98 | 781 | static const struct x86_cpu_id __initconst coretemp_ids[] = { |
5cfc7ac7 | 782 | X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_DTHERM, NULL), |
9b38096f AK |
783 | {} |
784 | }; | |
785 | MODULE_DEVICE_TABLE(x86cpu, coretemp_ids); | |
786 | ||
e00ca5df TG |
787 | static enum cpuhp_state coretemp_hp_online; |
788 | ||
bebe4678 RM |
789 | static int __init coretemp_init(void) |
790 | { | |
6d03bbff | 791 | int i, err; |
bebe4678 | 792 | |
9b38096f AK |
793 | /* |
794 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
795 | * sensors. We check this bit only, all the early CPUs | |
796 | * without thermal sensors will be filtered out. | |
797 | */ | |
798 | if (!x86_match_cpu(coretemp_ids)) | |
799 | return -ENODEV; | |
bebe4678 | 800 | |
bd745d1c | 801 | max_zones = topology_max_packages() * topology_max_dies_per_package(); |
835896a5 | 802 | zone_devices = kcalloc(max_zones, sizeof(struct platform_device *), |
71266846 | 803 | GFP_KERNEL); |
835896a5 | 804 | if (!zone_devices) |
71266846 TG |
805 | return -ENOMEM; |
806 | ||
6d03bbff RM |
807 | for (i = 0; i < max_zones; i++) { |
808 | err = coretemp_device_add(i); | |
809 | if (err) | |
810 | goto outzone; | |
811 | } | |
bebe4678 | 812 | |
e00ca5df TG |
813 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online", |
814 | coretemp_cpu_online, coretemp_cpu_offline); | |
815 | if (err < 0) | |
6d03bbff | 816 | goto outzone; |
e00ca5df | 817 | coretemp_hp_online = err; |
bebe4678 RM |
818 | return 0; |
819 | ||
e027a2de | 820 | outzone: |
6d03bbff RM |
821 | while (i--) |
822 | coretemp_device_remove(i); | |
835896a5 | 823 | kfree(zone_devices); |
bebe4678 RM |
824 | return err; |
825 | } | |
e00ca5df | 826 | module_init(coretemp_init) |
bebe4678 RM |
827 | |
828 | static void __exit coretemp_exit(void) | |
829 | { | |
6d03bbff RM |
830 | int i; |
831 | ||
e00ca5df | 832 | cpuhp_remove_state(coretemp_hp_online); |
6d03bbff RM |
833 | for (i = 0; i < max_zones; i++) |
834 | coretemp_device_remove(i); | |
835896a5 | 835 | kfree(zone_devices); |
bebe4678 | 836 | } |
e00ca5df | 837 | module_exit(coretemp_exit) |
bebe4678 RM |
838 | |
839 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
840 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
841 | MODULE_LICENSE("GPL"); |