Commit | Line | Data |
---|---|---|
bebe4678 RM |
1 | /* |
2 | * coretemp.c - Linux kernel module for hardware monitoring | |
3 | * | |
4 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
5 | * | |
6 | * Inspired from many hwmon drivers | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA. | |
21 | */ | |
22 | ||
f8bb8925 JP |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
24 | ||
bebe4678 | 25 | #include <linux/module.h> |
bebe4678 RM |
26 | #include <linux/init.h> |
27 | #include <linux/slab.h> | |
28 | #include <linux/jiffies.h> | |
29 | #include <linux/hwmon.h> | |
30 | #include <linux/sysfs.h> | |
31 | #include <linux/hwmon-sysfs.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/mutex.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/cpu.h> | |
1fe63ab4 | 37 | #include <linux/pci.h> |
4cc45275 | 38 | #include <linux/smp.h> |
bebe4678 RM |
39 | #include <asm/msr.h> |
40 | #include <asm/processor.h> | |
41 | ||
42 | #define DRVNAME "coretemp" | |
43 | ||
199e0de7 D |
44 | #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ |
45 | #define NUM_REAL_CORES 16 /* Number of Real cores per cpu */ | |
46 | #define CORETEMP_NAME_LENGTH 17 /* String Length of attrs */ | |
47 | #define MAX_ATTRS 5 /* Maximum no of per-core attrs */ | |
48 | #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) | |
49 | ||
50 | #ifdef CONFIG_SMP | |
51 | #define TO_PHYS_ID(cpu) cpu_data(cpu).phys_proc_id | |
52 | #define TO_CORE_ID(cpu) cpu_data(cpu).cpu_core_id | |
53 | #define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO) | |
54 | #else | |
55 | #define TO_PHYS_ID(cpu) (cpu) | |
56 | #define TO_CORE_ID(cpu) (cpu) | |
57 | #define TO_ATTR_NO(cpu) (cpu) | |
58 | #endif | |
bebe4678 RM |
59 | |
60 | /* | |
199e0de7 D |
61 | * Per-Core Temperature Data |
62 | * @last_updated: The time when the current temperature value was updated | |
63 | * earlier (in jiffies). | |
64 | * @cpu_core_id: The CPU Core from which temperature values should be read | |
65 | * This value is passed as "id" field to rdmsr/wrmsr functions. | |
66 | * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS, | |
67 | * from where the temperature values should be read. | |
68 | * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data. | |
69 | * Otherwise, temp_data holds coretemp data. | |
70 | * @valid: If this is 1, the current temperature is valid. | |
bebe4678 | 71 | */ |
199e0de7 | 72 | struct temp_data { |
bebe4678 | 73 | int temp; |
6369a288 | 74 | int ttarget; |
199e0de7 D |
75 | int tjmax; |
76 | unsigned long last_updated; | |
77 | unsigned int cpu; | |
78 | u32 cpu_core_id; | |
79 | u32 status_reg; | |
80 | bool is_pkg_data; | |
81 | bool valid; | |
82 | struct sensor_device_attribute sd_attrs[MAX_ATTRS]; | |
83 | char attr_name[MAX_ATTRS][CORETEMP_NAME_LENGTH]; | |
84 | struct mutex update_lock; | |
bebe4678 RM |
85 | }; |
86 | ||
199e0de7 D |
87 | /* Platform Data per Physical CPU */ |
88 | struct platform_data { | |
89 | struct device *hwmon_dev; | |
90 | u16 phys_proc_id; | |
91 | struct temp_data *core_data[MAX_CORE_DATA]; | |
92 | struct device_attribute name_attr; | |
93 | }; | |
bebe4678 | 94 | |
199e0de7 D |
95 | struct pdev_entry { |
96 | struct list_head list; | |
97 | struct platform_device *pdev; | |
98 | unsigned int cpu; | |
99 | u16 phys_proc_id; | |
100 | u16 cpu_core_id; | |
101 | }; | |
102 | ||
103 | static LIST_HEAD(pdev_list); | |
104 | static DEFINE_MUTEX(pdev_list_mutex); | |
105 | ||
106 | static ssize_t show_name(struct device *dev, | |
107 | struct device_attribute *devattr, char *buf) | |
108 | { | |
109 | return sprintf(buf, "%s\n", DRVNAME); | |
110 | } | |
111 | ||
112 | static ssize_t show_label(struct device *dev, | |
113 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 114 | { |
bebe4678 | 115 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
199e0de7 D |
116 | struct platform_data *pdata = dev_get_drvdata(dev); |
117 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
118 | ||
119 | if (tdata->is_pkg_data) | |
120 | return sprintf(buf, "Physical id %u\n", pdata->phys_proc_id); | |
bebe4678 | 121 | |
199e0de7 | 122 | return sprintf(buf, "Core %u\n", tdata->cpu_core_id); |
bebe4678 RM |
123 | } |
124 | ||
199e0de7 D |
125 | static ssize_t show_crit_alarm(struct device *dev, |
126 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 127 | { |
199e0de7 D |
128 | u32 eax, edx; |
129 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
130 | struct platform_data *pdata = dev_get_drvdata(dev); | |
131 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
132 | ||
133 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
134 | ||
135 | return sprintf(buf, "%d\n", (eax >> 5) & 1); | |
bebe4678 RM |
136 | } |
137 | ||
199e0de7 D |
138 | static ssize_t show_tjmax(struct device *dev, |
139 | struct device_attribute *devattr, char *buf) | |
bebe4678 RM |
140 | { |
141 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
199e0de7 | 142 | struct platform_data *pdata = dev_get_drvdata(dev); |
bebe4678 | 143 | |
199e0de7 | 144 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tjmax); |
bebe4678 RM |
145 | } |
146 | ||
199e0de7 D |
147 | static ssize_t show_ttarget(struct device *dev, |
148 | struct device_attribute *devattr, char *buf) | |
149 | { | |
150 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
151 | struct platform_data *pdata = dev_get_drvdata(dev); | |
bebe4678 | 152 | |
199e0de7 D |
153 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget); |
154 | } | |
bebe4678 | 155 | |
199e0de7 D |
156 | static ssize_t show_temp(struct device *dev, |
157 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 158 | { |
199e0de7 D |
159 | u32 eax, edx; |
160 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
161 | struct platform_data *pdata = dev_get_drvdata(dev); | |
162 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
bebe4678 | 163 | |
199e0de7 | 164 | mutex_lock(&tdata->update_lock); |
bebe4678 | 165 | |
199e0de7 D |
166 | /* Check whether the time interval has elapsed */ |
167 | if (!tdata->valid || time_after(jiffies, tdata->last_updated + HZ)) { | |
168 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
169 | tdata->valid = 0; | |
170 | /* Check whether the data is valid */ | |
bebe4678 | 171 | if (eax & 0x80000000) { |
199e0de7 | 172 | tdata->temp = tdata->tjmax - |
4cc45275 | 173 | ((eax >> 16) & 0x7f) * 1000; |
199e0de7 | 174 | tdata->valid = 1; |
bebe4678 | 175 | } |
199e0de7 | 176 | tdata->last_updated = jiffies; |
bebe4678 RM |
177 | } |
178 | ||
199e0de7 D |
179 | mutex_unlock(&tdata->update_lock); |
180 | return tdata->valid ? sprintf(buf, "%d\n", tdata->temp) : -EAGAIN; | |
bebe4678 RM |
181 | } |
182 | ||
199e0de7 | 183 | static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
118a8871 RM |
184 | { |
185 | /* The 100C is default for both mobile and non mobile CPUs */ | |
186 | ||
187 | int tjmax = 100000; | |
eccfed42 | 188 | int tjmax_ee = 85000; |
708a62bc | 189 | int usemsr_ee = 1; |
118a8871 RM |
190 | int err; |
191 | u32 eax, edx; | |
1fe63ab4 | 192 | struct pci_dev *host_bridge; |
118a8871 RM |
193 | |
194 | /* Early chips have no MSR for TjMax */ | |
195 | ||
4cc45275 | 196 | if (c->x86_model == 0xf && c->x86_mask < 4) |
708a62bc | 197 | usemsr_ee = 0; |
118a8871 | 198 | |
1fe63ab4 | 199 | /* Atom CPUs */ |
708a62bc RM |
200 | |
201 | if (c->x86_model == 0x1c) { | |
202 | usemsr_ee = 0; | |
1fe63ab4 YW |
203 | |
204 | host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); | |
205 | ||
206 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL | |
207 | && (host_bridge->device == 0xa000 /* NM10 based nettop */ | |
208 | || host_bridge->device == 0xa010)) /* NM10 based netbook */ | |
209 | tjmax = 100000; | |
210 | else | |
211 | tjmax = 90000; | |
212 | ||
213 | pci_dev_put(host_bridge); | |
708a62bc RM |
214 | } |
215 | ||
4cc45275 | 216 | if (c->x86_model > 0xe && usemsr_ee) { |
eccfed42 | 217 | u8 platform_id; |
118a8871 | 218 | |
4cc45275 GR |
219 | /* |
220 | * Now we can detect the mobile CPU using Intel provided table | |
221 | * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
222 | * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
223 | */ | |
118a8871 RM |
224 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); |
225 | if (err) { | |
226 | dev_warn(dev, | |
227 | "Unable to access MSR 0x17, assuming desktop" | |
228 | " CPU\n"); | |
708a62bc | 229 | usemsr_ee = 0; |
eccfed42 | 230 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
4cc45275 GR |
231 | /* |
232 | * Trust bit 28 up to Penryn, I could not find any | |
233 | * documentation on that; if you happen to know | |
234 | * someone at Intel please ask | |
235 | */ | |
708a62bc | 236 | usemsr_ee = 0; |
eccfed42 RM |
237 | } else { |
238 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
239 | platform_id = (edx >> 18) & 0x7; | |
240 | ||
4cc45275 GR |
241 | /* |
242 | * Mobile Penryn CPU seems to be platform ID 7 or 5 | |
243 | * (guesswork) | |
244 | */ | |
245 | if (c->x86_model == 0x17 && | |
246 | (platform_id == 5 || platform_id == 7)) { | |
247 | /* | |
248 | * If MSR EE bit is set, set it to 90 degrees C, | |
249 | * otherwise 105 degrees C | |
250 | */ | |
eccfed42 RM |
251 | tjmax_ee = 90000; |
252 | tjmax = 105000; | |
253 | } | |
118a8871 RM |
254 | } |
255 | } | |
256 | ||
708a62bc | 257 | if (usemsr_ee) { |
118a8871 RM |
258 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); |
259 | if (err) { | |
260 | dev_warn(dev, | |
261 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 262 | " at default\n"); |
118a8871 | 263 | } else if (eax & 0x40000000) { |
eccfed42 | 264 | tjmax = tjmax_ee; |
118a8871 | 265 | } |
708a62bc | 266 | } else if (tjmax == 100000) { |
4cc45275 GR |
267 | /* |
268 | * If we don't use msr EE it means we are desktop CPU | |
269 | * (with exeception of Atom) | |
270 | */ | |
118a8871 RM |
271 | dev_warn(dev, "Using relative temperature scale!\n"); |
272 | } | |
273 | ||
274 | return tjmax; | |
275 | } | |
276 | ||
199e0de7 | 277 | static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
a321cedb CE |
278 | { |
279 | /* The 100C is default for both mobile and non mobile CPUs */ | |
280 | int err; | |
281 | u32 eax, edx; | |
282 | u32 val; | |
283 | ||
4cc45275 GR |
284 | /* |
285 | * A new feature of current Intel(R) processors, the | |
286 | * IA32_TEMPERATURE_TARGET contains the TjMax value | |
287 | */ | |
a321cedb CE |
288 | err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
289 | if (err) { | |
290 | dev_warn(dev, "Unable to read TjMax from CPU.\n"); | |
291 | } else { | |
292 | val = (eax >> 16) & 0xff; | |
293 | /* | |
294 | * If the TjMax is not plausible, an assumption | |
295 | * will be used | |
296 | */ | |
4cc45275 | 297 | if (val > 80 && val < 120) { |
a321cedb CE |
298 | dev_info(dev, "TjMax is %d C.\n", val); |
299 | return val * 1000; | |
300 | } | |
301 | } | |
302 | ||
303 | /* | |
304 | * An assumption is made for early CPUs and unreadable MSR. | |
305 | * NOTE: the given value may not be correct. | |
306 | */ | |
307 | ||
308 | switch (c->x86_model) { | |
309 | case 0xe: | |
310 | case 0xf: | |
311 | case 0x16: | |
312 | case 0x1a: | |
313 | dev_warn(dev, "TjMax is assumed as 100 C!\n"); | |
314 | return 100000; | |
a321cedb CE |
315 | case 0x17: |
316 | case 0x1c: /* Atom CPUs */ | |
317 | return adjust_tjmax(c, id, dev); | |
a321cedb CE |
318 | default: |
319 | dev_warn(dev, "CPU (model=0x%x) is not supported yet," | |
320 | " using default TjMax of 100C.\n", c->x86_model); | |
321 | return 100000; | |
322 | } | |
323 | } | |
324 | ||
32478006 JB |
325 | static void __devinit get_ucode_rev_on_cpu(void *edx) |
326 | { | |
327 | u32 eax; | |
328 | ||
329 | wrmsr(MSR_IA32_UCODE_REV, 0, 0); | |
330 | sync_core(); | |
331 | rdmsr(MSR_IA32_UCODE_REV, eax, *(u32 *)edx); | |
332 | } | |
333 | ||
199e0de7 | 334 | static int get_pkg_tjmax(unsigned int cpu, struct device *dev) |
bebe4678 | 335 | { |
bebe4678 | 336 | int err; |
199e0de7 | 337 | u32 eax, edx, val; |
bebe4678 | 338 | |
199e0de7 D |
339 | err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
340 | if (!err) { | |
341 | val = (eax >> 16) & 0xff; | |
4cc45275 | 342 | if (val > 80 && val < 120) |
199e0de7 | 343 | return val * 1000; |
bebe4678 | 344 | } |
199e0de7 D |
345 | dev_warn(dev, "Unable to read Pkg-TjMax from CPU:%u\n", cpu); |
346 | return 100000; /* Default TjMax: 100 degree celsius */ | |
347 | } | |
bebe4678 | 348 | |
199e0de7 D |
349 | static int create_name_attr(struct platform_data *pdata, struct device *dev) |
350 | { | |
351 | pdata->name_attr.attr.name = "name"; | |
352 | pdata->name_attr.attr.mode = S_IRUGO; | |
353 | pdata->name_attr.show = show_name; | |
354 | return device_create_file(dev, &pdata->name_attr); | |
355 | } | |
bebe4678 | 356 | |
199e0de7 D |
357 | static int create_core_attrs(struct temp_data *tdata, struct device *dev, |
358 | int attr_no) | |
359 | { | |
360 | int err, i; | |
361 | static ssize_t (*rd_ptr[MAX_ATTRS]) (struct device *dev, | |
362 | struct device_attribute *devattr, char *buf) = { | |
363 | show_label, show_crit_alarm, show_ttarget, | |
364 | show_temp, show_tjmax }; | |
365 | static const char *names[MAX_ATTRS] = { | |
366 | "temp%d_label", "temp%d_crit_alarm", | |
367 | "temp%d_max", "temp%d_input", | |
368 | "temp%d_crit" }; | |
369 | ||
370 | for (i = 0; i < MAX_ATTRS; i++) { | |
371 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, names[i], | |
372 | attr_no); | |
373 | tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i]; | |
374 | tdata->sd_attrs[i].dev_attr.attr.mode = S_IRUGO; | |
375 | tdata->sd_attrs[i].dev_attr.show = rd_ptr[i]; | |
376 | tdata->sd_attrs[i].dev_attr.store = NULL; | |
377 | tdata->sd_attrs[i].index = attr_no; | |
378 | err = device_create_file(dev, &tdata->sd_attrs[i].dev_attr); | |
379 | if (err) | |
380 | goto exit_free; | |
bebe4678 | 381 | } |
199e0de7 D |
382 | return 0; |
383 | ||
384 | exit_free: | |
385 | while (--i >= 0) | |
386 | device_remove_file(dev, &tdata->sd_attrs[i].dev_attr); | |
387 | return err; | |
388 | } | |
389 | ||
390 | static void update_ttarget(__u8 cpu_model, struct temp_data *tdata, | |
391 | struct device *dev) | |
392 | { | |
393 | int err; | |
394 | u32 eax, edx; | |
395 | ||
396 | /* | |
397 | * Initialize ttarget value. Eventually this will be | |
398 | * initialized with the value from MSR_IA32_THERM_INTERRUPT | |
399 | * register. If IA32_TEMPERATURE_TARGET is supported, this | |
400 | * value will be over written below. | |
401 | * To Do: Patch to initialize ttarget from MSR_IA32_THERM_INTERRUPT | |
402 | */ | |
403 | tdata->ttarget = tdata->tjmax - 20000; | |
bebe4678 | 404 | |
199e0de7 D |
405 | /* |
406 | * Read the still undocumented IA32_TEMPERATURE_TARGET. It exists | |
407 | * on older CPUs but not in this register, | |
408 | * Atoms don't have it either. | |
409 | */ | |
4cc45275 | 410 | if (cpu_model > 0xe && cpu_model != 0x1c) { |
199e0de7 D |
411 | err = rdmsr_safe_on_cpu(tdata->cpu, |
412 | MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); | |
413 | if (err) { | |
414 | dev_warn(dev, | |
415 | "Unable to read IA32_TEMPERATURE_TARGET MSR\n"); | |
416 | } else { | |
417 | tdata->ttarget = tdata->tjmax - | |
4cc45275 | 418 | ((eax >> 8) & 0xff) * 1000; |
199e0de7 D |
419 | } |
420 | } | |
421 | } | |
422 | ||
423 | static int chk_ucode_version(struct platform_device *pdev) | |
424 | { | |
425 | struct cpuinfo_x86 *c = &cpu_data(pdev->id); | |
426 | int err; | |
427 | u32 edx; | |
67f363b1 | 428 | |
199e0de7 D |
429 | /* |
430 | * Check if we have problem with errata AE18 of Core processors: | |
431 | * Readings might stop update when processor visited too deep sleep, | |
432 | * fixed for stepping D0 (6EC). | |
433 | */ | |
4cc45275 | 434 | if (c->x86_model == 0xe && c->x86_mask < 0xc) { |
67f363b1 | 435 | /* check for microcode update */ |
199e0de7 | 436 | err = smp_call_function_single(pdev->id, get_ucode_rev_on_cpu, |
32478006 JB |
437 | &edx, 1); |
438 | if (err) { | |
439 | dev_err(&pdev->dev, | |
440 | "Cannot determine microcode revision of " | |
199e0de7 D |
441 | "CPU#%u (%d)!\n", pdev->id, err); |
442 | return -ENODEV; | |
32478006 | 443 | } else if (edx < 0x39) { |
67f363b1 RM |
444 | dev_err(&pdev->dev, |
445 | "Errata AE18 not fixed, update BIOS or " | |
446 | "microcode of the CPU!\n"); | |
199e0de7 | 447 | return -ENODEV; |
67f363b1 RM |
448 | } |
449 | } | |
199e0de7 D |
450 | return 0; |
451 | } | |
452 | ||
453 | static struct platform_device *coretemp_get_pdev(unsigned int cpu) | |
454 | { | |
455 | u16 phys_proc_id = TO_PHYS_ID(cpu); | |
456 | struct pdev_entry *p; | |
457 | ||
458 | mutex_lock(&pdev_list_mutex); | |
459 | ||
460 | list_for_each_entry(p, &pdev_list, list) | |
461 | if (p->phys_proc_id == phys_proc_id) { | |
462 | mutex_unlock(&pdev_list_mutex); | |
463 | return p->pdev; | |
464 | } | |
465 | ||
466 | mutex_unlock(&pdev_list_mutex); | |
467 | return NULL; | |
468 | } | |
469 | ||
470 | static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag) | |
471 | { | |
472 | struct temp_data *tdata; | |
473 | ||
474 | tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL); | |
475 | if (!tdata) | |
476 | return NULL; | |
477 | ||
478 | tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS : | |
479 | MSR_IA32_THERM_STATUS; | |
480 | tdata->is_pkg_data = pkg_flag; | |
481 | tdata->cpu = cpu; | |
482 | tdata->cpu_core_id = TO_CORE_ID(cpu); | |
483 | mutex_init(&tdata->update_lock); | |
484 | return tdata; | |
485 | } | |
67f363b1 | 486 | |
199e0de7 D |
487 | static int create_core_data(struct platform_data *pdata, |
488 | struct platform_device *pdev, | |
489 | unsigned int cpu, int pkg_flag) | |
490 | { | |
491 | struct temp_data *tdata; | |
492 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
493 | u32 eax, edx; | |
494 | int err, attr_no; | |
bebe4678 | 495 | |
a321cedb | 496 | /* |
199e0de7 D |
497 | * Find attr number for sysfs: |
498 | * We map the attr number to core id of the CPU | |
499 | * The attr number is always core id + 2 | |
500 | * The Pkgtemp will always show up as temp1_*, if available | |
a321cedb | 501 | */ |
199e0de7 | 502 | attr_no = pkg_flag ? 1 : TO_ATTR_NO(cpu); |
6369a288 | 503 | |
199e0de7 D |
504 | if (attr_no > MAX_CORE_DATA - 1) |
505 | return -ERANGE; | |
506 | ||
507 | /* Skip if it is a HT core, Not an error */ | |
508 | if (pdata->core_data[attr_no] != NULL) | |
509 | return 0; | |
6369a288 | 510 | |
199e0de7 D |
511 | tdata = init_temp_data(cpu, pkg_flag); |
512 | if (!tdata) | |
513 | return -ENOMEM; | |
bebe4678 | 514 | |
199e0de7 D |
515 | /* Test if we can access the status register */ |
516 | err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); | |
517 | if (err) | |
518 | goto exit_free; | |
519 | ||
520 | /* We can access status register. Get Critical Temperature */ | |
521 | if (pkg_flag) | |
522 | tdata->tjmax = get_pkg_tjmax(pdev->id, &pdev->dev); | |
523 | else | |
524 | tdata->tjmax = get_tjmax(c, cpu, &pdev->dev); | |
525 | ||
526 | update_ttarget(c->x86_model, tdata, &pdev->dev); | |
527 | pdata->core_data[attr_no] = tdata; | |
528 | ||
529 | /* Create sysfs interfaces */ | |
530 | err = create_core_attrs(tdata, &pdev->dev, attr_no); | |
531 | if (err) | |
532 | goto exit_free; | |
bebe4678 RM |
533 | |
534 | return 0; | |
199e0de7 D |
535 | exit_free: |
536 | kfree(tdata); | |
537 | return err; | |
538 | } | |
539 | ||
540 | static void coretemp_add_core(unsigned int cpu, int pkg_flag) | |
541 | { | |
542 | struct platform_data *pdata; | |
543 | struct platform_device *pdev = coretemp_get_pdev(cpu); | |
544 | int err; | |
545 | ||
546 | if (!pdev) | |
547 | return; | |
548 | ||
549 | pdata = platform_get_drvdata(pdev); | |
550 | ||
551 | err = create_core_data(pdata, pdev, cpu, pkg_flag); | |
552 | if (err) | |
553 | dev_err(&pdev->dev, "Adding Core %u failed\n", cpu); | |
554 | } | |
555 | ||
556 | static void coretemp_remove_core(struct platform_data *pdata, | |
557 | struct device *dev, int indx) | |
558 | { | |
559 | int i; | |
560 | struct temp_data *tdata = pdata->core_data[indx]; | |
561 | ||
562 | /* Remove the sysfs attributes */ | |
563 | for (i = 0; i < MAX_ATTRS; i++) | |
564 | device_remove_file(dev, &tdata->sd_attrs[i].dev_attr); | |
565 | ||
566 | kfree(pdata->core_data[indx]); | |
567 | pdata->core_data[indx] = NULL; | |
568 | } | |
569 | ||
570 | static int __devinit coretemp_probe(struct platform_device *pdev) | |
571 | { | |
572 | struct platform_data *pdata; | |
573 | int err; | |
bebe4678 | 574 | |
199e0de7 D |
575 | /* Check the microcode version of the CPU */ |
576 | err = chk_ucode_version(pdev); | |
577 | if (err) | |
578 | return err; | |
579 | ||
580 | /* Initialize the per-package data structures */ | |
581 | pdata = kzalloc(sizeof(struct platform_data), GFP_KERNEL); | |
582 | if (!pdata) | |
583 | return -ENOMEM; | |
584 | ||
585 | err = create_name_attr(pdata, &pdev->dev); | |
586 | if (err) | |
587 | goto exit_free; | |
588 | ||
589 | pdata->phys_proc_id = TO_PHYS_ID(pdev->id); | |
590 | platform_set_drvdata(pdev, pdata); | |
591 | ||
592 | pdata->hwmon_dev = hwmon_device_register(&pdev->dev); | |
593 | if (IS_ERR(pdata->hwmon_dev)) { | |
594 | err = PTR_ERR(pdata->hwmon_dev); | |
595 | dev_err(&pdev->dev, "Class registration failed (%d)\n", err); | |
596 | goto exit_name; | |
597 | } | |
598 | return 0; | |
599 | ||
600 | exit_name: | |
601 | device_remove_file(&pdev->dev, &pdata->name_attr); | |
602 | platform_set_drvdata(pdev, NULL); | |
bebe4678 | 603 | exit_free: |
199e0de7 | 604 | kfree(pdata); |
bebe4678 RM |
605 | return err; |
606 | } | |
607 | ||
608 | static int __devexit coretemp_remove(struct platform_device *pdev) | |
609 | { | |
199e0de7 D |
610 | struct platform_data *pdata = platform_get_drvdata(pdev); |
611 | int i; | |
bebe4678 | 612 | |
199e0de7 D |
613 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) |
614 | if (pdata->core_data[i]) | |
615 | coretemp_remove_core(pdata, &pdev->dev, i); | |
616 | ||
617 | device_remove_file(&pdev->dev, &pdata->name_attr); | |
618 | hwmon_device_unregister(pdata->hwmon_dev); | |
bebe4678 | 619 | platform_set_drvdata(pdev, NULL); |
199e0de7 | 620 | kfree(pdata); |
bebe4678 RM |
621 | return 0; |
622 | } | |
623 | ||
624 | static struct platform_driver coretemp_driver = { | |
625 | .driver = { | |
626 | .owner = THIS_MODULE, | |
627 | .name = DRVNAME, | |
628 | }, | |
629 | .probe = coretemp_probe, | |
630 | .remove = __devexit_p(coretemp_remove), | |
631 | }; | |
632 | ||
bebe4678 RM |
633 | static int __cpuinit coretemp_device_add(unsigned int cpu) |
634 | { | |
635 | int err; | |
636 | struct platform_device *pdev; | |
637 | struct pdev_entry *pdev_entry; | |
d883b9f0 JD |
638 | |
639 | mutex_lock(&pdev_list_mutex); | |
640 | ||
bebe4678 RM |
641 | pdev = platform_device_alloc(DRVNAME, cpu); |
642 | if (!pdev) { | |
643 | err = -ENOMEM; | |
f8bb8925 | 644 | pr_err("Device allocation failed\n"); |
bebe4678 RM |
645 | goto exit; |
646 | } | |
647 | ||
648 | pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL); | |
649 | if (!pdev_entry) { | |
650 | err = -ENOMEM; | |
651 | goto exit_device_put; | |
652 | } | |
653 | ||
654 | err = platform_device_add(pdev); | |
655 | if (err) { | |
f8bb8925 | 656 | pr_err("Device addition failed (%d)\n", err); |
bebe4678 RM |
657 | goto exit_device_free; |
658 | } | |
659 | ||
660 | pdev_entry->pdev = pdev; | |
661 | pdev_entry->cpu = cpu; | |
199e0de7 D |
662 | pdev_entry->phys_proc_id = TO_PHYS_ID(cpu); |
663 | pdev_entry->cpu_core_id = TO_CORE_ID(cpu); | |
664 | ||
bebe4678 RM |
665 | list_add_tail(&pdev_entry->list, &pdev_list); |
666 | mutex_unlock(&pdev_list_mutex); | |
667 | ||
668 | return 0; | |
669 | ||
670 | exit_device_free: | |
671 | kfree(pdev_entry); | |
672 | exit_device_put: | |
673 | platform_device_put(pdev); | |
674 | exit: | |
d883b9f0 | 675 | mutex_unlock(&pdev_list_mutex); |
bebe4678 RM |
676 | return err; |
677 | } | |
678 | ||
199e0de7 | 679 | static void coretemp_device_remove(unsigned int cpu) |
bebe4678 | 680 | { |
199e0de7 D |
681 | struct pdev_entry *p, *n; |
682 | u16 phys_proc_id = TO_PHYS_ID(cpu); | |
e40cc4bd | 683 | |
bebe4678 | 684 | mutex_lock(&pdev_list_mutex); |
199e0de7 D |
685 | list_for_each_entry_safe(p, n, &pdev_list, list) { |
686 | if (p->phys_proc_id != phys_proc_id) | |
e40cc4bd | 687 | continue; |
e40cc4bd JB |
688 | platform_device_unregister(p->pdev); |
689 | list_del(&p->list); | |
e40cc4bd | 690 | kfree(p); |
bebe4678 RM |
691 | } |
692 | mutex_unlock(&pdev_list_mutex); | |
693 | } | |
694 | ||
199e0de7 D |
695 | static bool is_any_core_online(struct platform_data *pdata) |
696 | { | |
697 | int i; | |
698 | ||
699 | /* Find online cores, except pkgtemp data */ | |
700 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) { | |
701 | if (pdata->core_data[i] && | |
702 | !pdata->core_data[i]->is_pkg_data) { | |
703 | return true; | |
704 | } | |
705 | } | |
706 | return false; | |
707 | } | |
708 | ||
709 | static void __cpuinit get_core_online(unsigned int cpu) | |
710 | { | |
711 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
712 | struct platform_device *pdev = coretemp_get_pdev(cpu); | |
713 | int err; | |
714 | ||
715 | /* | |
716 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
717 | * sensors. We check this bit only, all the early CPUs | |
718 | * without thermal sensors will be filtered out. | |
719 | */ | |
720 | if (!cpu_has(c, X86_FEATURE_DTS)) | |
721 | return; | |
722 | ||
723 | if (!pdev) { | |
724 | /* | |
725 | * Alright, we have DTS support. | |
726 | * We are bringing the _first_ core in this pkg | |
727 | * online. So, initialize per-pkg data structures and | |
728 | * then bring this core online. | |
729 | */ | |
730 | err = coretemp_device_add(cpu); | |
731 | if (err) | |
732 | return; | |
733 | /* | |
734 | * Check whether pkgtemp support is available. | |
735 | * If so, add interfaces for pkgtemp. | |
736 | */ | |
737 | if (cpu_has(c, X86_FEATURE_PTS)) | |
738 | coretemp_add_core(cpu, 1); | |
739 | } | |
740 | /* | |
741 | * Physical CPU device already exists. | |
742 | * So, just add interfaces for this core. | |
743 | */ | |
744 | coretemp_add_core(cpu, 0); | |
745 | } | |
746 | ||
747 | static void __cpuinit put_core_offline(unsigned int cpu) | |
748 | { | |
749 | int i, indx; | |
750 | struct platform_data *pdata; | |
751 | struct platform_device *pdev = coretemp_get_pdev(cpu); | |
752 | ||
753 | /* If the physical CPU device does not exist, just return */ | |
754 | if (!pdev) | |
755 | return; | |
756 | ||
757 | pdata = platform_get_drvdata(pdev); | |
758 | ||
759 | indx = TO_ATTR_NO(cpu); | |
760 | ||
761 | if (pdata->core_data[indx] && pdata->core_data[indx]->cpu == cpu) | |
762 | coretemp_remove_core(pdata, &pdev->dev, indx); | |
763 | ||
764 | /* Online the HT version of this core, if any */ | |
765 | for_each_cpu(i, cpu_sibling_mask(cpu)) { | |
766 | if (i != cpu) { | |
767 | get_core_online(i); | |
768 | break; | |
769 | } | |
770 | } | |
771 | /* | |
772 | * If all cores in this pkg are offline, remove the device. | |
773 | * coretemp_device_remove calls unregister_platform_device, | |
774 | * which in turn calls coretemp_remove. This removes the | |
775 | * pkgtemp entry and does other clean ups. | |
776 | */ | |
777 | if (!is_any_core_online(pdata)) | |
778 | coretemp_device_remove(cpu); | |
779 | } | |
780 | ||
ba7c1927 | 781 | static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb, |
bebe4678 RM |
782 | unsigned long action, void *hcpu) |
783 | { | |
784 | unsigned int cpu = (unsigned long) hcpu; | |
785 | ||
786 | switch (action) { | |
787 | case CPU_ONLINE: | |
561d9a96 | 788 | case CPU_DOWN_FAILED: |
199e0de7 | 789 | get_core_online(cpu); |
bebe4678 | 790 | break; |
561d9a96 | 791 | case CPU_DOWN_PREPARE: |
199e0de7 | 792 | put_core_offline(cpu); |
bebe4678 RM |
793 | break; |
794 | } | |
795 | return NOTIFY_OK; | |
796 | } | |
797 | ||
ba7c1927 | 798 | static struct notifier_block coretemp_cpu_notifier __refdata = { |
bebe4678 RM |
799 | .notifier_call = coretemp_cpu_callback, |
800 | }; | |
bebe4678 RM |
801 | |
802 | static int __init coretemp_init(void) | |
803 | { | |
804 | int i, err = -ENODEV; | |
bebe4678 | 805 | |
bebe4678 | 806 | /* quick check if we run Intel */ |
92cb7612 | 807 | if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL) |
bebe4678 RM |
808 | goto exit; |
809 | ||
810 | err = platform_driver_register(&coretemp_driver); | |
811 | if (err) | |
812 | goto exit; | |
813 | ||
a4659053 | 814 | for_each_online_cpu(i) |
199e0de7 | 815 | get_core_online(i); |
89a3fd35 JB |
816 | |
817 | #ifndef CONFIG_HOTPLUG_CPU | |
bebe4678 RM |
818 | if (list_empty(&pdev_list)) { |
819 | err = -ENODEV; | |
820 | goto exit_driver_unreg; | |
821 | } | |
89a3fd35 | 822 | #endif |
bebe4678 | 823 | |
bebe4678 | 824 | register_hotcpu_notifier(&coretemp_cpu_notifier); |
bebe4678 RM |
825 | return 0; |
826 | ||
0dca94ba | 827 | #ifndef CONFIG_HOTPLUG_CPU |
89a3fd35 | 828 | exit_driver_unreg: |
bebe4678 | 829 | platform_driver_unregister(&coretemp_driver); |
0dca94ba | 830 | #endif |
bebe4678 RM |
831 | exit: |
832 | return err; | |
833 | } | |
834 | ||
835 | static void __exit coretemp_exit(void) | |
836 | { | |
837 | struct pdev_entry *p, *n; | |
17c10d61 | 838 | |
bebe4678 | 839 | unregister_hotcpu_notifier(&coretemp_cpu_notifier); |
bebe4678 RM |
840 | mutex_lock(&pdev_list_mutex); |
841 | list_for_each_entry_safe(p, n, &pdev_list, list) { | |
842 | platform_device_unregister(p->pdev); | |
843 | list_del(&p->list); | |
844 | kfree(p); | |
845 | } | |
846 | mutex_unlock(&pdev_list_mutex); | |
847 | platform_driver_unregister(&coretemp_driver); | |
848 | } | |
849 | ||
850 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
851 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
852 | MODULE_LICENSE("GPL"); | |
853 | ||
854 | module_init(coretemp_init) | |
855 | module_exit(coretemp_exit) |