Commit | Line | Data |
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935912c5 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
bebe4678 RM |
2 | /* |
3 | * coretemp.c - Linux kernel module for hardware monitoring | |
4 | * | |
5 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
6 | * | |
7 | * Inspired from many hwmon drivers | |
bebe4678 RM |
8 | */ |
9 | ||
f8bb8925 JP |
10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
11 | ||
bebe4678 | 12 | #include <linux/module.h> |
bebe4678 RM |
13 | #include <linux/init.h> |
14 | #include <linux/slab.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/hwmon.h> | |
17 | #include <linux/sysfs.h> | |
18 | #include <linux/hwmon-sysfs.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/mutex.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/cpu.h> | |
4cc45275 | 24 | #include <linux/smp.h> |
a45a8c85 | 25 | #include <linux/moduleparam.h> |
14513ee6 | 26 | #include <linux/pci.h> |
bebe4678 RM |
27 | #include <asm/msr.h> |
28 | #include <asm/processor.h> | |
9b38096f | 29 | #include <asm/cpu_device_id.h> |
bebe4678 RM |
30 | |
31 | #define DRVNAME "coretemp" | |
32 | ||
a45a8c85 JD |
33 | /* |
34 | * force_tjmax only matters when TjMax can't be read from the CPU itself. | |
35 | * When set, it replaces the driver's suboptimal heuristic. | |
36 | */ | |
37 | static int force_tjmax; | |
38 | module_param_named(tjmax, force_tjmax, int, 0444); | |
39 | MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); | |
40 | ||
723f5734 | 41 | #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ |
199e0de7 | 42 | #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ |
cc904f9c | 43 | #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ |
3f9aec76 | 44 | #define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ |
c814a4c7 | 45 | #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ |
f4af6fd6 | 46 | #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) |
199e0de7 D |
47 | #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) |
48 | ||
780affe0 | 49 | #define TO_CORE_ID(cpu) (cpu_data(cpu).cpu_core_id) |
141168c3 KW |
50 | #define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO) |
51 | ||
52 | #ifdef CONFIG_SMP | |
19a34eea BG |
53 | #define for_each_sibling(i, cpu) \ |
54 | for_each_cpu(i, topology_sibling_cpumask(cpu)) | |
199e0de7 | 55 | #else |
bb74e8ca | 56 | #define for_each_sibling(i, cpu) for (i = 0; false; ) |
199e0de7 | 57 | #endif |
bebe4678 RM |
58 | |
59 | /* | |
199e0de7 D |
60 | * Per-Core Temperature Data |
61 | * @last_updated: The time when the current temperature value was updated | |
62 | * earlier (in jiffies). | |
63 | * @cpu_core_id: The CPU Core from which temperature values should be read | |
64 | * This value is passed as "id" field to rdmsr/wrmsr functions. | |
65 | * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS, | |
66 | * from where the temperature values should be read. | |
c814a4c7 | 67 | * @attr_size: Total number of pre-core attrs displayed in the sysfs. |
199e0de7 D |
68 | * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data. |
69 | * Otherwise, temp_data holds coretemp data. | |
70 | * @valid: If this is 1, the current temperature is valid. | |
bebe4678 | 71 | */ |
199e0de7 | 72 | struct temp_data { |
bebe4678 | 73 | int temp; |
6369a288 | 74 | int ttarget; |
199e0de7 D |
75 | int tjmax; |
76 | unsigned long last_updated; | |
77 | unsigned int cpu; | |
78 | u32 cpu_core_id; | |
79 | u32 status_reg; | |
c814a4c7 | 80 | int attr_size; |
199e0de7 D |
81 | bool is_pkg_data; |
82 | bool valid; | |
c814a4c7 D |
83 | struct sensor_device_attribute sd_attrs[TOTAL_ATTRS]; |
84 | char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH]; | |
1075305d GR |
85 | struct attribute *attrs[TOTAL_ATTRS + 1]; |
86 | struct attribute_group attr_group; | |
199e0de7 | 87 | struct mutex update_lock; |
bebe4678 RM |
88 | }; |
89 | ||
199e0de7 D |
90 | /* Platform Data per Physical CPU */ |
91 | struct platform_data { | |
e1b370b6 | 92 | struct device *hwmon_dev; |
71266846 | 93 | u16 pkg_id; |
e1b370b6 TG |
94 | struct cpumask cpumask; |
95 | struct temp_data *core_data[MAX_CORE_DATA]; | |
199e0de7 D |
96 | struct device_attribute name_attr; |
97 | }; | |
bebe4678 | 98 | |
835896a5 LB |
99 | /* Keep track of how many zone pointers we allocated in init() */ |
100 | static int max_zones __read_mostly; | |
101 | /* Array of zone pointers. Serialized by cpu hotplug lock */ | |
102 | static struct platform_device **zone_devices; | |
199e0de7 | 103 | |
199e0de7 D |
104 | static ssize_t show_label(struct device *dev, |
105 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 106 | { |
bebe4678 | 107 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
199e0de7 D |
108 | struct platform_data *pdata = dev_get_drvdata(dev); |
109 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
110 | ||
111 | if (tdata->is_pkg_data) | |
71266846 | 112 | return sprintf(buf, "Package id %u\n", pdata->pkg_id); |
bebe4678 | 113 | |
199e0de7 | 114 | return sprintf(buf, "Core %u\n", tdata->cpu_core_id); |
bebe4678 RM |
115 | } |
116 | ||
199e0de7 D |
117 | static ssize_t show_crit_alarm(struct device *dev, |
118 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 119 | { |
199e0de7 D |
120 | u32 eax, edx; |
121 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
122 | struct platform_data *pdata = dev_get_drvdata(dev); | |
123 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
124 | ||
723f5734 | 125 | mutex_lock(&tdata->update_lock); |
199e0de7 | 126 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); |
723f5734 | 127 | mutex_unlock(&tdata->update_lock); |
199e0de7 D |
128 | |
129 | return sprintf(buf, "%d\n", (eax >> 5) & 1); | |
bebe4678 RM |
130 | } |
131 | ||
199e0de7 D |
132 | static ssize_t show_tjmax(struct device *dev, |
133 | struct device_attribute *devattr, char *buf) | |
bebe4678 RM |
134 | { |
135 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
199e0de7 | 136 | struct platform_data *pdata = dev_get_drvdata(dev); |
bebe4678 | 137 | |
199e0de7 | 138 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tjmax); |
bebe4678 RM |
139 | } |
140 | ||
199e0de7 D |
141 | static ssize_t show_ttarget(struct device *dev, |
142 | struct device_attribute *devattr, char *buf) | |
143 | { | |
144 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
145 | struct platform_data *pdata = dev_get_drvdata(dev); | |
bebe4678 | 146 | |
199e0de7 D |
147 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget); |
148 | } | |
bebe4678 | 149 | |
199e0de7 D |
150 | static ssize_t show_temp(struct device *dev, |
151 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 152 | { |
199e0de7 D |
153 | u32 eax, edx; |
154 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
155 | struct platform_data *pdata = dev_get_drvdata(dev); | |
156 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
bebe4678 | 157 | |
199e0de7 | 158 | mutex_lock(&tdata->update_lock); |
bebe4678 | 159 | |
199e0de7 D |
160 | /* Check whether the time interval has elapsed */ |
161 | if (!tdata->valid || time_after(jiffies, tdata->last_updated + HZ)) { | |
162 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
bf6ea084 GR |
163 | /* |
164 | * Ignore the valid bit. In all observed cases the register | |
165 | * value is either low or zero if the valid bit is 0. | |
166 | * Return it instead of reporting an error which doesn't | |
167 | * really help at all. | |
168 | */ | |
169 | tdata->temp = tdata->tjmax - ((eax >> 16) & 0x7f) * 1000; | |
170 | tdata->valid = 1; | |
199e0de7 | 171 | tdata->last_updated = jiffies; |
bebe4678 RM |
172 | } |
173 | ||
199e0de7 | 174 | mutex_unlock(&tdata->update_lock); |
bf6ea084 | 175 | return sprintf(buf, "%d\n", tdata->temp); |
bebe4678 RM |
176 | } |
177 | ||
14513ee6 GR |
178 | struct tjmax_pci { |
179 | unsigned int device; | |
180 | int tjmax; | |
181 | }; | |
182 | ||
183 | static const struct tjmax_pci tjmax_pci_table[] = { | |
347c16cf | 184 | { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */ |
14513ee6 GR |
185 | { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */ |
186 | { 0x0c73, 95000 }, /* Atom S1220 (Centerton) */ | |
187 | { 0x0c75, 95000 }, /* Atom S1260 (Centerton) */ | |
188 | }; | |
189 | ||
41e58a1f GR |
190 | struct tjmax { |
191 | char const *id; | |
192 | int tjmax; | |
193 | }; | |
194 | ||
d23e2ae1 | 195 | static const struct tjmax tjmax_table[] = { |
1102dcab GR |
196 | { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */ |
197 | { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */ | |
41e58a1f GR |
198 | }; |
199 | ||
2fa5222e GR |
200 | struct tjmax_model { |
201 | u8 model; | |
202 | u8 mask; | |
203 | int tjmax; | |
204 | }; | |
205 | ||
206 | #define ANY 0xff | |
207 | ||
d23e2ae1 | 208 | static const struct tjmax_model tjmax_model_table[] = { |
9e3970fb | 209 | { 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */ |
2fa5222e GR |
210 | { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others |
211 | * Note: Also matches 230 and 330, | |
212 | * which are covered by tjmax_table | |
213 | */ | |
214 | { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx) | |
215 | * Note: TjMax for E6xxT is 110C, but CPU type | |
216 | * is undetectable by software | |
217 | */ | |
218 | { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */ | |
14513ee6 GR |
219 | { 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */ |
220 | { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) | |
221 | * Also matches S12x0 (stepping 9), covered by | |
222 | * PCI table | |
223 | */ | |
2fa5222e GR |
224 | }; |
225 | ||
d23e2ae1 | 226 | static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
118a8871 RM |
227 | { |
228 | /* The 100C is default for both mobile and non mobile CPUs */ | |
229 | ||
230 | int tjmax = 100000; | |
eccfed42 | 231 | int tjmax_ee = 85000; |
708a62bc | 232 | int usemsr_ee = 1; |
118a8871 RM |
233 | int err; |
234 | u32 eax, edx; | |
41e58a1f | 235 | int i; |
b9ccff23 SK |
236 | u16 devfn = PCI_DEVFN(0, 0); |
237 | struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn); | |
14513ee6 GR |
238 | |
239 | /* | |
240 | * Explicit tjmax table entries override heuristics. | |
241 | * First try PCI host bridge IDs, followed by model ID strings | |
242 | * and model/stepping information. | |
243 | */ | |
244 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
245 | for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) { | |
246 | if (host_bridge->device == tjmax_pci_table[i].device) | |
247 | return tjmax_pci_table[i].tjmax; | |
248 | } | |
249 | } | |
41e58a1f | 250 | |
41e58a1f GR |
251 | for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) { |
252 | if (strstr(c->x86_model_id, tjmax_table[i].id)) | |
253 | return tjmax_table[i].tjmax; | |
254 | } | |
118a8871 | 255 | |
2fa5222e GR |
256 | for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { |
257 | const struct tjmax_model *tm = &tjmax_model_table[i]; | |
258 | if (c->x86_model == tm->model && | |
b399151c | 259 | (tm->mask == ANY || c->x86_stepping == tm->mask)) |
2fa5222e | 260 | return tm->tjmax; |
72cbdddc | 261 | } |
1fe63ab4 | 262 | |
72cbdddc | 263 | /* Early chips have no MSR for TjMax */ |
1fe63ab4 | 264 | |
b399151c | 265 | if (c->x86_model == 0xf && c->x86_stepping < 4) |
5592906f | 266 | usemsr_ee = 0; |
708a62bc | 267 | |
4cc45275 | 268 | if (c->x86_model > 0xe && usemsr_ee) { |
eccfed42 | 269 | u8 platform_id; |
118a8871 | 270 | |
4cc45275 GR |
271 | /* |
272 | * Now we can detect the mobile CPU using Intel provided table | |
273 | * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
274 | * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
275 | */ | |
118a8871 RM |
276 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); |
277 | if (err) { | |
278 | dev_warn(dev, | |
279 | "Unable to access MSR 0x17, assuming desktop" | |
280 | " CPU\n"); | |
708a62bc | 281 | usemsr_ee = 0; |
eccfed42 | 282 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
4cc45275 GR |
283 | /* |
284 | * Trust bit 28 up to Penryn, I could not find any | |
285 | * documentation on that; if you happen to know | |
286 | * someone at Intel please ask | |
287 | */ | |
708a62bc | 288 | usemsr_ee = 0; |
eccfed42 RM |
289 | } else { |
290 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
291 | platform_id = (edx >> 18) & 0x7; | |
292 | ||
4cc45275 GR |
293 | /* |
294 | * Mobile Penryn CPU seems to be platform ID 7 or 5 | |
295 | * (guesswork) | |
296 | */ | |
297 | if (c->x86_model == 0x17 && | |
298 | (platform_id == 5 || platform_id == 7)) { | |
299 | /* | |
300 | * If MSR EE bit is set, set it to 90 degrees C, | |
301 | * otherwise 105 degrees C | |
302 | */ | |
eccfed42 RM |
303 | tjmax_ee = 90000; |
304 | tjmax = 105000; | |
305 | } | |
118a8871 RM |
306 | } |
307 | } | |
308 | ||
708a62bc | 309 | if (usemsr_ee) { |
118a8871 RM |
310 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); |
311 | if (err) { | |
312 | dev_warn(dev, | |
313 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 314 | " at default\n"); |
118a8871 | 315 | } else if (eax & 0x40000000) { |
eccfed42 | 316 | tjmax = tjmax_ee; |
118a8871 | 317 | } |
708a62bc | 318 | } else if (tjmax == 100000) { |
4cc45275 GR |
319 | /* |
320 | * If we don't use msr EE it means we are desktop CPU | |
321 | * (with exeception of Atom) | |
322 | */ | |
118a8871 RM |
323 | dev_warn(dev, "Using relative temperature scale!\n"); |
324 | } | |
325 | ||
326 | return tjmax; | |
327 | } | |
328 | ||
1c2faa22 GR |
329 | static bool cpu_has_tjmax(struct cpuinfo_x86 *c) |
330 | { | |
331 | u8 model = c->x86_model; | |
332 | ||
333 | return model > 0xe && | |
334 | model != 0x1c && | |
335 | model != 0x26 && | |
336 | model != 0x27 && | |
337 | model != 0x35 && | |
338 | model != 0x36; | |
339 | } | |
340 | ||
d23e2ae1 | 341 | static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
a321cedb | 342 | { |
a321cedb CE |
343 | int err; |
344 | u32 eax, edx; | |
345 | u32 val; | |
346 | ||
4cc45275 GR |
347 | /* |
348 | * A new feature of current Intel(R) processors, the | |
349 | * IA32_TEMPERATURE_TARGET contains the TjMax value | |
350 | */ | |
a321cedb CE |
351 | err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
352 | if (err) { | |
1c2faa22 | 353 | if (cpu_has_tjmax(c)) |
6bf9e9b0 | 354 | dev_warn(dev, "Unable to read TjMax from CPU %u\n", id); |
a321cedb | 355 | } else { |
c0940e95 | 356 | val = (eax >> 16) & 0xff; |
a321cedb CE |
357 | /* |
358 | * If the TjMax is not plausible, an assumption | |
359 | * will be used | |
360 | */ | |
c0940e95 | 361 | if (val) { |
6bf9e9b0 | 362 | dev_dbg(dev, "TjMax is %d degrees C\n", val); |
a321cedb CE |
363 | return val * 1000; |
364 | } | |
365 | } | |
366 | ||
a45a8c85 JD |
367 | if (force_tjmax) { |
368 | dev_notice(dev, "TjMax forced to %d degrees C by user\n", | |
369 | force_tjmax); | |
370 | return force_tjmax * 1000; | |
371 | } | |
372 | ||
a321cedb CE |
373 | /* |
374 | * An assumption is made for early CPUs and unreadable MSR. | |
4f5f71a7 | 375 | * NOTE: the calculated value may not be correct. |
a321cedb | 376 | */ |
4f5f71a7 | 377 | return adjust_tjmax(c, id, dev); |
a321cedb CE |
378 | } |
379 | ||
d23e2ae1 PG |
380 | static int create_core_attrs(struct temp_data *tdata, struct device *dev, |
381 | int attr_no) | |
199e0de7 | 382 | { |
1075305d | 383 | int i; |
e3204ed3 | 384 | static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev, |
199e0de7 | 385 | struct device_attribute *devattr, char *buf) = { |
c814a4c7 | 386 | show_label, show_crit_alarm, show_temp, show_tjmax, |
f4af6fd6 | 387 | show_ttarget }; |
1055b5f9 RV |
388 | static const char *const suffixes[TOTAL_ATTRS] = { |
389 | "label", "crit_alarm", "input", "crit", "max" | |
390 | }; | |
199e0de7 | 391 | |
c814a4c7 | 392 | for (i = 0; i < tdata->attr_size; i++) { |
1055b5f9 RV |
393 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, |
394 | "temp%d_%s", attr_no, suffixes[i]); | |
4258781a | 395 | sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr); |
199e0de7 | 396 | tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i]; |
0cd709d0 | 397 | tdata->sd_attrs[i].dev_attr.attr.mode = 0444; |
199e0de7 | 398 | tdata->sd_attrs[i].dev_attr.show = rd_ptr[i]; |
199e0de7 | 399 | tdata->sd_attrs[i].index = attr_no; |
1075305d | 400 | tdata->attrs[i] = &tdata->sd_attrs[i].dev_attr.attr; |
bebe4678 | 401 | } |
1075305d GR |
402 | tdata->attr_group.attrs = tdata->attrs; |
403 | return sysfs_create_group(&dev->kobj, &tdata->attr_group); | |
199e0de7 D |
404 | } |
405 | ||
199e0de7 | 406 | |
d23e2ae1 | 407 | static int chk_ucode_version(unsigned int cpu) |
199e0de7 | 408 | { |
0eb9782a | 409 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
67f363b1 | 410 | |
199e0de7 D |
411 | /* |
412 | * Check if we have problem with errata AE18 of Core processors: | |
413 | * Readings might stop update when processor visited too deep sleep, | |
414 | * fixed for stepping D0 (6EC). | |
415 | */ | |
b399151c | 416 | if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) { |
b55f3757 | 417 | pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); |
ca8bc8dc | 418 | return -ENODEV; |
67f363b1 | 419 | } |
199e0de7 D |
420 | return 0; |
421 | } | |
422 | ||
d23e2ae1 | 423 | static struct platform_device *coretemp_get_pdev(unsigned int cpu) |
199e0de7 | 424 | { |
835896a5 | 425 | int id = topology_logical_die_id(cpu); |
199e0de7 | 426 | |
835896a5 LB |
427 | if (id >= 0 && id < max_zones) |
428 | return zone_devices[id]; | |
199e0de7 D |
429 | return NULL; |
430 | } | |
431 | ||
d23e2ae1 | 432 | static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag) |
199e0de7 D |
433 | { |
434 | struct temp_data *tdata; | |
435 | ||
436 | tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL); | |
437 | if (!tdata) | |
438 | return NULL; | |
439 | ||
440 | tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS : | |
441 | MSR_IA32_THERM_STATUS; | |
442 | tdata->is_pkg_data = pkg_flag; | |
443 | tdata->cpu = cpu; | |
444 | tdata->cpu_core_id = TO_CORE_ID(cpu); | |
c814a4c7 | 445 | tdata->attr_size = MAX_CORE_ATTRS; |
199e0de7 D |
446 | mutex_init(&tdata->update_lock); |
447 | return tdata; | |
448 | } | |
67f363b1 | 449 | |
d23e2ae1 PG |
450 | static int create_core_data(struct platform_device *pdev, unsigned int cpu, |
451 | int pkg_flag) | |
199e0de7 D |
452 | { |
453 | struct temp_data *tdata; | |
2f1c3db0 | 454 | struct platform_data *pdata = platform_get_drvdata(pdev); |
199e0de7 D |
455 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
456 | u32 eax, edx; | |
457 | int err, attr_no; | |
bebe4678 | 458 | |
a321cedb | 459 | /* |
199e0de7 D |
460 | * Find attr number for sysfs: |
461 | * We map the attr number to core id of the CPU | |
462 | * The attr number is always core id + 2 | |
463 | * The Pkgtemp will always show up as temp1_*, if available | |
a321cedb | 464 | */ |
723f5734 | 465 | attr_no = pkg_flag ? PKG_SYSFS_ATTR_NO : TO_ATTR_NO(cpu); |
6369a288 | 466 | |
199e0de7 D |
467 | if (attr_no > MAX_CORE_DATA - 1) |
468 | return -ERANGE; | |
469 | ||
199e0de7 D |
470 | tdata = init_temp_data(cpu, pkg_flag); |
471 | if (!tdata) | |
472 | return -ENOMEM; | |
bebe4678 | 473 | |
199e0de7 D |
474 | /* Test if we can access the status register */ |
475 | err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); | |
476 | if (err) | |
477 | goto exit_free; | |
478 | ||
479 | /* We can access status register. Get Critical Temperature */ | |
6bf9e9b0 | 480 | tdata->tjmax = get_tjmax(c, cpu, &pdev->dev); |
199e0de7 | 481 | |
c814a4c7 | 482 | /* |
f4af6fd6 GR |
483 | * Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. |
484 | * The target temperature is available on older CPUs but not in this | |
485 | * register. Atoms don't have the register at all. | |
c814a4c7 | 486 | */ |
f4af6fd6 GR |
487 | if (c->x86_model > 0xe && c->x86_model != 0x1c) { |
488 | err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, | |
489 | &eax, &edx); | |
490 | if (!err) { | |
491 | tdata->ttarget | |
492 | = tdata->tjmax - ((eax >> 8) & 0xff) * 1000; | |
493 | tdata->attr_size++; | |
494 | } | |
c814a4c7 D |
495 | } |
496 | ||
199e0de7 D |
497 | pdata->core_data[attr_no] = tdata; |
498 | ||
499 | /* Create sysfs interfaces */ | |
d72d19c2 | 500 | err = create_core_attrs(tdata, pdata->hwmon_dev, attr_no); |
199e0de7 D |
501 | if (err) |
502 | goto exit_free; | |
bebe4678 RM |
503 | |
504 | return 0; | |
199e0de7 | 505 | exit_free: |
20ecb499 | 506 | pdata->core_data[attr_no] = NULL; |
199e0de7 D |
507 | kfree(tdata); |
508 | return err; | |
509 | } | |
510 | ||
4b138cf7 TG |
511 | static void |
512 | coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag) | |
199e0de7 | 513 | { |
4b138cf7 | 514 | if (create_core_data(pdev, cpu, pkg_flag)) |
199e0de7 D |
515 | dev_err(&pdev->dev, "Adding Core %u failed\n", cpu); |
516 | } | |
517 | ||
4b138cf7 | 518 | static void coretemp_remove_core(struct platform_data *pdata, int indx) |
199e0de7 | 519 | { |
199e0de7 D |
520 | struct temp_data *tdata = pdata->core_data[indx]; |
521 | ||
522 | /* Remove the sysfs attributes */ | |
d72d19c2 | 523 | sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group); |
199e0de7 D |
524 | |
525 | kfree(pdata->core_data[indx]); | |
526 | pdata->core_data[indx] = NULL; | |
527 | } | |
528 | ||
6c931ae1 | 529 | static int coretemp_probe(struct platform_device *pdev) |
199e0de7 | 530 | { |
c503a811 | 531 | struct device *dev = &pdev->dev; |
199e0de7 | 532 | struct platform_data *pdata; |
bebe4678 | 533 | |
835896a5 | 534 | /* Initialize the per-zone data structures */ |
c503a811 | 535 | pdata = devm_kzalloc(dev, sizeof(struct platform_data), GFP_KERNEL); |
199e0de7 D |
536 | if (!pdata) |
537 | return -ENOMEM; | |
538 | ||
71266846 | 539 | pdata->pkg_id = pdev->id; |
199e0de7 D |
540 | platform_set_drvdata(pdev, pdata); |
541 | ||
d72d19c2 GR |
542 | pdata->hwmon_dev = devm_hwmon_device_register_with_groups(dev, DRVNAME, |
543 | pdata, NULL); | |
544 | return PTR_ERR_OR_ZERO(pdata->hwmon_dev); | |
bebe4678 RM |
545 | } |
546 | ||
281dfd0b | 547 | static int coretemp_remove(struct platform_device *pdev) |
bebe4678 | 548 | { |
199e0de7 D |
549 | struct platform_data *pdata = platform_get_drvdata(pdev); |
550 | int i; | |
bebe4678 | 551 | |
199e0de7 D |
552 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) |
553 | if (pdata->core_data[i]) | |
d72d19c2 | 554 | coretemp_remove_core(pdata, i); |
199e0de7 | 555 | |
bebe4678 RM |
556 | return 0; |
557 | } | |
558 | ||
559 | static struct platform_driver coretemp_driver = { | |
560 | .driver = { | |
bebe4678 RM |
561 | .name = DRVNAME, |
562 | }, | |
563 | .probe = coretemp_probe, | |
9e5e9b7a | 564 | .remove = coretemp_remove, |
bebe4678 RM |
565 | }; |
566 | ||
71266846 | 567 | static struct platform_device *coretemp_device_add(unsigned int cpu) |
bebe4678 | 568 | { |
835896a5 | 569 | int err, zoneid = topology_logical_die_id(cpu); |
bebe4678 | 570 | struct platform_device *pdev; |
d883b9f0 | 571 | |
835896a5 | 572 | if (zoneid < 0) |
71266846 | 573 | return ERR_PTR(-ENOMEM); |
d883b9f0 | 574 | |
835896a5 | 575 | pdev = platform_device_alloc(DRVNAME, zoneid); |
71266846 TG |
576 | if (!pdev) |
577 | return ERR_PTR(-ENOMEM); | |
bebe4678 RM |
578 | |
579 | err = platform_device_add(pdev); | |
580 | if (err) { | |
71266846 TG |
581 | platform_device_put(pdev); |
582 | return ERR_PTR(err); | |
bebe4678 RM |
583 | } |
584 | ||
835896a5 | 585 | zone_devices[zoneid] = pdev; |
71266846 | 586 | return pdev; |
bebe4678 RM |
587 | } |
588 | ||
e00ca5df | 589 | static int coretemp_cpu_online(unsigned int cpu) |
199e0de7 | 590 | { |
199e0de7 | 591 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 TG |
592 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
593 | struct platform_data *pdata; | |
199e0de7 | 594 | |
90b4f30b TG |
595 | /* |
596 | * Don't execute this on resume as the offline callback did | |
597 | * not get executed on suspend. | |
598 | */ | |
599 | if (cpuhp_tasks_frozen) | |
600 | return 0; | |
601 | ||
199e0de7 D |
602 | /* |
603 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
604 | * sensors. We check this bit only, all the early CPUs | |
605 | * without thermal sensors will be filtered out. | |
606 | */ | |
4ad33411 | 607 | if (!cpu_has(c, X86_FEATURE_DTHERM)) |
2195c31b | 608 | return -ENODEV; |
199e0de7 D |
609 | |
610 | if (!pdev) { | |
0eb9782a JD |
611 | /* Check the microcode version of the CPU */ |
612 | if (chk_ucode_version(cpu)) | |
2195c31b | 613 | return -EINVAL; |
0eb9782a | 614 | |
199e0de7 D |
615 | /* |
616 | * Alright, we have DTS support. | |
617 | * We are bringing the _first_ core in this pkg | |
618 | * online. So, initialize per-pkg data structures and | |
619 | * then bring this core online. | |
620 | */ | |
71266846 TG |
621 | pdev = coretemp_device_add(cpu); |
622 | if (IS_ERR(pdev)) | |
623 | return PTR_ERR(pdev); | |
e1b370b6 | 624 | |
199e0de7 D |
625 | /* |
626 | * Check whether pkgtemp support is available. | |
627 | * If so, add interfaces for pkgtemp. | |
628 | */ | |
629 | if (cpu_has(c, X86_FEATURE_PTS)) | |
4b138cf7 | 630 | coretemp_add_core(pdev, cpu, 1); |
199e0de7 | 631 | } |
e1b370b6 TG |
632 | |
633 | pdata = platform_get_drvdata(pdev); | |
199e0de7 | 634 | /* |
e1b370b6 TG |
635 | * Check whether a thread sibling is already online. If not add the |
636 | * interface for this CPU core. | |
199e0de7 | 637 | */ |
e1b370b6 | 638 | if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu))) |
4b138cf7 | 639 | coretemp_add_core(pdev, cpu, 0); |
e1b370b6 TG |
640 | |
641 | cpumask_set_cpu(cpu, &pdata->cpumask); | |
e00ca5df | 642 | return 0; |
199e0de7 D |
643 | } |
644 | ||
e00ca5df | 645 | static int coretemp_cpu_offline(unsigned int cpu) |
199e0de7 | 646 | { |
199e0de7 | 647 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 | 648 | struct platform_data *pd; |
723f5734 | 649 | struct temp_data *tdata; |
e1b370b6 | 650 | int indx, target; |
199e0de7 | 651 | |
90b4f30b TG |
652 | /* |
653 | * Don't execute this on suspend as the device remove locks | |
654 | * up the machine. | |
655 | */ | |
656 | if (cpuhp_tasks_frozen) | |
657 | return 0; | |
658 | ||
199e0de7 D |
659 | /* If the physical CPU device does not exist, just return */ |
660 | if (!pdev) | |
e00ca5df | 661 | return 0; |
199e0de7 | 662 | |
b7048711 | 663 | /* The core id is too big, just return */ |
e1b370b6 | 664 | indx = TO_ATTR_NO(cpu); |
b7048711 | 665 | if (indx > MAX_CORE_DATA - 1) |
e00ca5df | 666 | return 0; |
b7048711 | 667 | |
e1b370b6 TG |
668 | pd = platform_get_drvdata(pdev); |
669 | tdata = pd->core_data[indx]; | |
670 | ||
671 | cpumask_clear_cpu(cpu, &pd->cpumask); | |
199e0de7 | 672 | |
f4e0bcf0 | 673 | /* |
e1b370b6 TG |
674 | * If this is the last thread sibling, remove the CPU core |
675 | * interface, If there is still a sibling online, transfer the | |
676 | * target cpu of that core interface to it. | |
f4e0bcf0 | 677 | */ |
e1b370b6 TG |
678 | target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu)); |
679 | if (target >= nr_cpu_ids) { | |
680 | coretemp_remove_core(pd, indx); | |
681 | } else if (tdata && tdata->cpu == cpu) { | |
682 | mutex_lock(&tdata->update_lock); | |
683 | tdata->cpu = target; | |
684 | mutex_unlock(&tdata->update_lock); | |
199e0de7 | 685 | } |
e1b370b6 | 686 | |
199e0de7 | 687 | /* |
71266846 TG |
688 | * If all cores in this pkg are offline, remove the device. This |
689 | * will invoke the platform driver remove function, which cleans up | |
690 | * the rest. | |
199e0de7 | 691 | */ |
e1b370b6 | 692 | if (cpumask_empty(&pd->cpumask)) { |
835896a5 | 693 | zone_devices[topology_logical_die_id(cpu)] = NULL; |
71266846 | 694 | platform_device_unregister(pdev); |
e00ca5df | 695 | return 0; |
723f5734 | 696 | } |
71266846 | 697 | |
723f5734 TG |
698 | /* |
699 | * Check whether this core is the target for the package | |
700 | * interface. We need to assign it to some other cpu. | |
701 | */ | |
e1b370b6 | 702 | tdata = pd->core_data[PKG_SYSFS_ATTR_NO]; |
723f5734 | 703 | if (tdata && tdata->cpu == cpu) { |
e1b370b6 | 704 | target = cpumask_first(&pd->cpumask); |
723f5734 TG |
705 | mutex_lock(&tdata->update_lock); |
706 | tdata->cpu = target; | |
707 | mutex_unlock(&tdata->update_lock); | |
708 | } | |
e00ca5df | 709 | return 0; |
199e0de7 | 710 | } |
e273bd98 | 711 | static const struct x86_cpu_id __initconst coretemp_ids[] = { |
4ad33411 | 712 | { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, X86_FEATURE_DTHERM }, |
9b38096f AK |
713 | {} |
714 | }; | |
715 | MODULE_DEVICE_TABLE(x86cpu, coretemp_ids); | |
716 | ||
e00ca5df TG |
717 | static enum cpuhp_state coretemp_hp_online; |
718 | ||
bebe4678 RM |
719 | static int __init coretemp_init(void) |
720 | { | |
e00ca5df | 721 | int err; |
bebe4678 | 722 | |
9b38096f AK |
723 | /* |
724 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
725 | * sensors. We check this bit only, all the early CPUs | |
726 | * without thermal sensors will be filtered out. | |
727 | */ | |
728 | if (!x86_match_cpu(coretemp_ids)) | |
729 | return -ENODEV; | |
bebe4678 | 730 | |
835896a5 LB |
731 | max_zones = topology_max_packages() * topology_max_die_per_package(); |
732 | zone_devices = kcalloc(max_zones, sizeof(struct platform_device *), | |
71266846 | 733 | GFP_KERNEL); |
835896a5 | 734 | if (!zone_devices) |
71266846 TG |
735 | return -ENOMEM; |
736 | ||
bebe4678 RM |
737 | err = platform_driver_register(&coretemp_driver); |
738 | if (err) | |
e027a2de | 739 | goto outzone; |
bebe4678 | 740 | |
e00ca5df TG |
741 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online", |
742 | coretemp_cpu_online, coretemp_cpu_offline); | |
743 | if (err < 0) | |
2195c31b | 744 | goto outdrv; |
e00ca5df | 745 | coretemp_hp_online = err; |
bebe4678 RM |
746 | return 0; |
747 | ||
2195c31b | 748 | outdrv: |
bebe4678 | 749 | platform_driver_unregister(&coretemp_driver); |
e027a2de | 750 | outzone: |
835896a5 | 751 | kfree(zone_devices); |
bebe4678 RM |
752 | return err; |
753 | } | |
e00ca5df | 754 | module_init(coretemp_init) |
bebe4678 RM |
755 | |
756 | static void __exit coretemp_exit(void) | |
757 | { | |
e00ca5df | 758 | cpuhp_remove_state(coretemp_hp_online); |
bebe4678 | 759 | platform_driver_unregister(&coretemp_driver); |
835896a5 | 760 | kfree(zone_devices); |
bebe4678 | 761 | } |
e00ca5df | 762 | module_exit(coretemp_exit) |
bebe4678 RM |
763 | |
764 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
765 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
766 | MODULE_LICENSE("GPL"); |