Commit | Line | Data |
---|---|---|
bebe4678 RM |
1 | /* |
2 | * coretemp.c - Linux kernel module for hardware monitoring | |
3 | * | |
4 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
5 | * | |
6 | * Inspired from many hwmon drivers | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA. | |
21 | */ | |
22 | ||
f8bb8925 JP |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
24 | ||
bebe4678 | 25 | #include <linux/module.h> |
bebe4678 RM |
26 | #include <linux/init.h> |
27 | #include <linux/slab.h> | |
28 | #include <linux/jiffies.h> | |
29 | #include <linux/hwmon.h> | |
30 | #include <linux/sysfs.h> | |
31 | #include <linux/hwmon-sysfs.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/mutex.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/cpu.h> | |
4cc45275 | 37 | #include <linux/smp.h> |
a45a8c85 | 38 | #include <linux/moduleparam.h> |
14513ee6 | 39 | #include <linux/pci.h> |
bebe4678 RM |
40 | #include <asm/msr.h> |
41 | #include <asm/processor.h> | |
9b38096f | 42 | #include <asm/cpu_device_id.h> |
bebe4678 RM |
43 | |
44 | #define DRVNAME "coretemp" | |
45 | ||
a45a8c85 JD |
46 | /* |
47 | * force_tjmax only matters when TjMax can't be read from the CPU itself. | |
48 | * When set, it replaces the driver's suboptimal heuristic. | |
49 | */ | |
50 | static int force_tjmax; | |
51 | module_param_named(tjmax, force_tjmax, int, 0444); | |
52 | MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); | |
53 | ||
723f5734 | 54 | #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ |
199e0de7 | 55 | #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ |
cc904f9c | 56 | #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ |
3f9aec76 | 57 | #define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ |
c814a4c7 | 58 | #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ |
f4af6fd6 | 59 | #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) |
199e0de7 D |
60 | #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) |
61 | ||
780affe0 | 62 | #define TO_CORE_ID(cpu) (cpu_data(cpu).cpu_core_id) |
141168c3 KW |
63 | #define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO) |
64 | ||
65 | #ifdef CONFIG_SMP | |
19a34eea BG |
66 | #define for_each_sibling(i, cpu) \ |
67 | for_each_cpu(i, topology_sibling_cpumask(cpu)) | |
199e0de7 | 68 | #else |
bb74e8ca | 69 | #define for_each_sibling(i, cpu) for (i = 0; false; ) |
199e0de7 | 70 | #endif |
bebe4678 RM |
71 | |
72 | /* | |
199e0de7 D |
73 | * Per-Core Temperature Data |
74 | * @last_updated: The time when the current temperature value was updated | |
75 | * earlier (in jiffies). | |
76 | * @cpu_core_id: The CPU Core from which temperature values should be read | |
77 | * This value is passed as "id" field to rdmsr/wrmsr functions. | |
78 | * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS, | |
79 | * from where the temperature values should be read. | |
c814a4c7 | 80 | * @attr_size: Total number of pre-core attrs displayed in the sysfs. |
199e0de7 D |
81 | * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data. |
82 | * Otherwise, temp_data holds coretemp data. | |
83 | * @valid: If this is 1, the current temperature is valid. | |
bebe4678 | 84 | */ |
199e0de7 | 85 | struct temp_data { |
bebe4678 | 86 | int temp; |
6369a288 | 87 | int ttarget; |
199e0de7 D |
88 | int tjmax; |
89 | unsigned long last_updated; | |
90 | unsigned int cpu; | |
91 | u32 cpu_core_id; | |
92 | u32 status_reg; | |
c814a4c7 | 93 | int attr_size; |
199e0de7 D |
94 | bool is_pkg_data; |
95 | bool valid; | |
c814a4c7 D |
96 | struct sensor_device_attribute sd_attrs[TOTAL_ATTRS]; |
97 | char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH]; | |
1075305d GR |
98 | struct attribute *attrs[TOTAL_ATTRS + 1]; |
99 | struct attribute_group attr_group; | |
199e0de7 | 100 | struct mutex update_lock; |
bebe4678 RM |
101 | }; |
102 | ||
199e0de7 D |
103 | /* Platform Data per Physical CPU */ |
104 | struct platform_data { | |
e1b370b6 | 105 | struct device *hwmon_dev; |
71266846 | 106 | u16 pkg_id; |
e1b370b6 TG |
107 | struct cpumask cpumask; |
108 | struct temp_data *core_data[MAX_CORE_DATA]; | |
199e0de7 D |
109 | struct device_attribute name_attr; |
110 | }; | |
bebe4678 | 111 | |
71266846 TG |
112 | /* Keep track of how many package pointers we allocated in init() */ |
113 | static int max_packages __read_mostly; | |
114 | /* Array of package pointers. Serialized by cpu hotplug lock */ | |
115 | static struct platform_device **pkg_devices; | |
199e0de7 | 116 | |
199e0de7 D |
117 | static ssize_t show_label(struct device *dev, |
118 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 119 | { |
bebe4678 | 120 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
199e0de7 D |
121 | struct platform_data *pdata = dev_get_drvdata(dev); |
122 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
123 | ||
124 | if (tdata->is_pkg_data) | |
71266846 | 125 | return sprintf(buf, "Package id %u\n", pdata->pkg_id); |
bebe4678 | 126 | |
199e0de7 | 127 | return sprintf(buf, "Core %u\n", tdata->cpu_core_id); |
bebe4678 RM |
128 | } |
129 | ||
199e0de7 D |
130 | static ssize_t show_crit_alarm(struct device *dev, |
131 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 132 | { |
199e0de7 D |
133 | u32 eax, edx; |
134 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
135 | struct platform_data *pdata = dev_get_drvdata(dev); | |
136 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
137 | ||
723f5734 | 138 | mutex_lock(&tdata->update_lock); |
199e0de7 | 139 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); |
723f5734 | 140 | mutex_unlock(&tdata->update_lock); |
199e0de7 D |
141 | |
142 | return sprintf(buf, "%d\n", (eax >> 5) & 1); | |
bebe4678 RM |
143 | } |
144 | ||
199e0de7 D |
145 | static ssize_t show_tjmax(struct device *dev, |
146 | struct device_attribute *devattr, char *buf) | |
bebe4678 RM |
147 | { |
148 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
199e0de7 | 149 | struct platform_data *pdata = dev_get_drvdata(dev); |
bebe4678 | 150 | |
199e0de7 | 151 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tjmax); |
bebe4678 RM |
152 | } |
153 | ||
199e0de7 D |
154 | static ssize_t show_ttarget(struct device *dev, |
155 | struct device_attribute *devattr, char *buf) | |
156 | { | |
157 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
158 | struct platform_data *pdata = dev_get_drvdata(dev); | |
bebe4678 | 159 | |
199e0de7 D |
160 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget); |
161 | } | |
bebe4678 | 162 | |
199e0de7 D |
163 | static ssize_t show_temp(struct device *dev, |
164 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 165 | { |
199e0de7 D |
166 | u32 eax, edx; |
167 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
168 | struct platform_data *pdata = dev_get_drvdata(dev); | |
169 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
bebe4678 | 170 | |
199e0de7 | 171 | mutex_lock(&tdata->update_lock); |
bebe4678 | 172 | |
199e0de7 D |
173 | /* Check whether the time interval has elapsed */ |
174 | if (!tdata->valid || time_after(jiffies, tdata->last_updated + HZ)) { | |
175 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
bf6ea084 GR |
176 | /* |
177 | * Ignore the valid bit. In all observed cases the register | |
178 | * value is either low or zero if the valid bit is 0. | |
179 | * Return it instead of reporting an error which doesn't | |
180 | * really help at all. | |
181 | */ | |
182 | tdata->temp = tdata->tjmax - ((eax >> 16) & 0x7f) * 1000; | |
183 | tdata->valid = 1; | |
199e0de7 | 184 | tdata->last_updated = jiffies; |
bebe4678 RM |
185 | } |
186 | ||
199e0de7 | 187 | mutex_unlock(&tdata->update_lock); |
bf6ea084 | 188 | return sprintf(buf, "%d\n", tdata->temp); |
bebe4678 RM |
189 | } |
190 | ||
14513ee6 GR |
191 | struct tjmax_pci { |
192 | unsigned int device; | |
193 | int tjmax; | |
194 | }; | |
195 | ||
196 | static const struct tjmax_pci tjmax_pci_table[] = { | |
347c16cf | 197 | { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */ |
14513ee6 GR |
198 | { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */ |
199 | { 0x0c73, 95000 }, /* Atom S1220 (Centerton) */ | |
200 | { 0x0c75, 95000 }, /* Atom S1260 (Centerton) */ | |
201 | }; | |
202 | ||
41e58a1f GR |
203 | struct tjmax { |
204 | char const *id; | |
205 | int tjmax; | |
206 | }; | |
207 | ||
d23e2ae1 | 208 | static const struct tjmax tjmax_table[] = { |
1102dcab GR |
209 | { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */ |
210 | { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */ | |
41e58a1f GR |
211 | }; |
212 | ||
2fa5222e GR |
213 | struct tjmax_model { |
214 | u8 model; | |
215 | u8 mask; | |
216 | int tjmax; | |
217 | }; | |
218 | ||
219 | #define ANY 0xff | |
220 | ||
d23e2ae1 | 221 | static const struct tjmax_model tjmax_model_table[] = { |
9e3970fb | 222 | { 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */ |
2fa5222e GR |
223 | { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others |
224 | * Note: Also matches 230 and 330, | |
225 | * which are covered by tjmax_table | |
226 | */ | |
227 | { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx) | |
228 | * Note: TjMax for E6xxT is 110C, but CPU type | |
229 | * is undetectable by software | |
230 | */ | |
231 | { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */ | |
14513ee6 GR |
232 | { 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */ |
233 | { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) | |
234 | * Also matches S12x0 (stepping 9), covered by | |
235 | * PCI table | |
236 | */ | |
2fa5222e GR |
237 | }; |
238 | ||
d23e2ae1 | 239 | static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
118a8871 RM |
240 | { |
241 | /* The 100C is default for both mobile and non mobile CPUs */ | |
242 | ||
243 | int tjmax = 100000; | |
eccfed42 | 244 | int tjmax_ee = 85000; |
708a62bc | 245 | int usemsr_ee = 1; |
118a8871 RM |
246 | int err; |
247 | u32 eax, edx; | |
41e58a1f | 248 | int i; |
14513ee6 GR |
249 | struct pci_dev *host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
250 | ||
251 | /* | |
252 | * Explicit tjmax table entries override heuristics. | |
253 | * First try PCI host bridge IDs, followed by model ID strings | |
254 | * and model/stepping information. | |
255 | */ | |
256 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
257 | for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) { | |
258 | if (host_bridge->device == tjmax_pci_table[i].device) | |
259 | return tjmax_pci_table[i].tjmax; | |
260 | } | |
261 | } | |
41e58a1f | 262 | |
41e58a1f GR |
263 | for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) { |
264 | if (strstr(c->x86_model_id, tjmax_table[i].id)) | |
265 | return tjmax_table[i].tjmax; | |
266 | } | |
118a8871 | 267 | |
2fa5222e GR |
268 | for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { |
269 | const struct tjmax_model *tm = &tjmax_model_table[i]; | |
270 | if (c->x86_model == tm->model && | |
271 | (tm->mask == ANY || c->x86_mask == tm->mask)) | |
272 | return tm->tjmax; | |
72cbdddc | 273 | } |
1fe63ab4 | 274 | |
72cbdddc | 275 | /* Early chips have no MSR for TjMax */ |
1fe63ab4 | 276 | |
72cbdddc | 277 | if (c->x86_model == 0xf && c->x86_mask < 4) |
5592906f | 278 | usemsr_ee = 0; |
708a62bc | 279 | |
4cc45275 | 280 | if (c->x86_model > 0xe && usemsr_ee) { |
eccfed42 | 281 | u8 platform_id; |
118a8871 | 282 | |
4cc45275 GR |
283 | /* |
284 | * Now we can detect the mobile CPU using Intel provided table | |
285 | * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
286 | * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
287 | */ | |
118a8871 RM |
288 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); |
289 | if (err) { | |
290 | dev_warn(dev, | |
291 | "Unable to access MSR 0x17, assuming desktop" | |
292 | " CPU\n"); | |
708a62bc | 293 | usemsr_ee = 0; |
eccfed42 | 294 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
4cc45275 GR |
295 | /* |
296 | * Trust bit 28 up to Penryn, I could not find any | |
297 | * documentation on that; if you happen to know | |
298 | * someone at Intel please ask | |
299 | */ | |
708a62bc | 300 | usemsr_ee = 0; |
eccfed42 RM |
301 | } else { |
302 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
303 | platform_id = (edx >> 18) & 0x7; | |
304 | ||
4cc45275 GR |
305 | /* |
306 | * Mobile Penryn CPU seems to be platform ID 7 or 5 | |
307 | * (guesswork) | |
308 | */ | |
309 | if (c->x86_model == 0x17 && | |
310 | (platform_id == 5 || platform_id == 7)) { | |
311 | /* | |
312 | * If MSR EE bit is set, set it to 90 degrees C, | |
313 | * otherwise 105 degrees C | |
314 | */ | |
eccfed42 RM |
315 | tjmax_ee = 90000; |
316 | tjmax = 105000; | |
317 | } | |
118a8871 RM |
318 | } |
319 | } | |
320 | ||
708a62bc | 321 | if (usemsr_ee) { |
118a8871 RM |
322 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); |
323 | if (err) { | |
324 | dev_warn(dev, | |
325 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 326 | " at default\n"); |
118a8871 | 327 | } else if (eax & 0x40000000) { |
eccfed42 | 328 | tjmax = tjmax_ee; |
118a8871 | 329 | } |
708a62bc | 330 | } else if (tjmax == 100000) { |
4cc45275 GR |
331 | /* |
332 | * If we don't use msr EE it means we are desktop CPU | |
333 | * (with exeception of Atom) | |
334 | */ | |
118a8871 RM |
335 | dev_warn(dev, "Using relative temperature scale!\n"); |
336 | } | |
337 | ||
338 | return tjmax; | |
339 | } | |
340 | ||
1c2faa22 GR |
341 | static bool cpu_has_tjmax(struct cpuinfo_x86 *c) |
342 | { | |
343 | u8 model = c->x86_model; | |
344 | ||
345 | return model > 0xe && | |
346 | model != 0x1c && | |
347 | model != 0x26 && | |
348 | model != 0x27 && | |
349 | model != 0x35 && | |
350 | model != 0x36; | |
351 | } | |
352 | ||
d23e2ae1 | 353 | static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
a321cedb | 354 | { |
a321cedb CE |
355 | int err; |
356 | u32 eax, edx; | |
357 | u32 val; | |
358 | ||
4cc45275 GR |
359 | /* |
360 | * A new feature of current Intel(R) processors, the | |
361 | * IA32_TEMPERATURE_TARGET contains the TjMax value | |
362 | */ | |
a321cedb CE |
363 | err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
364 | if (err) { | |
1c2faa22 | 365 | if (cpu_has_tjmax(c)) |
6bf9e9b0 | 366 | dev_warn(dev, "Unable to read TjMax from CPU %u\n", id); |
a321cedb | 367 | } else { |
c0940e95 | 368 | val = (eax >> 16) & 0xff; |
a321cedb CE |
369 | /* |
370 | * If the TjMax is not plausible, an assumption | |
371 | * will be used | |
372 | */ | |
c0940e95 | 373 | if (val) { |
6bf9e9b0 | 374 | dev_dbg(dev, "TjMax is %d degrees C\n", val); |
a321cedb CE |
375 | return val * 1000; |
376 | } | |
377 | } | |
378 | ||
a45a8c85 JD |
379 | if (force_tjmax) { |
380 | dev_notice(dev, "TjMax forced to %d degrees C by user\n", | |
381 | force_tjmax); | |
382 | return force_tjmax * 1000; | |
383 | } | |
384 | ||
a321cedb CE |
385 | /* |
386 | * An assumption is made for early CPUs and unreadable MSR. | |
4f5f71a7 | 387 | * NOTE: the calculated value may not be correct. |
a321cedb | 388 | */ |
4f5f71a7 | 389 | return adjust_tjmax(c, id, dev); |
a321cedb CE |
390 | } |
391 | ||
d23e2ae1 PG |
392 | static int create_core_attrs(struct temp_data *tdata, struct device *dev, |
393 | int attr_no) | |
199e0de7 | 394 | { |
1075305d | 395 | int i; |
e3204ed3 | 396 | static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev, |
199e0de7 | 397 | struct device_attribute *devattr, char *buf) = { |
c814a4c7 | 398 | show_label, show_crit_alarm, show_temp, show_tjmax, |
f4af6fd6 | 399 | show_ttarget }; |
1055b5f9 RV |
400 | static const char *const suffixes[TOTAL_ATTRS] = { |
401 | "label", "crit_alarm", "input", "crit", "max" | |
402 | }; | |
199e0de7 | 403 | |
c814a4c7 | 404 | for (i = 0; i < tdata->attr_size; i++) { |
1055b5f9 RV |
405 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, |
406 | "temp%d_%s", attr_no, suffixes[i]); | |
4258781a | 407 | sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr); |
199e0de7 D |
408 | tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i]; |
409 | tdata->sd_attrs[i].dev_attr.attr.mode = S_IRUGO; | |
410 | tdata->sd_attrs[i].dev_attr.show = rd_ptr[i]; | |
199e0de7 | 411 | tdata->sd_attrs[i].index = attr_no; |
1075305d | 412 | tdata->attrs[i] = &tdata->sd_attrs[i].dev_attr.attr; |
bebe4678 | 413 | } |
1075305d GR |
414 | tdata->attr_group.attrs = tdata->attrs; |
415 | return sysfs_create_group(&dev->kobj, &tdata->attr_group); | |
199e0de7 D |
416 | } |
417 | ||
199e0de7 | 418 | |
d23e2ae1 | 419 | static int chk_ucode_version(unsigned int cpu) |
199e0de7 | 420 | { |
0eb9782a | 421 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
67f363b1 | 422 | |
199e0de7 D |
423 | /* |
424 | * Check if we have problem with errata AE18 of Core processors: | |
425 | * Readings might stop update when processor visited too deep sleep, | |
426 | * fixed for stepping D0 (6EC). | |
427 | */ | |
ca8bc8dc | 428 | if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) { |
b55f3757 | 429 | pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); |
ca8bc8dc | 430 | return -ENODEV; |
67f363b1 | 431 | } |
199e0de7 D |
432 | return 0; |
433 | } | |
434 | ||
d23e2ae1 | 435 | static struct platform_device *coretemp_get_pdev(unsigned int cpu) |
199e0de7 | 436 | { |
71266846 | 437 | int pkgid = topology_logical_package_id(cpu); |
199e0de7 | 438 | |
71266846 TG |
439 | if (pkgid >= 0 && pkgid < max_packages) |
440 | return pkg_devices[pkgid]; | |
199e0de7 D |
441 | return NULL; |
442 | } | |
443 | ||
d23e2ae1 | 444 | static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag) |
199e0de7 D |
445 | { |
446 | struct temp_data *tdata; | |
447 | ||
448 | tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL); | |
449 | if (!tdata) | |
450 | return NULL; | |
451 | ||
452 | tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS : | |
453 | MSR_IA32_THERM_STATUS; | |
454 | tdata->is_pkg_data = pkg_flag; | |
455 | tdata->cpu = cpu; | |
456 | tdata->cpu_core_id = TO_CORE_ID(cpu); | |
c814a4c7 | 457 | tdata->attr_size = MAX_CORE_ATTRS; |
199e0de7 D |
458 | mutex_init(&tdata->update_lock); |
459 | return tdata; | |
460 | } | |
67f363b1 | 461 | |
d23e2ae1 PG |
462 | static int create_core_data(struct platform_device *pdev, unsigned int cpu, |
463 | int pkg_flag) | |
199e0de7 D |
464 | { |
465 | struct temp_data *tdata; | |
2f1c3db0 | 466 | struct platform_data *pdata = platform_get_drvdata(pdev); |
199e0de7 D |
467 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
468 | u32 eax, edx; | |
469 | int err, attr_no; | |
bebe4678 | 470 | |
a321cedb | 471 | /* |
199e0de7 D |
472 | * Find attr number for sysfs: |
473 | * We map the attr number to core id of the CPU | |
474 | * The attr number is always core id + 2 | |
475 | * The Pkgtemp will always show up as temp1_*, if available | |
a321cedb | 476 | */ |
723f5734 | 477 | attr_no = pkg_flag ? PKG_SYSFS_ATTR_NO : TO_ATTR_NO(cpu); |
6369a288 | 478 | |
199e0de7 D |
479 | if (attr_no > MAX_CORE_DATA - 1) |
480 | return -ERANGE; | |
481 | ||
199e0de7 D |
482 | tdata = init_temp_data(cpu, pkg_flag); |
483 | if (!tdata) | |
484 | return -ENOMEM; | |
bebe4678 | 485 | |
199e0de7 D |
486 | /* Test if we can access the status register */ |
487 | err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); | |
488 | if (err) | |
489 | goto exit_free; | |
490 | ||
491 | /* We can access status register. Get Critical Temperature */ | |
6bf9e9b0 | 492 | tdata->tjmax = get_tjmax(c, cpu, &pdev->dev); |
199e0de7 | 493 | |
c814a4c7 | 494 | /* |
f4af6fd6 GR |
495 | * Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. |
496 | * The target temperature is available on older CPUs but not in this | |
497 | * register. Atoms don't have the register at all. | |
c814a4c7 | 498 | */ |
f4af6fd6 GR |
499 | if (c->x86_model > 0xe && c->x86_model != 0x1c) { |
500 | err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, | |
501 | &eax, &edx); | |
502 | if (!err) { | |
503 | tdata->ttarget | |
504 | = tdata->tjmax - ((eax >> 8) & 0xff) * 1000; | |
505 | tdata->attr_size++; | |
506 | } | |
c814a4c7 D |
507 | } |
508 | ||
199e0de7 D |
509 | pdata->core_data[attr_no] = tdata; |
510 | ||
511 | /* Create sysfs interfaces */ | |
d72d19c2 | 512 | err = create_core_attrs(tdata, pdata->hwmon_dev, attr_no); |
199e0de7 D |
513 | if (err) |
514 | goto exit_free; | |
bebe4678 RM |
515 | |
516 | return 0; | |
199e0de7 | 517 | exit_free: |
20ecb499 | 518 | pdata->core_data[attr_no] = NULL; |
199e0de7 D |
519 | kfree(tdata); |
520 | return err; | |
521 | } | |
522 | ||
4b138cf7 TG |
523 | static void |
524 | coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag) | |
199e0de7 | 525 | { |
4b138cf7 | 526 | if (create_core_data(pdev, cpu, pkg_flag)) |
199e0de7 D |
527 | dev_err(&pdev->dev, "Adding Core %u failed\n", cpu); |
528 | } | |
529 | ||
4b138cf7 | 530 | static void coretemp_remove_core(struct platform_data *pdata, int indx) |
199e0de7 | 531 | { |
199e0de7 D |
532 | struct temp_data *tdata = pdata->core_data[indx]; |
533 | ||
534 | /* Remove the sysfs attributes */ | |
d72d19c2 | 535 | sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group); |
199e0de7 D |
536 | |
537 | kfree(pdata->core_data[indx]); | |
538 | pdata->core_data[indx] = NULL; | |
539 | } | |
540 | ||
6c931ae1 | 541 | static int coretemp_probe(struct platform_device *pdev) |
199e0de7 | 542 | { |
c503a811 | 543 | struct device *dev = &pdev->dev; |
199e0de7 | 544 | struct platform_data *pdata; |
bebe4678 | 545 | |
199e0de7 | 546 | /* Initialize the per-package data structures */ |
c503a811 | 547 | pdata = devm_kzalloc(dev, sizeof(struct platform_data), GFP_KERNEL); |
199e0de7 D |
548 | if (!pdata) |
549 | return -ENOMEM; | |
550 | ||
71266846 | 551 | pdata->pkg_id = pdev->id; |
199e0de7 D |
552 | platform_set_drvdata(pdev, pdata); |
553 | ||
d72d19c2 GR |
554 | pdata->hwmon_dev = devm_hwmon_device_register_with_groups(dev, DRVNAME, |
555 | pdata, NULL); | |
556 | return PTR_ERR_OR_ZERO(pdata->hwmon_dev); | |
bebe4678 RM |
557 | } |
558 | ||
281dfd0b | 559 | static int coretemp_remove(struct platform_device *pdev) |
bebe4678 | 560 | { |
199e0de7 D |
561 | struct platform_data *pdata = platform_get_drvdata(pdev); |
562 | int i; | |
bebe4678 | 563 | |
199e0de7 D |
564 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) |
565 | if (pdata->core_data[i]) | |
d72d19c2 | 566 | coretemp_remove_core(pdata, i); |
199e0de7 | 567 | |
bebe4678 RM |
568 | return 0; |
569 | } | |
570 | ||
571 | static struct platform_driver coretemp_driver = { | |
572 | .driver = { | |
bebe4678 RM |
573 | .name = DRVNAME, |
574 | }, | |
575 | .probe = coretemp_probe, | |
9e5e9b7a | 576 | .remove = coretemp_remove, |
bebe4678 RM |
577 | }; |
578 | ||
71266846 | 579 | static struct platform_device *coretemp_device_add(unsigned int cpu) |
bebe4678 | 580 | { |
71266846 | 581 | int err, pkgid = topology_logical_package_id(cpu); |
bebe4678 | 582 | struct platform_device *pdev; |
d883b9f0 | 583 | |
71266846 TG |
584 | if (pkgid < 0) |
585 | return ERR_PTR(-ENOMEM); | |
d883b9f0 | 586 | |
71266846 TG |
587 | pdev = platform_device_alloc(DRVNAME, pkgid); |
588 | if (!pdev) | |
589 | return ERR_PTR(-ENOMEM); | |
bebe4678 RM |
590 | |
591 | err = platform_device_add(pdev); | |
592 | if (err) { | |
71266846 TG |
593 | platform_device_put(pdev); |
594 | return ERR_PTR(err); | |
bebe4678 RM |
595 | } |
596 | ||
71266846 TG |
597 | pkg_devices[pkgid] = pdev; |
598 | return pdev; | |
bebe4678 RM |
599 | } |
600 | ||
e00ca5df | 601 | static int coretemp_cpu_online(unsigned int cpu) |
199e0de7 | 602 | { |
199e0de7 | 603 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 TG |
604 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
605 | struct platform_data *pdata; | |
199e0de7 D |
606 | |
607 | /* | |
608 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
609 | * sensors. We check this bit only, all the early CPUs | |
610 | * without thermal sensors will be filtered out. | |
611 | */ | |
4ad33411 | 612 | if (!cpu_has(c, X86_FEATURE_DTHERM)) |
2195c31b | 613 | return -ENODEV; |
199e0de7 D |
614 | |
615 | if (!pdev) { | |
0eb9782a JD |
616 | /* Check the microcode version of the CPU */ |
617 | if (chk_ucode_version(cpu)) | |
2195c31b | 618 | return -EINVAL; |
0eb9782a | 619 | |
199e0de7 D |
620 | /* |
621 | * Alright, we have DTS support. | |
622 | * We are bringing the _first_ core in this pkg | |
623 | * online. So, initialize per-pkg data structures and | |
624 | * then bring this core online. | |
625 | */ | |
71266846 TG |
626 | pdev = coretemp_device_add(cpu); |
627 | if (IS_ERR(pdev)) | |
628 | return PTR_ERR(pdev); | |
e1b370b6 | 629 | |
199e0de7 D |
630 | /* |
631 | * Check whether pkgtemp support is available. | |
632 | * If so, add interfaces for pkgtemp. | |
633 | */ | |
634 | if (cpu_has(c, X86_FEATURE_PTS)) | |
4b138cf7 | 635 | coretemp_add_core(pdev, cpu, 1); |
199e0de7 | 636 | } |
e1b370b6 TG |
637 | |
638 | pdata = platform_get_drvdata(pdev); | |
199e0de7 | 639 | /* |
e1b370b6 TG |
640 | * Check whether a thread sibling is already online. If not add the |
641 | * interface for this CPU core. | |
199e0de7 | 642 | */ |
e1b370b6 | 643 | if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu))) |
4b138cf7 | 644 | coretemp_add_core(pdev, cpu, 0); |
e1b370b6 TG |
645 | |
646 | cpumask_set_cpu(cpu, &pdata->cpumask); | |
e00ca5df | 647 | return 0; |
199e0de7 D |
648 | } |
649 | ||
e00ca5df | 650 | static int coretemp_cpu_offline(unsigned int cpu) |
199e0de7 | 651 | { |
199e0de7 | 652 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 | 653 | struct platform_data *pd; |
723f5734 | 654 | struct temp_data *tdata; |
e1b370b6 | 655 | int indx, target; |
199e0de7 D |
656 | |
657 | /* If the physical CPU device does not exist, just return */ | |
658 | if (!pdev) | |
e00ca5df | 659 | return 0; |
199e0de7 | 660 | |
b7048711 | 661 | /* The core id is too big, just return */ |
e1b370b6 | 662 | indx = TO_ATTR_NO(cpu); |
b7048711 | 663 | if (indx > MAX_CORE_DATA - 1) |
e00ca5df | 664 | return 0; |
b7048711 | 665 | |
e1b370b6 TG |
666 | pd = platform_get_drvdata(pdev); |
667 | tdata = pd->core_data[indx]; | |
668 | ||
669 | cpumask_clear_cpu(cpu, &pd->cpumask); | |
199e0de7 | 670 | |
f4e0bcf0 | 671 | /* |
e1b370b6 TG |
672 | * If this is the last thread sibling, remove the CPU core |
673 | * interface, If there is still a sibling online, transfer the | |
674 | * target cpu of that core interface to it. | |
f4e0bcf0 | 675 | */ |
e1b370b6 TG |
676 | target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu)); |
677 | if (target >= nr_cpu_ids) { | |
678 | coretemp_remove_core(pd, indx); | |
679 | } else if (tdata && tdata->cpu == cpu) { | |
680 | mutex_lock(&tdata->update_lock); | |
681 | tdata->cpu = target; | |
682 | mutex_unlock(&tdata->update_lock); | |
199e0de7 | 683 | } |
e1b370b6 | 684 | |
199e0de7 | 685 | /* |
71266846 TG |
686 | * If all cores in this pkg are offline, remove the device. This |
687 | * will invoke the platform driver remove function, which cleans up | |
688 | * the rest. | |
199e0de7 | 689 | */ |
e1b370b6 | 690 | if (cpumask_empty(&pd->cpumask)) { |
71266846 TG |
691 | pkg_devices[topology_logical_package_id(cpu)] = NULL; |
692 | platform_device_unregister(pdev); | |
e00ca5df | 693 | return 0; |
723f5734 | 694 | } |
71266846 | 695 | |
723f5734 TG |
696 | /* |
697 | * Check whether this core is the target for the package | |
698 | * interface. We need to assign it to some other cpu. | |
699 | */ | |
e1b370b6 | 700 | tdata = pd->core_data[PKG_SYSFS_ATTR_NO]; |
723f5734 | 701 | if (tdata && tdata->cpu == cpu) { |
e1b370b6 | 702 | target = cpumask_first(&pd->cpumask); |
723f5734 TG |
703 | mutex_lock(&tdata->update_lock); |
704 | tdata->cpu = target; | |
705 | mutex_unlock(&tdata->update_lock); | |
706 | } | |
e00ca5df | 707 | return 0; |
199e0de7 | 708 | } |
e273bd98 | 709 | static const struct x86_cpu_id __initconst coretemp_ids[] = { |
4ad33411 | 710 | { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, X86_FEATURE_DTHERM }, |
9b38096f AK |
711 | {} |
712 | }; | |
713 | MODULE_DEVICE_TABLE(x86cpu, coretemp_ids); | |
714 | ||
e00ca5df TG |
715 | static enum cpuhp_state coretemp_hp_online; |
716 | ||
bebe4678 RM |
717 | static int __init coretemp_init(void) |
718 | { | |
e00ca5df | 719 | int err; |
bebe4678 | 720 | |
9b38096f AK |
721 | /* |
722 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
723 | * sensors. We check this bit only, all the early CPUs | |
724 | * without thermal sensors will be filtered out. | |
725 | */ | |
726 | if (!x86_match_cpu(coretemp_ids)) | |
727 | return -ENODEV; | |
bebe4678 | 728 | |
71266846 TG |
729 | max_packages = topology_max_packages(); |
730 | pkg_devices = kzalloc(max_packages * sizeof(struct platform_device *), | |
731 | GFP_KERNEL); | |
732 | if (!pkg_devices) | |
733 | return -ENOMEM; | |
734 | ||
bebe4678 RM |
735 | err = platform_driver_register(&coretemp_driver); |
736 | if (err) | |
e00ca5df | 737 | return err; |
bebe4678 | 738 | |
e00ca5df TG |
739 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online", |
740 | coretemp_cpu_online, coretemp_cpu_offline); | |
741 | if (err < 0) | |
2195c31b | 742 | goto outdrv; |
e00ca5df | 743 | coretemp_hp_online = err; |
bebe4678 RM |
744 | return 0; |
745 | ||
2195c31b | 746 | outdrv: |
bebe4678 | 747 | platform_driver_unregister(&coretemp_driver); |
71266846 | 748 | kfree(pkg_devices); |
bebe4678 RM |
749 | return err; |
750 | } | |
e00ca5df | 751 | module_init(coretemp_init) |
bebe4678 RM |
752 | |
753 | static void __exit coretemp_exit(void) | |
754 | { | |
e00ca5df | 755 | cpuhp_remove_state(coretemp_hp_online); |
bebe4678 | 756 | platform_driver_unregister(&coretemp_driver); |
71266846 | 757 | kfree(pkg_devices); |
bebe4678 | 758 | } |
e00ca5df | 759 | module_exit(coretemp_exit) |
bebe4678 RM |
760 | |
761 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
762 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
763 | MODULE_LICENSE("GPL"); |