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2d7a548a JRN |
1 | /* |
2 | * Copyright (c) 2016 Google, Inc | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 or later as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
54b943e6 | 10 | #include <linux/delay.h> |
7ed1c5e5 | 11 | #include <linux/errno.h> |
2d7a548a | 12 | #include <linux/gpio/consumer.h> |
2d7a548a JRN |
13 | #include <linux/hwmon.h> |
14 | #include <linux/hwmon-sysfs.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
2d7a548a | 18 | #include <linux/of_device.h> |
54b943e6 | 19 | #include <linux/of_platform.h> |
2d7a548a | 20 | #include <linux/platform_device.h> |
2d7a548a | 21 | #include <linux/regmap.h> |
18c514cc | 22 | #include <linux/reset.h> |
54b943e6 | 23 | #include <linux/sysfs.h> |
f198907d | 24 | #include <linux/thermal.h> |
2d7a548a JRN |
25 | |
26 | /* ASPEED PWM & FAN Tach Register Definition */ | |
27 | #define ASPEED_PTCR_CTRL 0x00 | |
28 | #define ASPEED_PTCR_CLK_CTRL 0x04 | |
29 | #define ASPEED_PTCR_DUTY0_CTRL 0x08 | |
30 | #define ASPEED_PTCR_DUTY1_CTRL 0x0c | |
31 | #define ASPEED_PTCR_TYPEM_CTRL 0x10 | |
32 | #define ASPEED_PTCR_TYPEM_CTRL1 0x14 | |
33 | #define ASPEED_PTCR_TYPEN_CTRL 0x18 | |
34 | #define ASPEED_PTCR_TYPEN_CTRL1 0x1c | |
35 | #define ASPEED_PTCR_TACH_SOURCE 0x20 | |
36 | #define ASPEED_PTCR_TRIGGER 0x28 | |
37 | #define ASPEED_PTCR_RESULT 0x2c | |
38 | #define ASPEED_PTCR_INTR_CTRL 0x30 | |
39 | #define ASPEED_PTCR_INTR_STS 0x34 | |
40 | #define ASPEED_PTCR_TYPEM_LIMIT 0x38 | |
41 | #define ASPEED_PTCR_TYPEN_LIMIT 0x3C | |
42 | #define ASPEED_PTCR_CTRL_EXT 0x40 | |
43 | #define ASPEED_PTCR_CLK_CTRL_EXT 0x44 | |
44 | #define ASPEED_PTCR_DUTY2_CTRL 0x48 | |
45 | #define ASPEED_PTCR_DUTY3_CTRL 0x4c | |
46 | #define ASPEED_PTCR_TYPEO_CTRL 0x50 | |
47 | #define ASPEED_PTCR_TYPEO_CTRL1 0x54 | |
48 | #define ASPEED_PTCR_TACH_SOURCE_EXT 0x60 | |
49 | #define ASPEED_PTCR_TYPEO_LIMIT 0x78 | |
50 | ||
51 | /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */ | |
52 | #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1 15 | |
53 | #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2 6 | |
54 | #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15)) | |
55 | ||
56 | #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1 14 | |
57 | #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2 5 | |
58 | #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14)) | |
59 | ||
60 | #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1 13 | |
61 | #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2 4 | |
62 | #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13)) | |
63 | ||
64 | #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1 12 | |
65 | #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2 3 | |
66 | #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12)) | |
67 | ||
68 | #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x)) | |
69 | ||
70 | #define ASPEED_PTCR_CTRL_PWMD_EN BIT(11) | |
71 | #define ASPEED_PTCR_CTRL_PWMC_EN BIT(10) | |
72 | #define ASPEED_PTCR_CTRL_PWMB_EN BIT(9) | |
73 | #define ASPEED_PTCR_CTRL_PWMA_EN BIT(8) | |
74 | ||
75 | #define ASPEED_PTCR_CTRL_CLK_SRC BIT(1) | |
76 | #define ASPEED_PTCR_CTRL_CLK_EN BIT(0) | |
77 | ||
78 | /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */ | |
79 | /* TYPE N */ | |
80 | #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16) | |
81 | #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT 24 | |
82 | #define ASPEED_PTCR_CLK_CTRL_TYPEN_H 20 | |
83 | #define ASPEED_PTCR_CLK_CTRL_TYPEN_L 16 | |
84 | /* TYPE M */ | |
85 | #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0) | |
86 | #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT 8 | |
87 | #define ASPEED_PTCR_CLK_CTRL_TYPEM_H 4 | |
88 | #define ASPEED_PTCR_CLK_CTRL_TYPEM_L 0 | |
89 | ||
90 | /* | |
91 | * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control | |
92 | * 0/1/2/3 register | |
93 | */ | |
94 | #define DUTY_CTRL_PWM2_FALL_POINT 24 | |
95 | #define DUTY_CTRL_PWM2_RISE_POINT 16 | |
96 | #define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16) | |
97 | #define DUTY_CTRL_PWM1_FALL_POINT 8 | |
98 | #define DUTY_CTRL_PWM1_RISE_POINT 0 | |
99 | #define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0) | |
100 | ||
101 | /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */ | |
102 | #define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16)) | |
103 | #define TYPE_CTRL_FAN1_MASK GENMASK(31, 0) | |
104 | #define TYPE_CTRL_FAN_PERIOD 16 | |
105 | #define TYPE_CTRL_FAN_MODE 4 | |
106 | #define TYPE_CTRL_FAN_DIVISION 1 | |
107 | #define TYPE_CTRL_FAN_TYPE_EN 1 | |
108 | ||
109 | /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */ | |
110 | /* bit [0,1] at 0x20, bit [2] at 0x60 */ | |
111 | #define TACH_PWM_SOURCE_BIT01(x) ((x) * 2) | |
112 | #define TACH_PWM_SOURCE_BIT2(x) ((x) * 2) | |
113 | #define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3 << ((x) * 2)) | |
114 | #define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2) | |
115 | ||
116 | /* ASPEED_PTCR_RESULT : 0x2c - Result Register */ | |
117 | #define RESULT_STATUS_MASK BIT(31) | |
118 | #define RESULT_VALUE_MASK 0xfffff | |
119 | ||
120 | /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */ | |
121 | #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1 15 | |
122 | #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2 6 | |
123 | #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15)) | |
124 | ||
125 | #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1 14 | |
126 | #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2 5 | |
127 | #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14)) | |
128 | ||
129 | #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1 13 | |
130 | #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2 4 | |
131 | #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13)) | |
132 | ||
133 | #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1 12 | |
134 | #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2 3 | |
135 | #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12)) | |
136 | ||
137 | #define ASPEED_PTCR_CTRL_PWMH_EN BIT(11) | |
138 | #define ASPEED_PTCR_CTRL_PWMG_EN BIT(10) | |
139 | #define ASPEED_PTCR_CTRL_PWMF_EN BIT(9) | |
140 | #define ASPEED_PTCR_CTRL_PWME_EN BIT(8) | |
141 | ||
142 | /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */ | |
143 | /* TYPE O */ | |
144 | #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0) | |
145 | #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT 8 | |
146 | #define ASPEED_PTCR_CLK_CTRL_TYPEO_H 4 | |
147 | #define ASPEED_PTCR_CLK_CTRL_TYPEO_L 0 | |
148 | ||
149 | #define PWM_MAX 255 | |
150 | ||
1e276292 PV |
151 | #define BOTH_EDGES 0x02 /* 10b */ |
152 | ||
2d7a548a JRN |
153 | #define M_PWM_DIV_H 0x00 |
154 | #define M_PWM_DIV_L 0x05 | |
155 | #define M_PWM_PERIOD 0x5F | |
156 | #define M_TACH_CLK_DIV 0x00 | |
1e276292 PV |
157 | /* |
158 | * 5:4 Type N fan tach mode selection bit: | |
159 | * 00: falling | |
160 | * 01: rising | |
161 | * 10: both | |
162 | * 11: reserved. | |
163 | */ | |
164 | #define M_TACH_MODE 0x02 /* 10b */ | |
762b1e88 | 165 | #define M_TACH_UNIT 0x0210 |
2d7a548a JRN |
166 | #define INIT_FAN_CTRL 0xFF |
167 | ||
44b41366 PV |
168 | /* How long we sleep in us while waiting for an RPM result. */ |
169 | #define ASPEED_RPM_STATUS_SLEEP_USEC 500 | |
170 | ||
f198907d MK |
171 | #define MAX_CDEV_NAME_LEN 16 |
172 | ||
173 | struct aspeed_cooling_device { | |
174 | char name[16]; | |
175 | struct aspeed_pwm_tacho_data *priv; | |
176 | struct thermal_cooling_device *tcdev; | |
177 | int pwm_port; | |
178 | u8 *cooling_levels; | |
179 | u8 max_state; | |
180 | u8 cur_state; | |
181 | }; | |
182 | ||
2d7a548a JRN |
183 | struct aspeed_pwm_tacho_data { |
184 | struct regmap *regmap; | |
18c514cc | 185 | struct reset_control *rst; |
2d7a548a JRN |
186 | unsigned long clk_freq; |
187 | bool pwm_present[8]; | |
188 | bool fan_tach_present[16]; | |
189 | u8 type_pwm_clock_unit[3]; | |
190 | u8 type_pwm_clock_division_h[3]; | |
191 | u8 type_pwm_clock_division_l[3]; | |
192 | u8 type_fan_tach_clock_division[3]; | |
1e276292 | 193 | u8 type_fan_tach_mode[3]; |
2d7a548a JRN |
194 | u16 type_fan_tach_unit[3]; |
195 | u8 pwm_port_type[8]; | |
196 | u8 pwm_port_fan_ctrl[8]; | |
197 | u8 fan_tach_ch_source[16]; | |
f198907d | 198 | struct aspeed_cooling_device *cdev[8]; |
2d7a548a JRN |
199 | const struct attribute_group *groups[3]; |
200 | }; | |
201 | ||
202 | enum type { TYPEM, TYPEN, TYPEO }; | |
203 | ||
204 | struct type_params { | |
205 | u32 l_value; | |
206 | u32 h_value; | |
207 | u32 unit_value; | |
208 | u32 clk_ctrl_mask; | |
209 | u32 clk_ctrl_reg; | |
210 | u32 ctrl_reg; | |
211 | u32 ctrl_reg1; | |
212 | }; | |
213 | ||
214 | static const struct type_params type_params[] = { | |
215 | [TYPEM] = { | |
216 | .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L, | |
217 | .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H, | |
218 | .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT, | |
219 | .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK, | |
220 | .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, | |
221 | .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL, | |
222 | .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1, | |
223 | }, | |
224 | [TYPEN] = { | |
225 | .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L, | |
226 | .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H, | |
227 | .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT, | |
228 | .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK, | |
229 | .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, | |
230 | .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL, | |
231 | .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1, | |
232 | }, | |
233 | [TYPEO] = { | |
234 | .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L, | |
235 | .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H, | |
236 | .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT, | |
237 | .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK, | |
238 | .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT, | |
239 | .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL, | |
240 | .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1, | |
241 | } | |
242 | }; | |
243 | ||
244 | enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH }; | |
245 | ||
246 | struct pwm_port_params { | |
247 | u32 pwm_en; | |
248 | u32 ctrl_reg; | |
249 | u32 type_part1; | |
250 | u32 type_part2; | |
251 | u32 type_mask; | |
252 | u32 duty_ctrl_rise_point; | |
253 | u32 duty_ctrl_fall_point; | |
254 | u32 duty_ctrl_reg; | |
255 | u32 duty_ctrl_rise_fall_mask; | |
256 | }; | |
257 | ||
258 | static const struct pwm_port_params pwm_port_params[] = { | |
259 | [PWMA] = { | |
260 | .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN, | |
261 | .ctrl_reg = ASPEED_PTCR_CTRL, | |
262 | .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1, | |
263 | .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2, | |
264 | .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK, | |
265 | .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, | |
266 | .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, | |
267 | .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, | |
268 | .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, | |
269 | }, | |
270 | [PWMB] = { | |
271 | .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN, | |
272 | .ctrl_reg = ASPEED_PTCR_CTRL, | |
273 | .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1, | |
274 | .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2, | |
275 | .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK, | |
276 | .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, | |
277 | .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, | |
278 | .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, | |
279 | .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, | |
280 | }, | |
281 | [PWMC] = { | |
282 | .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN, | |
283 | .ctrl_reg = ASPEED_PTCR_CTRL, | |
284 | .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1, | |
285 | .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2, | |
286 | .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK, | |
287 | .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, | |
288 | .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, | |
289 | .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, | |
290 | .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, | |
291 | }, | |
292 | [PWMD] = { | |
293 | .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN, | |
294 | .ctrl_reg = ASPEED_PTCR_CTRL, | |
295 | .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1, | |
296 | .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2, | |
297 | .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK, | |
298 | .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, | |
299 | .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, | |
300 | .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, | |
301 | .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, | |
302 | }, | |
303 | [PWME] = { | |
304 | .pwm_en = ASPEED_PTCR_CTRL_PWME_EN, | |
305 | .ctrl_reg = ASPEED_PTCR_CTRL_EXT, | |
306 | .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1, | |
307 | .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2, | |
308 | .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK, | |
309 | .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, | |
310 | .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, | |
311 | .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, | |
312 | .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, | |
313 | }, | |
314 | [PWMF] = { | |
315 | .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN, | |
316 | .ctrl_reg = ASPEED_PTCR_CTRL_EXT, | |
317 | .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1, | |
318 | .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2, | |
319 | .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK, | |
320 | .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, | |
321 | .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, | |
322 | .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, | |
323 | .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, | |
324 | }, | |
325 | [PWMG] = { | |
326 | .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN, | |
327 | .ctrl_reg = ASPEED_PTCR_CTRL_EXT, | |
328 | .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1, | |
329 | .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2, | |
330 | .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK, | |
331 | .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, | |
332 | .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, | |
333 | .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, | |
334 | .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, | |
335 | }, | |
336 | [PWMH] = { | |
337 | .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN, | |
338 | .ctrl_reg = ASPEED_PTCR_CTRL_EXT, | |
339 | .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1, | |
340 | .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2, | |
341 | .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK, | |
342 | .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, | |
343 | .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, | |
344 | .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, | |
345 | .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, | |
346 | } | |
347 | }; | |
348 | ||
349 | static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg, | |
350 | unsigned int val) | |
351 | { | |
352 | void __iomem *regs = (void __iomem *)context; | |
353 | ||
354 | writel(val, regs + reg); | |
355 | return 0; | |
356 | } | |
357 | ||
358 | static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg, | |
359 | unsigned int *val) | |
360 | { | |
361 | void __iomem *regs = (void __iomem *)context; | |
362 | ||
363 | *val = readl(regs + reg); | |
364 | return 0; | |
365 | } | |
366 | ||
367 | static const struct regmap_config aspeed_pwm_tacho_regmap_config = { | |
368 | .reg_bits = 32, | |
369 | .val_bits = 32, | |
370 | .reg_stride = 4, | |
371 | .max_register = ASPEED_PTCR_TYPEO_LIMIT, | |
372 | .reg_write = regmap_aspeed_pwm_tacho_reg_write, | |
373 | .reg_read = regmap_aspeed_pwm_tacho_reg_read, | |
374 | .fast_io = true, | |
375 | }; | |
376 | ||
377 | static void aspeed_set_clock_enable(struct regmap *regmap, bool val) | |
378 | { | |
379 | regmap_update_bits(regmap, ASPEED_PTCR_CTRL, | |
380 | ASPEED_PTCR_CTRL_CLK_EN, | |
381 | val ? ASPEED_PTCR_CTRL_CLK_EN : 0); | |
382 | } | |
383 | ||
384 | static void aspeed_set_clock_source(struct regmap *regmap, int val) | |
385 | { | |
386 | regmap_update_bits(regmap, ASPEED_PTCR_CTRL, | |
387 | ASPEED_PTCR_CTRL_CLK_SRC, | |
388 | val ? ASPEED_PTCR_CTRL_CLK_SRC : 0); | |
389 | } | |
390 | ||
391 | static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type, | |
392 | u8 div_high, u8 div_low, u8 unit) | |
393 | { | |
394 | u32 reg_value = ((div_high << type_params[type].h_value) | | |
395 | (div_low << type_params[type].l_value) | | |
396 | (unit << type_params[type].unit_value)); | |
397 | ||
398 | regmap_update_bits(regmap, type_params[type].clk_ctrl_reg, | |
399 | type_params[type].clk_ctrl_mask, reg_value); | |
400 | } | |
401 | ||
402 | static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port, | |
403 | bool enable) | |
404 | { | |
405 | regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, | |
406 | pwm_port_params[pwm_port].pwm_en, | |
407 | enable ? pwm_port_params[pwm_port].pwm_en : 0); | |
408 | } | |
409 | ||
410 | static void aspeed_set_pwm_port_type(struct regmap *regmap, | |
411 | u8 pwm_port, u8 type) | |
412 | { | |
413 | u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1; | |
414 | ||
415 | reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2; | |
416 | ||
417 | regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, | |
418 | pwm_port_params[pwm_port].type_mask, reg_value); | |
419 | } | |
420 | ||
421 | static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap, | |
422 | u8 pwm_port, u8 rising, | |
423 | u8 falling) | |
424 | { | |
425 | u32 reg_value = (rising << | |
426 | pwm_port_params[pwm_port].duty_ctrl_rise_point); | |
427 | reg_value |= (falling << | |
428 | pwm_port_params[pwm_port].duty_ctrl_fall_point); | |
429 | ||
430 | regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg, | |
431 | pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask, | |
432 | reg_value); | |
433 | } | |
434 | ||
435 | static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type, | |
436 | bool enable) | |
437 | { | |
438 | regmap_update_bits(regmap, type_params[type].ctrl_reg, | |
439 | TYPE_CTRL_FAN_TYPE_EN, | |
440 | enable ? TYPE_CTRL_FAN_TYPE_EN : 0); | |
441 | } | |
442 | ||
443 | static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type, | |
444 | u8 mode, u16 unit, u8 division) | |
445 | { | |
446 | u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) | | |
447 | (unit << TYPE_CTRL_FAN_PERIOD) | | |
448 | (division << TYPE_CTRL_FAN_DIVISION)); | |
449 | ||
450 | regmap_update_bits(regmap, type_params[type].ctrl_reg, | |
451 | TYPE_CTRL_FAN_MASK, reg_value); | |
452 | regmap_update_bits(regmap, type_params[type].ctrl_reg1, | |
453 | TYPE_CTRL_FAN1_MASK, unit << 16); | |
454 | } | |
455 | ||
456 | static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch, | |
457 | bool enable) | |
458 | { | |
459 | regmap_update_bits(regmap, ASPEED_PTCR_CTRL, | |
460 | ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch), | |
461 | enable ? | |
462 | ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0); | |
463 | } | |
464 | ||
465 | static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch, | |
466 | u8 fan_tach_ch_source) | |
467 | { | |
468 | u32 reg_value1 = ((fan_tach_ch_source & 0x3) << | |
469 | TACH_PWM_SOURCE_BIT01(fan_tach_ch)); | |
470 | u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) << | |
471 | TACH_PWM_SOURCE_BIT2(fan_tach_ch)); | |
472 | ||
473 | regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE, | |
474 | TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch), | |
475 | reg_value1); | |
476 | ||
477 | regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT, | |
478 | TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch), | |
479 | reg_value2); | |
480 | } | |
481 | ||
482 | static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv, | |
483 | u8 index, u8 fan_ctrl) | |
484 | { | |
485 | u16 period, dc_time_on; | |
486 | ||
487 | period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]]; | |
488 | period += 1; | |
489 | dc_time_on = (fan_ctrl * period) / PWM_MAX; | |
490 | ||
491 | if (dc_time_on == 0) { | |
492 | aspeed_set_pwm_port_enable(priv->regmap, index, false); | |
493 | } else { | |
494 | if (dc_time_on == period) | |
495 | dc_time_on = 0; | |
496 | ||
497 | aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0, | |
498 | dc_time_on); | |
499 | aspeed_set_pwm_port_enable(priv->regmap, index, true); | |
500 | } | |
501 | } | |
502 | ||
503 | static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data | |
504 | *priv, u8 type) | |
505 | { | |
506 | u32 clk; | |
507 | u16 tacho_unit; | |
508 | u8 clk_unit, div_h, div_l, tacho_div; | |
509 | ||
510 | clk = priv->clk_freq; | |
511 | clk_unit = priv->type_pwm_clock_unit[type]; | |
512 | div_h = priv->type_pwm_clock_division_h[type]; | |
513 | div_h = 0x1 << div_h; | |
514 | div_l = priv->type_pwm_clock_division_l[type]; | |
515 | if (div_l == 0) | |
516 | div_l = 1; | |
517 | else | |
518 | div_l = div_l * 2; | |
519 | ||
520 | tacho_unit = priv->type_fan_tach_unit[type]; | |
521 | tacho_div = priv->type_fan_tach_clock_division[type]; | |
522 | ||
523 | tacho_div = 0x4 << (tacho_div * 2); | |
524 | return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit); | |
525 | } | |
526 | ||
7ed1c5e5 | 527 | static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv, |
2d7a548a JRN |
528 | u8 fan_tach_ch) |
529 | { | |
44b41366 | 530 | u32 raw_data, tach_div, clk_source, msec, usec, val; |
1e276292 | 531 | u8 fan_tach_ch_source, type, mode, both; |
44b41366 | 532 | int ret; |
2d7a548a JRN |
533 | |
534 | regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0); | |
535 | regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch); | |
536 | ||
537 | fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch]; | |
538 | type = priv->pwm_port_type[fan_tach_ch_source]; | |
539 | ||
44b41366 PV |
540 | msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type)); |
541 | usec = msec * 1000; | |
542 | ||
543 | ret = regmap_read_poll_timeout( | |
544 | priv->regmap, | |
545 | ASPEED_PTCR_RESULT, | |
546 | val, | |
547 | (val & RESULT_STATUS_MASK), | |
548 | ASPEED_RPM_STATUS_SLEEP_USEC, | |
549 | usec); | |
2d7a548a | 550 | |
44b41366 PV |
551 | /* return -ETIMEDOUT if we didn't get an answer. */ |
552 | if (ret) | |
553 | return ret; | |
7ed1c5e5 | 554 | |
2d7a548a JRN |
555 | raw_data = val & RESULT_VALUE_MASK; |
556 | tach_div = priv->type_fan_tach_clock_division[type]; | |
1e276292 PV |
557 | /* |
558 | * We need the mode to determine if the raw_data is double (from | |
559 | * counting both edges). | |
560 | */ | |
561 | mode = priv->type_fan_tach_mode[type]; | |
562 | both = (mode & BOTH_EDGES) ? 1 : 0; | |
563 | ||
564 | tach_div = (0x4 << both) << (tach_div * 2); | |
2d7a548a JRN |
565 | clk_source = priv->clk_freq; |
566 | ||
567 | if (raw_data == 0) | |
568 | return 0; | |
569 | ||
570 | return (clk_source * 60) / (2 * raw_data * tach_div); | |
571 | } | |
572 | ||
e98dd538 GR |
573 | static ssize_t pwm_store(struct device *dev, struct device_attribute *attr, |
574 | const char *buf, size_t count) | |
2d7a548a JRN |
575 | { |
576 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
577 | int index = sensor_attr->index; | |
578 | int ret; | |
579 | struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); | |
580 | long fan_ctrl; | |
581 | ||
582 | ret = kstrtol(buf, 10, &fan_ctrl); | |
583 | if (ret != 0) | |
584 | return ret; | |
585 | ||
586 | if (fan_ctrl < 0 || fan_ctrl > PWM_MAX) | |
587 | return -EINVAL; | |
588 | ||
589 | if (priv->pwm_port_fan_ctrl[index] == fan_ctrl) | |
590 | return count; | |
591 | ||
592 | priv->pwm_port_fan_ctrl[index] = fan_ctrl; | |
593 | aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl); | |
594 | ||
595 | return count; | |
596 | } | |
597 | ||
e98dd538 | 598 | static ssize_t pwm_show(struct device *dev, struct device_attribute *attr, |
2d7a548a JRN |
599 | char *buf) |
600 | { | |
601 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
602 | int index = sensor_attr->index; | |
603 | struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); | |
604 | ||
605 | return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]); | |
606 | } | |
607 | ||
e98dd538 | 608 | static ssize_t rpm_show(struct device *dev, struct device_attribute *attr, |
2d7a548a JRN |
609 | char *buf) |
610 | { | |
611 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
612 | int index = sensor_attr->index; | |
7ed1c5e5 | 613 | int rpm; |
2d7a548a JRN |
614 | struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); |
615 | ||
616 | rpm = aspeed_get_fan_tach_ch_rpm(priv, index); | |
7ed1c5e5 PV |
617 | if (rpm < 0) |
618 | return rpm; | |
2d7a548a | 619 | |
7ed1c5e5 | 620 | return sprintf(buf, "%d\n", rpm); |
2d7a548a JRN |
621 | } |
622 | ||
623 | static umode_t pwm_is_visible(struct kobject *kobj, | |
624 | struct attribute *a, int index) | |
625 | { | |
626 | struct device *dev = container_of(kobj, struct device, kobj); | |
627 | struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); | |
628 | ||
629 | if (!priv->pwm_present[index]) | |
630 | return 0; | |
631 | return a->mode; | |
632 | } | |
633 | ||
634 | static umode_t fan_dev_is_visible(struct kobject *kobj, | |
635 | struct attribute *a, int index) | |
636 | { | |
637 | struct device *dev = container_of(kobj, struct device, kobj); | |
638 | struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); | |
639 | ||
640 | if (!priv->fan_tach_present[index]) | |
641 | return 0; | |
642 | return a->mode; | |
643 | } | |
644 | ||
e98dd538 GR |
645 | static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0); |
646 | static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1); | |
647 | static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2); | |
648 | static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3); | |
649 | static SENSOR_DEVICE_ATTR_RW(pwm5, pwm, 4); | |
650 | static SENSOR_DEVICE_ATTR_RW(pwm6, pwm, 5); | |
651 | static SENSOR_DEVICE_ATTR_RW(pwm7, pwm, 6); | |
652 | static SENSOR_DEVICE_ATTR_RW(pwm8, pwm, 7); | |
2d7a548a | 653 | static struct attribute *pwm_dev_attrs[] = { |
2d7a548a JRN |
654 | &sensor_dev_attr_pwm1.dev_attr.attr, |
655 | &sensor_dev_attr_pwm2.dev_attr.attr, | |
656 | &sensor_dev_attr_pwm3.dev_attr.attr, | |
657 | &sensor_dev_attr_pwm4.dev_attr.attr, | |
658 | &sensor_dev_attr_pwm5.dev_attr.attr, | |
659 | &sensor_dev_attr_pwm6.dev_attr.attr, | |
660 | &sensor_dev_attr_pwm7.dev_attr.attr, | |
5f348fa3 | 661 | &sensor_dev_attr_pwm8.dev_attr.attr, |
2d7a548a JRN |
662 | NULL, |
663 | }; | |
664 | ||
665 | static const struct attribute_group pwm_dev_group = { | |
666 | .attrs = pwm_dev_attrs, | |
667 | .is_visible = pwm_is_visible, | |
668 | }; | |
669 | ||
e98dd538 GR |
670 | static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0); |
671 | static SENSOR_DEVICE_ATTR_RO(fan2_input, rpm, 1); | |
672 | static SENSOR_DEVICE_ATTR_RO(fan3_input, rpm, 2); | |
673 | static SENSOR_DEVICE_ATTR_RO(fan4_input, rpm, 3); | |
674 | static SENSOR_DEVICE_ATTR_RO(fan5_input, rpm, 4); | |
675 | static SENSOR_DEVICE_ATTR_RO(fan6_input, rpm, 5); | |
676 | static SENSOR_DEVICE_ATTR_RO(fan7_input, rpm, 6); | |
677 | static SENSOR_DEVICE_ATTR_RO(fan8_input, rpm, 7); | |
678 | static SENSOR_DEVICE_ATTR_RO(fan9_input, rpm, 8); | |
679 | static SENSOR_DEVICE_ATTR_RO(fan10_input, rpm, 9); | |
680 | static SENSOR_DEVICE_ATTR_RO(fan11_input, rpm, 10); | |
681 | static SENSOR_DEVICE_ATTR_RO(fan12_input, rpm, 11); | |
682 | static SENSOR_DEVICE_ATTR_RO(fan13_input, rpm, 12); | |
683 | static SENSOR_DEVICE_ATTR_RO(fan14_input, rpm, 13); | |
684 | static SENSOR_DEVICE_ATTR_RO(fan15_input, rpm, 14); | |
685 | static SENSOR_DEVICE_ATTR_RO(fan16_input, rpm, 15); | |
2d7a548a | 686 | static struct attribute *fan_dev_attrs[] = { |
2d7a548a JRN |
687 | &sensor_dev_attr_fan1_input.dev_attr.attr, |
688 | &sensor_dev_attr_fan2_input.dev_attr.attr, | |
689 | &sensor_dev_attr_fan3_input.dev_attr.attr, | |
690 | &sensor_dev_attr_fan4_input.dev_attr.attr, | |
691 | &sensor_dev_attr_fan5_input.dev_attr.attr, | |
692 | &sensor_dev_attr_fan6_input.dev_attr.attr, | |
693 | &sensor_dev_attr_fan7_input.dev_attr.attr, | |
694 | &sensor_dev_attr_fan8_input.dev_attr.attr, | |
695 | &sensor_dev_attr_fan9_input.dev_attr.attr, | |
696 | &sensor_dev_attr_fan10_input.dev_attr.attr, | |
697 | &sensor_dev_attr_fan11_input.dev_attr.attr, | |
698 | &sensor_dev_attr_fan12_input.dev_attr.attr, | |
699 | &sensor_dev_attr_fan13_input.dev_attr.attr, | |
700 | &sensor_dev_attr_fan14_input.dev_attr.attr, | |
701 | &sensor_dev_attr_fan15_input.dev_attr.attr, | |
5f348fa3 | 702 | &sensor_dev_attr_fan16_input.dev_attr.attr, |
2d7a548a JRN |
703 | NULL |
704 | }; | |
705 | ||
706 | static const struct attribute_group fan_dev_group = { | |
707 | .attrs = fan_dev_attrs, | |
708 | .is_visible = fan_dev_is_visible, | |
709 | }; | |
710 | ||
711 | /* | |
712 | * The clock type is type M : | |
713 | * The PWM frequency = 24MHz / (type M clock division L bit * | |
714 | * type M clock division H bit * (type M PWM period bit + 1)) | |
715 | */ | |
716 | static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv) | |
717 | { | |
718 | priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H; | |
719 | priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L; | |
720 | priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD; | |
721 | aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H, | |
722 | M_PWM_DIV_L, M_PWM_PERIOD); | |
723 | aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true); | |
724 | priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV; | |
725 | priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT; | |
1e276292 | 726 | priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE; |
2d7a548a JRN |
727 | aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE, |
728 | M_TACH_UNIT, M_TACH_CLK_DIV); | |
729 | } | |
730 | ||
731 | static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv, | |
732 | u8 pwm_port) | |
733 | { | |
734 | aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true); | |
735 | priv->pwm_present[pwm_port] = true; | |
736 | ||
737 | priv->pwm_port_type[pwm_port] = TYPEM; | |
738 | aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM); | |
739 | ||
740 | priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL; | |
741 | aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL); | |
742 | } | |
743 | ||
744 | static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv, | |
745 | u8 *fan_tach_ch, | |
746 | int count, | |
747 | u8 pwm_source) | |
748 | { | |
749 | u8 val, index; | |
750 | ||
751 | for (val = 0; val < count; val++) { | |
752 | index = fan_tach_ch[val]; | |
753 | aspeed_set_fan_tach_ch_enable(priv->regmap, index, true); | |
754 | priv->fan_tach_present[index] = true; | |
755 | priv->fan_tach_ch_source[index] = pwm_source; | |
756 | aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source); | |
757 | } | |
758 | } | |
759 | ||
f198907d MK |
760 | static int |
761 | aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev, | |
762 | unsigned long *state) | |
763 | { | |
764 | struct aspeed_cooling_device *cdev = tcdev->devdata; | |
765 | ||
766 | *state = cdev->max_state; | |
767 | ||
768 | return 0; | |
769 | } | |
770 | ||
771 | static int | |
772 | aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev, | |
773 | unsigned long *state) | |
774 | { | |
775 | struct aspeed_cooling_device *cdev = tcdev->devdata; | |
776 | ||
777 | *state = cdev->cur_state; | |
778 | ||
779 | return 0; | |
780 | } | |
781 | ||
782 | static int | |
783 | aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev, | |
784 | unsigned long state) | |
785 | { | |
786 | struct aspeed_cooling_device *cdev = tcdev->devdata; | |
787 | ||
788 | if (state > cdev->max_state) | |
789 | return -EINVAL; | |
790 | ||
791 | cdev->cur_state = state; | |
792 | cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] = | |
793 | cdev->cooling_levels[cdev->cur_state]; | |
794 | aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port, | |
795 | cdev->cooling_levels[cdev->cur_state]); | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = { | |
801 | .get_max_state = aspeed_pwm_cz_get_max_state, | |
802 | .get_cur_state = aspeed_pwm_cz_get_cur_state, | |
803 | .set_cur_state = aspeed_pwm_cz_set_cur_state, | |
804 | }; | |
805 | ||
806 | static int aspeed_create_pwm_cooling(struct device *dev, | |
807 | struct device_node *child, | |
808 | struct aspeed_pwm_tacho_data *priv, | |
809 | u32 pwm_port, u8 num_levels) | |
810 | { | |
811 | int ret; | |
812 | struct aspeed_cooling_device *cdev; | |
813 | ||
814 | cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); | |
815 | ||
816 | if (!cdev) | |
817 | return -ENOMEM; | |
818 | ||
819 | cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); | |
820 | if (!cdev->cooling_levels) | |
821 | return -ENOMEM; | |
822 | ||
823 | cdev->max_state = num_levels - 1; | |
824 | ret = of_property_read_u8_array(child, "cooling-levels", | |
825 | cdev->cooling_levels, | |
826 | num_levels); | |
827 | if (ret) { | |
828 | dev_err(dev, "Property 'cooling-levels' cannot be read.\n"); | |
829 | return ret; | |
830 | } | |
0debe4d0 | 831 | snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port); |
f198907d MK |
832 | |
833 | cdev->tcdev = thermal_of_cooling_device_register(child, | |
834 | cdev->name, | |
835 | cdev, | |
836 | &aspeed_pwm_cool_ops); | |
837 | if (IS_ERR(cdev->tcdev)) | |
838 | return PTR_ERR(cdev->tcdev); | |
839 | ||
840 | cdev->priv = priv; | |
841 | cdev->pwm_port = pwm_port; | |
842 | ||
843 | priv->cdev[pwm_port] = cdev; | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
2d7a548a JRN |
848 | static int aspeed_create_fan(struct device *dev, |
849 | struct device_node *child, | |
850 | struct aspeed_pwm_tacho_data *priv) | |
851 | { | |
852 | u8 *fan_tach_ch; | |
853 | u32 pwm_port; | |
854 | int ret, count; | |
855 | ||
856 | ret = of_property_read_u32(child, "reg", &pwm_port); | |
857 | if (ret) | |
858 | return ret; | |
859 | aspeed_create_pwm_port(priv, (u8)pwm_port); | |
860 | ||
f198907d MK |
861 | ret = of_property_count_u8_elems(child, "cooling-levels"); |
862 | ||
863 | if (ret > 0) { | |
864 | ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port, | |
865 | ret); | |
866 | if (ret) | |
867 | return ret; | |
868 | } | |
869 | ||
2d7a548a JRN |
870 | count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch"); |
871 | if (count < 1) | |
872 | return -EINVAL; | |
a86854d0 | 873 | fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch), |
2d7a548a JRN |
874 | GFP_KERNEL); |
875 | if (!fan_tach_ch) | |
876 | return -ENOMEM; | |
877 | ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch", | |
878 | fan_tach_ch, count); | |
879 | if (ret) | |
880 | return ret; | |
881 | aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port); | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
18c514cc J |
886 | static void aspeed_pwm_tacho_remove(void *data) |
887 | { | |
888 | struct aspeed_pwm_tacho_data *priv = data; | |
889 | ||
890 | reset_control_assert(priv->rst); | |
891 | } | |
892 | ||
2d7a548a JRN |
893 | static int aspeed_pwm_tacho_probe(struct platform_device *pdev) |
894 | { | |
895 | struct device *dev = &pdev->dev; | |
896 | struct device_node *np, *child; | |
897 | struct aspeed_pwm_tacho_data *priv; | |
898 | void __iomem *regs; | |
899 | struct resource *res; | |
900 | struct device *hwmon; | |
901 | struct clk *clk; | |
902 | int ret; | |
903 | ||
904 | np = dev->of_node; | |
905 | ||
906 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
907 | if (!res) | |
908 | return -ENOENT; | |
909 | regs = devm_ioremap_resource(dev, res); | |
910 | if (IS_ERR(regs)) | |
911 | return PTR_ERR(regs); | |
912 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
913 | if (!priv) | |
914 | return -ENOMEM; | |
915 | priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs, | |
916 | &aspeed_pwm_tacho_regmap_config); | |
917 | if (IS_ERR(priv->regmap)) | |
918 | return PTR_ERR(priv->regmap); | |
18c514cc J |
919 | |
920 | priv->rst = devm_reset_control_get_exclusive(dev, NULL); | |
921 | if (IS_ERR(priv->rst)) { | |
922 | dev_err(dev, | |
923 | "missing or invalid reset controller device tree entry"); | |
924 | return PTR_ERR(priv->rst); | |
925 | } | |
926 | reset_control_deassert(priv->rst); | |
927 | ||
928 | ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv); | |
929 | if (ret) | |
930 | return ret; | |
931 | ||
2d7a548a JRN |
932 | regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0); |
933 | regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0); | |
934 | ||
935 | clk = devm_clk_get(dev, NULL); | |
936 | if (IS_ERR(clk)) | |
937 | return -ENODEV; | |
938 | priv->clk_freq = clk_get_rate(clk); | |
939 | aspeed_set_clock_enable(priv->regmap, true); | |
940 | aspeed_set_clock_source(priv->regmap, 0); | |
941 | ||
942 | aspeed_create_type(priv); | |
943 | ||
944 | for_each_child_of_node(np, child) { | |
945 | ret = aspeed_create_fan(dev, child, priv); | |
f198907d MK |
946 | if (ret) { |
947 | of_node_put(child); | |
2d7a548a | 948 | return ret; |
f198907d | 949 | } |
2d7a548a | 950 | } |
2d7a548a JRN |
951 | |
952 | priv->groups[0] = &pwm_dev_group; | |
953 | priv->groups[1] = &fan_dev_group; | |
954 | priv->groups[2] = NULL; | |
955 | hwmon = devm_hwmon_device_register_with_groups(dev, | |
956 | "aspeed_pwm_tacho", | |
957 | priv, priv->groups); | |
958 | return PTR_ERR_OR_ZERO(hwmon); | |
959 | } | |
960 | ||
961 | static const struct of_device_id of_pwm_tacho_match_table[] = { | |
962 | { .compatible = "aspeed,ast2400-pwm-tacho", }, | |
963 | { .compatible = "aspeed,ast2500-pwm-tacho", }, | |
964 | {}, | |
965 | }; | |
966 | MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table); | |
967 | ||
968 | static struct platform_driver aspeed_pwm_tacho_driver = { | |
969 | .probe = aspeed_pwm_tacho_probe, | |
970 | .driver = { | |
971 | .name = "aspeed_pwm_tacho", | |
972 | .of_match_table = of_pwm_tacho_match_table, | |
973 | }, | |
974 | }; | |
975 | ||
976 | module_platform_driver(aspeed_pwm_tacho_driver); | |
977 | ||
978 | MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>"); | |
979 | MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver"); | |
980 | MODULE_LICENSE("GPL"); |