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3faa1ffb HG |
1 | /* |
2 | abituguru3.c Copyright (c) 2006 Hans de Goede <j.w.r.degoede@hhs.nl> | |
3 | ||
4 | This program is free software; you can redistribute it and/or modify | |
5 | it under the terms of the GNU General Public License as published by | |
6 | the Free Software Foundation; either version 2 of the License, or | |
7 | (at your option) any later version. | |
8 | ||
9 | This program is distributed in the hope that it will be useful, | |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | GNU General Public License for more details. | |
13 | ||
14 | You should have received a copy of the GNU General Public License | |
15 | along with this program; if not, write to the Free Software | |
16 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | /* | |
19 | This driver supports the sensor part of revision 3 of the custom Abit uGuru | |
20 | chip found on newer Abit uGuru motherboards. Note: because of lack of specs | |
21 | only reading the sensors and their settings is supported. | |
22 | */ | |
23 | #include <linux/module.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/jiffies.h> | |
27 | #include <linux/mutex.h> | |
28 | #include <linux/err.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/hwmon.h> | |
32 | #include <linux/hwmon-sysfs.h> | |
33 | #include <asm/io.h> | |
34 | ||
35 | /* uGuru3 bank addresses */ | |
36 | #define ABIT_UGURU3_SETTINGS_BANK 0x01 | |
37 | #define ABIT_UGURU3_SENSORS_BANK 0x08 | |
38 | #define ABIT_UGURU3_MISC_BANK 0x09 | |
39 | #define ABIT_UGURU3_ALARMS_START 0x1E | |
40 | #define ABIT_UGURU3_SETTINGS_START 0x24 | |
41 | #define ABIT_UGURU3_VALUES_START 0x80 | |
42 | #define ABIT_UGURU3_BOARD_ID 0x0A | |
43 | /* uGuru3 sensor bank flags */ /* Alarm if: */ | |
44 | #define ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE 0x01 /* temp over warn */ | |
45 | #define ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE 0x02 /* volt over max */ | |
46 | #define ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE 0x04 /* volt under min */ | |
47 | #define ABIT_UGURU3_TEMP_HIGH_ALARM_FLAG 0x10 /* temp is over warn */ | |
48 | #define ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG 0x20 /* volt is over max */ | |
49 | #define ABIT_UGURU3_VOLT_LOW_ALARM_FLAG 0x40 /* volt is under min */ | |
50 | #define ABIT_UGURU3_FAN_LOW_ALARM_ENABLE 0x01 /* fan under min */ | |
51 | #define ABIT_UGURU3_BEEP_ENABLE 0x08 /* beep if alarm */ | |
52 | #define ABIT_UGURU3_SHUTDOWN_ENABLE 0x80 /* shutdown if alarm */ | |
53 | /* sensor types */ | |
54 | #define ABIT_UGURU3_IN_SENSOR 0 | |
55 | #define ABIT_UGURU3_TEMP_SENSOR 1 | |
56 | #define ABIT_UGURU3_FAN_SENSOR 2 | |
57 | ||
58 | /* Timeouts / Retries, if these turn out to need a lot of fiddling we could | |
59 | convert them to params. Determined by trial and error. I assume this is | |
60 | cpu-speed independent, since the ISA-bus and not the CPU should be the | |
61 | bottleneck. */ | |
62 | #define ABIT_UGURU3_WAIT_TIMEOUT 250 | |
63 | /* Normally the 0xAC at the end of synchronize() is reported after the | |
64 | first read, but sometimes not and we need to poll */ | |
65 | #define ABIT_UGURU3_SYNCHRONIZE_TIMEOUT 5 | |
66 | /* utility macros */ | |
67 | #define ABIT_UGURU3_NAME "abituguru3" | |
68 | #define ABIT_UGURU3_DEBUG(format, arg...) \ | |
69 | if (verbose) \ | |
70 | printk(KERN_DEBUG ABIT_UGURU3_NAME ": " format , ## arg) | |
71 | ||
72 | /* Macros to help calculate the sysfs_names array length */ | |
73 | #define ABIT_UGURU3_MAX_NO_SENSORS 26 | |
74 | /* sum of strlen +1 of: in??_input\0, in??_{min,max}\0, in??_{min,max}_alarm\0, | |
75 | in??_{min,max}_alarm_enable\0, in??_beep\0, in??_shutdown\0, in??_label\0 */ | |
76 | #define ABIT_UGURU3_IN_NAMES_LENGTH (11 + 2 * 9 + 2 * 15 + 2 * 22 + 10 + 14 + 11) | |
77 | /* sum of strlen +1 of: temp??_input\0, temp??_max\0, temp??_crit\0, | |
78 | temp??_alarm\0, temp??_alarm_enable\0, temp??_beep\0, temp??_shutdown\0, | |
79 | temp??_label\0 */ | |
80 | #define ABIT_UGURU3_TEMP_NAMES_LENGTH (13 + 11 + 12 + 13 + 20 + 12 + 16 + 13) | |
81 | /* sum of strlen +1 of: fan??_input\0, fan??_min\0, fan??_alarm\0, | |
82 | fan??_alarm_enable\0, fan??_beep\0, fan??_shutdown\0, fan??_label\0 */ | |
83 | #define ABIT_UGURU3_FAN_NAMES_LENGTH (12 + 10 + 12 + 19 + 11 + 15 + 12) | |
84 | /* Worst case scenario 16 in sensors (longest names_length) and the rest | |
85 | temp sensors (second longest names_length). */ | |
86 | #define ABIT_UGURU3_SYSFS_NAMES_LENGTH (16 * ABIT_UGURU3_IN_NAMES_LENGTH + \ | |
87 | (ABIT_UGURU3_MAX_NO_SENSORS - 16) * ABIT_UGURU3_TEMP_NAMES_LENGTH) | |
88 | ||
89 | /* All the macros below are named identical to the openguru2 program | |
90 | reverse engineered by Louis Kruger, hence the names might not be 100% | |
91 | logical. I could come up with better names, but I prefer keeping the names | |
92 | identical so that this driver can be compared with his work more easily. */ | |
93 | /* Two i/o-ports are used by uGuru */ | |
94 | #define ABIT_UGURU3_BASE 0x00E0 | |
95 | #define ABIT_UGURU3_CMD 0x00 | |
96 | #define ABIT_UGURU3_DATA 0x04 | |
97 | #define ABIT_UGURU3_REGION_LENGTH 5 | |
98 | /* The wait_xxx functions return this on success and the last contents | |
99 | of the DATA register (0-255) on failure. */ | |
100 | #define ABIT_UGURU3_SUCCESS -1 | |
101 | /* uGuru status flags */ | |
102 | #define ABIT_UGURU3_STATUS_READY_FOR_READ 0x01 | |
103 | #define ABIT_UGURU3_STATUS_BUSY 0x02 | |
104 | ||
105 | ||
106 | /* Structures */ | |
107 | struct abituguru3_sensor_info { | |
108 | const char* name; | |
109 | int port; | |
110 | int type; | |
111 | int multiplier; | |
112 | int divisor; | |
113 | int offset; | |
114 | }; | |
115 | ||
116 | struct abituguru3_motherboard_info { | |
117 | u16 id; | |
118 | const char *name; | |
119 | /* + 1 -> end of sensors indicated by a sensor with name == NULL */ | |
120 | struct abituguru3_sensor_info sensors[ABIT_UGURU3_MAX_NO_SENSORS + 1]; | |
121 | }; | |
122 | ||
123 | /* For the Abit uGuru, we need to keep some data in memory. | |
124 | The structure is dynamically allocated, at the same time when a new | |
125 | abituguru3 device is allocated. */ | |
126 | struct abituguru3_data { | |
1beeffe4 | 127 | struct device *hwmon_dev; /* hwmon registered device */ |
3faa1ffb HG |
128 | struct mutex update_lock; /* protect access to data and uGuru */ |
129 | unsigned short addr; /* uguru base address */ | |
130 | char valid; /* !=0 if following fields are valid */ | |
131 | unsigned long last_updated; /* In jiffies */ | |
132 | ||
133 | /* For convenience the sysfs attr and their names are generated | |
134 | automatically. We have max 10 entries per sensor (for in sensors) */ | |
135 | struct sensor_device_attribute_2 sysfs_attr[ABIT_UGURU3_MAX_NO_SENSORS | |
136 | * 10]; | |
137 | ||
138 | /* Buffer to store the dynamically generated sysfs names */ | |
139 | char sysfs_names[ABIT_UGURU3_SYSFS_NAMES_LENGTH]; | |
140 | ||
141 | /* Pointer to the sensors info for the detected motherboard */ | |
142 | const struct abituguru3_sensor_info *sensors; | |
143 | ||
144 | /* The abituguru3 supports upto 48 sensors, and thus has registers | |
145 | sets for 48 sensors, for convienence reasons / simplicity of the | |
146 | code we always read and store all registers for all 48 sensors */ | |
147 | ||
148 | /* Alarms for all 48 sensors (1 bit per sensor) */ | |
149 | u8 alarms[48/8]; | |
150 | ||
151 | /* Value of all 48 sensors */ | |
152 | u8 value[48]; | |
153 | ||
154 | /* Settings of all 48 sensors, note in and temp sensors (the first 32 | |
155 | sensors) have 3 bytes of settings, while fans only have 2 bytes, | |
156 | for convenience we use 3 bytes for all sensors */ | |
157 | u8 settings[48][3]; | |
158 | }; | |
159 | ||
160 | ||
161 | /* Constants */ | |
162 | static const struct abituguru3_motherboard_info abituguru3_motherboards[] = { | |
163 | { 0x000C, "unknown", { | |
164 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
165 | { "DDR", 1, 0, 10, 1, 0 }, | |
166 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
167 | { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, | |
168 | { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, | |
169 | { "MCH 2.5V", 5, 0, 20, 1, 0 }, | |
170 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
171 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
172 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
173 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
174 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
175 | { "5VSB", 11, 0, 30, 1, 0 }, | |
176 | { "CPU", 24, 1, 1, 1, 0 }, | |
177 | { "System ", 25, 1, 1, 1, 0 }, | |
178 | { "PWM", 26, 1, 1, 1, 0 }, | |
179 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
180 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
181 | { "SYS FAN", 34, 2, 60, 1, 0 }, | |
182 | { "AUX1 Fan", 35, 2, 60, 1, 0 }, | |
183 | { NULL, 0, 0, 0, 0, 0 } } | |
184 | }, | |
185 | { 0x000D, "Abit AW8", { | |
186 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
187 | { "DDR", 1, 0, 10, 1, 0 }, | |
188 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
189 | { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, | |
190 | { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, | |
191 | { "MCH 2.5V", 5, 0, 20, 1, 0 }, | |
192 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
193 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
194 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
195 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
196 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
197 | { "5VSB", 11, 0, 30, 1, 0 }, | |
198 | { "CPU", 24, 1, 1, 1, 0 }, | |
199 | { "System ", 25, 1, 1, 1, 0 }, | |
200 | { "PWM1", 26, 1, 1, 1, 0 }, | |
201 | { "PWM2", 27, 1, 1, 1, 0 }, | |
202 | { "PWM3", 28, 1, 1, 1, 0 }, | |
203 | { "PWM4", 29, 1, 1, 1, 0 }, | |
204 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
205 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
206 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
207 | { "AUX1 Fan", 35, 2, 60, 1, 0 }, | |
208 | { "AUX2 Fan", 36, 2, 60, 1, 0 }, | |
209 | { "AUX3 Fan", 37, 2, 60, 1, 0 }, | |
210 | { "AUX4 Fan", 38, 2, 60, 1, 0 }, | |
211 | { "AUX5 Fan", 39, 2, 60, 1, 0 }, | |
212 | { NULL, 0, 0, 0, 0, 0 } } | |
213 | }, | |
214 | { 0x000E, "AL-8", { | |
215 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
216 | { "DDR", 1, 0, 10, 1, 0 }, | |
217 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
218 | { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, | |
219 | { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, | |
220 | { "MCH 2.5V", 5, 0, 20, 1, 0 }, | |
221 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
222 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
223 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
224 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
225 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
226 | { "5VSB", 11, 0, 30, 1, 0 }, | |
227 | { "CPU", 24, 1, 1, 1, 0 }, | |
228 | { "System ", 25, 1, 1, 1, 0 }, | |
229 | { "PWM", 26, 1, 1, 1, 0 }, | |
230 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
231 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
232 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
233 | { NULL, 0, 0, 0, 0, 0 } } | |
234 | }, | |
235 | { 0x000F, "unknown", { | |
236 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
237 | { "DDR", 1, 0, 10, 1, 0 }, | |
238 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
239 | { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, | |
240 | { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, | |
241 | { "MCH 2.5V", 5, 0, 20, 1, 0 }, | |
242 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
243 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
244 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
245 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
246 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
247 | { "5VSB", 11, 0, 30, 1, 0 }, | |
248 | { "CPU", 24, 1, 1, 1, 0 }, | |
249 | { "System ", 25, 1, 1, 1, 0 }, | |
250 | { "PWM", 26, 1, 1, 1, 0 }, | |
251 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
252 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
253 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
254 | { NULL, 0, 0, 0, 0, 0 } } | |
255 | }, | |
256 | { 0x0010, "Abit NI8 SLI GR", { | |
257 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
258 | { "DDR", 1, 0, 10, 1, 0 }, | |
259 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
260 | { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, | |
261 | { "NB 1.4V", 4, 0, 10, 1, 0 }, | |
262 | { "SB 1.5V", 6, 0, 10, 1, 0 }, | |
263 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
264 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
265 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
266 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
267 | { "5VSB", 11, 0, 30, 1, 0 }, | |
268 | { "CPU", 24, 1, 1, 1, 0 }, | |
269 | { "SYS", 25, 1, 1, 1, 0 }, | |
270 | { "PWM", 26, 1, 1, 1, 0 }, | |
271 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
272 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
273 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
274 | { "AUX1 Fan", 35, 2, 60, 1, 0 }, | |
275 | { "OTES1 Fan", 36, 2, 60, 1, 0 }, | |
276 | { NULL, 0, 0, 0, 0, 0 } } | |
277 | }, | |
278 | { 0x0011, "Abit AT8 32X", { | |
279 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
280 | { "DDR", 1, 0, 20, 1, 0 }, | |
281 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
282 | { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 }, | |
283 | { "NB 1.8V", 4, 0, 10, 1, 0 }, | |
284 | { "NB 1.8V Dual", 5, 0, 10, 1, 0 }, | |
285 | { "HTV 1.2", 3, 0, 10, 1, 0 }, | |
286 | { "PCIE 1.2V", 12, 0, 10, 1, 0 }, | |
287 | { "NB 1.2V", 13, 0, 10, 1, 0 }, | |
288 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
289 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
290 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
291 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
292 | { "5VSB", 11, 0, 30, 1, 0 }, | |
293 | { "CPU", 24, 1, 1, 1, 0 }, | |
294 | { "NB", 25, 1, 1, 1, 0 }, | |
295 | { "System", 26, 1, 1, 1, 0 }, | |
296 | { "PWM", 27, 1, 1, 1, 0 }, | |
297 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
298 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
299 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
300 | { "AUX1 Fan", 35, 2, 60, 1, 0 }, | |
301 | { "AUX2 Fan", 36, 2, 60, 1, 0 }, | |
302 | { NULL, 0, 0, 0, 0, 0 } } | |
303 | }, | |
304 | { 0x0012, "Abit AN8 32X", { | |
305 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
306 | { "DDR", 1, 0, 20, 1, 0 }, | |
307 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
308 | { "HyperTransport", 3, 0, 10, 1, 0 }, | |
309 | { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 }, | |
310 | { "NB", 4, 0, 10, 1, 0 }, | |
311 | { "SB", 6, 0, 10, 1, 0 }, | |
312 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
313 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
314 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
315 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
316 | { "5VSB", 11, 0, 30, 1, 0 }, | |
317 | { "CPU", 24, 1, 1, 1, 0 }, | |
318 | { "SYS", 25, 1, 1, 1, 0 }, | |
319 | { "PWM", 26, 1, 1, 1, 0 }, | |
320 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
321 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
322 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
323 | { "AUX1 Fan", 36, 2, 60, 1, 0 }, | |
324 | { NULL, 0, 0, 0, 0, 0 } } | |
325 | }, | |
1604e78b | 326 | { 0x0013, "Abit AW8D", { |
3faa1ffb HG |
327 | { "CPU Core", 0, 0, 10, 1, 0 }, |
328 | { "DDR", 1, 0, 10, 1, 0 }, | |
329 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
330 | { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, | |
331 | { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, | |
332 | { "MCH 2.5V", 5, 0, 20, 1, 0 }, | |
333 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
334 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
335 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
336 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
337 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
338 | { "5VSB", 11, 0, 30, 1, 0 }, | |
339 | { "CPU", 24, 1, 1, 1, 0 }, | |
340 | { "System ", 25, 1, 1, 1, 0 }, | |
341 | { "PWM1", 26, 1, 1, 1, 0 }, | |
342 | { "PWM2", 27, 1, 1, 1, 0 }, | |
343 | { "PWM3", 28, 1, 1, 1, 0 }, | |
344 | { "PWM4", 29, 1, 1, 1, 0 }, | |
345 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
346 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
347 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
348 | { "AUX1 Fan", 35, 2, 60, 1, 0 }, | |
349 | { "AUX2 Fan", 36, 2, 60, 1, 0 }, | |
350 | { "AUX3 Fan", 37, 2, 60, 1, 0 }, | |
351 | { "AUX4 Fan", 38, 2, 60, 1, 0 }, | |
1604e78b | 352 | { "AUX5 Fan", 39, 2, 60, 1, 0 }, |
3faa1ffb HG |
353 | { NULL, 0, 0, 0, 0, 0 } } |
354 | }, | |
9c2e14af | 355 | { 0x0014, "Abit AB9 Pro", { |
3faa1ffb HG |
356 | { "CPU Core", 0, 0, 10, 1, 0 }, |
357 | { "DDR", 1, 0, 10, 1, 0 }, | |
358 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
359 | { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, | |
360 | { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, | |
361 | { "MCH 2.5V", 5, 0, 20, 1, 0 }, | |
362 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
363 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
364 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
365 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
366 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
367 | { "5VSB", 11, 0, 30, 1, 0 }, | |
368 | { "CPU", 24, 1, 1, 1, 0 }, | |
369 | { "System ", 25, 1, 1, 1, 0 }, | |
370 | { "PWM", 26, 1, 1, 1, 0 }, | |
371 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
372 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
373 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
374 | { NULL, 0, 0, 0, 0, 0 } } | |
375 | }, | |
376 | { 0x0015, "unknown", { | |
377 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
378 | { "DDR", 1, 0, 20, 1, 0 }, | |
379 | { "DDR VTT", 2, 0, 10, 1, 0 }, | |
380 | { "HyperTransport", 3, 0, 10, 1, 0 }, | |
381 | { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 }, | |
382 | { "NB", 4, 0, 10, 1, 0 }, | |
383 | { "SB", 6, 0, 10, 1, 0 }, | |
384 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
385 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
386 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
387 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
388 | { "5VSB", 11, 0, 30, 1, 0 }, | |
389 | { "CPU", 24, 1, 1, 1, 0 }, | |
390 | { "SYS", 25, 1, 1, 1, 0 }, | |
391 | { "PWM", 26, 1, 1, 1, 0 }, | |
392 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
393 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
394 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
395 | { "AUX1 Fan", 33, 2, 60, 1, 0 }, | |
396 | { "AUX2 Fan", 35, 2, 60, 1, 0 }, | |
397 | { "AUX3 Fan", 36, 2, 60, 1, 0 }, | |
398 | { NULL, 0, 0, 0, 0, 0 } } | |
399 | }, | |
400 | { 0x0016, "AW9D-MAX", { | |
401 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
402 | { "DDR2", 1, 0, 20, 1, 0 }, | |
403 | { "DDR2 VTT", 2, 0, 10, 1, 0 }, | |
404 | { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, | |
405 | { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, | |
406 | { "MCH 2.5V", 5, 0, 20, 1, 0 }, | |
407 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
408 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
409 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
410 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
411 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
412 | { "5VSB", 11, 0, 30, 1, 0 }, | |
413 | { "CPU", 24, 1, 1, 1, 0 }, | |
414 | { "System ", 25, 1, 1, 1, 0 }, | |
415 | { "PWM1", 26, 1, 1, 1, 0 }, | |
416 | { "PWM2", 27, 1, 1, 1, 0 }, | |
417 | { "PWM3", 28, 1, 1, 1, 0 }, | |
418 | { "PWM4", 29, 1, 1, 1, 0 }, | |
419 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
420 | { "NB Fan", 33, 2, 60, 1, 0 }, | |
421 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
422 | { "AUX1 Fan", 35, 2, 60, 1, 0 }, | |
423 | { "AUX2 Fan", 36, 2, 60, 1, 0 }, | |
424 | { "AUX3 Fan", 37, 2, 60, 1, 0 }, | |
425 | { "OTES1 Fan", 38, 2, 60, 1, 0 }, | |
426 | { NULL, 0, 0, 0, 0, 0 } } | |
427 | }, | |
428 | { 0x0017, "unknown", { | |
429 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
430 | { "DDR2", 1, 0, 20, 1, 0 }, | |
431 | { "DDR2 VTT", 2, 0, 10, 1, 0 }, | |
432 | { "HyperTransport", 3, 0, 10, 1, 0 }, | |
433 | { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 }, | |
434 | { "NB 1.8V", 4, 0, 10, 1, 0 }, | |
435 | { "NB 1.2V ", 13, 0, 10, 1, 0 }, | |
436 | { "SB 1.2V", 5, 0, 10, 1, 0 }, | |
437 | { "PCIE 1.2V", 12, 0, 10, 1, 0 }, | |
438 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
439 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
440 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
441 | { "ATX +3.3V", 10, 0, 20, 1, 0 }, | |
442 | { "ATX 5VSB", 11, 0, 30, 1, 0 }, | |
443 | { "CPU", 24, 1, 1, 1, 0 }, | |
444 | { "System ", 26, 1, 1, 1, 0 }, | |
445 | { "PWM", 27, 1, 1, 1, 0 }, | |
446 | { "CPU FAN", 32, 2, 60, 1, 0 }, | |
447 | { "SYS FAN", 34, 2, 60, 1, 0 }, | |
448 | { "AUX1 FAN", 35, 2, 60, 1, 0 }, | |
449 | { "AUX2 FAN", 36, 2, 60, 1, 0 }, | |
450 | { "AUX3 FAN", 37, 2, 60, 1, 0 }, | |
451 | { NULL, 0, 0, 0, 0, 0 } } | |
452 | }, | |
453 | { 0x0018, "unknown", { | |
454 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
455 | { "DDR2", 1, 0, 20, 1, 0 }, | |
456 | { "DDR2 VTT", 2, 0, 10, 1, 0 }, | |
457 | { "CPU VTT", 3, 0, 10, 1, 0 }, | |
458 | { "MCH 1.25V", 4, 0, 10, 1, 0 }, | |
459 | { "ICHIO 1.5V", 5, 0, 10, 1, 0 }, | |
460 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
461 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
462 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
463 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
464 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
465 | { "5VSB", 11, 0, 30, 1, 0 }, | |
466 | { "CPU", 24, 1, 1, 1, 0 }, | |
467 | { "System ", 25, 1, 1, 1, 0 }, | |
468 | { "PWM Phase1", 26, 1, 1, 1, 0 }, | |
469 | { "PWM Phase2", 27, 1, 1, 1, 0 }, | |
470 | { "PWM Phase3", 28, 1, 1, 1, 0 }, | |
471 | { "PWM Phase4", 29, 1, 1, 1, 0 }, | |
472 | { "PWM Phase5", 30, 1, 1, 1, 0 }, | |
473 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
474 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
475 | { "AUX1 Fan", 33, 2, 60, 1, 0 }, | |
476 | { "AUX2 Fan", 35, 2, 60, 1, 0 }, | |
477 | { "AUX3 Fan", 36, 2, 60, 1, 0 }, | |
478 | { NULL, 0, 0, 0, 0, 0 } } | |
479 | }, | |
480 | { 0x0019, "unknown", { | |
481 | { "CPU Core", 7, 0, 10, 1, 0 }, | |
482 | { "DDR2", 13, 0, 20, 1, 0 }, | |
483 | { "DDR2 VTT", 14, 0, 10, 1, 0 }, | |
484 | { "CPU VTT", 3, 0, 20, 1, 0 }, | |
485 | { "NB 1.2V ", 4, 0, 10, 1, 0 }, | |
486 | { "SB 1.5V", 6, 0, 10, 1, 0 }, | |
487 | { "HyperTransport", 5, 0, 10, 1, 0 }, | |
488 | { "ATX +12V (24-Pin)", 12, 0, 60, 1, 0 }, | |
489 | { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, | |
490 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
491 | { "ATX +3.3V", 10, 0, 20, 1, 0 }, | |
492 | { "ATX 5VSB", 11, 0, 30, 1, 0 }, | |
493 | { "CPU", 24, 1, 1, 1, 0 }, | |
494 | { "System ", 25, 1, 1, 1, 0 }, | |
495 | { "PWM Phase1", 26, 1, 1, 1, 0 }, | |
496 | { "PWM Phase2", 27, 1, 1, 1, 0 }, | |
497 | { "PWM Phase3", 28, 1, 1, 1, 0 }, | |
498 | { "PWM Phase4", 29, 1, 1, 1, 0 }, | |
499 | { "PWM Phase5", 30, 1, 1, 1, 0 }, | |
500 | { "CPU FAN", 32, 2, 60, 1, 0 }, | |
501 | { "SYS FAN", 34, 2, 60, 1, 0 }, | |
502 | { "AUX1 FAN", 33, 2, 60, 1, 0 }, | |
503 | { "AUX2 FAN", 35, 2, 60, 1, 0 }, | |
504 | { "AUX3 FAN", 36, 2, 60, 1, 0 }, | |
505 | { NULL, 0, 0, 0, 0, 0 } } | |
506 | }, | |
dcbd9f68 | 507 | { 0x001A, "Abit IP35 Pro", { |
3faa1ffb HG |
508 | { "CPU Core", 0, 0, 10, 1, 0 }, |
509 | { "DDR2", 1, 0, 20, 1, 0 }, | |
510 | { "DDR2 VTT", 2, 0, 10, 1, 0 }, | |
511 | { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, | |
512 | { "MCH 1.25V", 4, 0, 10, 1, 0 }, | |
513 | { "ICHIO 1.5V", 5, 0, 10, 1, 0 }, | |
514 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
515 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
516 | { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 }, | |
517 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
518 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
519 | { "5VSB", 11, 0, 30, 1, 0 }, | |
520 | { "CPU", 24, 1, 1, 1, 0 }, | |
521 | { "System ", 25, 1, 1, 1, 0 }, | |
522 | { "PWM ", 26, 1, 1, 1, 0 }, | |
523 | { "PWM Phase2", 27, 1, 1, 1, 0 }, | |
524 | { "PWM Phase3", 28, 1, 1, 1, 0 }, | |
525 | { "PWM Phase4", 29, 1, 1, 1, 0 }, | |
526 | { "PWM Phase5", 30, 1, 1, 1, 0 }, | |
527 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
528 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
529 | { "AUX1 Fan", 33, 2, 60, 1, 0 }, | |
530 | { "AUX2 Fan", 35, 2, 60, 1, 0 }, | |
531 | { "AUX3 Fan", 36, 2, 60, 1, 0 }, | |
cb96b8ca | 532 | { "AUX4 Fan", 37, 2, 60, 1, 0 }, |
3faa1ffb HG |
533 | { NULL, 0, 0, 0, 0, 0 } } |
534 | }, | |
ff8966ac HG |
535 | { 0x001B, "unknown", { |
536 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
537 | { "DDR3", 1, 0, 20, 1, 0 }, | |
538 | { "DDR3 VTT", 2, 0, 10, 1, 0 }, | |
539 | { "CPU VTT", 3, 0, 10, 1, 0 }, | |
540 | { "MCH 1.25V", 4, 0, 10, 1, 0 }, | |
541 | { "ICHIO 1.5V", 5, 0, 10, 1, 0 }, | |
542 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
543 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
544 | { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 }, | |
545 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
546 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
547 | { "5VSB", 11, 0, 30, 1, 0 }, | |
548 | { "CPU", 24, 1, 1, 1, 0 }, | |
549 | { "System", 25, 1, 1, 1, 0 }, | |
550 | { "PWM Phase1", 26, 1, 1, 1, 0 }, | |
551 | { "PWM Phase2", 27, 1, 1, 1, 0 }, | |
552 | { "PWM Phase3", 28, 1, 1, 1, 0 }, | |
553 | { "PWM Phase4", 29, 1, 1, 1, 0 }, | |
554 | { "PWM Phase5", 30, 1, 1, 1, 0 }, | |
555 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
556 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
557 | { "AUX1 Fan", 33, 2, 60, 1, 0 }, | |
558 | { "AUX2 Fan", 35, 2, 60, 1, 0 }, | |
559 | { "AUX3 Fan", 36, 2, 60, 1, 0 }, | |
560 | { NULL, 0, 0, 0, 0, 0 } } | |
561 | }, | |
562 | { 0x001C, "unknown", { | |
563 | { "CPU Core", 0, 0, 10, 1, 0 }, | |
564 | { "DDR2", 1, 0, 20, 1, 0 }, | |
565 | { "DDR2 VTT", 2, 0, 10, 1, 0 }, | |
566 | { "CPU VTT", 3, 0, 10, 1, 0 }, | |
567 | { "MCH 1.25V", 4, 0, 10, 1, 0 }, | |
568 | { "ICHIO 1.5V", 5, 0, 10, 1, 0 }, | |
569 | { "ICH 1.05V", 6, 0, 10, 1, 0 }, | |
570 | { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, | |
571 | { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 }, | |
572 | { "ATX +5V", 9, 0, 30, 1, 0 }, | |
573 | { "+3.3V", 10, 0, 20, 1, 0 }, | |
574 | { "5VSB", 11, 0, 30, 1, 0 }, | |
575 | { "CPU", 24, 1, 1, 1, 0 }, | |
576 | { "System", 25, 1, 1, 1, 0 }, | |
577 | { "PWM Phase1", 26, 1, 1, 1, 0 }, | |
578 | { "PWM Phase2", 27, 1, 1, 1, 0 }, | |
579 | { "PWM Phase3", 28, 1, 1, 1, 0 }, | |
580 | { "PWM Phase4", 29, 1, 1, 1, 0 }, | |
581 | { "PWM Phase5", 30, 1, 1, 1, 0 }, | |
582 | { "CPU Fan", 32, 2, 60, 1, 0 }, | |
583 | { "SYS Fan", 34, 2, 60, 1, 0 }, | |
584 | { "AUX1 Fan", 33, 2, 60, 1, 0 }, | |
585 | { "AUX2 Fan", 35, 2, 60, 1, 0 }, | |
586 | { "AUX3 Fan", 36, 2, 60, 1, 0 }, | |
587 | { NULL, 0, 0, 0, 0, 0 } } | |
588 | }, | |
3faa1ffb HG |
589 | { 0x0000, NULL, { { NULL, 0, 0, 0, 0, 0 } } } |
590 | }; | |
591 | ||
592 | ||
593 | /* Insmod parameters */ | |
594 | static int force; | |
595 | module_param(force, bool, 0); | |
596 | MODULE_PARM_DESC(force, "Set to one to force detection."); | |
597 | /* Default verbose is 1, since this driver is still in the testing phase */ | |
598 | static int verbose = 1; | |
599 | module_param(verbose, bool, 0644); | |
600 | MODULE_PARM_DESC(verbose, "Enable/disable verbose error reporting"); | |
601 | ||
602 | ||
603 | /* wait while the uguru is busy (usually after a write) */ | |
604 | static int abituguru3_wait_while_busy(struct abituguru3_data *data) | |
605 | { | |
606 | u8 x; | |
607 | int timeout = ABIT_UGURU3_WAIT_TIMEOUT; | |
608 | ||
609 | while ((x = inb_p(data->addr + ABIT_UGURU3_DATA)) & | |
610 | ABIT_UGURU3_STATUS_BUSY) { | |
611 | timeout--; | |
612 | if (timeout == 0) | |
613 | return x; | |
614 | /* sleep a bit before our last try, to give the uGuru3 one | |
615 | last chance to respond. */ | |
616 | if (timeout == 1) | |
617 | msleep(1); | |
618 | } | |
619 | return ABIT_UGURU3_SUCCESS; | |
620 | } | |
621 | ||
622 | /* wait till uguru is ready to be read */ | |
623 | static int abituguru3_wait_for_read(struct abituguru3_data *data) | |
624 | { | |
625 | u8 x; | |
626 | int timeout = ABIT_UGURU3_WAIT_TIMEOUT; | |
627 | ||
628 | while (!((x = inb_p(data->addr + ABIT_UGURU3_DATA)) & | |
629 | ABIT_UGURU3_STATUS_READY_FOR_READ)) { | |
630 | timeout--; | |
631 | if (timeout == 0) | |
632 | return x; | |
633 | /* sleep a bit before our last try, to give the uGuru3 one | |
634 | last chance to respond. */ | |
635 | if (timeout == 1) | |
636 | msleep(1); | |
637 | } | |
638 | return ABIT_UGURU3_SUCCESS; | |
639 | } | |
640 | ||
641 | /* This synchronizes us with the uGuru3's protocol state machine, this | |
642 | must be done before each command. */ | |
643 | static int abituguru3_synchronize(struct abituguru3_data *data) | |
644 | { | |
645 | int x, timeout = ABIT_UGURU3_SYNCHRONIZE_TIMEOUT; | |
646 | ||
647 | if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { | |
648 | ABIT_UGURU3_DEBUG("synchronize timeout during initial busy " | |
649 | "wait, status: 0x%02x\n", x); | |
650 | return -EIO; | |
651 | } | |
652 | ||
653 | outb(0x20, data->addr + ABIT_UGURU3_DATA); | |
654 | if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { | |
655 | ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x20, " | |
656 | "status: 0x%02x\n", x); | |
657 | return -EIO; | |
658 | } | |
659 | ||
660 | outb(0x10, data->addr + ABIT_UGURU3_CMD); | |
661 | if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { | |
662 | ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x10, " | |
663 | "status: 0x%02x\n", x); | |
664 | return -EIO; | |
665 | } | |
666 | ||
667 | outb(0x00, data->addr + ABIT_UGURU3_CMD); | |
668 | if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { | |
669 | ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x00, " | |
670 | "status: 0x%02x\n", x); | |
671 | return -EIO; | |
672 | } | |
673 | ||
674 | if ((x = abituguru3_wait_for_read(data)) != ABIT_UGURU3_SUCCESS) { | |
675 | ABIT_UGURU3_DEBUG("synchronize timeout waiting for read, " | |
676 | "status: 0x%02x\n", x); | |
677 | return -EIO; | |
678 | } | |
679 | ||
680 | while ((x = inb(data->addr + ABIT_UGURU3_CMD)) != 0xAC) { | |
681 | timeout--; | |
682 | if (timeout == 0) { | |
683 | ABIT_UGURU3_DEBUG("synchronize timeout cmd does not " | |
684 | "hold 0xAC after synchronize, cmd: 0x%02x\n", | |
685 | x); | |
686 | return -EIO; | |
687 | } | |
688 | msleep(1); | |
689 | } | |
690 | return 0; | |
691 | } | |
692 | ||
693 | /* Read count bytes from sensor sensor_addr in bank bank_addr and store the | |
694 | result in buf */ | |
695 | static int abituguru3_read(struct abituguru3_data *data, u8 bank, u8 offset, | |
696 | u8 count, u8 *buf) | |
697 | { | |
698 | int i, x; | |
699 | ||
700 | if ((x = abituguru3_synchronize(data))) | |
701 | return x; | |
702 | ||
703 | outb(0x1A, data->addr + ABIT_UGURU3_DATA); | |
704 | if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { | |
705 | ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " | |
706 | "sending 0x1A, status: 0x%02x\n", (unsigned int)bank, | |
707 | (unsigned int)offset, x); | |
708 | return -EIO; | |
709 | } | |
710 | ||
711 | outb(bank, data->addr + ABIT_UGURU3_CMD); | |
712 | if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { | |
713 | ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " | |
714 | "sending the bank, status: 0x%02x\n", | |
715 | (unsigned int)bank, (unsigned int)offset, x); | |
716 | return -EIO; | |
717 | } | |
718 | ||
719 | outb(offset, data->addr + ABIT_UGURU3_CMD); | |
720 | if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { | |
721 | ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " | |
722 | "sending the offset, status: 0x%02x\n", | |
723 | (unsigned int)bank, (unsigned int)offset, x); | |
724 | return -EIO; | |
725 | } | |
726 | ||
727 | outb(count, data->addr + ABIT_UGURU3_CMD); | |
728 | if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { | |
729 | ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " | |
730 | "sending the count, status: 0x%02x\n", | |
731 | (unsigned int)bank, (unsigned int)offset, x); | |
732 | return -EIO; | |
733 | } | |
734 | ||
735 | for (i = 0; i < count; i++) { | |
736 | if ((x = abituguru3_wait_for_read(data)) != | |
737 | ABIT_UGURU3_SUCCESS) { | |
738 | ABIT_UGURU3_DEBUG("timeout reading byte %d from " | |
739 | "0x%02x:0x%02x, status: 0x%02x\n", i, | |
740 | (unsigned int)bank, (unsigned int)offset, x); | |
741 | break; | |
742 | } | |
743 | buf[i] = inb(data->addr + ABIT_UGURU3_CMD); | |
744 | } | |
745 | return i; | |
746 | } | |
747 | ||
748 | /* Sensor settings are stored 1 byte per offset with the bytes | |
749 | placed add consecutive offsets. */ | |
4688902d AB |
750 | static int abituguru3_read_increment_offset(struct abituguru3_data *data, |
751 | u8 bank, u8 offset, u8 count, | |
752 | u8 *buf, int offset_count) | |
3faa1ffb HG |
753 | { |
754 | int i, x; | |
755 | ||
756 | for (i = 0; i < offset_count; i++) | |
757 | if ((x = abituguru3_read(data, bank, offset + i, count, | |
758 | buf + i * count)) != count) | |
759 | return i * count + (i && (x < 0)) ? 0 : x; | |
760 | ||
761 | return i * count; | |
762 | } | |
763 | ||
764 | /* Following are the sysfs callback functions. These functions expect: | |
765 | sensor_device_attribute_2->index: index into the data->sensors array | |
766 | sensor_device_attribute_2->nr: register offset, bitmask or NA. */ | |
767 | static struct abituguru3_data *abituguru3_update_device(struct device *dev); | |
768 | ||
769 | static ssize_t show_value(struct device *dev, | |
770 | struct device_attribute *devattr, char *buf) | |
771 | { | |
772 | int value; | |
773 | struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr); | |
774 | struct abituguru3_data *data = abituguru3_update_device(dev); | |
775 | const struct abituguru3_sensor_info *sensor; | |
776 | ||
777 | if (!data) | |
778 | return -EIO; | |
779 | ||
780 | sensor = &data->sensors[attr->index]; | |
781 | ||
782 | /* are we reading a setting, or is this a normal read? */ | |
783 | if (attr->nr) | |
784 | value = data->settings[sensor->port][attr->nr]; | |
785 | else | |
786 | value = data->value[sensor->port]; | |
787 | ||
788 | /* convert the value */ | |
789 | value = (value * sensor->multiplier) / sensor->divisor + | |
790 | sensor->offset; | |
791 | ||
792 | /* alternatively we could update the sensors settings struct for this, | |
793 | but then its contents would differ from the windows sw ini files */ | |
794 | if (sensor->type == ABIT_UGURU3_TEMP_SENSOR) | |
795 | value *= 1000; | |
796 | ||
797 | return sprintf(buf, "%d\n", value); | |
798 | } | |
799 | ||
800 | static ssize_t show_alarm(struct device *dev, | |
801 | struct device_attribute *devattr, char *buf) | |
802 | { | |
803 | int port; | |
804 | struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr); | |
805 | struct abituguru3_data *data = abituguru3_update_device(dev); | |
806 | ||
807 | if (!data) | |
808 | return -EIO; | |
809 | ||
810 | port = data->sensors[attr->index].port; | |
811 | ||
812 | /* See if the alarm bit for this sensor is set and if a bitmask is | |
813 | given in attr->nr also check if the alarm matches the type of alarm | |
814 | we're looking for (for volt it can be either low or high). The type | |
815 | is stored in a few readonly bits in the settings of the sensor. */ | |
816 | if ((data->alarms[port / 8] & (0x01 << (port % 8))) && | |
817 | (!attr->nr || (data->settings[port][0] & attr->nr))) | |
818 | return sprintf(buf, "1\n"); | |
819 | else | |
820 | return sprintf(buf, "0\n"); | |
821 | } | |
822 | ||
823 | static ssize_t show_mask(struct device *dev, | |
824 | struct device_attribute *devattr, char *buf) | |
825 | { | |
826 | struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr); | |
827 | struct abituguru3_data *data = dev_get_drvdata(dev); | |
828 | ||
829 | if (data->settings[data->sensors[attr->index].port][0] & attr->nr) | |
830 | return sprintf(buf, "1\n"); | |
831 | else | |
832 | return sprintf(buf, "0\n"); | |
833 | } | |
834 | ||
835 | static ssize_t show_label(struct device *dev, | |
836 | struct device_attribute *devattr, char *buf) | |
837 | { | |
838 | struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr); | |
839 | struct abituguru3_data *data = dev_get_drvdata(dev); | |
840 | ||
841 | return sprintf(buf, "%s\n", data->sensors[attr->index].name); | |
842 | } | |
843 | ||
844 | static ssize_t show_name(struct device *dev, | |
845 | struct device_attribute *devattr, char *buf) | |
846 | { | |
847 | return sprintf(buf, "%s\n", ABIT_UGURU3_NAME); | |
848 | } | |
849 | ||
850 | /* Sysfs attr templates, the real entries are generated automatically. */ | |
851 | static const | |
852 | struct sensor_device_attribute_2 abituguru3_sysfs_templ[3][10] = { { | |
853 | SENSOR_ATTR_2(in%d_input, 0444, show_value, NULL, 0, 0), | |
854 | SENSOR_ATTR_2(in%d_min, 0444, show_value, NULL, 1, 0), | |
855 | SENSOR_ATTR_2(in%d_max, 0444, show_value, NULL, 2, 0), | |
856 | SENSOR_ATTR_2(in%d_min_alarm, 0444, show_alarm, NULL, | |
857 | ABIT_UGURU3_VOLT_LOW_ALARM_FLAG, 0), | |
858 | SENSOR_ATTR_2(in%d_max_alarm, 0444, show_alarm, NULL, | |
859 | ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG, 0), | |
860 | SENSOR_ATTR_2(in%d_beep, 0444, show_mask, NULL, | |
861 | ABIT_UGURU3_BEEP_ENABLE, 0), | |
862 | SENSOR_ATTR_2(in%d_shutdown, 0444, show_mask, NULL, | |
863 | ABIT_UGURU3_SHUTDOWN_ENABLE, 0), | |
864 | SENSOR_ATTR_2(in%d_min_alarm_enable, 0444, show_mask, NULL, | |
865 | ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE, 0), | |
866 | SENSOR_ATTR_2(in%d_max_alarm_enable, 0444, show_mask, NULL, | |
867 | ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE, 0), | |
868 | SENSOR_ATTR_2(in%d_label, 0444, show_label, NULL, 0, 0) | |
869 | }, { | |
870 | SENSOR_ATTR_2(temp%d_input, 0444, show_value, NULL, 0, 0), | |
871 | SENSOR_ATTR_2(temp%d_max, 0444, show_value, NULL, 1, 0), | |
872 | SENSOR_ATTR_2(temp%d_crit, 0444, show_value, NULL, 2, 0), | |
873 | SENSOR_ATTR_2(temp%d_alarm, 0444, show_alarm, NULL, 0, 0), | |
874 | SENSOR_ATTR_2(temp%d_beep, 0444, show_mask, NULL, | |
875 | ABIT_UGURU3_BEEP_ENABLE, 0), | |
876 | SENSOR_ATTR_2(temp%d_shutdown, 0444, show_mask, NULL, | |
877 | ABIT_UGURU3_SHUTDOWN_ENABLE, 0), | |
878 | SENSOR_ATTR_2(temp%d_alarm_enable, 0444, show_mask, NULL, | |
879 | ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE, 0), | |
880 | SENSOR_ATTR_2(temp%d_label, 0444, show_label, NULL, 0, 0) | |
881 | }, { | |
882 | SENSOR_ATTR_2(fan%d_input, 0444, show_value, NULL, 0, 0), | |
883 | SENSOR_ATTR_2(fan%d_min, 0444, show_value, NULL, 1, 0), | |
884 | SENSOR_ATTR_2(fan%d_alarm, 0444, show_alarm, NULL, 0, 0), | |
885 | SENSOR_ATTR_2(fan%d_beep, 0444, show_mask, NULL, | |
886 | ABIT_UGURU3_BEEP_ENABLE, 0), | |
887 | SENSOR_ATTR_2(fan%d_shutdown, 0444, show_mask, NULL, | |
888 | ABIT_UGURU3_SHUTDOWN_ENABLE, 0), | |
889 | SENSOR_ATTR_2(fan%d_alarm_enable, 0444, show_mask, NULL, | |
890 | ABIT_UGURU3_FAN_LOW_ALARM_ENABLE, 0), | |
891 | SENSOR_ATTR_2(fan%d_label, 0444, show_label, NULL, 0, 0) | |
892 | } }; | |
893 | ||
894 | static struct sensor_device_attribute_2 abituguru3_sysfs_attr[] = { | |
895 | SENSOR_ATTR_2(name, 0444, show_name, NULL, 0, 0), | |
896 | }; | |
897 | ||
898 | static int __devinit abituguru3_probe(struct platform_device *pdev) | |
899 | { | |
900 | const int no_sysfs_attr[3] = { 10, 8, 7 }; | |
901 | int sensor_index[3] = { 0, 1, 1 }; | |
902 | struct abituguru3_data *data; | |
903 | int i, j, type, used, sysfs_names_free, sysfs_attr_i, res = -ENODEV; | |
904 | char *sysfs_filename; | |
905 | u8 buf[2]; | |
906 | u16 id; | |
907 | ||
908 | if (!(data = kzalloc(sizeof(struct abituguru3_data), GFP_KERNEL))) | |
909 | return -ENOMEM; | |
910 | ||
911 | data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start; | |
912 | mutex_init(&data->update_lock); | |
913 | platform_set_drvdata(pdev, data); | |
914 | ||
915 | /* Read the motherboard ID */ | |
916 | if ((i = abituguru3_read(data, ABIT_UGURU3_MISC_BANK, | |
917 | ABIT_UGURU3_BOARD_ID, 2, buf)) != 2) { | |
918 | goto abituguru3_probe_error; | |
919 | } | |
920 | ||
921 | /* Completely read the uGuru to see if one really is there */ | |
922 | if (!abituguru3_update_device(&pdev->dev)) | |
923 | goto abituguru3_probe_error; | |
924 | ||
925 | /* lookup the ID in our motherboard table */ | |
926 | id = ((u16)buf[0] << 8) | (u16)buf[1]; | |
927 | for (i = 0; abituguru3_motherboards[i].id; i++) | |
928 | if (abituguru3_motherboards[i].id == id) | |
929 | break; | |
930 | if (!abituguru3_motherboards[i].id) { | |
931 | printk(KERN_ERR ABIT_UGURU3_NAME ": error unknown motherboard " | |
932 | "ID: %04X. Please report this to the abituguru3 " | |
933 | "maintainer (see MAINTAINERS)\n", (unsigned int)id); | |
934 | goto abituguru3_probe_error; | |
935 | } | |
936 | data->sensors = abituguru3_motherboards[i].sensors; | |
937 | printk(KERN_INFO ABIT_UGURU3_NAME ": found Abit uGuru3, motherboard " | |
938 | "ID: %04X (%s)\n", (unsigned int)id, | |
939 | abituguru3_motherboards[i].name); | |
940 | ||
941 | /* Fill the sysfs attr array */ | |
942 | sysfs_attr_i = 0; | |
943 | sysfs_filename = data->sysfs_names; | |
944 | sysfs_names_free = ABIT_UGURU3_SYSFS_NAMES_LENGTH; | |
945 | for (i = 0; data->sensors[i].name; i++) { | |
946 | /* Fail safe check, this should never happen! */ | |
947 | if (i >= ABIT_UGURU3_MAX_NO_SENSORS) { | |
948 | printk(KERN_ERR ABIT_UGURU3_NAME | |
949 | ": Fatal error motherboard has more sensors " | |
950 | "then ABIT_UGURU3_MAX_NO_SENSORS. This should " | |
951 | "never happen please report to the abituguru3 " | |
952 | "maintainer (see MAINTAINERS)\n"); | |
953 | res = -ENAMETOOLONG; | |
954 | goto abituguru3_probe_error; | |
955 | } | |
956 | type = data->sensors[i].type; | |
957 | for (j = 0; j < no_sysfs_attr[type]; j++) { | |
958 | used = snprintf(sysfs_filename, sysfs_names_free, | |
959 | abituguru3_sysfs_templ[type][j].dev_attr.attr. | |
960 | name, sensor_index[type]) + 1; | |
961 | data->sysfs_attr[sysfs_attr_i] = | |
962 | abituguru3_sysfs_templ[type][j]; | |
963 | data->sysfs_attr[sysfs_attr_i].dev_attr.attr.name = | |
964 | sysfs_filename; | |
965 | data->sysfs_attr[sysfs_attr_i].index = i; | |
966 | sysfs_filename += used; | |
967 | sysfs_names_free -= used; | |
968 | sysfs_attr_i++; | |
969 | } | |
970 | sensor_index[type]++; | |
971 | } | |
972 | /* Fail safe check, this should never happen! */ | |
973 | if (sysfs_names_free < 0) { | |
974 | printk(KERN_ERR ABIT_UGURU3_NAME | |
975 | ": Fatal error ran out of space for sysfs attr names. " | |
976 | "This should never happen please report to the " | |
977 | "abituguru3 maintainer (see MAINTAINERS)\n"); | |
978 | res = -ENAMETOOLONG; | |
979 | goto abituguru3_probe_error; | |
980 | } | |
981 | ||
982 | /* Register sysfs hooks */ | |
983 | for (i = 0; i < sysfs_attr_i; i++) | |
984 | if (device_create_file(&pdev->dev, | |
985 | &data->sysfs_attr[i].dev_attr)) | |
986 | goto abituguru3_probe_error; | |
987 | for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++) | |
988 | if (device_create_file(&pdev->dev, | |
989 | &abituguru3_sysfs_attr[i].dev_attr)) | |
990 | goto abituguru3_probe_error; | |
991 | ||
1beeffe4 TJ |
992 | data->hwmon_dev = hwmon_device_register(&pdev->dev); |
993 | if (IS_ERR(data->hwmon_dev)) { | |
994 | res = PTR_ERR(data->hwmon_dev); | |
3faa1ffb HG |
995 | goto abituguru3_probe_error; |
996 | } | |
997 | ||
998 | return 0; /* success */ | |
999 | ||
1000 | abituguru3_probe_error: | |
1001 | for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++) | |
1002 | device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr); | |
1003 | for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++) | |
1004 | device_remove_file(&pdev->dev, | |
1005 | &abituguru3_sysfs_attr[i].dev_attr); | |
1006 | kfree(data); | |
1007 | return res; | |
1008 | } | |
1009 | ||
1010 | static int __devexit abituguru3_remove(struct platform_device *pdev) | |
1011 | { | |
1012 | int i; | |
1013 | struct abituguru3_data *data = platform_get_drvdata(pdev); | |
1014 | ||
1015 | platform_set_drvdata(pdev, NULL); | |
1beeffe4 | 1016 | hwmon_device_unregister(data->hwmon_dev); |
3faa1ffb HG |
1017 | for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++) |
1018 | device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr); | |
1019 | for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++) | |
1020 | device_remove_file(&pdev->dev, | |
1021 | &abituguru3_sysfs_attr[i].dev_attr); | |
1022 | kfree(data); | |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | static struct abituguru3_data *abituguru3_update_device(struct device *dev) | |
1028 | { | |
1029 | int i; | |
1030 | struct abituguru3_data *data = dev_get_drvdata(dev); | |
1031 | ||
1032 | mutex_lock(&data->update_lock); | |
1033 | if (!data->valid || time_after(jiffies, data->last_updated + HZ)) { | |
1034 | /* Clear data->valid while updating */ | |
1035 | data->valid = 0; | |
1036 | /* Read alarms */ | |
1037 | if (abituguru3_read_increment_offset(data, | |
1038 | ABIT_UGURU3_SETTINGS_BANK, | |
1039 | ABIT_UGURU3_ALARMS_START, | |
1040 | 1, data->alarms, 48/8) != (48/8)) | |
1041 | goto LEAVE_UPDATE; | |
1042 | /* Read in and temp sensors (3 byte settings / sensor) */ | |
1043 | for (i = 0; i < 32; i++) { | |
1044 | if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK, | |
1045 | ABIT_UGURU3_VALUES_START + i, | |
1046 | 1, &data->value[i]) != 1) | |
1047 | goto LEAVE_UPDATE; | |
1048 | if (abituguru3_read_increment_offset(data, | |
1049 | ABIT_UGURU3_SETTINGS_BANK, | |
1050 | ABIT_UGURU3_SETTINGS_START + i * 3, | |
1051 | 1, | |
1052 | data->settings[i], 3) != 3) | |
1053 | goto LEAVE_UPDATE; | |
1054 | } | |
1055 | /* Read temp sensors (2 byte settings / sensor) */ | |
1056 | for (i = 0; i < 16; i++) { | |
1057 | if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK, | |
1058 | ABIT_UGURU3_VALUES_START + 32 + i, | |
1059 | 1, &data->value[32 + i]) != 1) | |
1060 | goto LEAVE_UPDATE; | |
1061 | if (abituguru3_read_increment_offset(data, | |
1062 | ABIT_UGURU3_SETTINGS_BANK, | |
1063 | ABIT_UGURU3_SETTINGS_START + 32 * 3 + | |
1064 | i * 2, 1, | |
1065 | data->settings[32 + i], 2) != 2) | |
1066 | goto LEAVE_UPDATE; | |
1067 | } | |
1068 | data->last_updated = jiffies; | |
1069 | data->valid = 1; | |
1070 | } | |
1071 | LEAVE_UPDATE: | |
1072 | mutex_unlock(&data->update_lock); | |
1073 | if (data->valid) | |
1074 | return data; | |
1075 | else | |
1076 | return NULL; | |
1077 | } | |
1078 | ||
1079 | #ifdef CONFIG_PM | |
1080 | static int abituguru3_suspend(struct platform_device *pdev, pm_message_t state) | |
1081 | { | |
1082 | struct abituguru3_data *data = platform_get_drvdata(pdev); | |
1083 | /* make sure all communications with the uguru3 are done and no new | |
1084 | ones are started */ | |
1085 | mutex_lock(&data->update_lock); | |
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | static int abituguru3_resume(struct platform_device *pdev) | |
1090 | { | |
1091 | struct abituguru3_data *data = platform_get_drvdata(pdev); | |
1092 | mutex_unlock(&data->update_lock); | |
1093 | return 0; | |
1094 | } | |
1095 | #else | |
1096 | #define abituguru3_suspend NULL | |
1097 | #define abituguru3_resume NULL | |
1098 | #endif /* CONFIG_PM */ | |
1099 | ||
1100 | static struct platform_driver abituguru3_driver = { | |
1101 | .driver = { | |
1102 | .owner = THIS_MODULE, | |
1103 | .name = ABIT_UGURU3_NAME, | |
1104 | }, | |
1105 | .probe = abituguru3_probe, | |
1106 | .remove = __devexit_p(abituguru3_remove), | |
1107 | .suspend = abituguru3_suspend, | |
1108 | .resume = abituguru3_resume | |
1109 | }; | |
1110 | ||
1111 | static int __init abituguru3_detect(void) | |
1112 | { | |
9c2e14af HG |
1113 | /* See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or |
1114 | 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05 | |
1115 | at CMD instead, why is unknown. So we test for 0x05 too. */ | |
3faa1ffb HG |
1116 | u8 data_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_DATA); |
1117 | u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD); | |
9c2e14af HG |
1118 | if (((data_val == 0x00) || (data_val == 0x08)) && |
1119 | ((cmd_val == 0xAC) || (cmd_val == 0x05))) | |
3faa1ffb HG |
1120 | return ABIT_UGURU3_BASE; |
1121 | ||
1122 | ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = " | |
1123 | "0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val); | |
1124 | ||
1125 | if (force) { | |
1126 | printk(KERN_INFO ABIT_UGURU3_NAME ": Assuming Abit uGuru3 is " | |
1127 | "present because of \"force\" parameter\n"); | |
1128 | return ABIT_UGURU3_BASE; | |
1129 | } | |
1130 | ||
1131 | /* No uGuru3 found */ | |
1132 | return -ENODEV; | |
1133 | } | |
1134 | ||
1135 | static struct platform_device *abituguru3_pdev; | |
1136 | ||
1137 | static int __init abituguru3_init(void) | |
1138 | { | |
1139 | int address, err; | |
1140 | struct resource res = { .flags = IORESOURCE_IO }; | |
1141 | ||
1142 | address = abituguru3_detect(); | |
1143 | if (address < 0) | |
1144 | return address; | |
1145 | ||
1146 | err = platform_driver_register(&abituguru3_driver); | |
1147 | if (err) | |
1148 | goto exit; | |
1149 | ||
1150 | abituguru3_pdev = platform_device_alloc(ABIT_UGURU3_NAME, address); | |
1151 | if (!abituguru3_pdev) { | |
1152 | printk(KERN_ERR ABIT_UGURU3_NAME | |
1153 | ": Device allocation failed\n"); | |
1154 | err = -ENOMEM; | |
1155 | goto exit_driver_unregister; | |
1156 | } | |
1157 | ||
1158 | res.start = address; | |
1159 | res.end = address + ABIT_UGURU3_REGION_LENGTH - 1; | |
1160 | res.name = ABIT_UGURU3_NAME; | |
1161 | ||
1162 | err = platform_device_add_resources(abituguru3_pdev, &res, 1); | |
1163 | if (err) { | |
1164 | printk(KERN_ERR ABIT_UGURU3_NAME | |
1165 | ": Device resource addition failed (%d)\n", err); | |
1166 | goto exit_device_put; | |
1167 | } | |
1168 | ||
1169 | err = platform_device_add(abituguru3_pdev); | |
1170 | if (err) { | |
1171 | printk(KERN_ERR ABIT_UGURU3_NAME | |
1172 | ": Device addition failed (%d)\n", err); | |
1173 | goto exit_device_put; | |
1174 | } | |
1175 | ||
1176 | return 0; | |
1177 | ||
1178 | exit_device_put: | |
1179 | platform_device_put(abituguru3_pdev); | |
1180 | exit_driver_unregister: | |
1181 | platform_driver_unregister(&abituguru3_driver); | |
1182 | exit: | |
1183 | return err; | |
1184 | } | |
1185 | ||
1186 | static void __exit abituguru3_exit(void) | |
1187 | { | |
1188 | platform_device_unregister(abituguru3_pdev); | |
1189 | platform_driver_unregister(&abituguru3_driver); | |
1190 | } | |
1191 | ||
1192 | MODULE_AUTHOR("Hans de Goede <j.w.r.degoede@hhs.nl>"); | |
1193 | MODULE_DESCRIPTION("Abit uGuru3 Sensor device"); | |
1194 | MODULE_LICENSE("GPL"); | |
1195 | ||
1196 | module_init(abituguru3_init); | |
1197 | module_exit(abituguru3_exit); |