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09574cca DP |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (c) 2021-2022 NVIDIA Corporation | |
4 | * | |
5 | * Author: Dipen Patel <dipenp@nvidia.com> | |
6 | */ | |
7 | ||
8 | #include <linux/err.h> | |
9 | #include <linux/io.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/stat.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/of.h> | |
09574cca DP |
15 | #include <linux/platform_device.h> |
16 | #include <linux/hte.h> | |
17 | #include <linux/uaccess.h> | |
18 | #include <linux/gpio/driver.h> | |
19 | #include <linux/gpio/consumer.h> | |
20 | ||
21 | #define HTE_SUSPEND 0 | |
22 | ||
23 | /* HTE source clock TSC is 31.25MHz */ | |
24 | #define HTE_TS_CLK_RATE_HZ 31250000ULL | |
25 | #define HTE_CLK_RATE_NS 32 | |
26 | #define HTE_TS_NS_SHIFT __builtin_ctz(HTE_CLK_RATE_NS) | |
27 | ||
28 | #define NV_AON_SLICE_INVALID -1 | |
29 | #define NV_LINES_IN_SLICE 32 | |
30 | ||
31 | /* AON HTE line map For slice 1 */ | |
32 | #define NV_AON_HTE_SLICE1_IRQ_GPIO_28 12 | |
33 | #define NV_AON_HTE_SLICE1_IRQ_GPIO_29 13 | |
34 | ||
35 | /* AON HTE line map For slice 2 */ | |
36 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_0 0 | |
37 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_1 1 | |
38 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_2 2 | |
39 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_3 3 | |
40 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_4 4 | |
41 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_5 5 | |
42 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_6 6 | |
43 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_7 7 | |
44 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_8 8 | |
45 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_9 9 | |
46 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_10 10 | |
47 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_11 11 | |
48 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_12 12 | |
49 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_13 13 | |
50 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_14 14 | |
51 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_15 15 | |
52 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_16 16 | |
53 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_17 17 | |
54 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_18 18 | |
55 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_19 19 | |
56 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_20 20 | |
57 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_21 21 | |
58 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_22 22 | |
59 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_23 23 | |
60 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_24 24 | |
61 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 | |
62 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 | |
63 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 | |
b003fb5c DP |
64 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 |
65 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 | |
66 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 | |
67 | #define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 | |
09574cca DP |
68 | |
69 | #define HTE_TECTRL 0x0 | |
70 | #define HTE_TETSCH 0x4 | |
71 | #define HTE_TETSCL 0x8 | |
72 | #define HTE_TESRC 0xC | |
73 | #define HTE_TECCV 0x10 | |
74 | #define HTE_TEPCV 0x14 | |
75 | #define HTE_TECMD 0x1C | |
76 | #define HTE_TESTATUS 0x20 | |
77 | #define HTE_SLICE0_TETEN 0x40 | |
78 | #define HTE_SLICE1_TETEN 0x60 | |
79 | ||
80 | #define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN) | |
81 | ||
82 | #define HTE_TECTRL_ENABLE_ENABLE 0x1 | |
83 | ||
84 | #define HTE_TECTRL_OCCU_SHIFT 0x8 | |
85 | #define HTE_TECTRL_INTR_SHIFT 0x1 | |
86 | #define HTE_TECTRL_INTR_ENABLE 0x1 | |
87 | ||
88 | #define HTE_TESRC_SLICE_SHIFT 16 | |
89 | #define HTE_TESRC_SLICE_DEFAULT_MASK 0xFF | |
90 | ||
91 | #define HTE_TECMD_CMD_POP 0x1 | |
92 | ||
93 | #define HTE_TESTATUS_OCCUPANCY_SHIFT 8 | |
94 | #define HTE_TESTATUS_OCCUPANCY_MASK 0xFF | |
95 | ||
96 | enum tegra_hte_type { | |
97 | HTE_TEGRA_TYPE_GPIO = 1U << 0, | |
98 | HTE_TEGRA_TYPE_LIC = 1U << 1, | |
99 | }; | |
100 | ||
101 | struct hte_slices { | |
102 | u32 r_val; | |
103 | unsigned long flags; | |
104 | /* to prevent lines mapped to same slice updating its register */ | |
105 | spinlock_t s_lock; | |
106 | }; | |
107 | ||
108 | struct tegra_hte_line_mapped { | |
109 | int slice; | |
110 | u32 bit_index; | |
111 | }; | |
112 | ||
113 | struct tegra_hte_line_data { | |
114 | unsigned long flags; | |
115 | void *data; | |
116 | }; | |
117 | ||
118 | struct tegra_hte_data { | |
119 | enum tegra_hte_type type; | |
0ebc475f | 120 | u32 slices; |
09574cca DP |
121 | u32 map_sz; |
122 | u32 sec_map_sz; | |
123 | const struct tegra_hte_line_mapped *map; | |
124 | const struct tegra_hte_line_mapped *sec_map; | |
125 | }; | |
126 | ||
127 | struct tegra_hte_soc { | |
128 | int hte_irq; | |
129 | u32 itr_thrshld; | |
130 | u32 conf_rval; | |
131 | struct hte_slices *sl; | |
132 | const struct tegra_hte_data *prov_data; | |
133 | struct tegra_hte_line_data *line_data; | |
134 | struct hte_chip *chip; | |
dc850faa | 135 | struct gpio_device *gdev; |
09574cca DP |
136 | void __iomem *regs; |
137 | }; | |
138 | ||
139 | static const struct tegra_hte_line_mapped tegra194_aon_gpio_map[] = { | |
140 | /* gpio, slice, bit_index */ | |
141 | /* AA port */ | |
142 | [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, | |
143 | [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, | |
144 | [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, | |
145 | [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, | |
146 | [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, | |
147 | [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, | |
148 | [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, | |
149 | [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, | |
150 | /* BB port */ | |
151 | [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, | |
152 | [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, | |
153 | [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, | |
154 | [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, | |
155 | /* CC port */ | |
156 | [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, | |
157 | [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, | |
158 | [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, | |
159 | [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, | |
160 | [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, | |
161 | [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, | |
162 | [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, | |
163 | [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, | |
164 | /* DD port */ | |
165 | [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, | |
166 | [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, | |
167 | [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, | |
168 | /* EE port */ | |
169 | [23] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, | |
170 | [24] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, | |
171 | [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, | |
172 | [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, | |
173 | [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, | |
174 | [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, | |
175 | [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, | |
176 | }; | |
177 | ||
178 | static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { | |
179 | /* gpio, slice, bit_index */ | |
180 | /* AA port */ | |
181 | [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, | |
182 | [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, | |
183 | [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, | |
184 | [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, | |
185 | [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, | |
186 | [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, | |
187 | [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, | |
188 | [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, | |
189 | /* BB port */ | |
190 | [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, | |
191 | [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, | |
192 | [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, | |
193 | [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, | |
194 | [12] = {NV_AON_SLICE_INVALID, 0}, | |
195 | [13] = {NV_AON_SLICE_INVALID, 0}, | |
196 | [14] = {NV_AON_SLICE_INVALID, 0}, | |
197 | [15] = {NV_AON_SLICE_INVALID, 0}, | |
198 | /* CC port */ | |
199 | [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, | |
200 | [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, | |
201 | [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, | |
202 | [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, | |
203 | [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, | |
204 | [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, | |
205 | [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, | |
206 | [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, | |
207 | /* DD port */ | |
208 | [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, | |
209 | [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, | |
210 | [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, | |
211 | [27] = {NV_AON_SLICE_INVALID, 0}, | |
212 | [28] = {NV_AON_SLICE_INVALID, 0}, | |
213 | [29] = {NV_AON_SLICE_INVALID, 0}, | |
214 | [30] = {NV_AON_SLICE_INVALID, 0}, | |
215 | [31] = {NV_AON_SLICE_INVALID, 0}, | |
216 | /* EE port */ | |
217 | [32] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, | |
218 | [33] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, | |
219 | [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, | |
220 | [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, | |
221 | [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, | |
222 | [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, | |
223 | [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, | |
224 | [39] = {NV_AON_SLICE_INVALID, 0}, | |
225 | }; | |
226 | ||
b003fb5c DP |
227 | static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { |
228 | /* gpio, slice, bit_index */ | |
229 | /* AA port */ | |
230 | [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, | |
231 | [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, | |
232 | [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, | |
233 | [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, | |
234 | [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, | |
235 | [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, | |
236 | [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, | |
237 | [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, | |
238 | /* BB port */ | |
239 | [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, | |
240 | [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, | |
241 | [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, | |
242 | [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, | |
243 | /* CC port */ | |
244 | [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, | |
245 | [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, | |
246 | [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, | |
247 | [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, | |
248 | [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, | |
249 | [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, | |
250 | [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, | |
251 | [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, | |
252 | /* DD port */ | |
253 | [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, | |
254 | [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, | |
255 | [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, | |
256 | /* EE port */ | |
257 | [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, | |
258 | [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, | |
259 | [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, | |
260 | [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, | |
261 | [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, | |
262 | [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, | |
263 | [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, | |
264 | [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, | |
265 | /* GG port */ | |
266 | [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, | |
267 | }; | |
268 | ||
269 | static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { | |
270 | /* gpio, slice, bit_index */ | |
271 | /* AA port */ | |
272 | [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, | |
273 | [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, | |
274 | [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, | |
275 | [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, | |
276 | [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, | |
277 | [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, | |
278 | [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, | |
279 | [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, | |
280 | /* BB port */ | |
281 | [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, | |
282 | [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, | |
283 | [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, | |
284 | [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, | |
285 | [12] = {NV_AON_SLICE_INVALID, 0}, | |
286 | [13] = {NV_AON_SLICE_INVALID, 0}, | |
287 | [14] = {NV_AON_SLICE_INVALID, 0}, | |
288 | [15] = {NV_AON_SLICE_INVALID, 0}, | |
289 | /* CC port */ | |
290 | [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, | |
291 | [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, | |
292 | [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, | |
293 | [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, | |
294 | [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, | |
295 | [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, | |
296 | [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, | |
297 | [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, | |
298 | /* DD port */ | |
299 | [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, | |
300 | [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, | |
301 | [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, | |
302 | [27] = {NV_AON_SLICE_INVALID, 0}, | |
303 | [28] = {NV_AON_SLICE_INVALID, 0}, | |
304 | [29] = {NV_AON_SLICE_INVALID, 0}, | |
305 | [30] = {NV_AON_SLICE_INVALID, 0}, | |
306 | [31] = {NV_AON_SLICE_INVALID, 0}, | |
307 | /* EE port */ | |
308 | [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, | |
309 | [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, | |
310 | [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, | |
311 | [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, | |
312 | [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, | |
313 | [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, | |
314 | [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, | |
315 | [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, | |
316 | /* GG port */ | |
317 | [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, | |
318 | }; | |
319 | ||
320 | static const struct tegra_hte_data t194_aon_hte = { | |
09574cca DP |
321 | .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), |
322 | .map = tegra194_aon_gpio_map, | |
323 | .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), | |
324 | .sec_map = tegra194_aon_gpio_sec_map, | |
325 | .type = HTE_TEGRA_TYPE_GPIO, | |
0ebc475f | 326 | .slices = 3, |
09574cca DP |
327 | }; |
328 | ||
b003fb5c DP |
329 | static const struct tegra_hte_data t234_aon_hte = { |
330 | .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), | |
331 | .map = tegra234_aon_gpio_map, | |
332 | .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), | |
333 | .sec_map = tegra234_aon_gpio_sec_map, | |
334 | .type = HTE_TEGRA_TYPE_GPIO, | |
0ebc475f | 335 | .slices = 3, |
b003fb5c DP |
336 | }; |
337 | ||
0ebc475f | 338 | static const struct tegra_hte_data t194_lic_hte = { |
09574cca DP |
339 | .map_sz = 0, |
340 | .map = NULL, | |
341 | .type = HTE_TEGRA_TYPE_LIC, | |
0ebc475f DP |
342 | .slices = 11, |
343 | }; | |
344 | ||
345 | static const struct tegra_hte_data t234_lic_hte = { | |
346 | .map_sz = 0, | |
347 | .map = NULL, | |
348 | .type = HTE_TEGRA_TYPE_LIC, | |
349 | .slices = 17, | |
09574cca DP |
350 | }; |
351 | ||
352 | static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) | |
353 | { | |
354 | return readl(hte->regs + reg); | |
355 | } | |
356 | ||
357 | static inline void tegra_hte_writel(struct tegra_hte_soc *hte, u32 reg, | |
358 | u32 val) | |
359 | { | |
360 | writel(val, hte->regs + reg); | |
361 | } | |
362 | ||
363 | static int tegra_hte_map_to_line_id(u32 eid, | |
364 | const struct tegra_hte_line_mapped *m, | |
365 | u32 map_sz, u32 *mapped) | |
366 | { | |
367 | ||
368 | if (m) { | |
e078180d | 369 | if (eid >= map_sz) |
09574cca DP |
370 | return -EINVAL; |
371 | if (m[eid].slice == NV_AON_SLICE_INVALID) | |
372 | return -EINVAL; | |
373 | ||
374 | *mapped = (m[eid].slice << 5) + m[eid].bit_index; | |
375 | } else { | |
376 | *mapped = eid; | |
377 | } | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static int tegra_hte_line_xlate(struct hte_chip *gc, | |
383 | const struct of_phandle_args *args, | |
384 | struct hte_ts_desc *desc, u32 *xlated_id) | |
385 | { | |
386 | int ret = 0; | |
387 | u32 line_id; | |
388 | struct tegra_hte_soc *gs; | |
389 | const struct tegra_hte_line_mapped *map = NULL; | |
390 | u32 map_sz = 0; | |
391 | ||
392 | if (!gc || !desc || !xlated_id) | |
393 | return -EINVAL; | |
394 | ||
395 | if (args) { | |
396 | if (gc->of_hte_n_cells < 1) | |
397 | return -EINVAL; | |
398 | ||
399 | if (args->args_count != gc->of_hte_n_cells) | |
400 | return -EINVAL; | |
401 | ||
402 | desc->attr.line_id = args->args[0]; | |
403 | } | |
404 | ||
405 | gs = gc->data; | |
406 | if (!gs || !gs->prov_data) | |
407 | return -EINVAL; | |
408 | ||
409 | /* | |
06eaa531 | 410 | * GPIO consumers can access GPIOs in two ways: |
09574cca | 411 | * |
06eaa531 BG |
412 | * 1) Using the global GPIO numberspace. |
413 | * | |
414 | * This is the old, now DEPRECATED method and should not be used in | |
415 | * new code. TODO: Check if tegra is even concerned by this. | |
416 | * | |
417 | * 2) Using GPIO descriptors that can be assigned to consumer devices | |
418 | * using device-tree, ACPI or lookup tables. | |
09574cca DP |
419 | * |
420 | * The code below addresses both the consumer use cases and maps into | |
421 | * HTE/GTE namespace. | |
422 | */ | |
423 | if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && !args) { | |
dc850faa | 424 | line_id = desc->attr.line_id - gpio_device_get_base(gs->gdev); |
09574cca DP |
425 | map = gs->prov_data->map; |
426 | map_sz = gs->prov_data->map_sz; | |
427 | } else if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && args) { | |
428 | line_id = desc->attr.line_id; | |
429 | map = gs->prov_data->sec_map; | |
430 | map_sz = gs->prov_data->sec_map_sz; | |
431 | } else { | |
432 | line_id = desc->attr.line_id; | |
433 | } | |
434 | ||
435 | ret = tegra_hte_map_to_line_id(line_id, map, map_sz, xlated_id); | |
436 | if (ret < 0) { | |
437 | dev_err(gc->dev, "line_id:%u mapping failed\n", | |
438 | desc->attr.line_id); | |
439 | return ret; | |
440 | } | |
441 | ||
442 | if (*xlated_id > gc->nlines) | |
443 | return -EINVAL; | |
444 | ||
445 | dev_dbg(gc->dev, "requested id:%u, xlated id:%u\n", | |
446 | desc->attr.line_id, *xlated_id); | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
451 | static int tegra_hte_line_xlate_plat(struct hte_chip *gc, | |
452 | struct hte_ts_desc *desc, u32 *xlated_id) | |
453 | { | |
454 | return tegra_hte_line_xlate(gc, NULL, desc, xlated_id); | |
455 | } | |
456 | ||
457 | static int tegra_hte_en_dis_common(struct hte_chip *chip, u32 line_id, bool en) | |
458 | { | |
459 | u32 slice, sl_bit_shift, line_bit, val, reg; | |
460 | struct tegra_hte_soc *gs; | |
461 | ||
462 | sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); | |
463 | ||
464 | if (!chip) | |
465 | return -EINVAL; | |
466 | ||
467 | gs = chip->data; | |
468 | ||
469 | if (line_id > chip->nlines) { | |
470 | dev_err(chip->dev, | |
471 | "line id: %u is not supported by this controller\n", | |
472 | line_id); | |
473 | return -EINVAL; | |
474 | } | |
475 | ||
476 | slice = line_id >> sl_bit_shift; | |
477 | line_bit = line_id & (HTE_SLICE_SIZE - 1); | |
478 | reg = (slice << sl_bit_shift) + HTE_SLICE0_TETEN; | |
479 | ||
480 | spin_lock(&gs->sl[slice].s_lock); | |
481 | ||
482 | if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { | |
483 | spin_unlock(&gs->sl[slice].s_lock); | |
484 | dev_dbg(chip->dev, "device suspended"); | |
485 | return -EBUSY; | |
486 | } | |
487 | ||
488 | val = tegra_hte_readl(gs, reg); | |
489 | if (en) | |
490 | val = val | (1 << line_bit); | |
491 | else | |
492 | val = val & (~(1 << line_bit)); | |
493 | tegra_hte_writel(gs, reg, val); | |
494 | ||
495 | spin_unlock(&gs->sl[slice].s_lock); | |
496 | ||
497 | dev_dbg(chip->dev, "line: %u, slice %u, line_bit %u, reg:0x%x\n", | |
498 | line_id, slice, line_bit, reg); | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
503 | static int tegra_hte_enable(struct hte_chip *chip, u32 line_id) | |
504 | { | |
505 | if (!chip) | |
506 | return -EINVAL; | |
507 | ||
508 | return tegra_hte_en_dis_common(chip, line_id, true); | |
509 | } | |
510 | ||
511 | static int tegra_hte_disable(struct hte_chip *chip, u32 line_id) | |
512 | { | |
513 | if (!chip) | |
514 | return -EINVAL; | |
515 | ||
516 | return tegra_hte_en_dis_common(chip, line_id, false); | |
517 | } | |
518 | ||
519 | static int tegra_hte_request(struct hte_chip *chip, struct hte_ts_desc *desc, | |
520 | u32 line_id) | |
521 | { | |
522 | int ret; | |
523 | struct tegra_hte_soc *gs; | |
524 | struct hte_line_attr *attr; | |
525 | ||
526 | if (!chip || !chip->data || !desc) | |
527 | return -EINVAL; | |
528 | ||
529 | gs = chip->data; | |
530 | attr = &desc->attr; | |
531 | ||
532 | if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { | |
533 | if (!attr->line_data) | |
534 | return -EINVAL; | |
535 | ||
536 | ret = gpiod_enable_hw_timestamp_ns(attr->line_data, | |
537 | attr->edge_flags); | |
538 | if (ret) | |
539 | return ret; | |
540 | ||
541 | gs->line_data[line_id].data = attr->line_data; | |
542 | gs->line_data[line_id].flags = attr->edge_flags; | |
543 | } | |
544 | ||
545 | return tegra_hte_en_dis_common(chip, line_id, true); | |
546 | } | |
547 | ||
548 | static int tegra_hte_release(struct hte_chip *chip, struct hte_ts_desc *desc, | |
549 | u32 line_id) | |
550 | { | |
551 | struct tegra_hte_soc *gs; | |
552 | struct hte_line_attr *attr; | |
553 | int ret; | |
554 | ||
555 | if (!chip || !chip->data || !desc) | |
556 | return -EINVAL; | |
557 | ||
558 | gs = chip->data; | |
559 | attr = &desc->attr; | |
560 | ||
561 | if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { | |
562 | ret = gpiod_disable_hw_timestamp_ns(attr->line_data, | |
563 | gs->line_data[line_id].flags); | |
564 | if (ret) | |
565 | return ret; | |
566 | ||
567 | gs->line_data[line_id].data = NULL; | |
568 | gs->line_data[line_id].flags = 0; | |
569 | } | |
570 | ||
571 | return tegra_hte_en_dis_common(chip, line_id, false); | |
572 | } | |
573 | ||
574 | static int tegra_hte_clk_src_info(struct hte_chip *chip, | |
575 | struct hte_clk_info *ci) | |
576 | { | |
577 | (void)chip; | |
578 | ||
579 | if (!ci) | |
580 | return -EINVAL; | |
581 | ||
582 | ci->hz = HTE_TS_CLK_RATE_HZ; | |
583 | ci->type = CLOCK_MONOTONIC; | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | static int tegra_hte_get_level(struct tegra_hte_soc *gs, u32 line_id) | |
589 | { | |
590 | struct gpio_desc *desc; | |
591 | ||
592 | if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { | |
593 | desc = gs->line_data[line_id].data; | |
594 | if (desc) | |
595 | return gpiod_get_raw_value(desc); | |
596 | } | |
597 | ||
598 | return -1; | |
599 | } | |
600 | ||
601 | static void tegra_hte_read_fifo(struct tegra_hte_soc *gs) | |
602 | { | |
603 | u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id; | |
604 | u64 tsc; | |
605 | struct hte_ts_data el; | |
606 | ||
607 | while ((tegra_hte_readl(gs, HTE_TESTATUS) >> | |
608 | HTE_TESTATUS_OCCUPANCY_SHIFT) & | |
609 | HTE_TESTATUS_OCCUPANCY_MASK) { | |
610 | tsh = tegra_hte_readl(gs, HTE_TETSCH); | |
611 | tsl = tegra_hte_readl(gs, HTE_TETSCL); | |
612 | tsc = (((u64)tsh << 32) | tsl); | |
613 | ||
614 | src = tegra_hte_readl(gs, HTE_TESRC); | |
615 | slice = (src >> HTE_TESRC_SLICE_SHIFT) & | |
616 | HTE_TESRC_SLICE_DEFAULT_MASK; | |
617 | ||
618 | pv = tegra_hte_readl(gs, HTE_TEPCV); | |
619 | cv = tegra_hte_readl(gs, HTE_TECCV); | |
620 | acv = pv ^ cv; | |
621 | while (acv) { | |
622 | bit_index = __builtin_ctz(acv); | |
623 | line_id = bit_index + (slice << 5); | |
624 | el.tsc = tsc << HTE_TS_NS_SHIFT; | |
625 | el.raw_level = tegra_hte_get_level(gs, line_id); | |
626 | hte_push_ts_ns(gs->chip, line_id, &el); | |
627 | acv &= ~BIT(bit_index); | |
628 | } | |
629 | tegra_hte_writel(gs, HTE_TECMD, HTE_TECMD_CMD_POP); | |
630 | } | |
631 | } | |
632 | ||
633 | static irqreturn_t tegra_hte_isr(int irq, void *dev_id) | |
634 | { | |
635 | struct tegra_hte_soc *gs = dev_id; | |
636 | (void)irq; | |
637 | ||
638 | tegra_hte_read_fifo(gs); | |
639 | ||
640 | return IRQ_HANDLED; | |
641 | } | |
642 | ||
643 | static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, | |
644 | const struct hte_ts_desc *hdesc) | |
645 | { | |
646 | struct tegra_hte_soc *hte_dev = chip->data; | |
647 | ||
648 | if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO)) | |
649 | return false; | |
650 | ||
dc850faa | 651 | return hte_dev->gdev == gpiod_to_gpio_device(hdesc->attr.line_data); |
09574cca DP |
652 | } |
653 | ||
654 | static const struct of_device_id tegra_hte_of_match[] = { | |
0ebc475f | 655 | { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte}, |
b003fb5c | 656 | { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, |
0ebc475f | 657 | { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte}, |
b003fb5c | 658 | { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, |
09574cca DP |
659 | { } |
660 | }; | |
661 | MODULE_DEVICE_TABLE(of, tegra_hte_of_match); | |
662 | ||
663 | static const struct hte_ops g_ops = { | |
664 | .request = tegra_hte_request, | |
665 | .release = tegra_hte_release, | |
666 | .enable = tegra_hte_enable, | |
667 | .disable = tegra_hte_disable, | |
668 | .get_clk_src_info = tegra_hte_clk_src_info, | |
669 | }; | |
670 | ||
671 | static void tegra_gte_disable(void *data) | |
672 | { | |
673 | struct platform_device *pdev = data; | |
674 | struct tegra_hte_soc *gs = dev_get_drvdata(&pdev->dev); | |
675 | ||
676 | tegra_hte_writel(gs, HTE_TECTRL, 0); | |
677 | } | |
678 | ||
dc850faa | 679 | static void tegra_hte_put_gpio_device(void *data) |
09574cca | 680 | { |
dc850faa | 681 | struct gpio_device *gdev = data; |
09574cca | 682 | |
dc850faa | 683 | gpio_device_put(gdev); |
d02b1cab DP |
684 | } |
685 | ||
09574cca DP |
686 | static int tegra_hte_probe(struct platform_device *pdev) |
687 | { | |
688 | int ret; | |
689 | u32 i, slices, val = 0; | |
690 | u32 nlines; | |
691 | struct device *dev; | |
692 | struct tegra_hte_soc *hte_dev; | |
693 | struct hte_chip *gc; | |
d02b1cab | 694 | struct device_node *gpio_ctrl; |
09574cca DP |
695 | |
696 | dev = &pdev->dev; | |
697 | ||
09574cca DP |
698 | hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); |
699 | if (!hte_dev) | |
700 | return -ENOMEM; | |
701 | ||
702 | gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); | |
703 | if (!gc) | |
704 | return -ENOMEM; | |
705 | ||
706 | dev_set_drvdata(&pdev->dev, hte_dev); | |
707 | hte_dev->prov_data = of_device_get_match_data(&pdev->dev); | |
708 | ||
0ebc475f DP |
709 | ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); |
710 | if (ret != 0) | |
711 | slices = hte_dev->prov_data->slices; | |
712 | ||
713 | dev_dbg(dev, "slices:%d\n", slices); | |
714 | nlines = slices << 5; | |
715 | ||
09574cca DP |
716 | hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); |
717 | if (IS_ERR(hte_dev->regs)) | |
718 | return PTR_ERR(hte_dev->regs); | |
719 | ||
720 | ret = of_property_read_u32(dev->of_node, "nvidia,int-threshold", | |
721 | &hte_dev->itr_thrshld); | |
722 | if (ret != 0) | |
723 | hte_dev->itr_thrshld = 1; | |
724 | ||
725 | hte_dev->sl = devm_kcalloc(dev, slices, sizeof(*hte_dev->sl), | |
726 | GFP_KERNEL); | |
727 | if (!hte_dev->sl) | |
728 | return -ENOMEM; | |
729 | ||
730 | ret = platform_get_irq(pdev, 0); | |
0b40f91d | 731 | if (ret < 0) |
09574cca | 732 | return ret; |
09574cca DP |
733 | hte_dev->hte_irq = ret; |
734 | ret = devm_request_irq(dev, hte_dev->hte_irq, tegra_hte_isr, 0, | |
735 | dev_name(dev), hte_dev); | |
736 | if (ret < 0) { | |
737 | dev_err(dev, "request irq failed.\n"); | |
738 | return ret; | |
739 | } | |
740 | ||
741 | gc->nlines = nlines; | |
742 | gc->ops = &g_ops; | |
743 | gc->dev = dev; | |
744 | gc->data = hte_dev; | |
745 | gc->xlate_of = tegra_hte_line_xlate; | |
746 | gc->xlate_plat = tegra_hte_line_xlate_plat; | |
747 | gc->of_hte_n_cells = 1; | |
748 | ||
749 | if (hte_dev->prov_data && | |
750 | hte_dev->prov_data->type == HTE_TEGRA_TYPE_GPIO) { | |
751 | hte_dev->line_data = devm_kcalloc(dev, nlines, | |
752 | sizeof(*hte_dev->line_data), | |
753 | GFP_KERNEL); | |
754 | if (!hte_dev->line_data) | |
755 | return -ENOMEM; | |
756 | ||
757 | gc->match_from_linedata = tegra_hte_match_from_linedata; | |
758 | ||
b003fb5c | 759 | if (of_device_is_compatible(dev->of_node, |
d02b1cab | 760 | "nvidia,tegra194-gte-aon")) { |
dc850faa BG |
761 | hte_dev->gdev = |
762 | gpio_device_find_by_label("tegra194-gpio-aon"); | |
d02b1cab DP |
763 | } else { |
764 | gpio_ctrl = of_parse_phandle(dev->of_node, | |
765 | "nvidia,gpio-controller", | |
766 | 0); | |
767 | if (!gpio_ctrl) { | |
768 | dev_err(dev, | |
769 | "gpio controller node not found\n"); | |
770 | return -ENODEV; | |
771 | } | |
772 | ||
dc850faa BG |
773 | hte_dev->gdev = |
774 | gpio_device_find_by_fwnode(of_fwnode_handle(gpio_ctrl)); | |
d02b1cab DP |
775 | of_node_put(gpio_ctrl); |
776 | } | |
b003fb5c | 777 | |
dc850faa | 778 | if (!hte_dev->gdev) |
09574cca DP |
779 | return dev_err_probe(dev, -EPROBE_DEFER, |
780 | "wait for gpio controller\n"); | |
dc850faa BG |
781 | |
782 | ret = devm_add_action_or_reset(dev, tegra_hte_put_gpio_device, | |
783 | hte_dev->gdev); | |
784 | if (ret) | |
785 | return ret; | |
09574cca DP |
786 | } |
787 | ||
788 | hte_dev->chip = gc; | |
789 | ||
790 | ret = devm_hte_register_chip(hte_dev->chip); | |
791 | if (ret) { | |
792 | dev_err(gc->dev, "hte chip register failed"); | |
793 | return ret; | |
794 | } | |
795 | ||
796 | for (i = 0; i < slices; i++) { | |
797 | hte_dev->sl[i].flags = 0; | |
798 | spin_lock_init(&hte_dev->sl[i].s_lock); | |
799 | } | |
800 | ||
801 | val = HTE_TECTRL_ENABLE_ENABLE | | |
802 | (HTE_TECTRL_INTR_ENABLE << HTE_TECTRL_INTR_SHIFT) | | |
803 | (hte_dev->itr_thrshld << HTE_TECTRL_OCCU_SHIFT); | |
804 | tegra_hte_writel(hte_dev, HTE_TECTRL, val); | |
805 | ||
806 | ret = devm_add_action_or_reset(&pdev->dev, tegra_gte_disable, pdev); | |
807 | if (ret) | |
808 | return ret; | |
809 | ||
810 | dev_dbg(gc->dev, "lines: %d, slices:%d", gc->nlines, slices); | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
091ac92d | 815 | static int tegra_hte_resume_early(struct device *dev) |
09574cca DP |
816 | { |
817 | u32 i; | |
818 | struct tegra_hte_soc *gs = dev_get_drvdata(dev); | |
819 | u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; | |
820 | u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); | |
821 | ||
822 | tegra_hte_writel(gs, HTE_TECTRL, gs->conf_rval); | |
823 | ||
824 | for (i = 0; i < slices; i++) { | |
825 | spin_lock(&gs->sl[i].s_lock); | |
826 | tegra_hte_writel(gs, | |
827 | ((i << sl_bit_shift) + HTE_SLICE0_TETEN), | |
828 | gs->sl[i].r_val); | |
829 | clear_bit(HTE_SUSPEND, &gs->sl[i].flags); | |
830 | spin_unlock(&gs->sl[i].s_lock); | |
831 | } | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
091ac92d | 836 | static int tegra_hte_suspend_late(struct device *dev) |
09574cca DP |
837 | { |
838 | u32 i; | |
839 | struct tegra_hte_soc *gs = dev_get_drvdata(dev); | |
840 | u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; | |
841 | u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); | |
842 | ||
843 | gs->conf_rval = tegra_hte_readl(gs, HTE_TECTRL); | |
844 | for (i = 0; i < slices; i++) { | |
845 | spin_lock(&gs->sl[i].s_lock); | |
846 | gs->sl[i].r_val = tegra_hte_readl(gs, | |
847 | ((i << sl_bit_shift) + HTE_SLICE0_TETEN)); | |
848 | set_bit(HTE_SUSPEND, &gs->sl[i].flags); | |
849 | spin_unlock(&gs->sl[i].s_lock); | |
850 | } | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
855 | static const struct dev_pm_ops tegra_hte_pm = { | |
091ac92d | 856 | LATE_SYSTEM_SLEEP_PM_OPS(tegra_hte_suspend_late, tegra_hte_resume_early) |
09574cca DP |
857 | }; |
858 | ||
859 | static struct platform_driver tegra_hte_driver = { | |
860 | .probe = tegra_hte_probe, | |
861 | .driver = { | |
862 | .name = "tegra_hte", | |
091ac92d | 863 | .pm = pm_sleep_ptr(&tegra_hte_pm), |
09574cca DP |
864 | .of_match_table = tegra_hte_of_match, |
865 | }, | |
866 | }; | |
867 | ||
868 | module_platform_driver(tegra_hte_driver); | |
869 | ||
870 | MODULE_AUTHOR("Dipen Patel <dipenp@nvidia.com>"); | |
871 | MODULE_DESCRIPTION("NVIDIA Tegra HTE (Hardware Timestamping Engine) driver"); | |
872 | MODULE_LICENSE("GPL"); |